From 92aa436d7fc63580e894ed2b841ef5be67310fe4 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Thu, 20 Apr 2023 00:54:47 -0400 Subject: [PATCH 01/16] Fix null pointer dereferencing Add null check for return values of functions that are mostly (but not always) checked for null. E.g., since 98% of calls to protocol_stack_interface_info_get_by_id check for null, it is likely that the function can return null values in some cases, and omitting the check could crash the program. --- .../cordio_stack/ble-host/sources/stack/att/att_eatt.c | 9 +++++++-- connectivity/FEATURE_BLE/source/generic/SecurityDb.cpp | 8 ++++++++ .../FEATURE_BLE/source/generic/SecurityManagerImpl.cpp | 3 +++ .../coap-service/source/coap_connection_handler.c | 2 +- .../nanostack/mbed-mesh-api/source/thread_tasklet.c | 3 +++ .../source/6LoWPAN/Thread/thread_bbr_api.c | 3 +++ .../source/6LoWPAN/Thread/thread_bbr_commercial.c | 5 ++++- .../source/6LoWPAN/Thread/thread_ccm.c | 5 +++++ .../source/6LoWPAN/Thread/thread_common.c | 6 ++++-- .../source/6LoWPAN/Thread/thread_joiner_application.c | 4 ++-- .../sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c | 3 +++ 11 files changed, 43 insertions(+), 8 deletions(-) diff --git a/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/att/att_eatt.c b/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/att/att_eatt.c index 330d9efe93e..5a9376425ca 100644 --- a/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/att/att_eatt.c +++ b/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/att/att_eatt.c @@ -267,7 +267,7 @@ static uint8_t eattL2cCocAcceptCback(dmConnId_t connId, uint8_t numChans) { eattConnCb_t *pCcb = eattGetConnCb(connId); - if ((pCcb->state == EATT_CONN_STATE_INITIATING) || (pCcb->state == EATT_CONN_STATE_RECONFIG)) + if (!pCcb || (pCcb->state == EATT_CONN_STATE_INITIATING) || (pCcb->state == EATT_CONN_STATE_RECONFIG)) { // Reject all requests while busy connecting and configuring channels return 0; @@ -348,6 +348,10 @@ static void eattReqNextChannels(dmConnId_t connId) eattConnCb_t *pConnCb = eattGetConnCb(connId); uint8_t numChans = pEattCfg->numChans - EattGetNumChannelsInUse(connId); + if (!pConnCb) { + return; + } + numChans = (numChans > L2C_MAX_EN_CHAN) ? L2C_MAX_EN_CHAN : numChans; EATT_TRACE_INFO1("eattReqNextChannels: numChans: %d", numChans); @@ -783,7 +787,7 @@ static void eattDmCback(dmEvt_t *pDmEvt) * \param connId DM channel ID. * \param slot EATT slot. * - * \return None + * \return L2CAP channel identifier. */ /*************************************************************************************************/ uint16_t eattGetCid(dmConnId_t connId, uint8_t slot) @@ -795,6 +799,7 @@ uint16_t eattGetCid(dmConnId_t connId, uint8_t slot) else { eattConnCb_t *pCcb = eattGetConnCb(connId); + WSF_ASSERT(pCcb); return pCcb->pChanCb[slot-1].cid; } } diff --git a/connectivity/FEATURE_BLE/source/generic/SecurityDb.cpp b/connectivity/FEATURE_BLE/source/generic/SecurityDb.cpp index b72fbb8369b..b4a0cea83cb 100644 --- a/connectivity/FEATURE_BLE/source/generic/SecurityDb.cpp +++ b/connectivity/FEATURE_BLE/source/generic/SecurityDb.cpp @@ -63,10 +63,18 @@ void SecurityDb::get_entry_local_keys( /* set flags connected */ SecurityDistributionFlags_t* flags = get_distribution_flags(correct_handle); + if (!flags) { + cb(*db_handle, NULL); + return; + } flags->connected = true; /* update peer address */ SecurityDistributionFlags_t* old_flags = get_distribution_flags(*db_handle); + if (!old_flags) { + cb(*db_handle, NULL); + return; + } flags->peer_address = old_flags->peer_address; flags->peer_address_is_public = old_flags->peer_address_is_public; diff --git a/connectivity/FEATURE_BLE/source/generic/SecurityManagerImpl.cpp b/connectivity/FEATURE_BLE/source/generic/SecurityManagerImpl.cpp index 630e17741b9..f924bb85d66 100644 --- a/connectivity/FEATURE_BLE/source/generic/SecurityManagerImpl.cpp +++ b/connectivity/FEATURE_BLE/source/generic/SecurityManagerImpl.cpp @@ -1661,6 +1661,9 @@ void SecurityManager::on_connected( cb->db_entry = _db->open_entry(peer_address_type, peer_address); SecurityDistributionFlags_t* flags = _db->get_distribution_flags(cb->db_entry); + if (!flags) { + return; + } flags->peer_address = peer_address; flags->peer_address_is_public = diff --git a/connectivity/nanostack/coap-service/source/coap_connection_handler.c b/connectivity/nanostack/coap-service/source/coap_connection_handler.c index a749cac806b..92d17e35832 100644 --- a/connectivity/nanostack/coap-service/source/coap_connection_handler.c +++ b/connectivity/nanostack/coap-service/source/coap_connection_handler.c @@ -480,7 +480,7 @@ static int secure_session_recvfrom(int8_t socket_id, unsigned char *buf, size_t { (void)len; internal_socket_t *sock = int_socket_find_by_socket_id(socket_id); - if (sock->data && sock->data_len > 0) { + if (sock && sock->data && sock->data_len > 0) { memcpy(buf, sock->data, sock->data_len); int l = sock->data_len; ns_dyn_mem_free(sock->data); diff --git a/connectivity/nanostack/mbed-mesh-api/source/thread_tasklet.c b/connectivity/nanostack/mbed-mesh-api/source/thread_tasklet.c index 300707f761e..ddda7350909 100644 --- a/connectivity/nanostack/mbed-mesh-api/source/thread_tasklet.c +++ b/connectivity/nanostack/mbed-mesh-api/source/thread_tasklet.c @@ -238,6 +238,9 @@ void thread_tasklet_poll_network_status(void *param) } else { memcpy(thread_tasklet_data_ptr->ip, temp_ipv6, 16); link_configuration_s *link_cfg = thread_management_configuration_get(thread_tasklet_data_ptr->nwk_if_id); + if (!link_cfg) { + return; + } if (memcmp(thread_tasklet_data_ptr->ip, link_cfg->mesh_local_ula_prefix, 8) == 0) { thread_tasklet_network_state_changed(MESH_CONNECTED_LOCAL); } else { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_api.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_api.c index bae8e8a3c79..72989d7b418 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_api.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_api.c @@ -682,6 +682,9 @@ static void thread_bbr_status_check(thread_bbr_t *this, uint32_t seconds) } // Check if network data as border router is possible or modified protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(this->interface_id); + if (!cur) { + return; + } this->br_hosted = thread_bbr_i_host_prefix(cur, bbr_prefix_ptr, &this->br_count, &br_lowest_host); if (!this->br_info_published && bbr_prefix_ptr && this->br_count == 0) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_commercial.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_commercial.c index 3abd7735e22..f9c594094e1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_commercial.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bbr_commercial.c @@ -545,6 +545,9 @@ static int thread_pbbr_bb_qry_cb(int8_t service_id, uint8_t source_address[16], // Test code for b/ba response override if (ba_response_status_count) { device_configuration_s *device_config = thread_joiner_application_get_device_config(this->interface_id); + if (!device_config) { + return -1; + } ml_eid_ptr = device_config->eui64; last_transaction_time = protocol_core_monotonic_time; ba_response_status_count--; @@ -617,7 +620,7 @@ static int thread_pbbr_dua_duplicate_address_detection(int8_t service_id, uint8_ protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(this->interface_id); duplicate_dua_tr_t *tr_ptr = thread_border_router_dup_tr_find(this->interface_id, addr_data_ptr); - if (!tr_ptr) { + if (!cur || !tr_ptr) { return -1; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_ccm.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_ccm.c index 0795599e8b5..c68b9ce9efa 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_ccm.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_ccm.c @@ -756,6 +756,11 @@ static int thread_ccm_reenroll_registrar_addr_resp_cb(int8_t service_id, uint8_t return -1; } + if (!cur) { + tr_debug("Protocol stack interface info get failed"); + return -1; + } + if (!thread_meshcop_tlv_find(response_ptr->payload_ptr, response_ptr->payload_len, MESHCOP_TLV_REGISTRAR_IPV6_ADDRESS, &addr_ptr)) { tr_debug("Registrar addr get failed"); return -1; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c index 67fc029be81..6a5a4236095 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c @@ -751,8 +751,10 @@ void thread_child_id_request_info_init(thread_pending_child_id_req_t *child_info thread_pending_child_id_req_t *thread_child_id_request_allocate(void) { thread_pending_child_id_req_t *req = ns_dyn_mem_alloc(sizeof(thread_pending_child_id_req_t)); - memset(req->eiid, 0, 8); - thread_child_id_request_info_init(req); + if (req) { + memset(req->eiid, 0, 8); + thread_child_id_request_info_init(req); + } return req; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_joiner_application.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_joiner_application.c index 481dc23775e..c5dba1c685b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_joiner_application.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_joiner_application.c @@ -719,8 +719,9 @@ static void configuration_set_copy_mandatory(configuration_set_t *destination_pt static void configuration_set_generate(int8_t interface_id, configuration_set_t *destination_ptr, link_configuration_s *configuration_ptr) { uint8_t *response_ptr; + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!destination_ptr || !configuration_ptr) { + if (!destination_ptr || !configuration_ptr || !cur) { return; } response_ptr = destination_ptr->data; @@ -739,7 +740,6 @@ static void configuration_set_generate(int8_t interface_id, configuration_set_t response_ptr = thread_tmfcop_tlv_data_write(response_ptr, MESHCOP_TLV_PSKC, 16, configuration_ptr->PSKc); response_ptr = thread_tmfcop_tlv_data_write(response_ptr, MESHCOP_TLV_NETWORK_NAME, stringlen((char *)&configuration_ptr->name, 16), configuration_ptr->name); *response_ptr++ = MESHCOP_TLV_SECURITY_POLICY; // type - protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); if (thread_info(cur)->version >= THREAD_VERSION_1_2) { *response_ptr++ = 4; // length response_ptr = common_write_16_bit(configuration_ptr->key_rotation, response_ptr); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c index fa6b66da4b1..ca6e9e87b69 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c @@ -1057,6 +1057,9 @@ static int8_t ws_pae_auth_timer_if_stop(kmp_service_t *service, kmp_api_t *kmp) (void) service; supp_entry_t *supp_entry = kmp_api_data_get(kmp); + if (!supp_entry) { + return -1; + } kmp_entry_t *entry = ws_pae_lib_kmp_list_entry_get(&supp_entry->kmp_list, kmp); if (!entry) { From f4a4f549c2edf57b92d03b6548ad1d86b80e78be Mon Sep 17 00:00:00 2001 From: Ahmet Polat Date: Wed, 26 Apr 2023 14:37:03 +0300 Subject: [PATCH 02/16] Update MAX32660 peripheral drivers with final ones that use by SDK --- .../Device/Maxim/MAX32660/Include/dma_regs.h | 370 +++-- .../Device/Maxim/MAX32660/Include/fcr_regs.h | 44 +- .../Device/Maxim/MAX32660/Include/flc_regs.h | 126 +- .../Device/Maxim/MAX32660/Include/gcr_regs.h | 358 ++--- .../Device/Maxim/MAX32660/Include/gpio_regs.h | 430 +++--- .../Device/Maxim/MAX32660/Include/i2c_regs.h | 500 +++---- .../Device/Maxim/MAX32660/Include/icc_regs.h | 66 +- .../Device/Maxim/MAX32660/Include/max32660.h | 446 +++--- .../Maxim/MAX32660/Include/pwrseq_regs.h | 124 +- .../Device/Maxim/MAX32660/Include/rtc_regs.h | 182 +-- .../Device/Maxim/MAX32660/Include/sir_regs.h | 38 +- .../Device/Maxim/MAX32660/Include/spi_regs.h | 360 ++--- .../Maxim/MAX32660/Include/spimss_regs.h | 332 ++--- .../Maxim/MAX32660/Include/system_max32660.h | 24 +- .../Device/Maxim/MAX32660/Include/tmr_regs.h | 196 ++- .../Device/Maxim/MAX32660/Include/uart_regs.h | 332 ++--- .../Device/Maxim/MAX32660/Include/wdt_regs.h | 210 +-- .../Maxim/MAX32660/Source/system_max32660.c | 97 +- .../PeriphDrivers/Include/MAX32660/dma.h | 163 +-- .../PeriphDrivers/Include/MAX32660/flc.h | 42 +- .../PeriphDrivers/Include/MAX32660/gpio.h | 152 +- .../PeriphDrivers/Include/MAX32660/i2s.h | 60 +- .../PeriphDrivers/Include/MAX32660/icc.h | 26 +- .../PeriphDrivers/Include/MAX32660/lp.h | 36 +- .../PeriphDrivers/Include/MAX32660/msr.h | 144 +- .../Include/MAX32660/mxc_assert.h | 24 +- .../Include/MAX32660/mxc_delay.h | 40 +- .../Include/MAX32660/mxc_device.h | 32 +- .../Include/MAX32660/mxc_errors.h | 52 +- .../PeriphDrivers/Include/MAX32660/mxc_i2c.h | 176 +-- .../PeriphDrivers/Include/MAX32660/mxc_lock.h | 29 +- .../PeriphDrivers/Include/MAX32660/mxc_pins.h | 26 +- .../PeriphDrivers/Include/MAX32660/mxc_spi.h | 151 +- .../PeriphDrivers/Include/MAX32660/mxc_sys.h | 227 ++- .../PeriphDrivers/Include/MAX32660/rtc.h | 91 +- .../PeriphDrivers/Include/MAX32660/spimss.h | 65 +- .../PeriphDrivers/Include/MAX32660/tmr.h | 148 +- .../PeriphDrivers/Include/MAX32660/uart.h | 199 +-- .../PeriphDrivers/Include/MAX32660/wdt.h | 74 +- .../PeriphDrivers/Source/DMA/dma_me11.c | 46 +- .../PeriphDrivers/Source/DMA/dma_reva.c | 426 +++--- .../PeriphDrivers/Source/DMA/dma_reva.h | 25 +- .../PeriphDrivers/Source/DMA/dma_reva_regs.h | 39 +- .../PeriphDrivers/Source/FLC/flc_common.c | 74 +- .../PeriphDrivers/Source/FLC/flc_common.h | 26 +- .../PeriphDrivers/Source/FLC/flc_me11.c | 241 ++-- .../PeriphDrivers/Source/FLC/flc_reva.c | 289 ++-- .../PeriphDrivers/Source/FLC/flc_reva.h | 53 +- .../PeriphDrivers/Source/FLC/flc_reva_regs.h | 127 +- .../PeriphDrivers/Source/GPIO/gpio_common.c | 42 +- .../PeriphDrivers/Source/GPIO/gpio_common.h | 18 +- .../PeriphDrivers/Source/GPIO/gpio_me11.c | 127 +- .../PeriphDrivers/Source/GPIO/gpio_reva.c | 178 ++- .../PeriphDrivers/Source/GPIO/gpio_reva.h | 48 +- .../Source/GPIO/gpio_reva_regs.h | 748 +++++----- .../PeriphDrivers/Source/I2C/i2c_me11.c | 26 +- .../PeriphDrivers/Source/I2C/i2c_reva.c | 105 +- .../PeriphDrivers/Source/I2C/i2c_reva.h | 13 +- .../PeriphDrivers/Source/I2C/i2c_reva_regs.h | 7 +- .../PeriphDrivers/Source/ICC/icc_common.c | 7 +- .../PeriphDrivers/Source/ICC/icc_common.h | 11 +- .../PeriphDrivers/Source/ICC/icc_me11.c | 20 +- .../PeriphDrivers/Source/ICC/icc_reva.c | 33 +- .../PeriphDrivers/Source/ICC/icc_reva.h | 19 +- .../PeriphDrivers/Source/ICC/icc_reva_regs.h | 54 +- .../PeriphDrivers/Source/LP/lp_me11.c | 191 +-- .../PeriphDrivers/Source/RTC/rtc_me11.c | 100 +- .../PeriphDrivers/Source/RTC/rtc_reva.c | 489 ++++--- .../PeriphDrivers/Source/RTC/rtc_reva.h | 63 +- .../PeriphDrivers/Source/RTC/rtc_reva_regs.h | 7 +- .../PeriphDrivers/Source/SPI/spi_me11.c | 246 ++-- .../PeriphDrivers/Source/SPI/spi_reva.c | 1273 +++++++++-------- .../PeriphDrivers/Source/SPI/spi_reva.h | 131 +- .../PeriphDrivers/Source/SPI/spi_reva_regs.h | 7 +- .../PeriphDrivers/Source/SPIMSS/i2s_me11.c | 43 +- .../PeriphDrivers/Source/SPIMSS/i2s_reva.c | 254 +++- .../PeriphDrivers/Source/SPIMSS/i2s_reva.h | 16 +- .../PeriphDrivers/Source/SPIMSS/spimss_me11.c | 68 +- .../PeriphDrivers/Source/SPIMSS/spimss_reva.c | 348 +++-- .../PeriphDrivers/Source/SPIMSS/spimss_reva.h | 47 +- .../Source/SPIMSS/spimss_reva_regs.h | 7 +- .../PeriphDrivers/Source/SYS/mxc_assert.c | 9 +- .../PeriphDrivers/Source/SYS/mxc_delay.c | 96 +- .../PeriphDrivers/Source/SYS/mxc_lock.c | 38 +- .../PeriphDrivers/Source/SYS/pins_me11.c | 78 +- .../PeriphDrivers/Source/SYS/sys_me11.c | 223 +-- .../PeriphDrivers/Source/TMR/tmr_common.c | 48 +- .../PeriphDrivers/Source/TMR/tmr_common.h | 29 +- .../PeriphDrivers/Source/TMR/tmr_me11.c | 123 +- .../PeriphDrivers/Source/TMR/tmr_reva.c | 211 ++- .../PeriphDrivers/Source/TMR/tmr_reva.h | 35 +- .../PeriphDrivers/Source/TMR/tmr_reva_regs.h | 7 +- .../PeriphDrivers/Source/UART/uart_common.c | 18 +- .../PeriphDrivers/Source/UART/uart_common.h | 14 +- .../PeriphDrivers/Source/UART/uart_me11.c | 325 +++-- .../PeriphDrivers/Source/UART/uart_reva.c | 1076 ++++++++------ .../PeriphDrivers/Source/UART/uart_reva.h | 129 +- .../Source/UART/uart_reva_regs.h | 7 +- .../PeriphDrivers/Source/WDT/wdt_common.c | 6 +- .../PeriphDrivers/Source/WDT/wdt_me11.c | 72 +- .../PeriphDrivers/Source/WDT/wdt_reva.c | 45 +- .../PeriphDrivers/Source/WDT/wdt_reva.h | 35 +- .../PeriphDrivers/Source/WDT/wdt_reva_regs.h | 7 +- 103 files changed, 7978 insertions(+), 6937 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h index cf370a9d4d4..8f4eee91655 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h @@ -1,10 +1,11 @@ /** * @file dma_regs.h * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _DMA_REGS_H_ -#define _DMA_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,32 +78,28 @@ extern "C" { * @ingroup dma * @defgroup dma_registers DMA_Registers * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. - * @details DMA Controller Fully programmable, chaining capable DMA channels. + * @details DMA Controller Fully programmable, chaining capable DMA channels. */ /** * @ingroup dma_registers - * Structure type to access the DMA Channel Registers. + * Structure type to access the DMA Registers. */ typedef struct { - __IO uint32_t cfg; /**< \b 0x100: DMA CFG Register */ - __IO uint32_t stat; /**< \b 0x104: DMA STAT Register */ - __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ - __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ - __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ - __IO uint32_t src_rld; /**< \b 0x114: DMA SRC_RLD Register */ - __IO uint32_t dst_rld; /**< \b 0x118: DMA DST_RLD Register */ - __IO uint32_t cnt_rld; /**< \b 0x11C: DMA CNT_RLD Register */ + __IO uint32_t cfg; /**< \b 0x000: DMA CFG Register */ + __IO uint32_t stat; /**< \b 0x004: DMA STAT Register */ + __IO uint32_t src; /**< \b 0x008: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x00C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x010: DMA CNT Register */ + __IO uint32_t src_rld; /**< \b 0x014: DMA SRC_RLD Register */ + __IO uint32_t dst_rld; /**< \b 0x018: DMA DST_RLD Register */ + __IO uint32_t cnt_rld; /**< \b 0x01C: DMA CNT_RLD Register */ } mxc_dma_ch_regs_t; -/** - * @ingroup dma_registers - * Structure type to access the DMA Registers. - */ typedef struct { __IO uint32_t int_en; /**< \b 0x000: DMA INT_EN Register */ __I uint32_t int_fl; /**< \b 0x004: DMA INT_FL Register */ - __I uint32_t rsv_0x8_0xff[62]; + __R uint32_t rsv_0x8_0xff[62]; __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; @@ -109,20 +107,20 @@ typedef struct { /** * @ingroup dma_registers * @defgroup DMA_Register_Offsets Register Offsets - * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. * @{ */ - #define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ - #define MXC_R_DMA_STAT ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ - #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ - #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ - #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ - #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ - #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ - #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ - #define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ - #define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ - #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +#define MXC_R_DMA_CFG ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_STAT ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: 0x0008 */ +#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: 0x000C */ +#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: 0x0010 */ +#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: 0x0014 */ +#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: 0x0018 */ +#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: 0x001C */ +#define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ /**@} end of group dma_registers */ /** @@ -131,12 +129,12 @@ typedef struct { * @brief DMA Control Register. * @{ */ - #define MXC_F_DMA_INT_EN_CHIEN_POS 0 /**< INT_EN_CHIEN Position */ - #define MXC_F_DMA_INT_EN_CHIEN ((uint32_t)(0xFUL << MXC_F_DMA_INT_EN_CHIEN_POS)) /**< INT_EN_CHIEN Mask */ - #define MXC_V_DMA_INT_EN_CHIEN_DIS ((uint32_t)0x0UL) /**< INT_EN_CHIEN_DIS Value */ - #define MXC_S_DMA_INT_EN_CHIEN_DIS (MXC_V_DMA_INT_EN_CHIEN_DIS << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_DIS Setting */ - #define MXC_V_DMA_INT_EN_CHIEN_EN ((uint32_t)0x1UL) /**< INT_EN_CHIEN_EN Value */ - #define MXC_S_DMA_INT_EN_CHIEN_EN (MXC_V_DMA_INT_EN_CHIEN_EN << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_EN Setting */ +#define MXC_F_DMA_INT_EN_CHIEN_POS 0 /**< INT_EN_CHIEN Position */ +#define MXC_F_DMA_INT_EN_CHIEN ((uint32_t)(0xFUL << MXC_F_DMA_INT_EN_CHIEN_POS)) /**< INT_EN_CHIEN Mask */ +#define MXC_V_DMA_INT_EN_CHIEN_DIS ((uint32_t)0x0UL) /**< INT_EN_CHIEN_DIS Value */ +#define MXC_S_DMA_INT_EN_CHIEN_DIS (MXC_V_DMA_INT_EN_CHIEN_DIS << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_DIS Setting */ +#define MXC_V_DMA_INT_EN_CHIEN_EN ((uint32_t)0x1UL) /**< INT_EN_CHIEN_EN Value */ +#define MXC_S_DMA_INT_EN_CHIEN_EN (MXC_V_DMA_INT_EN_CHIEN_EN << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_EN Setting */ /**@} end of group DMA_INT_EN_Register */ @@ -146,12 +144,12 @@ typedef struct { * @brief DMA Interrupt Register. * @{ */ - #define MXC_F_DMA_INT_FL_IPEND_POS 0 /**< INT_FL_IPEND Position */ - #define MXC_F_DMA_INT_FL_IPEND ((uint32_t)(0xFUL << MXC_F_DMA_INT_FL_IPEND_POS)) /**< INT_FL_IPEND Mask */ - #define MXC_V_DMA_INT_FL_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IPEND_INACTIVE Value */ - #define MXC_S_DMA_INT_FL_IPEND_INACTIVE (MXC_V_DMA_INT_FL_IPEND_INACTIVE << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_INACTIVE Setting */ - #define MXC_V_DMA_INT_FL_IPEND_PENDING ((uint32_t)0x1UL) /**< INT_FL_IPEND_PENDING Value */ - #define MXC_S_DMA_INT_FL_IPEND_PENDING (MXC_V_DMA_INT_FL_IPEND_PENDING << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_PENDING Setting */ +#define MXC_F_DMA_INT_FL_IPEND_POS 0 /**< INT_FL_IPEND Position */ +#define MXC_F_DMA_INT_FL_IPEND ((uint32_t)(0xFUL << MXC_F_DMA_INT_FL_IPEND_POS)) /**< INT_FL_IPEND Mask */ +#define MXC_V_DMA_INT_FL_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IPEND_INACTIVE Value */ +#define MXC_S_DMA_INT_FL_IPEND_INACTIVE (MXC_V_DMA_INT_FL_IPEND_INACTIVE << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_INACTIVE Setting */ +#define MXC_V_DMA_INT_FL_IPEND_PENDING ((uint32_t)0x1UL) /**< INT_FL_IPEND_PENDING Value */ +#define MXC_S_DMA_INT_FL_IPEND_PENDING (MXC_V_DMA_INT_FL_IPEND_PENDING << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_PENDING Setting */ /**@} end of group DMA_INT_FL_Register */ @@ -161,117 +159,117 @@ typedef struct { * @brief DMA Channel Configuration Register. * @{ */ - #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ - #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ - - #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ - #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ - - #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ - #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ - #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ - #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ - #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ - #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ - #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ - #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ - #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ - #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ - - #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ - #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ - #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ - #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ - #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ - #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ - #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ - #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ - #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ - #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ - #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ - #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ - #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ - #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ - #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ - #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ - #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ - #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ - #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ - #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ - #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ - #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ - #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ - #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ - #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ - #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ - #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ - #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ - - #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ - #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ - - #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ - #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ - #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ - #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ - #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ - - #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ - #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ - #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ - #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ - #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ - #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ - #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ - #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ - #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ - #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ - - #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ - #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ - #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ - #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ - #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ - #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ - #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ - #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ - - #define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */ - #define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */ - - #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ - #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ - #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ - #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ - #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ - #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ - #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ - #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ - - #define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ - #define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ - - #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ - #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ - - #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ - #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ - - #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ - #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ +#define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ +#define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ + +#define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ +#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ + +#define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ +#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ +#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ +#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ +#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ +#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ +#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ +#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ +#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ +#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ + +#define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ +#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ +#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ +#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ +#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ +#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ +#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ +#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ +#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ +#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ +#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ +#define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ +#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ +#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ +#define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ +#define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ +#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ +#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ +#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ +#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ +#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ +#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ +#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ +#define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ +#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ +#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ +#define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ +#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ + +#define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ +#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ + +#define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ +#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ +#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ +#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ +#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ + +#define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ +#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ +#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ +#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ +#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ +#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ +#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ +#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ +#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ +#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ + +#define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ +#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ +#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ +#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ +#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ +#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ +#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ +#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ + +#define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */ +#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */ + +#define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ +#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ +#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ +#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ +#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ +#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ +#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ +#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ + +#define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ +#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ + +#define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ +#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ + +#define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ +#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ + +#define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ +#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ /**@} end of group DMA_CFG_Register */ @@ -281,23 +279,23 @@ typedef struct { * @brief DMA Channel Status Register. * @{ */ - #define MXC_F_DMA_STAT_CH_ST_POS 0 /**< STAT_CH_ST Position */ - #define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS)) /**< STAT_CH_ST Mask */ +#define MXC_F_DMA_STAT_CH_ST_POS 0 /**< STAT_CH_ST Position */ +#define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS)) /**< STAT_CH_ST Mask */ - #define MXC_F_DMA_STAT_IPEND_POS 1 /**< STAT_IPEND Position */ - #define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS)) /**< STAT_IPEND Mask */ +#define MXC_F_DMA_STAT_IPEND_POS 1 /**< STAT_IPEND Position */ +#define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS)) /**< STAT_IPEND Mask */ - #define MXC_F_DMA_STAT_CTZ_ST_POS 2 /**< STAT_CTZ_ST Position */ - #define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS)) /**< STAT_CTZ_ST Mask */ +#define MXC_F_DMA_STAT_CTZ_ST_POS 2 /**< STAT_CTZ_ST Position */ +#define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS)) /**< STAT_CTZ_ST Mask */ - #define MXC_F_DMA_STAT_RLD_ST_POS 3 /**< STAT_RLD_ST Position */ - #define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS)) /**< STAT_RLD_ST Mask */ +#define MXC_F_DMA_STAT_RLD_ST_POS 3 /**< STAT_RLD_ST Position */ +#define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS)) /**< STAT_RLD_ST Mask */ - #define MXC_F_DMA_STAT_BUS_ERR_POS 4 /**< STAT_BUS_ERR Position */ - #define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS)) /**< STAT_BUS_ERR Mask */ +#define MXC_F_DMA_STAT_BUS_ERR_POS 4 /**< STAT_BUS_ERR Position */ +#define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS)) /**< STAT_BUS_ERR Mask */ - #define MXC_F_DMA_STAT_TO_ST_POS 6 /**< STAT_TO_ST Position */ - #define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS)) /**< STAT_TO_ST Mask */ +#define MXC_F_DMA_STAT_TO_ST_POS 6 /**< STAT_TO_ST Position */ +#define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS)) /**< STAT_TO_ST Mask */ /**@} end of group DMA_STAT_Register */ @@ -311,8 +309,8 @@ typedef struct { * register is reloaded with the contents of DMA_SRC_RLD. * @{ */ - #define MXC_F_DMA_SRC_SRC_POS 0 /**< SRC_SRC Position */ - #define MXC_F_DMA_SRC_SRC ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_SRC_POS)) /**< SRC_SRC Mask */ +#define MXC_F_DMA_SRC_SRC_POS 0 /**< SRC_SRC Position */ +#define MXC_F_DMA_SRC_SRC ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_SRC_POS)) /**< SRC_SRC Mask */ /**@} end of group DMA_SRC_Register */ @@ -326,8 +324,8 @@ typedef struct { * while RLDEN=1, the register is reloaded with DMA_DST_RLD. * @{ */ - #define MXC_F_DMA_DST_DST_POS 0 /**< DST_DST Position */ - #define MXC_F_DMA_DST_DST ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_DST_POS)) /**< DST_DST Mask */ +#define MXC_F_DMA_DST_DST_POS 0 /**< DST_DST Position */ +#define MXC_F_DMA_DST_DST ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_DST_POS)) /**< DST_DST Mask */ /**@} end of group DMA_DST_Register */ @@ -340,8 +338,8 @@ typedef struct { * reaches 0, a count-to-zero condition is triggered. * @{ */ - #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ - #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ +#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ +#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ /**@} end of group DMA_CNT_Register */ @@ -352,8 +350,8 @@ typedef struct { * upon a count-to-zero condition. * @{ */ - #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ - #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ +#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ +#define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ /**@} end of group DMA_SRC_RLD_Register */ @@ -364,8 +362,8 @@ typedef struct { * DMA0_DST upon a count-to-zero condition. * @{ */ - #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ - #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ +#define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ +#define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ /**@} end of group DMA_DST_RLD_Register */ @@ -375,11 +373,11 @@ typedef struct { * @brief DMA Channel Count Reload Register. * @{ */ - #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ - #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ +#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ +#define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ - #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ - #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ +#define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ +#define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ /**@} end of group DMA_CNT_RLD_Register */ @@ -387,4 +385,4 @@ typedef struct { } #endif -#endif /* _DMA_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h index 6ece5a1ccfd..ff3389c449b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h @@ -1,10 +1,11 @@ /** * @file fcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FCR_REGS_H_ -#define _FCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup fcr * @defgroup fcr_registers FCR_Registers * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. - * @details Function Control. + * @details Function Control. */ /** @@ -91,10 +93,10 @@ typedef struct { /** * @ingroup fcr_registers * @defgroup FCR_Register_Offsets Register Offsets - * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. + * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. * @{ */ - #define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ +#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ /**@} end of group fcr_registers */ /** @@ -103,17 +105,17 @@ typedef struct { * @brief Register 0. * @{ */ - #define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */ - #define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */ +#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */ +#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */ - #define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */ - #define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */ +#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */ +#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */ - #define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */ - #define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */ +#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */ +#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */ - #define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */ - #define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */ +#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */ +#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */ /**@} end of group FCR_REG0_Register */ @@ -121,4 +123,4 @@ typedef struct { } #endif -#endif /* _FCR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h index f1f2d701dc8..18d474a7434 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h @@ -1,10 +1,11 @@ /** * @file flc_regs.h * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FLC_REGS_H_ -#define _FLC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup flc * @defgroup flc_registers FLC_Registers * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. - * @details Flash Memory Control. + * @details Flash Memory Control. */ /** @@ -87,9 +89,9 @@ typedef struct { __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ - __I uint32_t rsv_0xc_0x23[6]; + __R uint32_t rsv_0xc_0x23[6]; __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ - __I uint32_t rsv_0x28_0x2f[2]; + __R uint32_t rsv_0x28_0x2f[2]; __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ } mxc_flc_regs_t; @@ -98,15 +100,15 @@ typedef struct { /** * @ingroup flc_registers * @defgroup FLC_Register_Offsets Register Offsets - * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. * @{ */ - #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ - #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ - #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ - #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ - #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ - #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ +#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ +#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ +#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ +#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ +#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ /**@} end of group flc_registers */ /** @@ -115,8 +117,8 @@ typedef struct { * @brief Flash Write Address. * @{ */ - #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ - #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ +#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ /**@} end of group FLC_ADDR_Register */ @@ -127,8 +129,8 @@ typedef struct { * MHz clock for Flash controller. * @{ */ - #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ +#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ /**@} end of group FLC_CLKDIV_Register */ @@ -138,39 +140,39 @@ typedef struct { * @brief Flash Control Register. * @{ */ - #define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */ - #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */ +#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */ +#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */ - #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */ - #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */ +#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */ +#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */ - #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */ - #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */ +#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */ +#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */ - #define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */ - #define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */ +#define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */ +#define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */ - #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ - #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ - #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ - #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ - #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ - #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ - #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ - #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ - #define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */ - #define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ +#define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */ +#define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ - #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ - #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ +#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ - #define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */ - #define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */ - #define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */ - #define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */ - #define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */ - #define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */ +#define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */ +#define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */ +#define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */ +#define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */ /**@} end of group FLC_CTRL_Register */ @@ -180,17 +182,17 @@ typedef struct { * @brief Flash Interrupt Register. * @{ */ - #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ - #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ +#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ +#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ - #define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */ - #define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */ +#define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */ +#define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */ - #define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ - #define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ +#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ +#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ - #define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */ - #define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */ +#define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */ +#define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */ /**@} end of group FLC_INTR_Register */ @@ -200,8 +202,8 @@ typedef struct { * @brief Flash Write Data. * @{ */ - #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ /**@} end of group FLC_DATA_Register */ @@ -216,8 +218,8 @@ typedef struct { * this register is always zero. * @{ */ - #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ - #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ +#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ /**@} end of group FLC_ACTRL_Register */ @@ -225,4 +227,4 @@ typedef struct { } #endif -#endif /* _FLC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h index c85118ff3bf..d21a6d77a80 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h @@ -1,10 +1,11 @@ /** * @file gcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _GCR_REGS_H_ -#define _GCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup gcr * @defgroup gcr_registers GCR_Registers * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. - * @details Global Control Registers. + * @details Global Control Registers. */ /** @@ -88,11 +90,11 @@ typedef struct { __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ __IO uint32_t clk_ctrl; /**< \b 0x08: GCR CLK_CTRL Register */ __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ - __I uint32_t rsv_0x10_0x23[5]; + __R uint32_t rsv_0x10_0x23[5]; __IO uint32_t pclk_dis0; /**< \b 0x24: GCR PCLK_DIS0 Register */ __IO uint32_t mem_ctrl; /**< \b 0x28: GCR MEM_CTRL Register */ __IO uint32_t mem_zctrl; /**< \b 0x2C: GCR MEM_ZCTRL Register */ - __I uint32_t rsv_0x30_0x3f[4]; + __R uint32_t rsv_0x30_0x3f[4]; __IO uint32_t sys_stat; /**< \b 0x40: GCR SYS_STAT Register */ __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ __IO uint32_t pclk_dis1; /**< \b 0x48: GCR PCLK_DIS1 Register */ @@ -105,22 +107,22 @@ typedef struct { /** * @ingroup gcr_registers * @defgroup GCR_Register_Offsets Register Offsets - * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. * @{ */ - #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ - #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ - #define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ - #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ - #define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ - #define MXC_R_GCR_MEM_CTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ - #define MXC_R_GCR_MEM_ZCTRL ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ - #define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ - #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ - #define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ - #define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ - #define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ - #define MXC_R_GCR_SYS_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ +#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ +#define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ +#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ +#define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ +#define MXC_R_GCR_MEM_CTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ +#define MXC_R_GCR_MEM_ZCTRL ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ +#define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ +#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ +#define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ +#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ +#define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ +#define MXC_R_GCR_SYS_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ /**@} end of group gcr_registers */ /** @@ -129,17 +131,17 @@ typedef struct { * @brief System Control. * @{ */ - #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ - #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ +#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ +#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ - #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ - #define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ +#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ +#define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ - #define MXC_F_GCR_SCON_ICC0_FLUSH_POS 6 /**< SCON_ICC0_FLUSH Position */ - #define MXC_F_GCR_SCON_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) /**< SCON_ICC0_FLUSH Mask */ +#define MXC_F_GCR_SCON_ICC0_FLUSH_POS 6 /**< SCON_ICC0_FLUSH Position */ +#define MXC_F_GCR_SCON_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) /**< SCON_ICC0_FLUSH Mask */ - #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ - #define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ +#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ +#define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ /**@} end of group GCR_SCON_Register */ @@ -149,50 +151,50 @@ typedef struct { * @brief Reset. * @{ */ - #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ - #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ +#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ +#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ - #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ - #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ +#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ +#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ - #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ - #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ +#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ +#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ - #define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */ - #define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */ +#define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */ +#define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */ - #define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */ - #define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */ +#define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */ +#define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */ - #define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */ - #define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */ +#define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */ +#define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */ - #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ - #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ +#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ +#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ - #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ - #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ +#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ +#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ - #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ - #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ +#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ +#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ - #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ - #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ +#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ +#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ - #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ - #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ +#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ +#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ - #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ - #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ +#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ +#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ - #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ - #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ +#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ +#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ - #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ - #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ +#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ +#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ - #define MXC_F_GCR_RST0_SYSTEM_POS 31 /**< RST0_SYSTEM Position */ - #define MXC_F_GCR_RST0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) /**< RST0_SYSTEM Mask */ +#define MXC_F_GCR_RST0_SYSTEM_POS 31 /**< RST0_SYSTEM Position */ +#define MXC_F_GCR_RST0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) /**< RST0_SYSTEM Mask */ /**@} end of group GCR_RST0_Register */ @@ -202,51 +204,51 @@ typedef struct { * @brief Clock Control. * @{ */ - #define MXC_F_GCR_CLK_CTRL_PSC_POS 6 /**< CLK_CTRL_PSC Position */ - #define MXC_F_GCR_CLK_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) /**< CLK_CTRL_PSC Mask */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_PSC_DIV1 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV1 (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV1 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_PSC_DIV2 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV2 (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV2 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_PSC_DIV4 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV4 (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV4 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_PSC_DIV8 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV8 (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV8 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_PSC_DIV16 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV16 (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV16 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_PSC_DIV32 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV32 (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV32 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_PSC_DIV64 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV64 (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV64 Setting */ - #define MXC_V_GCR_CLK_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_PSC_DIV128 Value */ - #define MXC_S_GCR_CLK_CTRL_PSC_DIV128 (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV128 Setting */ - - #define MXC_F_GCR_CLK_CTRL_CLKSEL_POS 9 /**< CLK_CTRL_CLKSEL Position */ - #define MXC_F_GCR_CLK_CTRL_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) /**< CLK_CTRL_CLKSEL Mask */ - #define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLK_CTRL_CLKSEL_HIRC Value */ - #define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HIRC Setting */ - #define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_CLKSEL_NANORING Value */ - #define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_NANORING Setting */ - #define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLK_CTRL_CLKSEL_HFXIN Value */ - #define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HFXIN Setting */ - - #define MXC_F_GCR_CLK_CTRL_CLKRDY_POS 13 /**< CLK_CTRL_CLKRDY Position */ - #define MXC_F_GCR_CLK_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) /**< CLK_CTRL_CLKRDY Mask */ - - #define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */ - #define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */ - - #define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS 18 /**< CLK_CTRL_HIRC_EN Position */ - #define MXC_F_GCR_CLK_CTRL_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) /**< CLK_CTRL_HIRC_EN Mask */ - - #define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */ - #define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */ - - #define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS 26 /**< CLK_CTRL_HIRC_RDY Position */ - #define MXC_F_GCR_CLK_CTRL_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) /**< CLK_CTRL_HIRC_RDY Mask */ - - #define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 /**< CLK_CTRL_LIRC8K_RDY Position */ - #define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) /**< CLK_CTRL_LIRC8K_RDY Mask */ +#define MXC_F_GCR_CLK_CTRL_PSC_POS 6 /**< CLK_CTRL_PSC Position */ +#define MXC_F_GCR_CLK_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) /**< CLK_CTRL_PSC Mask */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_PSC_DIV1 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV1 (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV1 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_PSC_DIV2 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV2 (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV2 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_PSC_DIV4 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV4 (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV4 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_PSC_DIV8 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV8 (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV8 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_PSC_DIV16 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV16 (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV16 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_PSC_DIV32 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV32 (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV32 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_PSC_DIV64 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV64 (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV64 Setting */ +#define MXC_V_GCR_CLK_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_PSC_DIV128 Value */ +#define MXC_S_GCR_CLK_CTRL_PSC_DIV128 (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV128 Setting */ + +#define MXC_F_GCR_CLK_CTRL_CLKSEL_POS 9 /**< CLK_CTRL_CLKSEL Position */ +#define MXC_F_GCR_CLK_CTRL_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) /**< CLK_CTRL_CLKSEL Mask */ +#define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLK_CTRL_CLKSEL_HIRC Value */ +#define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HIRC Setting */ +#define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_CLKSEL_NANORING Value */ +#define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_NANORING Setting */ +#define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLK_CTRL_CLKSEL_HFXIN Value */ +#define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HFXIN Setting */ + +#define MXC_F_GCR_CLK_CTRL_CLKRDY_POS 13 /**< CLK_CTRL_CLKRDY Position */ +#define MXC_F_GCR_CLK_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) /**< CLK_CTRL_CLKRDY Mask */ + +#define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */ +#define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */ + +#define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS 18 /**< CLK_CTRL_HIRC_EN Position */ +#define MXC_F_GCR_CLK_CTRL_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) /**< CLK_CTRL_HIRC_EN Mask */ + +#define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */ +#define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */ + +#define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS 26 /**< CLK_CTRL_HIRC_RDY Position */ +#define MXC_F_GCR_CLK_CTRL_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) /**< CLK_CTRL_HIRC_RDY Mask */ + +#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 /**< CLK_CTRL_LIRC8K_RDY Position */ +#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) /**< CLK_CTRL_LIRC8K_RDY Mask */ /**@} end of group GCR_CLK_CTRL_Register */ @@ -256,23 +258,23 @@ typedef struct { * @brief Power Management. * @{ */ - #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ - #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ - #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ - #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ - #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ - #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ - #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ - #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ +#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ +#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ +#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ +#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ +#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ +#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ +#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ - #define MXC_F_GCR_PM_GPIOWK_EN_POS 4 /**< PM_GPIOWK_EN Position */ - #define MXC_F_GCR_PM_GPIOWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) /**< PM_GPIOWK_EN Mask */ +#define MXC_F_GCR_PM_GPIOWK_EN_POS 4 /**< PM_GPIOWK_EN Position */ +#define MXC_F_GCR_PM_GPIOWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) /**< PM_GPIOWK_EN Mask */ - #define MXC_F_GCR_PM_RTCWK_EN_POS 5 /**< PM_RTCWK_EN Position */ - #define MXC_F_GCR_PM_RTCWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) /**< PM_RTCWK_EN Mask */ +#define MXC_F_GCR_PM_RTCWK_EN_POS 5 /**< PM_RTCWK_EN Position */ +#define MXC_F_GCR_PM_RTCWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) /**< PM_RTCWK_EN Mask */ - #define MXC_F_GCR_PM_HFIOPD_POS 15 /**< PM_HFIOPD Position */ - #define MXC_F_GCR_PM_HFIOPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) /**< PM_HFIOPD Mask */ +#define MXC_F_GCR_PM_HFIOPD_POS 15 /**< PM_HFIOPD Position */ +#define MXC_F_GCR_PM_HFIOPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) /**< PM_HFIOPD Mask */ /**@} end of group GCR_PM_Register */ @@ -282,38 +284,38 @@ typedef struct { * @brief Peripheral Clock Disable. * @{ */ - #define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS 0 /**< PCLK_DIS0_GPIO0D Position */ - #define MXC_F_GCR_PCLK_DIS0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) /**< PCLK_DIS0_GPIO0D Mask */ +#define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS 0 /**< PCLK_DIS0_GPIO0D Position */ +#define MXC_F_GCR_PCLK_DIS0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) /**< PCLK_DIS0_GPIO0D Mask */ - #define MXC_F_GCR_PCLK_DIS0_DMAD_POS 5 /**< PCLK_DIS0_DMAD Position */ - #define MXC_F_GCR_PCLK_DIS0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) /**< PCLK_DIS0_DMAD Mask */ +#define MXC_F_GCR_PCLK_DIS0_DMAD_POS 5 /**< PCLK_DIS0_DMAD Position */ +#define MXC_F_GCR_PCLK_DIS0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) /**< PCLK_DIS0_DMAD Mask */ - #define MXC_F_GCR_PCLK_DIS0_SPI0D_POS 6 /**< PCLK_DIS0_SPI0D Position */ - #define MXC_F_GCR_PCLK_DIS0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) /**< PCLK_DIS0_SPI0D Mask */ +#define MXC_F_GCR_PCLK_DIS0_SPI0D_POS 6 /**< PCLK_DIS0_SPI0D Position */ +#define MXC_F_GCR_PCLK_DIS0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) /**< PCLK_DIS0_SPI0D Mask */ - #define MXC_F_GCR_PCLK_DIS0_SPI1D_POS 7 /**< PCLK_DIS0_SPI1D Position */ - #define MXC_F_GCR_PCLK_DIS0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) /**< PCLK_DIS0_SPI1D Mask */ +#define MXC_F_GCR_PCLK_DIS0_SPI1D_POS 7 /**< PCLK_DIS0_SPI1D Position */ +#define MXC_F_GCR_PCLK_DIS0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) /**< PCLK_DIS0_SPI1D Mask */ - #define MXC_F_GCR_PCLK_DIS0_UART0D_POS 9 /**< PCLK_DIS0_UART0D Position */ - #define MXC_F_GCR_PCLK_DIS0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) /**< PCLK_DIS0_UART0D Mask */ +#define MXC_F_GCR_PCLK_DIS0_UART0D_POS 9 /**< PCLK_DIS0_UART0D Position */ +#define MXC_F_GCR_PCLK_DIS0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) /**< PCLK_DIS0_UART0D Mask */ - #define MXC_F_GCR_PCLK_DIS0_UART1D_POS 10 /**< PCLK_DIS0_UART1D Position */ - #define MXC_F_GCR_PCLK_DIS0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) /**< PCLK_DIS0_UART1D Mask */ +#define MXC_F_GCR_PCLK_DIS0_UART1D_POS 10 /**< PCLK_DIS0_UART1D Position */ +#define MXC_F_GCR_PCLK_DIS0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) /**< PCLK_DIS0_UART1D Mask */ - #define MXC_F_GCR_PCLK_DIS0_I2C0D_POS 13 /**< PCLK_DIS0_I2C0D Position */ - #define MXC_F_GCR_PCLK_DIS0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) /**< PCLK_DIS0_I2C0D Mask */ +#define MXC_F_GCR_PCLK_DIS0_I2C0D_POS 13 /**< PCLK_DIS0_I2C0D Position */ +#define MXC_F_GCR_PCLK_DIS0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) /**< PCLK_DIS0_I2C0D Mask */ - #define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS 15 /**< PCLK_DIS0_TIMER0D Position */ - #define MXC_F_GCR_PCLK_DIS0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) /**< PCLK_DIS0_TIMER0D Mask */ +#define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS 15 /**< PCLK_DIS0_TIMER0D Position */ +#define MXC_F_GCR_PCLK_DIS0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) /**< PCLK_DIS0_TIMER0D Mask */ - #define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS 16 /**< PCLK_DIS0_TIMER1D Position */ - #define MXC_F_GCR_PCLK_DIS0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) /**< PCLK_DIS0_TIMER1D Mask */ +#define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS 16 /**< PCLK_DIS0_TIMER1D Position */ +#define MXC_F_GCR_PCLK_DIS0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) /**< PCLK_DIS0_TIMER1D Mask */ - #define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS 17 /**< PCLK_DIS0_TIMER2D Position */ - #define MXC_F_GCR_PCLK_DIS0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) /**< PCLK_DIS0_TIMER2D Mask */ +#define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS 17 /**< PCLK_DIS0_TIMER2D Position */ +#define MXC_F_GCR_PCLK_DIS0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) /**< PCLK_DIS0_TIMER2D Mask */ - #define MXC_F_GCR_PCLK_DIS0_I2C1D_POS 28 /**< PCLK_DIS0_I2C1D Position */ - #define MXC_F_GCR_PCLK_DIS0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) /**< PCLK_DIS0_I2C1D Mask */ +#define MXC_F_GCR_PCLK_DIS0_I2C1D_POS 28 /**< PCLK_DIS0_I2C1D Position */ +#define MXC_F_GCR_PCLK_DIS0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) /**< PCLK_DIS0_I2C1D Mask */ /**@} end of group GCR_PCLK_DIS0_Register */ @@ -323,23 +325,23 @@ typedef struct { * @brief Memory Clock Control Register. * @{ */ - #define MXC_F_GCR_MEM_CTRL_FWS_POS 0 /**< MEM_CTRL_FWS Position */ - #define MXC_F_GCR_MEM_CTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) /**< MEM_CTRL_FWS Mask */ +#define MXC_F_GCR_MEM_CTRL_FWS_POS 0 /**< MEM_CTRL_FWS Position */ +#define MXC_F_GCR_MEM_CTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) /**< MEM_CTRL_FWS Mask */ - #define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS 8 /**< MEM_CTRL_RAM0_LS Position */ - #define MXC_F_GCR_MEM_CTRL_RAM0_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) /**< MEM_CTRL_RAM0_LS Mask */ +#define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS 8 /**< MEM_CTRL_RAM0_LS Position */ +#define MXC_F_GCR_MEM_CTRL_RAM0_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) /**< MEM_CTRL_RAM0_LS Mask */ - #define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS 9 /**< MEM_CTRL_RAM1_LS Position */ - #define MXC_F_GCR_MEM_CTRL_RAM1_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) /**< MEM_CTRL_RAM1_LS Mask */ +#define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS 9 /**< MEM_CTRL_RAM1_LS Position */ +#define MXC_F_GCR_MEM_CTRL_RAM1_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) /**< MEM_CTRL_RAM1_LS Mask */ - #define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS 10 /**< MEM_CTRL_RAM2_LS Position */ - #define MXC_F_GCR_MEM_CTRL_RAM2_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) /**< MEM_CTRL_RAM2_LS Mask */ +#define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS 10 /**< MEM_CTRL_RAM2_LS Position */ +#define MXC_F_GCR_MEM_CTRL_RAM2_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) /**< MEM_CTRL_RAM2_LS Mask */ - #define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS 11 /**< MEM_CTRL_RAM3_LS Position */ - #define MXC_F_GCR_MEM_CTRL_RAM3_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) /**< MEM_CTRL_RAM3_LS Mask */ +#define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS 11 /**< MEM_CTRL_RAM3_LS Position */ +#define MXC_F_GCR_MEM_CTRL_RAM3_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) /**< MEM_CTRL_RAM3_LS Mask */ - #define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS 12 /**< MEM_CTRL_ICACHE_RET Position */ - #define MXC_F_GCR_MEM_CTRL_ICACHE_RET ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) /**< MEM_CTRL_ICACHE_RET Mask */ +#define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS 12 /**< MEM_CTRL_ICACHE_RET Position */ +#define MXC_F_GCR_MEM_CTRL_ICACHE_RET ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) /**< MEM_CTRL_ICACHE_RET Mask */ /**@} end of group GCR_MEM_CTRL_Register */ @@ -349,11 +351,11 @@ typedef struct { * @brief Memory Zeroize Control. * @{ */ - #define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS 0 /**< MEM_ZCTRL_SRAM_ZERO Position */ - #define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) /**< MEM_ZCTRL_SRAM_ZERO Mask */ +#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS 0 /**< MEM_ZCTRL_SRAM_ZERO Position */ +#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) /**< MEM_ZCTRL_SRAM_ZERO Mask */ - #define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS 1 /**< MEM_ZCTRL_ICACHE_ZERO Position */ - #define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) /**< MEM_ZCTRL_ICACHE_ZERO Mask */ +#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS 1 /**< MEM_ZCTRL_ICACHE_ZERO Position */ +#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) /**< MEM_ZCTRL_ICACHE_ZERO Mask */ /**@} end of group GCR_MEM_ZCTRL_Register */ @@ -363,8 +365,8 @@ typedef struct { * @brief System Status Register. * @{ */ - #define MXC_F_GCR_SYS_STAT_ICECLOCK_POS 0 /**< SYS_STAT_ICECLOCK Position */ - #define MXC_F_GCR_SYS_STAT_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) /**< SYS_STAT_ICECLOCK Mask */ +#define MXC_F_GCR_SYS_STAT_ICECLOCK_POS 0 /**< SYS_STAT_ICECLOCK Position */ +#define MXC_F_GCR_SYS_STAT_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) /**< SYS_STAT_ICECLOCK Mask */ /**@} end of group GCR_SYS_STAT_Register */ @@ -374,8 +376,8 @@ typedef struct { * @brief Reset 1. * @{ */ - #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ - #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ +#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ +#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ /**@} end of group GCR_RST1_Register */ @@ -385,11 +387,11 @@ typedef struct { * @brief Peripheral Clock Disable. * @{ */ - #define MXC_F_GCR_PCLK_DIS1_FLCD_POS 3 /**< PCLK_DIS1_FLCD Position */ - #define MXC_F_GCR_PCLK_DIS1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) /**< PCLK_DIS1_FLCD Mask */ +#define MXC_F_GCR_PCLK_DIS1_FLCD_POS 3 /**< PCLK_DIS1_FLCD Position */ +#define MXC_F_GCR_PCLK_DIS1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) /**< PCLK_DIS1_FLCD Mask */ - #define MXC_F_GCR_PCLK_DIS1_ICCD_POS 11 /**< PCLK_DIS1_ICCD Position */ - #define MXC_F_GCR_PCLK_DIS1_ICCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) /**< PCLK_DIS1_ICCD Mask */ +#define MXC_F_GCR_PCLK_DIS1_ICCD_POS 11 /**< PCLK_DIS1_ICCD Position */ +#define MXC_F_GCR_PCLK_DIS1_ICCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) /**< PCLK_DIS1_ICCD Mask */ /**@} end of group GCR_PCLK_DIS1_Register */ @@ -399,11 +401,11 @@ typedef struct { * @brief Event Enable Register. * @{ */ - #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ - #define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ +#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ +#define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ - #define MXC_F_GCR_EVTEN_RX_EVT_POS 1 /**< EVTEN_RX_EVT Position */ - #define MXC_F_GCR_EVTEN_RX_EVT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) /**< EVTEN_RX_EVT Mask */ +#define MXC_F_GCR_EVTEN_RX_EVT_POS 1 /**< EVTEN_RX_EVT Position */ +#define MXC_F_GCR_EVTEN_RX_EVT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) /**< EVTEN_RX_EVT Mask */ /**@} end of group GCR_EVTEN_Register */ @@ -413,8 +415,8 @@ typedef struct { * @brief Revision Register. * @{ */ - #define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */ - #define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */ +#define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */ +#define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */ /**@} end of group GCR_REV_Register */ @@ -424,8 +426,8 @@ typedef struct { * @brief System Status Interrupt Enable * @{ */ - #define MXC_F_GCR_SYS_IE_ICEULIE_POS 0 /**< SYS_IE_ICEULIE Position */ - #define MXC_F_GCR_SYS_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) /**< SYS_IE_ICEULIE Mask */ +#define MXC_F_GCR_SYS_IE_ICEULIE_POS 0 /**< SYS_IE_ICEULIE Position */ +#define MXC_F_GCR_SYS_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) /**< SYS_IE_ICEULIE Mask */ /**@} end of group GCR_SYS_IE_Register */ @@ -433,4 +435,4 @@ typedef struct { } #endif -#endif /* _GCR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h index 93db2513f4f..f791e4cfd43 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h @@ -1,10 +1,11 @@ /** * @file gpio_regs.h * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _GPIO_REGS_H_ -#define _GPIO_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup gpio * @defgroup gpio_registers GPIO_Registers * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. - * @details Individual I/O for each GPIO + * @details Individual I/O for each GPIO */ /** @@ -100,13 +102,13 @@ typedef struct { __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ - __IO uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ - __I uint32_t rsv_0x44; + __I uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ + __R uint32_t rsv_0x44; __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ - __I uint32_t rsv_0x58; + __R uint32_t rsv_0x58; __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ __IO uint32_t pad_cfg1; /**< \b 0x60: GPIO PAD_CFG1 Register */ __IO uint32_t pad_cfg2; /**< \b 0x64: GPIO PAD_CFG2 Register */ @@ -116,13 +118,13 @@ typedef struct { __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ - __I uint32_t rsv_0x80_0xa7[10]; + __R uint32_t rsv_0x80_0xa7[10]; __IO uint32_t is; /**< \b 0xA8: GPIO IS Register */ __IO uint32_t sr; /**< \b 0xAC: GPIO SR Register */ __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ - __I uint32_t rsv_0xbc; + __R uint32_t rsv_0xbc; __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ } mxc_gpio_regs_t; @@ -130,73 +132,73 @@ typedef struct { /** * @ingroup gpio_registers * @defgroup GPIO_Register_Offsets Register Offsets - * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. - * @{ - */ - #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ - #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ - #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ - #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ - #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ - #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ - #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ - #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ - #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ - #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ - #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ - #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ - #define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ - #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ - #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ - #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ - #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ - #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ - #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ - #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ - #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ - #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ - #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ - #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ - #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ - #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ - #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ - #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ - #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ - #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ - #define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ - #define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ - #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ - #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ - #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ - #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ +#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ +#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ +#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ +#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ +#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ +#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ +#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ +#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ +#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ +#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ +#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ +#define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ +#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ +#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ +#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ +#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ +#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ +#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ +#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ +#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ +#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ +#define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ +#define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ +#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ +#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ +#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ +#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ +#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ +#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ +#define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ +#define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ +#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ +#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ +#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ +#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ /**@} end of group gpio_registers */ /** * @ingroup gpio_registers * @defgroup GPIO_EN0 GPIO_EN0 - * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * @brief GPIO Function Enable 0 Register. Each bit controls the GPIO_EN setting for one * GPIO pin on the associated port. * @{ */ - #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ - #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ - #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ - #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ - #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ - #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ +#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ +#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ +#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ +#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ +#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ +#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ /**@} end of group GPIO_EN0_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_EN0_SET GPIO_EN0_SET - * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * @brief GPIO Set Function Enable 0 Register. Writing a 1 to one or more bits in this * register sets the bits in the same positions in GPIO_EN to 1, without affecting * other bits in that register. * @{ */ - #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ - #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ +#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ +#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ /**@} end of group GPIO_EN0_SET_Register */ @@ -208,8 +210,8 @@ typedef struct { * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ - #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ +#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ +#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ /**@} end of group GPIO_EN0_CLR_Register */ @@ -220,12 +222,12 @@ typedef struct { * GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ - #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ - #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ - #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ - #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ - #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ +#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ +#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ +#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ +#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ +#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ +#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ /**@} end of group GPIO_OUT_EN_Register */ @@ -237,8 +239,8 @@ typedef struct { * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ - #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ +#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ +#define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ /**@} end of group GPIO_OUT_EN_SET_Register */ @@ -250,8 +252,8 @@ typedef struct { * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ - #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ +#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ +#define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ /**@} end of group GPIO_OUT_EN_CLR_Register */ @@ -263,12 +265,12 @@ typedef struct { * GPIO_OUT_SET and GPIO_OUT_CLR registers. * @{ */ - #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ - #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ - #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ - #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ - #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ - #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ +#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ +#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ +#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ +#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ +#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ +#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ /**@} end of group GPIO_OUT_Register */ @@ -280,12 +282,12 @@ typedef struct { * register. * @{ */ - #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ - #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ - #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ - #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ - #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ - #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ /**@} end of group GPIO_OUT_SET_Register */ @@ -297,8 +299,8 @@ typedef struct { * that register. * @{ */ - #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ - #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ /**@} end of group GPIO_OUT_CLR_Register */ @@ -309,8 +311,8 @@ typedef struct { * GPIO pins on this port. * @{ */ - #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ - #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ +#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ +#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ /**@} end of group GPIO_IN_Register */ @@ -321,12 +323,12 @@ typedef struct { * mode setting for the associated GPIO pin on this port. * @{ */ - #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ - #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ - #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ - #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ - #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ - #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ +#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ +#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ +#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ +#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ +#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ +#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ /**@} end of group GPIO_INT_MOD_Register */ @@ -337,12 +339,12 @@ typedef struct { * interrupt polarity setting for one GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ - #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ - #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ - #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ - #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ - #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ +#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ +#define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ +#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ +#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ +#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ +#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ /**@} end of group GPIO_INT_POL_Register */ @@ -352,12 +354,12 @@ typedef struct { * @brief GPIO Port Input Enable. * @{ */ - #define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */ - #define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */ - #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */ - #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */ - #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */ - #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */ +#define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */ +#define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */ +#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */ +#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */ +#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */ +#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */ /**@} end of group GPIO_IN_EN_Register */ @@ -368,12 +370,12 @@ typedef struct { * interrupt enable for the associated pin on the GPIO port. * @{ */ - #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ - #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ - #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ - #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ - #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ - #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ +#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ +#define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ +#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ +#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ +#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ +#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ /**@} end of group GPIO_INT_EN_Register */ @@ -385,12 +387,12 @@ typedef struct { * in that register. * @{ */ - #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ - #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ - #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ - #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ - #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ - #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ +#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ +#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ +#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ +#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ +#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ +#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ /**@} end of group GPIO_INT_EN_SET_Register */ @@ -402,12 +404,12 @@ typedef struct { * other bits in that register. * @{ */ - #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ - #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ - #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ - #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ - #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ - #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ +#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ +#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ +#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ +#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ +#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ +#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ /**@} end of group GPIO_INT_EN_CLR_Register */ @@ -418,12 +420,12 @@ typedef struct { * interrupt status for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ - #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ - #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ - #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ - #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ - #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ +#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ +#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ +#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ +#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ +#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ +#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ /**@} end of group GPIO_INT_STAT_Register */ @@ -435,8 +437,8 @@ typedef struct { * in that register. * @{ */ - #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ - #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ +#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ +#define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ /**@} end of group GPIO_INT_CLR_Register */ @@ -447,12 +449,12 @@ typedef struct { * enable for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ - #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ - #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ - #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ - #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ - #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ +#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ +#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ +#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ +#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ +#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ +#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ /**@} end of group GPIO_WAKE_EN_Register */ @@ -464,8 +466,8 @@ typedef struct { * that register. * @{ */ - #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ - #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ +#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ +#define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ /**@} end of group GPIO_WAKE_EN_SET_Register */ @@ -477,8 +479,8 @@ typedef struct { * bits in that register. * @{ */ - #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ - #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ +#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ +#define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ /**@} end of group GPIO_WAKE_EN_CLR_Register */ @@ -489,12 +491,12 @@ typedef struct { * edge mode for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ - #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ - #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ - #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ - #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ - #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ +#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ +#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ +#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ +#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ +#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ +#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ /**@} end of group GPIO_INT_DUAL_EDGE_Register */ @@ -505,14 +507,14 @@ typedef struct { * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ - #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ - #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ - #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ - #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ - #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ - #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ - #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ +#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ +#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ +#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ +#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ +#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ /**@} end of group GPIO_PAD_CFG1_Register */ @@ -523,14 +525,14 @@ typedef struct { * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ - #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ - #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ - #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ - #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ - #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ - #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ - #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ +#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ +#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ +#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ +#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ +#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ /**@} end of group GPIO_PAD_CFG2_Register */ @@ -541,12 +543,12 @@ typedef struct { * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ - #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ - #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ - #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ - #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ - #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ +#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ +#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ +#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ +#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ +#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ +#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ /**@} end of group GPIO_EN1_Register */ @@ -558,8 +560,8 @@ typedef struct { * bits in that register. * @{ */ - #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ - #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ +#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ +#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ /**@} end of group GPIO_EN1_SET_Register */ @@ -571,8 +573,8 @@ typedef struct { * bits in that register. * @{ */ - #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ - #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ +#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ +#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ /**@} end of group GPIO_EN1_CLR_Register */ @@ -583,12 +585,12 @@ typedef struct { * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ - #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ - #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ - #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ - #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ - #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ +#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ +#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ +#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ +#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ +#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ +#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ /**@} end of group GPIO_EN2_Register */ @@ -600,8 +602,8 @@ typedef struct { * bits in that register. * @{ */ - #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ - #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ +#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ +#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ /**@} end of group GPIO_EN2_SET_Register */ @@ -613,11 +615,37 @@ typedef struct { * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ - #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ +#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ +#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ /**@} end of group GPIO_EN2_CLR_Register */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_IS GPIO_IS + * @brief GPIO Input Hysteresis Enable. + * @{ + */ +#define MXC_F_GPIO_IS_ALL_POS 0 /**< IS_ALL Position */ +#define MXC_F_GPIO_IS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IS_ALL_POS)) /**< IS_ALL Mask */ + +/**@} end of group GPIO_IS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_SR GPIO_SR + * @brief GPIO Slew Rate Enable Register. + * @{ + */ +#define MXC_F_GPIO_SR_ALL_POS 0 /**< SR_ALL Position */ +#define MXC_F_GPIO_SR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SR_ALL_POS)) /**< SR_ALL Mask */ +#define MXC_V_GPIO_SR_ALL_FAST ((uint32_t)0x0UL) /**< SR_ALL_FAST Value */ +#define MXC_S_GPIO_SR_ALL_FAST (MXC_V_GPIO_SR_ALL_FAST << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_FAST Setting */ +#define MXC_V_GPIO_SR_ALL_SLOW ((uint32_t)0x1UL) /**< SR_ALL_SLOW Value */ +#define MXC_S_GPIO_SR_ALL_SLOW (MXC_V_GPIO_SR_ALL_SLOW << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_SLOW Setting */ + +/**@} end of group GPIO_SR_Register */ + /** * @ingroup gpio_registers * @defgroup GPIO_DS0 GPIO_DS0 @@ -626,12 +654,12 @@ typedef struct { * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ - #define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ - #define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ - #define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ - #define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ - #define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ +#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ +#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ +#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ +#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ +#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ +#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ /**@} end of group GPIO_DS0_Register */ @@ -643,8 +671,8 @@ typedef struct { * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ - #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ +#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ +#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ /**@} end of group GPIO_DS1_Register */ @@ -654,8 +682,8 @@ typedef struct { * @brief GPIO Pull Select Mode. * @{ */ - #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ - #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ +#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ +#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ /**@} end of group GPIO_PS_Register */ @@ -665,8 +693,8 @@ typedef struct { * @brief GPIO Voltage Select. * @{ */ - #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ - #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ +#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ +#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ /**@} end of group GPIO_VSSEL_Register */ @@ -674,4 +702,4 @@ typedef struct { } #endif -#endif /* _GPIO_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h index e47b5550995..d370b74064d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h @@ -1,10 +1,11 @@ /** * @file i2c_regs.h * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _I2C_REGS_H_ -#define _I2C_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup i2c * @defgroup i2c_registers I2C_Registers * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. - * @details Inter-Integrated Circuit. + * @details Inter-Integrated Circuit. */ /** @@ -109,28 +111,28 @@ typedef struct { /** * @ingroup i2c_registers * @defgroup I2C_Register_Offsets Register Offsets - * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @{ */ - #define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ - #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ - #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ - #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ - #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ - #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ - #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ - #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ - #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ - #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ - #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ - #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ - #define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ - #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ - #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ - #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ - #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ - #define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ - #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ +#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ /**@} end of group i2c_registers */ /** @@ -139,47 +141,47 @@ typedef struct { * @brief Control Register0. * @{ */ - #define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */ - #define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */ +#define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */ +#define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */ - #define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */ - #define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */ +#define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */ +#define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */ - #define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */ - #define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */ +#define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */ +#define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */ - #define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */ - #define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */ +#define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */ +#define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */ - #define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */ - #define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */ +#define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */ +#define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */ - #define MXC_F_I2C_CTRL0_SCLO_POS 6 /**< CTRL0_SCLO Position */ - #define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) /**< CTRL0_SCLO Mask */ +#define MXC_F_I2C_CTRL0_SCLO_POS 6 /**< CTRL0_SCLO Position */ +#define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) /**< CTRL0_SCLO Mask */ - #define MXC_F_I2C_CTRL0_SDAO_POS 7 /**< CTRL0_SDAO Position */ - #define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) /**< CTRL0_SDAO Mask */ +#define MXC_F_I2C_CTRL0_SDAO_POS 7 /**< CTRL0_SDAO Position */ +#define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) /**< CTRL0_SDAO Mask */ - #define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */ - #define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */ +#define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */ +#define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */ - #define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */ - #define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */ +#define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */ +#define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */ - #define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */ - #define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */ +#define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */ +#define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */ - #define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */ - #define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */ +#define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */ +#define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */ - #define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */ - #define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */ +#define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */ +#define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */ - #define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */ - #define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */ +#define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */ +#define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */ - #define MXC_F_I2C_CTRL0_HSMODE_POS 15 /**< CTRL0_HSMODE Position */ - #define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) /**< CTRL0_HSMODE Mask */ +#define MXC_F_I2C_CTRL0_HSMODE_POS 15 /**< CTRL0_HSMODE Position */ +#define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) /**< CTRL0_HSMODE Mask */ /**@} end of group I2C_CTRL0_Register */ @@ -189,56 +191,56 @@ typedef struct { * @brief Status Register. * @{ */ - #define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - - #define MXC_F_I2C_STATUS_RXE_POS 1 /**< STATUS_RXE Position */ - #define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) /**< STATUS_RXE Mask */ - - #define MXC_F_I2C_STATUS_RXF_POS 2 /**< STATUS_RXF Position */ - #define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) /**< STATUS_RXF Mask */ - - #define MXC_F_I2C_STATUS_TXE_POS 3 /**< STATUS_TXE Position */ - #define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) /**< STATUS_TXE Mask */ - - #define MXC_F_I2C_STATUS_TXF_POS 4 /**< STATUS_TXF Position */ - #define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) /**< STATUS_TXF Mask */ - - #define MXC_F_I2C_STATUS_CKMD_POS 5 /**< STATUS_CKMD Position */ - #define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) /**< STATUS_CKMD Mask */ - - #define MXC_F_I2C_STATUS_STAT_POS 8 /**< STATUS_STAT Position */ - #define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) /**< STATUS_STAT Mask */ - #define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) /**< STATUS_STAT_IDLE Value */ - #define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_IDLE Setting */ - #define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STAT_MTX_ADDR Value */ - #define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_ADDR Setting */ - #define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STAT_MRX_ADDR_ACK Value */ - #define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_ADDR_ACK Setting */ - #define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STAT_MTX_EX_ADDR Value */ - #define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_EX_ADDR Setting */ - #define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STAT_MRX_EX_ADDR Value */ - #define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_EX_ADDR Setting */ - #define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STAT_SRX_ADDR Value */ - #define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_ADDR Setting */ - #define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STAT_STX_ADDR_ACK Value */ - #define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_ADDR_ACK Setting */ - #define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STAT_SRX_EX_ADDR Value */ - #define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_EX_ADDR Setting */ - #define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STAT_STX_EX_ADDR_ACK Value */ - #define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_EX_ADDR_ACK Setting */ - #define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) /**< STATUS_STAT_TX Value */ - #define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX Setting */ - #define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STAT_RX_ACK Value */ - #define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX_ACK Setting */ - #define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) /**< STATUS_STAT_RX Value */ - #define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX Setting */ - #define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STAT_TX_ACK Value */ - #define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX_ACK Setting */ - #define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) /**< STATUS_STAT_NACK Value */ - #define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_NACK Setting */ - #define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) /**< STATUS_STAT_BY_ST Value */ - #define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_BY_ST Setting */ +#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +#define MXC_F_I2C_STATUS_RXE_POS 1 /**< STATUS_RXE Position */ +#define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) /**< STATUS_RXE Mask */ + +#define MXC_F_I2C_STATUS_RXF_POS 2 /**< STATUS_RXF Position */ +#define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) /**< STATUS_RXF Mask */ + +#define MXC_F_I2C_STATUS_TXE_POS 3 /**< STATUS_TXE Position */ +#define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) /**< STATUS_TXE Mask */ + +#define MXC_F_I2C_STATUS_TXF_POS 4 /**< STATUS_TXF Position */ +#define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) /**< STATUS_TXF Mask */ + +#define MXC_F_I2C_STATUS_CKMD_POS 5 /**< STATUS_CKMD Position */ +#define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) /**< STATUS_CKMD Mask */ + +#define MXC_F_I2C_STATUS_STAT_POS 8 /**< STATUS_STAT Position */ +#define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) /**< STATUS_STAT Mask */ +#define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) /**< STATUS_STAT_IDLE Value */ +#define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_IDLE Setting */ +#define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STAT_MTX_ADDR Value */ +#define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_ADDR Setting */ +#define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STAT_MRX_ADDR_ACK Value */ +#define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_ADDR_ACK Setting */ +#define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STAT_MTX_EX_ADDR Value */ +#define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_EX_ADDR Setting */ +#define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STAT_MRX_EX_ADDR Value */ +#define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_EX_ADDR Setting */ +#define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STAT_SRX_ADDR Value */ +#define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_ADDR Setting */ +#define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STAT_STX_ADDR_ACK Value */ +#define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_ADDR_ACK Setting */ +#define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STAT_SRX_EX_ADDR Value */ +#define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_EX_ADDR Setting */ +#define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STAT_STX_EX_ADDR_ACK Value */ +#define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_EX_ADDR_ACK Setting */ +#define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) /**< STATUS_STAT_TX Value */ +#define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX Setting */ +#define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STAT_RX_ACK Value */ +#define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX_ACK Setting */ +#define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) /**< STATUS_STAT_RX Value */ +#define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX Setting */ +#define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STAT_TX_ACK Value */ +#define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX_ACK Setting */ +#define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) /**< STATUS_STAT_NACK Value */ +#define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_NACK Setting */ +#define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) /**< STATUS_STAT_BY_ST Value */ +#define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_BY_ST Setting */ /**@} end of group I2C_STATUS_Register */ @@ -248,53 +250,56 @@ typedef struct { * @brief Interrupt Status Register. * @{ */ - #define MXC_F_I2C_INTFL0_DONEI_POS 0 /**< INTFL0_DONEI Position */ - #define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) /**< INTFL0_DONEI Mask */ +#define MXC_F_I2C_INTFL0_DONEI_POS 0 /**< INTFL0_DONEI Position */ +#define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) /**< INTFL0_DONEI Mask */ - #define MXC_F_I2C_INTFL0_IRXMI_POS 1 /**< INTFL0_IRXMI Position */ - #define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) /**< INTFL0_IRXMI Mask */ +#define MXC_F_I2C_INTFL0_IRXMI_POS 1 /**< INTFL0_IRXMI Position */ +#define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) /**< INTFL0_IRXMI Mask */ - #define MXC_F_I2C_INTFL0_GCI_POS 2 /**< INTFL0_GCI Position */ - #define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) /**< INTFL0_GCI Mask */ +#define MXC_F_I2C_INTFL0_GCI_POS 2 /**< INTFL0_GCI Position */ +#define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) /**< INTFL0_GCI Mask */ - #define MXC_F_I2C_INTFL0_AMI_POS 3 /**< INTFL0_AMI Position */ - #define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) /**< INTFL0_AMI Mask */ +#define MXC_F_I2C_INTFL0_AMI_POS 3 /**< INTFL0_AMI Position */ +#define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) /**< INTFL0_AMI Mask */ - #define MXC_F_I2C_INTFL0_RXTHI_POS 4 /**< INTFL0_RXTHI Position */ - #define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) /**< INTFL0_RXTHI Mask */ +#define MXC_F_I2C_INTFL0_RXTHI_POS 4 /**< INTFL0_RXTHI Position */ +#define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) /**< INTFL0_RXTHI Mask */ - #define MXC_F_I2C_INTFL0_TXTHI_POS 5 /**< INTFL0_TXTHI Position */ - #define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) /**< INTFL0_TXTHI Mask */ +#define MXC_F_I2C_INTFL0_TXTHI_POS 5 /**< INTFL0_TXTHI Position */ +#define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) /**< INTFL0_TXTHI Mask */ - #define MXC_F_I2C_INTFL0_STOPI_POS 6 /**< INTFL0_STOPI Position */ - #define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) /**< INTFL0_STOPI Mask */ +#define MXC_F_I2C_INTFL0_STOPI_POS 6 /**< INTFL0_STOPI Position */ +#define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) /**< INTFL0_STOPI Mask */ - #define MXC_F_I2C_INTFL0_ADRACKI_POS 7 /**< INTFL0_ADRACKI Position */ - #define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) /**< INTFL0_ADRACKI Mask */ +#define MXC_F_I2C_INTFL0_ADRACKI_POS 7 /**< INTFL0_ADRACKI Position */ +#define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) /**< INTFL0_ADRACKI Mask */ - #define MXC_F_I2C_INTFL0_ARBERI_POS 8 /**< INTFL0_ARBERI Position */ - #define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) /**< INTFL0_ARBERI Mask */ +#define MXC_F_I2C_INTFL0_ARBERI_POS 8 /**< INTFL0_ARBERI Position */ +#define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) /**< INTFL0_ARBERI Mask */ - #define MXC_F_I2C_INTFL0_TOERI_POS 9 /**< INTFL0_TOERI Position */ - #define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) /**< INTFL0_TOERI Mask */ +#define MXC_F_I2C_INTFL0_TOERI_POS 9 /**< INTFL0_TOERI Position */ +#define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) /**< INTFL0_TOERI Mask */ - #define MXC_F_I2C_INTFL0_ADRERI_POS 10 /**< INTFL0_ADRERI Position */ - #define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) /**< INTFL0_ADRERI Mask */ +#define MXC_F_I2C_INTFL0_ADRERI_POS 10 /**< INTFL0_ADRERI Position */ +#define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) /**< INTFL0_ADRERI Mask */ - #define MXC_F_I2C_INTFL0_DATERI_POS 11 /**< INTFL0_DATERI Position */ - #define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) /**< INTFL0_DATERI Mask */ +#define MXC_F_I2C_INTFL0_DATERI_POS 11 /**< INTFL0_DATERI Position */ +#define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) /**< INTFL0_DATERI Mask */ - #define MXC_F_I2C_INTFL0_DNRERI_POS 12 /**< INTFL0_DNRERI Position */ - #define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) /**< INTFL0_DNRERI Mask */ +#define MXC_F_I2C_INTFL0_DNRERI_POS 12 /**< INTFL0_DNRERI Position */ +#define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) /**< INTFL0_DNRERI Mask */ - #define MXC_F_I2C_INTFL0_STRTERI_POS 13 /**< INTFL0_STRTERI Position */ - #define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) /**< INTFL0_STRTERI Mask */ +#define MXC_F_I2C_INTFL0_STRTERI_POS 13 /**< INTFL0_STRTERI Position */ +#define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) /**< INTFL0_STRTERI Mask */ - #define MXC_F_I2C_INTFL0_STOPERI_POS 14 /**< INTFL0_STOPERI Position */ - #define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) /**< INTFL0_STOPERI Mask */ +#define MXC_F_I2C_INTFL0_STOPERI_POS 14 /**< INTFL0_STOPERI Position */ +#define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) /**< INTFL0_STOPERI Mask */ - #define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */ - #define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */ +#define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */ +#define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */ + +#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0xFUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ /**@} end of group I2C_INTFL0_Register */ @@ -304,53 +309,56 @@ typedef struct { * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */ - #define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */ +#define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */ +#define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */ + +#define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */ +#define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */ - #define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */ - #define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */ +#define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */ +#define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */ - #define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */ - #define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */ +#define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */ +#define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */ - #define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */ - #define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */ +#define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */ +#define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */ - #define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */ - #define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */ +#define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */ +#define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */ - #define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */ - #define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */ +#define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */ +#define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */ - #define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */ - #define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */ +#define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */ +#define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */ - #define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */ - #define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */ +#define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */ +#define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */ - #define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */ - #define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */ +#define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */ +#define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */ - #define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */ - #define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */ +#define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */ +#define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */ - #define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */ - #define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */ +#define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */ +#define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */ - #define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */ - #define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */ +#define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */ +#define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */ - #define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */ - #define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */ +#define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */ +#define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */ - #define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */ - #define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */ +#define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */ +#define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */ - #define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */ - #define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */ +#define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */ +#define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */ - #define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */ - #define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */ +#define MXC_F_I2C_INTEN0_MAMIE_POS 16 /**< INTEN0_MAMIE Position */ +#define MXC_F_I2C_INTEN0_MAMIE ((uint32_t)(0xFUL << MXC_F_I2C_INTEN0_MAMIE_POS)) /**< INTEN0_MAMIE Mask */ /**@} end of group I2C_INTEN0_Register */ @@ -360,11 +368,11 @@ typedef struct { * @brief Interrupt Status Register 1. * @{ */ - #define MXC_F_I2C_INTFL1_RXOFI_POS 0 /**< INTFL1_RXOFI Position */ - #define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) /**< INTFL1_RXOFI Mask */ +#define MXC_F_I2C_INTFL1_RXOFI_POS 0 /**< INTFL1_RXOFI Position */ +#define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) /**< INTFL1_RXOFI Mask */ - #define MXC_F_I2C_INTFL1_TXUFI_POS 1 /**< INTFL1_TXUFI Position */ - #define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) /**< INTFL1_TXUFI Mask */ +#define MXC_F_I2C_INTFL1_TXUFI_POS 1 /**< INTFL1_TXUFI Position */ +#define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) /**< INTFL1_TXUFI Mask */ /**@} end of group I2C_INTFL1_Register */ @@ -374,11 +382,11 @@ typedef struct { * @brief Interrupt Staus Register 1. * @{ */ - #define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */ - #define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */ +#define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */ +#define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */ - #define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */ - #define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */ +#define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */ +#define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */ /**@} end of group I2C_INTEN1_Register */ @@ -388,11 +396,11 @@ typedef struct { * @brief FIFO Configuration Register. * @{ */ - #define MXC_F_I2C_FIFOLEN_RXLEN_POS 0 /**< FIFOLEN_RXLEN Position */ - #define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) /**< FIFOLEN_RXLEN Mask */ +#define MXC_F_I2C_FIFOLEN_RXLEN_POS 0 /**< FIFOLEN_RXLEN Position */ +#define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) /**< FIFOLEN_RXLEN Mask */ - #define MXC_F_I2C_FIFOLEN_TXLEN_POS 8 /**< FIFOLEN_TXLEN Position */ - #define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) /**< FIFOLEN_TXLEN Mask */ +#define MXC_F_I2C_FIFOLEN_TXLEN_POS 8 /**< FIFOLEN_TXLEN Position */ +#define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) /**< FIFOLEN_TXLEN Mask */ /**@} end of group I2C_FIFOLEN_Register */ @@ -402,14 +410,14 @@ typedef struct { * @brief Receive Control Register 0. * @{ */ - #define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ - #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ +#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - #define MXC_F_I2C_RXCTRL0_RXFSH_POS 7 /**< RXCTRL0_RXFSH Position */ - #define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) /**< RXCTRL0_RXFSH Mask */ +#define MXC_F_I2C_RXCTRL0_RXFSH_POS 7 /**< RXCTRL0_RXFSH Position */ +#define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) /**< RXCTRL0_RXFSH Mask */ - #define MXC_F_I2C_RXCTRL0_RXTH_POS 8 /**< RXCTRL0_RXTH Position */ - #define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) /**< RXCTRL0_RXTH Mask */ +#define MXC_F_I2C_RXCTRL0_RXTH_POS 8 /**< RXCTRL0_RXTH Position */ +#define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) /**< RXCTRL0_RXTH Mask */ /**@} end of group I2C_RXCTRL0_Register */ @@ -419,11 +427,11 @@ typedef struct { * @brief Receive Control Register 1. * @{ */ - #define MXC_F_I2C_RXCTRL1_RXCNT_POS 0 /**< RXCTRL1_RXCNT Position */ - #define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) /**< RXCTRL1_RXCNT Mask */ +#define MXC_F_I2C_RXCTRL1_RXCNT_POS 0 /**< RXCTRL1_RXCNT Position */ +#define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) /**< RXCTRL1_RXCNT Mask */ - #define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 /**< RXCTRL1_RXFIFO Position */ - #define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) /**< RXCTRL1_RXFIFO Mask */ +#define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 /**< RXCTRL1_RXFIFO Position */ +#define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) /**< RXCTRL1_RXFIFO Mask */ /**@} end of group I2C_RXCTRL1_Register */ @@ -433,17 +441,17 @@ typedef struct { * @brief Transmit Control Register 0. * @{ */ - #define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 /**< TXCTRL0_TXPRELD Position */ - #define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) /**< TXCTRL0_TXPRELD Mask */ +#define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 /**< TXCTRL0_TXPRELD Position */ +#define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) /**< TXCTRL0_TXPRELD Mask */ - #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ - #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ +#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - #define MXC_F_I2C_TXCTRL0_TXFSH_POS 7 /**< TXCTRL0_TXFSH Position */ - #define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) /**< TXCTRL0_TXFSH Mask */ +#define MXC_F_I2C_TXCTRL0_TXFSH_POS 7 /**< TXCTRL0_TXFSH Position */ +#define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) /**< TXCTRL0_TXFSH Mask */ - #define MXC_F_I2C_TXCTRL0_TXTH_POS 8 /**< TXCTRL0_TXTH Position */ - #define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) /**< TXCTRL0_TXTH Mask */ +#define MXC_F_I2C_TXCTRL0_TXTH_POS 8 /**< TXCTRL0_TXTH Position */ +#define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) /**< TXCTRL0_TXTH Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -453,23 +461,23 @@ typedef struct { * @brief Transmit Control Register 1. * @{ */ - #define MXC_F_I2C_TXCTRL1_TXRDY_POS 0 /**< TXCTRL1_TXRDY Position */ - #define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) /**< TXCTRL1_TXRDY Mask */ +#define MXC_F_I2C_TXCTRL1_TXRDY_POS 0 /**< TXCTRL1_TXRDY Position */ +#define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) /**< TXCTRL1_TXRDY Mask */ - #define MXC_F_I2C_TXCTRL1_TXLAST_POS 1 /**< TXCTRL1_TXLAST Position */ - #define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) /**< TXCTRL1_TXLAST Mask */ +#define MXC_F_I2C_TXCTRL1_TXLAST_POS 1 /**< TXCTRL1_TXLAST Position */ +#define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) /**< TXCTRL1_TXLAST Mask */ - #define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 /**< TXCTRL1_FLSH_GCADDR_DIS Position */ - #define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) /**< TXCTRL1_FLSH_GCADDR_DIS Mask */ +#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 /**< TXCTRL1_FLSH_GCADDR_DIS Position */ +#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) /**< TXCTRL1_FLSH_GCADDR_DIS Mask */ - #define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 /**< TXCTRL1_FLSH_SLADDR_DIS Position */ - #define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) /**< TXCTRL1_FLSH_SLADDR_DIS Mask */ +#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 /**< TXCTRL1_FLSH_SLADDR_DIS Position */ +#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) /**< TXCTRL1_FLSH_SLADDR_DIS Mask */ - #define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 /**< TXCTRL1_FLSH_NACK_DIS Position */ - #define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) /**< TXCTRL1_FLSH_NACK_DIS Mask */ +#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 /**< TXCTRL1_FLSH_NACK_DIS Position */ +#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) /**< TXCTRL1_FLSH_NACK_DIS Mask */ - #define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 /**< TXCTRL1_TXFIFO Position */ - #define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) /**< TXCTRL1_TXFIFO Mask */ +#define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 /**< TXCTRL1_TXFIFO Position */ +#define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) /**< TXCTRL1_TXFIFO Mask */ /**@} end of group I2C_TXCTRL1_Register */ @@ -479,8 +487,8 @@ typedef struct { * @brief Data Register. * @{ */ - #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group I2C_FIFO_Register */ @@ -490,17 +498,17 @@ typedef struct { * @brief Master Control Register. * @{ */ - #define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */ - #define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */ +#define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */ +#define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */ - #define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */ - #define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */ +#define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */ +#define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */ - #define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */ - #define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */ +#define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */ +#define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */ - #define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */ - #define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */ +#define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */ +#define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */ /**@} end of group I2C_MSTR_MODE_Register */ @@ -510,8 +518,8 @@ typedef struct { * @brief Clock Low Register. * @{ */ - #define MXC_F_I2C_CLKLO_SCL_LO_POS 0 /**< CLKLO_SCL_LO Position */ - #define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) /**< CLKLO_SCL_LO Mask */ +#define MXC_F_I2C_CLKLO_SCL_LO_POS 0 /**< CLKLO_SCL_LO Position */ +#define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) /**< CLKLO_SCL_LO Mask */ /**@} end of group I2C_CLKLO_Register */ @@ -521,8 +529,8 @@ typedef struct { * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_CLKHI_SCL_HI_POS 0 /**< CLKHI_SCL_HI Position */ - #define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) /**< CLKHI_SCL_HI Mask */ +#define MXC_F_I2C_CLKHI_SCL_HI_POS 0 /**< CLKHI_SCL_HI Position */ +#define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) /**< CLKHI_SCL_HI Mask */ /**@} end of group I2C_CLKHI_Register */ @@ -532,11 +540,11 @@ typedef struct { * @brief HS-Mode Clock Control Register * @{ */ - #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ - #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ +#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ +#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ - #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ - #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ +#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ +#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ /**@} end of group I2C_HS_CLK_Register */ @@ -546,8 +554,8 @@ typedef struct { * @brief Timeout Register * @{ */ - #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ - #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ +#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ +#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ /**@} end of group I2C_TIMEOUT_Register */ @@ -557,11 +565,17 @@ typedef struct { * @brief Slave Address Register. * @{ */ - #define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */ - #define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */ +#define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */ +#define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */ + +#define MXC_F_I2C_SLADDR_SLADIS_POS 10 /**< SLADDR_SLADIS Position */ +#define MXC_F_I2C_SLADDR_SLADIS ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_SLADIS_POS)) /**< SLADDR_SLADIS Mask */ + +#define MXC_F_I2C_SLADDR_SLAIDX_POS 11 /**< SLADDR_SLAIDX Position */ +#define MXC_F_I2C_SLADDR_SLAIDX ((uint32_t)(0xFUL << MXC_F_I2C_SLADDR_SLAIDX_POS)) /**< SLADDR_SLAIDX Mask */ - #define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */ - #define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */ +#define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */ +#define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */ /**@} end of group I2C_SLADDR_Register */ @@ -571,11 +585,11 @@ typedef struct { * @brief DMA Register. * @{ */ - #define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */ - #define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ +#define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */ +#define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ - #define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */ - #define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ +#define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */ +#define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ /**@} end of group I2C_DMA_Register */ @@ -583,4 +597,4 @@ typedef struct { } #endif -#endif /* _I2C_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h index 4a929955678..3ef38ffa969 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h @@ -1,10 +1,11 @@ /** * @file icc_regs.h * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _ICC_REGS_H_ -#define _ICC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup icc * @defgroup icc_registers ICC_Registers * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. - * @details Instruction Cache Controller Registers + * @details Instruction Cache Controller Registers */ /** @@ -86,9 +88,9 @@ extern "C" { typedef struct { __I uint32_t cache_id; /**< \b 0x0000: ICC CACHE_ID Register */ __I uint32_t mem_size; /**< \b 0x0004: ICC MEM_SIZE Register */ - __I uint32_t rsv_0x8_0xff[62]; + __R uint32_t rsv_0x8_0xff[62]; __IO uint32_t cache_ctrl; /**< \b 0x0100: ICC CACHE_CTRL Register */ - __I uint32_t rsv_0x104_0x6ff[383]; + __R uint32_t rsv_0x104_0x6ff[383]; __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ } mxc_icc_regs_t; @@ -96,13 +98,13 @@ typedef struct { /** * @ingroup icc_registers * @defgroup ICC_Register_Offsets Register Offsets - * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. * @{ */ - #define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ - #define MXC_R_ICC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ - #define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ - #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ +#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ +#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ /**@} end of group icc_registers */ /** @@ -111,14 +113,14 @@ typedef struct { * @brief Cache ID Register. * @{ */ - #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ - #define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ +#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ +#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ - #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ - #define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ +#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ +#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ - #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ - #define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ +#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ +#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ /**@} end of group ICC_CACHE_ID_Register */ @@ -128,11 +130,11 @@ typedef struct { * @brief Memory Configuration Register. * @{ */ - #define MXC_F_ICC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */ - #define MXC_F_ICC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */ +#define MXC_F_ICC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */ +#define MXC_F_ICC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */ - #define MXC_F_ICC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */ - #define MXC_F_ICC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */ +#define MXC_F_ICC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */ +#define MXC_F_ICC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */ /**@} end of group ICC_MEM_SIZE_Register */ @@ -142,11 +144,11 @@ typedef struct { * @brief Cache Control and Status Register. * @{ */ - #define MXC_F_ICC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */ - #define MXC_F_ICC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */ +#define MXC_F_ICC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */ +#define MXC_F_ICC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */ - #define MXC_F_ICC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */ - #define MXC_F_ICC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */ +#define MXC_F_ICC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */ +#define MXC_F_ICC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */ /**@} end of group ICC_CACHE_CTRL_Register */ @@ -154,4 +156,4 @@ typedef struct { } #endif -#endif /* _ICC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h index 14431a40b38..533cbcc8afd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h @@ -3,8 +3,8 @@ * @brief Device-specific perhiperal header file */ -/******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,36 +34,35 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * ******************************************************************************/ -#ifndef _MAX32660_REGS_H_ -#define _MAX32660_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ #ifndef TARGET_NUM -#define TARGET_NUM 32660 +#define TARGET_NUM 32660 #endif #include -#ifndef FALSE -#define FALSE (0) +#ifndef FALSE +#define FALSE (0) #endif -#ifndef TRUE -#define TRUE (1) +#ifndef TRUE +#define TRUE (1) #endif -#if !defined (__GNUC__) +#if !defined(__GNUC__) #define CMSIS_VECTAB_VIRTUAL #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" #endif /* !__GNUC__ */ /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ -#if defined ( __GNUC__ ) /* GCC */ +#if defined(__GNUC__) /* GCC */ #define __weak __attribute__((weak)) -#elif defined ( __CC_ARM) /* Keil */ +#elif defined(__CC_ARM) /* Keil */ #define inline __inline #pragma anon_unions @@ -71,15 +70,15 @@ #endif typedef enum { - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, /* Device-specific interrupt sources (external to ARM core) */ /* table entry number */ @@ -87,93 +86,91 @@ typedef enum { /* |||| table offset address */ /* vvvv vvvvvv */ - PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ - WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ - RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */ - RTC_IRQn, /* 0x13 0x004C 19: RTC */ - RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */ - TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ - TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ - TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ - RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */ - RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */ - RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */ - RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */ - RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */ - I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ - UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ - UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ - SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */ - SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */ - RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */ - RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */ - RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */ - RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */ - RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */ - FLC_IRQn, /* 0x27 0x009C 39: FLC */ - GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ - RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */ - RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */ - RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */ - DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ - DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ - DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ - DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ - RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */ - RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */ - RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */ - RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */ - I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ - RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */ - RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */ - RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */ - RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */ - RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */ - RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */ - RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */ - RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */ - RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */ - RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */ - RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */ - RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */ - RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */ - RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */ - RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */ - RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */ - RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */ - GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ + PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ + WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ + RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */ + RTC_IRQn, /* 0x13 0x004C 19: RTC */ + RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */ + TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ + TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ + TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ + RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */ + RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */ + RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */ + RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */ + RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */ + I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ + UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ + UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ + SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */ + SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */ + RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */ + RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */ + RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */ + RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */ + RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */ + FLC_IRQn, /* 0x27 0x009C 39: FLC */ + GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ + RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */ + RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */ + RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */ + DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ + DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ + DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ + DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ + RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */ + RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */ + RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */ + RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */ + I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ + RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */ + RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */ + RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */ + RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */ + RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */ + RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */ + RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */ + RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */ + RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */ + RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */ + RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */ + RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */ + RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */ + RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */ + RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */ + RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */ + RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */ + GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ MXC_IRQ_EXT_COUNT, } IRQn_Type; #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) - /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ -#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ - -#include /*!< Cortex-M4 processor and core peripherals */ -#include "system_max32660.h" /*!< System Header */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_max32660.h" /*!< System Header */ /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ /* ================================================================================ */ -#define MXC_FLASH_MEM_BASE 0x00000000UL -#define MXC_FLASH_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_MEM_SIZE 0x00040000UL -#define MXC_INFO_MEM_BASE 0x00040000UL -#define MXC_INFO_MEM_SIZE 0x00001000UL -#define MXC_SRAM_MEM_BASE 0x20000000UL -#define MXC_SRAM_MEM_SIZE 0x00018000UL +#define MXC_FLASH_MEM_BASE 0x00000000UL +#define MXC_FLASH_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_MEM_SIZE 0x00040000UL +#define MXC_INFO_MEM_BASE 0x00040000UL +#define MXC_INFO_MEM_SIZE 0x00001000UL +#define MXC_SRAM_MEM_BASE 0x20000000UL +#define MXC_SRAM_MEM_SIZE 0x00018000UL /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ @@ -185,224 +182,209 @@ typedef enum { /******************************************************************************/ /* Global control */ -#define MXC_BASE_GCR ((uint32_t)0x40000000UL) -#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR) +#define MXC_BASE_GCR ((uint32_t)0x40000000UL) +#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) /******************************************************************************/ /* Non-battery backed SI Registers */ -#define MXC_BASE_SIR ((uint32_t)0x40000400UL) -#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR) +#define MXC_BASE_SIR ((uint32_t)0x40000400UL) +#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) /******************************************************************************/ /* Watchdog */ -#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) -#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0) +#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) /******************************************************************************/ /* Real Time Clock */ -#define MXC_BASE_RTC ((uint32_t)0x40006000UL) -#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC) +#define MXC_BASE_RTC ((uint32_t)0x40006000UL) +#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) /******************************************************************************/ /* Power Sequencer */ -#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) -#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ) - +#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) /******************************************************************************/ /* GPIO */ -#define MXC_CFG_GPIO_INSTANCES (1) -#define MXC_CFG_GPIO_PINS_PORT (14) +#define MXC_CFG_GPIO_INSTANCES (1) +#define MXC_CFG_GPIO_PINS_PORT (14) -#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) -#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0) +#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) +#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) -#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1) +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1) -#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) -#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) /******************************************************************************/ /* Timer */ -#define MXC_CFG_TMR_INSTANCES (3) +#define SEC(s) (((uint32_t)s) * 1000000UL) +#define MSEC(ms) (ms * 1000UL) +#define USEC(us) (us) + +#define MXC_CFG_TMR_INSTANCES (3) -#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) -#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0) -#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) -#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1) -#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) -#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2) +#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) +#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) +#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) -#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ - (i) == 1 ? TMR1_IRQn : \ - (i) == 2 ? TMR2_IRQn : 0) +#define MXC_TMR_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? TMR0_IRQn : (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0) -#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ - (i) == 1 ? MXC_BASE_TMR1 : \ - (i) == 2 ? MXC_BASE_TMR2 : 0) +#define MXC_TMR_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0 : (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0) -#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ - (i) == 1 ? MXC_TMR1 : \ - (i) == 2 ? MXC_TMR2 : 0) +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0) -#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ - (p) == MXC_TMR1 ? 1 : \ - (p) == MXC_TMR2 ? 2 : -1) +#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1) /******************************************************************************/ /* SPIMSS */ +#define MXC_SPIMSS_INSTANCES (1) +#define MXC_SPIMSS_FIFO_DEPTH (8) -#define MXC_SPIMSS_INSTANCES (1) -#define MXC_SPIMSS_FIFO_DEPTH (8) +#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL) +#define MXC_SPIMSS ((mxc_spimss_regs_t *)MXC_BASE_SPIMSS) -#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL) -#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS) - -#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1) -#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0) +#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1) +#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0) /******************************************************************************/ /* I2C */ -#define MXC_I2C_INSTANCES (2) -#define MXC_I2C_FIFO_DEPTH (8) +#define MXC_I2C_INSTANCES (2) +#define MXC_I2C_FIFO_DEPTH (8) -#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) -#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0) -#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) -#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1) +#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) +#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) +#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) +#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) -#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \ - (i) == 1 ? I2C1_IRQn : 0) +#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0) -#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \ - (i) == 1 ? MXC_BASE_I2C1 : 0) +#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0) -#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \ - (i) == 1 ? MXC_I2C1 : 0) +#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0) -#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \ - (p) == MXC_I2C1 ? 1 : -1) +#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1) /******************************************************************************/ /* DMA */ -#define MXC_DMA_CHANNELS (4) -#define MXC_DMA_INSTANCES (1) +#define MXC_DMA_CHANNELS (4) +#define MXC_DMA_INSTANCES (1) -#define MXC_BASE_DMA ((uint32_t)0x40028000UL) -#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA) +#define MXC_BASE_DMA ((uint32_t)0x40028000UL) +#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) -#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) /******************************************************************************/ /* FLC */ -#define MXC_FLC_INSTANCES (1) +#define MXC_FLC_INSTANCES (1) -#define MXC_BASE_FLC ((uint32_t)0x40029000UL) -#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC) +#define MXC_BASE_FLC ((uint32_t)0x40029000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) +#define MXC_FLC0 MXC_FLC -#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) /******************************************************************************/ /* Instruction Cache */ -#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) -#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC) +#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) /******************************************************************************/ /* UART / Serial Port Interface */ +#define MXC_UART_INSTANCES (2) +#define MXC_UART_FIFO_DEPTH (8) -#define MXC_UART_INSTANCES (2) -#define MXC_UART_FIFO_DEPTH (8) - -#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) -#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0) -#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) -#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1) +#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) +#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) +#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) +#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) -#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ - (i) == 1 ? UART1_IRQn : 0) +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0) -#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ - (i) == 1 ? MXC_BASE_UART1 : 0) +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0) -#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ - (i) == 1 ? MXC_UART1 : 0) +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0) -#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ - (p) == MXC_UART1 ? 1 : -1) +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1) /******************************************************************************/ /* SPI */ -#include "spi_regs.h" - -#define MXC_SPI_INSTANCES (1) -#define MXC_SPI_SS_INSTANCES (1) -#define MXC_SPI_FIFO_DEPTH (32) +#define MXC_SPI_INSTANCES (1) +#define MXC_SPI_SS_INSTANCES (1) +#define MXC_SPI_FIFO_DEPTH (32) -#define MXC_BASE_SPI ((uint32_t)0x40046000UL) -#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI) +#define MXC_BASE_SPI ((uint32_t)0x40046000UL) +#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI) -#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1) +#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1) -#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) -#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0) +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0) /******************************************************************************/ /* Bit Shifting */ - -#define MXC_F_BIT_0 (1 << 0) -#define MXC_F_BIT_1 (1 << 1) -#define MXC_F_BIT_2 (1 << 2) -#define MXC_F_BIT_3 (1 << 3) -#define MXC_F_BIT_4 (1 << 4) -#define MXC_F_BIT_5 (1 << 5) -#define MXC_F_BIT_6 (1 << 6) -#define MXC_F_BIT_7 (1 << 7) -#define MXC_F_BIT_8 (1 << 8) -#define MXC_F_BIT_9 (1 << 9) -#define MXC_F_BIT_10 (1 << 10) -#define MXC_F_BIT_11 (1 << 11) -#define MXC_F_BIT_12 (1 << 12) -#define MXC_F_BIT_13 (1 << 13) -#define MXC_F_BIT_14 (1 << 14) -#define MXC_F_BIT_15 (1 << 15) -#define MXC_F_BIT_16 (1 << 16) -#define MXC_F_BIT_17 (1 << 17) -#define MXC_F_BIT_18 (1 << 18) -#define MXC_F_BIT_19 (1 << 19) -#define MXC_F_BIT_20 (1 << 20) -#define MXC_F_BIT_21 (1 << 21) -#define MXC_F_BIT_22 (1 << 22) -#define MXC_F_BIT_23 (1 << 23) -#define MXC_F_BIT_24 (1 << 24) -#define MXC_F_BIT_25 (1 << 25) -#define MXC_F_BIT_26 (1 << 26) -#define MXC_F_BIT_27 (1 << 27) -#define MXC_F_BIT_28 (1 << 28) -#define MXC_F_BIT_29 (1 << 29) -#define MXC_F_BIT_30 (1 << 30) -#define MXC_F_BIT_31 (1 << 31) +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) /******************************************************************************/ /* Bit Banding */ +#define BITBAND(reg, bit) \ + ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ + ((bit) << 2)) -#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ - (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) - -#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) -#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) -#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) -#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask)) +#define MXC_SETFIELD(reg, mask, value) ((reg) = ((reg) & ~(mask)) | ((value) & (mask))) /******************************************************************************/ /* SCB CPACR */ /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ -#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ -#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ -#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ -#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ -#endif /* _MAX32660_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h index 3fa8f797f52..95dbebaa069 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h @@ -1,10 +1,11 @@ /** * @file pwrseq_regs.h * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _PWRSEQ_REGS_H_ -#define _PWRSEQ_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup pwrseq * @defgroup pwrseq_registers PWRSEQ_Registers * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. - * @details Power Sequencer / Low Power Control Register. + * @details Power Sequencer / Low Power Control Register. */ /** @@ -87,7 +89,7 @@ typedef struct { __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ - __I uint32_t rsv_0xc_0x3f[13]; + __R uint32_t rsv_0xc_0x3f[13]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ } mxc_pwrseq_regs_t; @@ -95,13 +97,13 @@ typedef struct { /** * @ingroup pwrseq_registers * @defgroup PWRSEQ_Register_Offsets Register Offsets - * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. * @{ */ - #define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ - #define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ - #define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ - #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +#define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ +#define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ +#define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ +#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ /**@} end of group pwrseq_registers */ /** @@ -110,50 +112,50 @@ typedef struct { * @brief Low Power Control Register. * @{ */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */ - #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ - #define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ - #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ - #define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ - #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ - #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ - #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ - #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ +#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ +#define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ - #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ - #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */ - #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */ +#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */ - #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */ +#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ - #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ +#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */ - #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */ - #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */ +#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ - #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */ - #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ - #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */ +#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ +#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */ /**@} end of group PWRSEQ_LP_CTRL_Register */ @@ -163,8 +165,8 @@ typedef struct { * @brief Low Power Mode Wakeup Flags for GPIO0 * @{ */ - #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ - #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */ +#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ +#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */ /**@} end of group PWRSEQ_LP_WAKEFL_Register */ @@ -175,8 +177,8 @@ typedef struct { * functionality for GPIO0. * @{ */ - #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ - #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */ +#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ +#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */ /**@} end of group PWRSEQ_LPWK_EN_Register */ @@ -186,17 +188,17 @@ typedef struct { * @brief Low Power Memory Shutdown Control. * @{ */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */ - #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */ /**@} end of group PWRSEQ_LPMEMSD_Register */ @@ -204,4 +206,4 @@ typedef struct { } #endif -#endif /* _PWRSEQ_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h index f6fb132dccf..215c9156e4d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h @@ -1,10 +1,11 @@ /** * @file rtc_regs.h * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _RTC_REGS_H_ -#define _RTC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -78,7 +78,7 @@ extern "C" { * @ingroup rtc * @defgroup rtc_registers RTC_Registers * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. - * @details Real Time Clock and Alarm. + * @details Real Time Clock and Alarm. */ /** @@ -99,16 +99,16 @@ typedef struct { /** * @ingroup rtc_registers * @defgroup RTC_Register_Offsets Register Offsets - * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. * @{ */ - #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ - #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ - #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ - #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ - #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ - #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ - #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ +#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ +#define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ +#define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ +#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ +#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ +#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ /**@} end of group rtc_registers */ /** @@ -118,8 +118,8 @@ typedef struct { * when this register rolls over from 0xFF to 0x00. * @{ */ - #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ - #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ +#define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ +#define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ /**@} end of group RTC_SSEC_Register */ @@ -129,8 +129,8 @@ typedef struct { * @brief Time-of-day Alarm. * @{ */ - #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ - #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ +#define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ +#define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ /**@} end of group RTC_RAS_Register */ @@ -141,8 +141,8 @@ typedef struct { * second alarm. * @{ */ - #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ - #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ +#define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ +#define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ /**@} end of group RTC_RSSA_Register */ @@ -152,57 +152,57 @@ typedef struct { * @brief RTC Control Register. * @{ */ - #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ - #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ - - #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ - #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ - - #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ - #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ - - #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ - #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ - - #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ - #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ - - #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ - #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ - - #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ - #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ - - #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ - #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ - - #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ - #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ - - #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ - #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ - #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ - #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ - #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ - #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ - #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ - #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ - #define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ - #define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ - - #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ - #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ - #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ - #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ - #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ - #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ - #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ - #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ - #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ - #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ - - #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ - #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ +#define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ +#define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ + +#define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ +#define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ + +#define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ +#define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ + +#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ +#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + +#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ +#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +#define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ +#define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ + +#define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ +#define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ + +#define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ +#define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ + +#define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ +#define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ + +#define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ +#define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ +#define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ +#define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ +#define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ +#define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ +#define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ +#define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ +#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ +#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ + +#define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ +#define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ +#define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ +#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ +#define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ +#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ +#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ +#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ +#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ +#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ + +#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ +#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ /**@} end of group RTC_CTRL_Register */ @@ -212,11 +212,11 @@ typedef struct { * @brief RTC Trim Register. * @{ */ - #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ - #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ +#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ +#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ - #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ - #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ +#define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ +#define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ /**@} end of group RTC_TRIM_Register */ @@ -226,23 +226,23 @@ typedef struct { * @brief RTC Oscillator Control Register. * @{ */ - #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ - #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ +#define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ +#define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ - #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ - #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ +#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ +#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ - #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ - #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ +#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ +#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ - #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ - #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ +#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ +#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ - #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ - #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ +#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ +#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ - #define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ - #define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ +#define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ +#define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ /**@} end of group RTC_OSCCTRL_Register */ @@ -250,4 +250,4 @@ typedef struct { } #endif -#endif /* _RTC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h index 2eb73735908..f3be1972e06 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h @@ -1,10 +1,11 @@ /** * @file sir_regs.h * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _SIR_REGS_H_ -#define _SIR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -78,7 +78,7 @@ extern "C" { * @ingroup sir * @defgroup sir_registers SIR_Registers * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. - * @details System Initialization Registers. + * @details System Initialization Registers. */ /** @@ -94,11 +94,11 @@ typedef struct { /** * @ingroup sir_registers * @defgroup SIR_Register_Offsets Register Offsets - * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. * @{ */ - #define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ - #define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ +#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ /**@} end of group sir_registers */ /** @@ -107,11 +107,11 @@ typedef struct { * @brief System Initialization Status Register. * @{ */ - #define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */ - #define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */ +#define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */ +#define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */ - #define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */ - #define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */ +#define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */ +#define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */ /**@} end of group SIR_STATUS_Register */ @@ -123,8 +123,8 @@ typedef struct { * 1). * @{ */ - #define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ - #define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ +#define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ /**@} end of group SIR_ADDR_Register */ @@ -132,4 +132,4 @@ typedef struct { } #endif -#endif /* _SIR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h index e45ef62e6ea..35f8aec9842 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h @@ -1,10 +1,11 @@ /** * @file spi_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _SPI_REGS_H_ -#define _SPI_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup spi * @defgroup spi_registers SPI_Registers * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. - * @details SPI peripheral. + * @details SPI peripheral. */ /** @@ -90,7 +92,7 @@ typedef struct { __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ __IO uint32_t ss_time; /**< \b 0x10: SPI SS_TIME Register */ __IO uint32_t clk_cfg; /**< \b 0x14: SPI CLK_CFG Register */ - __I uint32_t rsv_0x18; + __R uint32_t rsv_0x18; __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ __IO uint32_t int_fl; /**< \b 0x20: SPI INT_FL Register */ __IO uint32_t int_en; /**< \b 0x24: SPI INT_EN Register */ @@ -103,21 +105,21 @@ typedef struct { /** * @ingroup spi_registers * @defgroup SPI_Register_Offsets Register Offsets - * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. + * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. * @{ */ - #define MXC_R_SPI_DATA ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ - #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ - #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ - #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ - #define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ - #define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ - #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ - #define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ - #define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ - #define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ - #define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ - #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +#define MXC_R_SPI_DATA ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ +#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ +#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ +#define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ +#define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ +#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ +#define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ +#define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ +#define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ +#define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ +#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ /**@} end of group spi_registers */ /** @@ -134,31 +136,31 @@ typedef struct { * @brief Register for controlling SPI peripheral. * @{ */ - #define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */ - #define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */ +#define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */ +#define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */ - #define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */ - #define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */ +#define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */ +#define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */ - #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ - #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ +#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ +#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ - #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ - #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ +#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ +#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ - #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ - #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ +#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ +#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ - #define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */ - #define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */ - #define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */ - #define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */ - #define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */ - #define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */ - #define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */ - #define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */ - #define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */ - #define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */ +#define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */ +#define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */ +#define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */ +#define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */ +#define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */ +#define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */ +#define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */ +#define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */ +#define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */ +#define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */ /**@} end of group SPI_CTRL0_Register */ @@ -168,11 +170,11 @@ typedef struct { * @brief Register for controlling SPI peripheral. * @{ */ - #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ - #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ - #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ - #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ /**@} end of group SPI_CTRL1_Register */ @@ -182,31 +184,31 @@ typedef struct { * @brief Register for controlling SPI peripheral. * @{ */ - #define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */ - #define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */ +#define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */ +#define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */ - #define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */ - #define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */ +#define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */ +#define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */ - #define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */ - #define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */ - #define MXC_V_SPI_CTRL2_NUM_BITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_0 Value */ - #define MXC_S_SPI_CTRL2_NUM_BITS_0 (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_0 Setting */ +#define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */ +#define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */ +#define MXC_V_SPI_CTRL2_NUM_BITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_0 Value */ +#define MXC_S_SPI_CTRL2_NUM_BITS_0 (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_0 Setting */ - #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ - #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ - #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ - #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ - #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ - #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ - #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ - #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ +#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ +#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ - #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ - #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ +#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ +#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ - #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ - #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ +#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ +#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ /**@} end of group SPI_CTRL2_Register */ @@ -216,20 +218,20 @@ typedef struct { * @brief Register for controlling SPI peripheral/Slave Select Timing. * @{ */ - #define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ - #define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ - #define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */ - #define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */ +#define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ +#define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ +#define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */ +#define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */ - #define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ - #define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ - #define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */ - #define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */ +#define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ +#define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ +#define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */ +#define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */ - #define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ - #define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ - #define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */ - #define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */ +#define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ +#define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ +#define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */ +#define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */ /**@} end of group SPI_SS_TIME_Register */ @@ -239,18 +241,18 @@ typedef struct { * @brief Register for controlling SPI clock rate. * @{ */ - #define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ - #define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ - #define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ - #define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ +#define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ +#define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ +#define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ +#define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ - #define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ - #define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ - #define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ - #define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ +#define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ +#define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ +#define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ +#define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ - #define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ - #define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ +#define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ +#define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ /**@} end of group SPI_CLK_CFG_Register */ @@ -260,35 +262,35 @@ typedef struct { * @brief Register for controlling DMA. * @{ */ - #define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ - #define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ +#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ +#define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ - #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ - #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ +#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ - #define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ - #define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ +#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ +#define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ - #define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ - #define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ +#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ +#define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ - #define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ - #define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ +#define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ +#define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ - #define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ - #define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ +#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ +#define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ - #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ - #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ +#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ - #define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ - #define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ +#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ +#define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ - #define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ - #define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ +#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ +#define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ - #define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ - #define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ +#define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ +#define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ /**@} end of group SPI_DMA_Register */ @@ -299,41 +301,41 @@ typedef struct { * clear. * @{ */ - #define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */ - #define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */ +#define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */ +#define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */ - #define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ - #define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ +#define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ +#define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ - #define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */ - #define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */ +#define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */ +#define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */ - #define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ - #define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ +#define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ +#define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ - #define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ - #define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ +#define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ +#define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ - #define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ - #define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ +#define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ +#define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ - #define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ - #define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ +#define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ +#define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ - #define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ - #define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ +#define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ +#define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ - #define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ - #define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ +#define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ +#define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ - #define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ - #define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ +#define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ +#define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ - #define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ - #define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ +#define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ +#define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ - #define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ - #define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ +#define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ +#define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ /**@} end of group SPI_INT_FL_Register */ @@ -343,44 +345,44 @@ typedef struct { * @brief Register for enabling interrupts. * @{ */ - #define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */ - #define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */ +#define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */ +#define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */ - #define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ - #define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ +#define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ +#define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ - #define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */ - #define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */ +#define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */ +#define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */ - #define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ - #define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ +#define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ +#define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ - #define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ - #define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ +#define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ +#define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ - #define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ - #define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ +#define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ +#define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ - #define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ - #define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ +#define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ +#define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ - #define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ - #define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ +#define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ +#define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ - #define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ - #define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ +#define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ +#define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ - #define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ - #define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ +#define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ +#define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ - #define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ - #define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ +#define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ +#define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ - #define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ - #define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ +#define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ +#define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ - #define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ - #define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ +#define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ +#define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ /**@} end of group SPI_INT_EN_Register */ @@ -390,17 +392,17 @@ typedef struct { * @brief Register for wake up flags. All bits in this register are write 1 to clear. * @{ */ - #define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */ - #define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */ +#define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */ +#define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */ - #define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ - #define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ +#define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ +#define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ - #define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */ - #define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */ +#define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */ +#define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */ - #define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ - #define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ +#define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ +#define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ /**@} end of group SPI_WAKE_FL_Register */ @@ -410,17 +412,17 @@ typedef struct { * @brief Register for wake up enable. * @{ */ - #define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */ - #define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */ +#define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */ +#define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */ - #define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ - #define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ +#define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ +#define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ - #define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */ - #define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */ +#define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */ +#define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */ - #define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ - #define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ +#define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ +#define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ /**@} end of group SPI_WAKE_EN_Register */ @@ -430,8 +432,8 @@ typedef struct { * @brief SPI Status register. * @{ */ - #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ - #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ +#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ +#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ /**@} end of group SPI_STAT_Register */ @@ -439,4 +441,4 @@ typedef struct { } #endif -#endif /* _SPI_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h index c2cb890c5ed..d5638e3e6ed 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h @@ -1,10 +1,11 @@ /** * @file spimss_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _SPIMSS_REGS_H_ -#define _SPIMSS_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup spimss * @defgroup spimss_registers SPIMSS_Registers * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. - * @details Serial Peripheral Interface. + * @details Serial Peripheral Interface. */ /** @@ -85,11 +87,11 @@ extern "C" { */ typedef struct { __IO uint16_t data; /**< \b 0x00: SPIMSS DATA Register */ - __I uint16_t rsv_0x2; + __R uint16_t rsv_0x2; __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ __IO uint32_t int_fl; /**< \b 0x08: SPIMSS INT_FL Register */ __IO uint32_t mode; /**< \b 0x0C: SPIMSS MODE Register */ - __I uint32_t rsv_0x10; + __R uint32_t rsv_0x10; __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ @@ -99,16 +101,16 @@ typedef struct { /** * @ingroup spimss_registers * @defgroup SPIMSS_Register_Offsets Register Offsets - * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. + * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. * @{ */ - #define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ - #define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: 0x0004 */ - #define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: 0x0008 */ - #define MXC_R_SPIMSS_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: 0x000C */ - #define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: 0x0014 */ - #define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: 0x0018 */ - #define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: 0x001C */ +#define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ +#define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: 0x0004 */ +#define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: 0x0008 */ +#define MXC_R_SPIMSS_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: 0x000C */ +#define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: 0x0014 */ +#define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: 0x0018 */ +#define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: 0x001C */ /**@} end of group spimss_registers */ /** @@ -117,8 +119,8 @@ typedef struct { * @brief SPI 16-bit Data Access * @{ */ - #define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_SPIMSS_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_SPIMSS_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */ /**@} end of group SPIMSS_DATA_Register */ @@ -128,29 +130,29 @@ typedef struct { * @brief SPI Control Register. * @{ */ - #define MXC_F_SPIMSS_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ - #define MXC_F_SPIMSS_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ +#define MXC_F_SPIMSS_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ +#define MXC_F_SPIMSS_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ - #define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ - #define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ +#define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ +#define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ - #define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ - #define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ +#define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ +#define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ - #define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ - #define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ +#define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ +#define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ - #define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ - #define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ +#define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ +#define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ - #define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ - #define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ +#define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ +#define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ - #define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */ - #define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */ +#define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */ +#define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */ - #define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ - #define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ +#define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ +#define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ /**@} end of group SPIMSS_CTRL_Register */ @@ -160,29 +162,29 @@ typedef struct { * @brief SPI Interrupt Flag Register. * @{ */ - #define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */ - #define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */ +#define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */ +#define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */ - #define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */ - #define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */ +#define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */ +#define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */ - #define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */ - #define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */ +#define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */ +#define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */ - #define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */ - #define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */ +#define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */ +#define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */ - #define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */ - #define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */ +#define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */ +#define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */ - #define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */ - #define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */ +#define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */ +#define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */ - #define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */ - #define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */ +#define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */ +#define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */ - #define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */ - #define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */ +#define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */ +#define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */ /**@} end of group SPIMSS_INT_FL_Register */ @@ -192,49 +194,49 @@ typedef struct { * @brief SPI Mode Register. * @{ */ - #define MXC_F_SPIMSS_MODE_SSV_POS 0 /**< MODE_SSV Position */ - #define MXC_F_SPIMSS_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS)) /**< MODE_SSV Mask */ - - #define MXC_F_SPIMSS_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */ - #define MXC_F_SPIMSS_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */ - - #define MXC_F_SPIMSS_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */ - #define MXC_F_SPIMSS_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */ - #define MXC_V_SPIMSS_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */ - #define MXC_S_SPIMSS_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */ - - #define MXC_F_SPIMSS_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */ - #define MXC_F_SPIMSS_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */ +#define MXC_F_SPIMSS_MODE_SSV_POS 0 /**< MODE_SSV Position */ +#define MXC_F_SPIMSS_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS)) /**< MODE_SSV Mask */ + +#define MXC_F_SPIMSS_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */ +#define MXC_F_SPIMSS_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */ + +#define MXC_F_SPIMSS_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */ +#define MXC_F_SPIMSS_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */ +#define MXC_V_SPIMSS_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */ +#define MXC_S_SPIMSS_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */ + +#define MXC_F_SPIMSS_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */ +#define MXC_F_SPIMSS_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */ /**@} end of group SPIMSS_MODE_Register */ @@ -247,8 +249,8 @@ typedef struct { * 4). * @{ */ - #define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */ - #define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */ +#define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */ +#define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */ /**@} end of group SPIMSS_BRG_Register */ @@ -258,61 +260,61 @@ typedef struct { * @brief SPI DMA Register. * @{ */ - #define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ - #define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */ - #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */ - #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */ - - #define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */ - #define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */ - - #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ - #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ - - #define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ - #define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ - - #define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ - #define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */ - #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */ - #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */ - - #define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */ - #define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ - - #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ - #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ - - #define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ - #define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ +#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ +#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */ +#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */ +#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */ + +#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */ +#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */ + +#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ +#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + +#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ +#define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + +#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ +#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */ +#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */ +#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */ + +#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */ +#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ + +#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ +#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + +#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ +#define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ /**@} end of group SPIMSS_DMA_Register */ @@ -322,20 +324,20 @@ typedef struct { * @brief I2S Control Register. * @{ */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ - #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ +#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ /**@} end of group SPIMSS_I2S_CTRL_Register */ @@ -343,4 +345,4 @@ typedef struct { } #endif -#endif /* _SPIMSS_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h index b2688facdaf..b398337686e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h @@ -3,9 +3,8 @@ * @brief System-specific header file */ - -/******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * ******************************************************************************/ -#ifndef _SYSTEM_MAX32660_H_ -#define _SYSTEM_MAX32660_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_ #ifdef __cplusplus extern "C" { @@ -52,20 +50,22 @@ extern "C" { *----------------------------------------------------------------------------*/ #ifndef HFX_FREQ -#define HFX_FREQ 32768 +#define HFX_FREQ 32768 #endif +/* NOTE: This is the nominal value for NANORING. The actual value may vary from chip to chip. + Update if use of this oscillator requires precise timing.*/ #ifndef NANORING_FREQ -#define NANORING_FREQ 8000 +#define NANORING_FREQ 8000 #endif #ifndef HIRC96_FREQ -#define HIRC96_FREQ 96000000 +#define HIRC96_FREQ 96000000 #endif -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ #ifndef PeripheralClock -#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */ +#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */ #endif /* @@ -88,4 +88,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MAX32660_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h index d9062f849cd..b1073ea226b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h @@ -1,10 +1,11 @@ /** * @file tmr_regs.h * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _TMR_REGS_H_ -#define _TMR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup tmr * @defgroup tmr_registers TMR_Registers * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. - * @details Low-Power Configurable Timer + * @details Low-Power Configurable Timer */ /** @@ -95,14 +97,14 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_Register_Offsets Register Offsets - * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. * @{ */ - #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ - #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ - #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ - #define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ - #define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ +#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ +#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ +#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ +#define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ /**@} end of group tmr_registers */ /** @@ -111,8 +113,8 @@ typedef struct { * @brief Timer Counter Register. * @{ */ - #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ - #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ +#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ /**@} end of group TMR_CNT_Register */ @@ -122,8 +124,8 @@ typedef struct { * @brief Timer Compare Register. * @{ */ - #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ - #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ +#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ /**@} end of group TMR_CMP_Register */ @@ -133,8 +135,8 @@ typedef struct { * @brief Timer PWM Register. * @{ */ - #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ - #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ +#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ +#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ /**@} end of group TMR_PWM_Register */ @@ -144,8 +146,8 @@ typedef struct { * @brief Timer Interrupt Status Register. * @{ */ - #define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */ - #define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */ +#define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */ +#define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */ /**@} end of group TMR_INTR_Register */ @@ -155,80 +157,76 @@ typedef struct { * @brief Timer Control Register. * @{ */ - #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ - #define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ - #define MXC_V_TMR_CN_TMODE_ONE_SHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONE_SHOT Value */ - #define MXC_S_TMR_CN_TMODE_ONE_SHOT (MXC_V_TMR_CN_TMODE_ONE_SHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONE_SHOT Setting */ - #define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ - #define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ - #define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ - #define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ - #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ - #define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ - #define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ - #define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ - #define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ - #define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ - #define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ - #define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ - #define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */ - #define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */ - #define MXC_V_TMR_CN_TMODE_DUAL_EDGE ((uint32_t)0x8UL) /**< CN_TMODE_DUAL_EDGE Value */ - #define MXC_S_TMR_CN_TMODE_DUAL_EDGE (MXC_V_TMR_CN_TMODE_DUAL_EDGE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_DUAL_EDGE Setting */ - #define MXC_V_TMR_CN_TMODE_IGATED ((uint32_t)0xCUL) /**< CN_TMODE_IGATED Value */ - #define MXC_S_TMR_CN_TMODE_IGATED (MXC_V_TMR_CN_TMODE_IGATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_IGATED Setting */ - - #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ - #define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ - #define MXC_V_TMR_CN_PRES_DIV_BY_1 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_1 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_1 (MXC_V_TMR_CN_PRES_DIV_BY_1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_2 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_2 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_2 (MXC_V_TMR_CN_PRES_DIV_BY_2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_4 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_4 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_4 (MXC_V_TMR_CN_PRES_DIV_BY_4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_8 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_8 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_8 (MXC_V_TMR_CN_PRES_DIV_BY_8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_16 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_16 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_16 (MXC_V_TMR_CN_PRES_DIV_BY_16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_16 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_32 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_32 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_32 (MXC_V_TMR_CN_PRES_DIV_BY_32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_32 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_64 ((uint32_t)0x6UL) /**< CN_PRES_DIV_BY_64 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x8UL) /**< CN_PRES_DIV_BY_256 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x9UL) /**< CN_PRES_DIV_BY_512 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0xAUL) /**< CN_PRES_DIV_BY_1024 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0xBUL) /**< CN_PRES_DIV_BY_2048 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0xCUL) /**< CN_PRES_DIV_BY_4096 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */ - #define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0xDUL) /**< CN_PRES_DIV_BY_8192 Value */ - #define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */ - - #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ - #define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ - - #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ - #define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ - - #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ - #define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ - - #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ - #define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ - - #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ - #define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ - - #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ - #define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ - - #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ - #define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ +#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ +#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ +#define MXC_V_TMR_CN_TMODE_ONE_SHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONE_SHOT Value */ +#define MXC_S_TMR_CN_TMODE_ONE_SHOT (MXC_V_TMR_CN_TMODE_ONE_SHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONE_SHOT Setting */ +#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ +#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ +#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ +#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ +#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ +#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ +#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ +#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ +#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ +#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ +#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ +#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ +#define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */ +#define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */ + +#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ +#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ +#define MXC_V_TMR_CN_PRES_DIV_BY_1 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_1 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_1 (MXC_V_TMR_CN_PRES_DIV_BY_1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_2 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_2 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_2 (MXC_V_TMR_CN_PRES_DIV_BY_2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_4 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_4 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_4 (MXC_V_TMR_CN_PRES_DIV_BY_4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_8 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_8 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_8 (MXC_V_TMR_CN_PRES_DIV_BY_8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_16 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_16 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_16 (MXC_V_TMR_CN_PRES_DIV_BY_16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_16 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_32 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_32 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_32 (MXC_V_TMR_CN_PRES_DIV_BY_32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_32 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_64 ((uint32_t)0x6UL) /**< CN_PRES_DIV_BY_64 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_256 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_512 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_1024 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_2048 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_4096 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */ +#define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_8192 Value */ +#define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */ + +#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ +#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ + +#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ +#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ + +#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ +#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ + +#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ +#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ + +#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ +#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ + +#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ +#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ + +#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ +#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ /**@} end of group TMR_CN_Register */ @@ -236,4 +234,4 @@ typedef struct { } #endif -#endif /* _TMR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h index 6340801d687..6eeec71d086 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h @@ -1,10 +1,11 @@ /** * @file uart_regs.h * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _UART_REGS_H_ -#define _UART_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup uart * @defgroup uart_registers UART_Registers * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. - * @details UART + * @details UART */ /** @@ -100,19 +102,19 @@ typedef struct { /** * @ingroup uart_registers * @defgroup UART_Register_Offsets Register Offsets - * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. * @{ */ - #define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ - #define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ - #define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ - #define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ - #define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ - #define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ - #define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ - #define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ - #define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ - #define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: 0x0024 */ +#define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ +#define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ +#define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ +#define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ +#define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ +#define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ +#define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ +#define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ +#define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ +#define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: 0x0024 */ /**@} end of group uart_registers */ /** @@ -121,66 +123,66 @@ typedef struct { * @brief Control Register. * @{ */ - #define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */ - #define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */ +#define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */ +#define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */ - #define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */ - #define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */ +#define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */ +#define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */ - #define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */ - #define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */ - #define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */ - #define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */ - #define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */ - #define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */ - #define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */ - #define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */ - #define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */ - #define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */ +#define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */ +#define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */ +#define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */ +#define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */ +#define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */ +#define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */ +#define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */ +#define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */ +#define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */ +#define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */ - #define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */ - #define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */ +#define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */ +#define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */ - #define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */ - #define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */ +#define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */ +#define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */ - #define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */ - #define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */ +#define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */ +#define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */ - #define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */ - #define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */ +#define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */ +#define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */ - #define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */ - #define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */ - #define MXC_V_UART_CTRL0_SIZE_5 ((uint32_t)0x0UL) /**< CTRL0_SIZE_5 Value */ - #define MXC_S_UART_CTRL0_SIZE_5 (MXC_V_UART_CTRL0_SIZE_5 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5 Setting */ - #define MXC_V_UART_CTRL0_SIZE_6 ((uint32_t)0x1UL) /**< CTRL0_SIZE_6 Value */ - #define MXC_S_UART_CTRL0_SIZE_6 (MXC_V_UART_CTRL0_SIZE_6 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6 Setting */ - #define MXC_V_UART_CTRL0_SIZE_7 ((uint32_t)0x2UL) /**< CTRL0_SIZE_7 Value */ - #define MXC_S_UART_CTRL0_SIZE_7 (MXC_V_UART_CTRL0_SIZE_7 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7 Setting */ - #define MXC_V_UART_CTRL0_SIZE_8 ((uint32_t)0x3UL) /**< CTRL0_SIZE_8 Value */ - #define MXC_S_UART_CTRL0_SIZE_8 (MXC_V_UART_CTRL0_SIZE_8 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8 Setting */ +#define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */ +#define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */ +#define MXC_V_UART_CTRL0_SIZE_5 ((uint32_t)0x0UL) /**< CTRL0_SIZE_5 Value */ +#define MXC_S_UART_CTRL0_SIZE_5 (MXC_V_UART_CTRL0_SIZE_5 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5 Setting */ +#define MXC_V_UART_CTRL0_SIZE_6 ((uint32_t)0x1UL) /**< CTRL0_SIZE_6 Value */ +#define MXC_S_UART_CTRL0_SIZE_6 (MXC_V_UART_CTRL0_SIZE_6 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6 Setting */ +#define MXC_V_UART_CTRL0_SIZE_7 ((uint32_t)0x2UL) /**< CTRL0_SIZE_7 Value */ +#define MXC_S_UART_CTRL0_SIZE_7 (MXC_V_UART_CTRL0_SIZE_7 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7 Setting */ +#define MXC_V_UART_CTRL0_SIZE_8 ((uint32_t)0x3UL) /**< CTRL0_SIZE_8 Value */ +#define MXC_S_UART_CTRL0_SIZE_8 (MXC_V_UART_CTRL0_SIZE_8 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8 Setting */ - #define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */ - #define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */ +#define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */ +#define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */ - #define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */ - #define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */ +#define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */ +#define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */ - #define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */ - #define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */ +#define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */ +#define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */ - #define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */ - #define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */ +#define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */ +#define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */ - #define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */ - #define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */ +#define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */ +#define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */ - #define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */ - #define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */ +#define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */ +#define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */ - #define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */ - #define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */ +#define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */ +#define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */ /**@} end of group UART_CTRL0_Register */ @@ -190,14 +192,14 @@ typedef struct { * @brief Threshold Control register. * @{ */ - #define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */ - #define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */ +#define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */ +#define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */ - #define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */ - #define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */ +#define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */ +#define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */ - #define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */ - #define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */ +#define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */ +#define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */ /**@} end of group UART_CTRL1_Register */ @@ -207,38 +209,38 @@ typedef struct { * @brief Status Register. * @{ */ - #define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */ - #define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */ +#define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */ +#define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */ - #define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */ - #define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */ +#define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */ +#define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */ - #define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */ - #define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */ +#define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */ +#define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */ - #define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */ - #define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */ +#define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */ +#define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */ - #define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */ - #define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */ +#define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */ +#define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */ - #define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */ - #define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */ +#define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */ +#define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */ - #define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */ - #define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */ +#define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */ +#define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */ - #define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */ - #define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */ +#define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */ +#define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */ - #define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */ - #define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */ +#define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */ +#define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */ - #define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */ - #define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */ +#define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */ +#define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */ - #define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */ - #define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */ +#define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */ +#define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */ /**@} end of group UART_STAT_Register */ @@ -248,35 +250,35 @@ typedef struct { * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ - #define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ +#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ +#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ - #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ - #define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ +#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ +#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ - #define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */ - #define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */ +#define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */ +#define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */ - #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ - #define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ +#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ +#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ - #define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */ - #define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */ +#define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */ +#define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */ - #define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */ - #define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */ +#define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */ +#define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */ - #define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */ - #define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */ +#define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */ +#define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */ - #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ - #define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ +#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ +#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ - #define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */ - #define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */ +#define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */ +#define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */ - #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ - #define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ +#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ +#define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ /**@} end of group UART_INT_EN_Register */ @@ -286,35 +288,35 @@ typedef struct { * @brief Interrupt Status Flags. * @{ */ - #define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */ - #define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */ +#define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */ +#define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */ - #define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */ - #define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */ +#define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */ +#define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */ - #define MXC_F_UART_INT_FL_CTS_POS 2 /**< INT_FL_CTS Position */ - #define MXC_F_UART_INT_FL_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_POS)) /**< INT_FL_CTS Mask */ +#define MXC_F_UART_INT_FL_CTS_POS 2 /**< INT_FL_CTS Position */ +#define MXC_F_UART_INT_FL_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_POS)) /**< INT_FL_CTS Mask */ - #define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */ - #define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ +#define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */ +#define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ - #define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */ - #define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */ +#define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */ +#define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */ - #define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */ - #define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */ +#define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */ +#define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */ - #define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */ - #define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */ +#define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */ +#define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */ - #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ - #define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ +#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ +#define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ - #define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */ - #define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */ +#define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */ +#define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */ - #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ - #define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ +#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ +#define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ /**@} end of group UART_INT_FL_Register */ @@ -324,21 +326,21 @@ typedef struct { * @brief Baud rate register. Integer portion. * @{ */ - #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ - #define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ - - #define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */ - #define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */ - #define MXC_V_UART_BAUD0_CLKDIV_128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_128 Value */ - #define MXC_S_UART_BAUD0_CLKDIV_128 (MXC_V_UART_BAUD0_CLKDIV_128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_128 Setting */ - #define MXC_V_UART_BAUD0_CLKDIV_64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_64 Value */ - #define MXC_S_UART_BAUD0_CLKDIV_64 (MXC_V_UART_BAUD0_CLKDIV_64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_64 Setting */ - #define MXC_V_UART_BAUD0_CLKDIV_32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_32 Value */ - #define MXC_S_UART_BAUD0_CLKDIV_32 (MXC_V_UART_BAUD0_CLKDIV_32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_32 Setting */ - #define MXC_V_UART_BAUD0_CLKDIV_16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_16 Value */ - #define MXC_S_UART_BAUD0_CLKDIV_16 (MXC_V_UART_BAUD0_CLKDIV_16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_16 Setting */ - #define MXC_V_UART_BAUD0_CLKDIV_8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_8 Value */ - #define MXC_S_UART_BAUD0_CLKDIV_8 (MXC_V_UART_BAUD0_CLKDIV_8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_8 Setting */ +#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ +#define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ + +#define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */ +#define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */ +#define MXC_V_UART_BAUD0_CLKDIV_128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_128 Value */ +#define MXC_S_UART_BAUD0_CLKDIV_128 (MXC_V_UART_BAUD0_CLKDIV_128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_128 Setting */ +#define MXC_V_UART_BAUD0_CLKDIV_64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_64 Value */ +#define MXC_S_UART_BAUD0_CLKDIV_64 (MXC_V_UART_BAUD0_CLKDIV_64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_64 Setting */ +#define MXC_V_UART_BAUD0_CLKDIV_32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_32 Value */ +#define MXC_S_UART_BAUD0_CLKDIV_32 (MXC_V_UART_BAUD0_CLKDIV_32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_32 Setting */ +#define MXC_V_UART_BAUD0_CLKDIV_16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_16 Value */ +#define MXC_S_UART_BAUD0_CLKDIV_16 (MXC_V_UART_BAUD0_CLKDIV_16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_16 Setting */ +#define MXC_V_UART_BAUD0_CLKDIV_8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_8 Value */ +#define MXC_S_UART_BAUD0_CLKDIV_8 (MXC_V_UART_BAUD0_CLKDIV_8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_8 Setting */ /**@} end of group UART_BAUD0_Register */ @@ -348,8 +350,8 @@ typedef struct { * @brief Baud rate register. Decimal Setting. * @{ */ - #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ - #define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ +#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ +#define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ /**@} end of group UART_BAUD1_Register */ @@ -359,8 +361,8 @@ typedef struct { * @brief FIFO Data buffer. * @{ */ - #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ - #define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ +#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ +#define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ /**@} end of group UART_FIFO_Register */ @@ -370,17 +372,17 @@ typedef struct { * @brief DMA Configuration. * @{ */ - #define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */ - #define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ +#define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */ +#define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ - #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ - #define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ +#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ +#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ - #define MXC_F_UART_DMA_TXDMA_LVL_POS 8 /**< DMA_TXDMA_LVL Position */ - #define MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) /**< DMA_TXDMA_LVL Mask */ +#define MXC_F_UART_DMA_TXDMA_LVL_POS 8 /**< DMA_TXDMA_LVL Position */ +#define MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) /**< DMA_TXDMA_LVL Mask */ - #define MXC_F_UART_DMA_RXDMA_LVL_POS 16 /**< DMA_RXDMA_LVL Position */ - #define MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) /**< DMA_RXDMA_LVL Mask */ +#define MXC_F_UART_DMA_RXDMA_LVL_POS 16 /**< DMA_RXDMA_LVL Position */ +#define MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) /**< DMA_RXDMA_LVL Mask */ /**@} end of group UART_DMA_Register */ @@ -390,8 +392,8 @@ typedef struct { * @brief Transmit FIFO Status register. * @{ */ - #define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */ - #define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */ +#define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */ +#define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */ /**@} end of group UART_TXFIFO_Register */ @@ -399,4 +401,4 @@ typedef struct { } #endif -#endif /* _UART_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h index ae0139f11d5..67f72795be2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h @@ -1,10 +1,11 @@ /** * @file wdt_regs.h * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _WDT_REGS_H_ -#define _WDT_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -67,7 +67,9 @@ extern "C" { #ifndef __O #define __O volatile #endif - +#ifndef __R +#define __R volatile const +#endif /// @endcond /* **** Definitions **** */ @@ -76,7 +78,7 @@ extern "C" { * @ingroup wdt * @defgroup wdt_registers WDT_Registers * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. - * @details Watchdog Timer 0 + * @details Watchdog Timer 0 */ /** @@ -92,11 +94,11 @@ typedef struct { /** * @ingroup wdt_registers * @defgroup WDT_Register_Offsets Register Offsets - * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. * @{ */ - #define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ - #define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ +#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ /**@} end of group wdt_registers */ /** @@ -105,90 +107,90 @@ typedef struct { * @brief Watchdog Timer Control Register. * @{ */ - #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ - #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ - #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ - #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ - - #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ - #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ - #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ - #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ - - #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ - #define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ - - #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ - #define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ - - #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ - #define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ - - #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ - #define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ - - #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ - #define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ +#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ +#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ +#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ +#define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ + +#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ +#define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ + +#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ +#define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ + +#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ +#define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ + +#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ +#define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ /**@} end of group WDT_CTRL_Register */ @@ -198,12 +200,12 @@ typedef struct { * @brief Watchdog Timer Reset Register. * @{ */ - #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ - #define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ - #define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ - #define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ - #define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ - #define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ +#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ +#define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ +#define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ +#define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ +#define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ +#define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ /**@} end of group WDT_RST_Register */ @@ -211,4 +213,4 @@ typedef struct { } #endif -#endif /* _WDT_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index 2d7f4f204da..3565907b90f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -3,8 +3,8 @@ * @brief System-level initialization implementation file */ -/******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,9 +34,6 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ - * $Revision: 40072 $ - * ******************************************************************************/ #include @@ -48,38 +45,38 @@ #include "tmr_regs.h" #include "wdt_regs.h" #include "mxc_sys.h" -#include "icc.h" +extern void (*const __isr_vector[])(void); uint32_t SystemCoreClock = HIRC96_FREQ; __weak void SystemCoreClockUpdate(void) { - uint32_t base_freq, div, clk_src,ovr; + uint32_t base_freq, div, clk_src, ovr; // Get the clock source and frequency clk_src = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL); - + if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) { base_freq = HFX_FREQ; } else { - if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING) { - base_freq = NANORING_FREQ; - } else { - ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); - if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) { - base_freq = HIRC96_FREQ/4; - } else { - if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) { - base_freq = HIRC96_FREQ/2; - } else { - base_freq = HIRC96_FREQ; - } - } - } + if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING) { + base_freq = NANORING_FREQ; + } else { + ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); + if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) { + base_freq = HIRC96_FREQ / 4; + } else { + if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) { + base_freq = HIRC96_FREQ / 2; + } else { + base_freq = HIRC96_FREQ; + } + } + } } // Get the clock divider - div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS; + div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; SystemCoreClock = base_freq >> div; } @@ -94,20 +91,15 @@ __weak void SystemCoreClockUpdate(void) */ __weak int PreInit(void) { - /* Switch system clock to HIRC, 96 MHz*/ - MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); - - /* Enable cache here to reduce boot time */ - MXC_ICC_Enable(); - + /* Do nothing */ return 0; } -/* Override this function for early platform initialization -*/ -__weak void low_level_init(void) +/* This function can be implemented by the application to initialize the board */ +__weak int Board_Init(void) { - + /* Do nothing */ + return 0; } /* This function is called just before control is transferred to main(). @@ -118,16 +110,23 @@ __weak void low_level_init(void) */ __weak void SystemInit(void) { - MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ + /* Configure the interrupt controller to use the application vector table in */ + /* the application space */ + /* IAR & Keil must set vector table after all memory initialization. */ + SCB->VTOR = (uint32_t)__isr_vector; + + MXC_WDT0->ctrl &= + ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ -#if (__FPU_PRESENT == 1) /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ /* Grant full access, per "Table B3-24 CPACR bit assignments". */ /* DDI0403D "ARMv7-M Architecture Reference Manual" */ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); -#endif + + /* Switch system clock to HIRC */ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); /* Disable clocks to peripherals by default to reduce power */ MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA); @@ -140,7 +139,27 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); - - /* Early platform initialization */ - low_level_init(); + + Board_Init(); +} + +#if defined(__CC_ARM) +/* Global variable initialization does not occur until post scatterload in Keil tools.*/ + +/* External function called after our post scatterload function implementation. */ +extern void $Super$$__main_after_scatterload(void); + +/** + * @brief Initialization function for SystemCoreClock and Board_Init. + * @details $Sub$$__main_after_scatterload is called during system startup in the Keil + * toolset. Global variable and static variable space must be set up by the compiler + * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init + * require global memory for variable storage and are called from this function in + * the Keil tool chain. + */ +void $Sub$$__main_after_scatterload(void) +{ + SystemInit(); + $Super$$__main_after_scatterload(); } +#endif /* __CC_ARM */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h index f8eda9c44a0..f675fcd7cdb 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h @@ -3,8 +3,8 @@ * @brief Direct Memory Access (DMA) driver function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,11 +33,11 @@ * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. - * - *************************************************************************** */ + * + ******************************************************************************/ -#ifndef _DMA_H_ -#define _DMA_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_ /* **** Includes **** */ #include @@ -57,53 +57,55 @@ extern "C" { /* **** Definitions **** */ - /** * @brief Enumeration for the DMA Channel's priority level. * */ typedef enum { - MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */ - MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */ - MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */ - MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */ + MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */ + MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */ + MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */ + MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */ } mxc_dma_priority_t; /** @brief DMA request select */ typedef enum { - MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection - MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection - MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection - MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection - MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection - MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection - MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection + MXC_DMA_REQUEST_MEMTOMEM = + MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection + MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection + MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection + MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection + MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART0TX = + MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART1TX = + MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection } mxc_dma_reqsel_t; /** @brief Enumeration for the DMA prescaler */ typedef enum { - MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled - MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256 - MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536 - MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216 + MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled + MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256 + MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536 + MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216 } mxc_dma_prescale_t; /** @brief Enumeration for the DMA timeout value */ typedef enum { - MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks - MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks - MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks - MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks - MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks - MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks - MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks - MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks + MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks + MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks + MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks + MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks + MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks + MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks + MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks + MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks } mxc_dma_timeout_t; /** @brief DMA transfer data width */ @@ -111,9 +113,9 @@ typedef enum { /* Using the '_V_' define instead of the '_S_' since these same values will be used to specify the DSTWD also. The API functions will shift the value the correct amount prior to writing the cfg register. */ - MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes - MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words - MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words + MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes + MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words + MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words } mxc_dma_width_t; /** @@ -122,12 +124,12 @@ typedef enum { * */ typedef struct { - int ch; ///< The channel to load the configuration data into - mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral) - mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) - mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) - int srcinc_en; ///< Whether to increment the source address during the transfer - int dstinc_en; ///< Whether to increment the source address during the transfer + int ch; ///< The channel to load the configuration data into + mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) + mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) + mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) + int srcinc_en; ///< Whether to increment the source address during the transfer + int dstinc_en; ///< Whether to increment the source address during the transfer } mxc_dma_config_t; /** @@ -135,10 +137,10 @@ typedef struct { * */ typedef struct { - int ch; ///< The channel to use for the transfer - void* source; ///< Pointer to the source address, if applicable - void* dest; ///< Pointer to the destination address, if applicable - int len; ///< Number of bytes to transfer + int ch; ///< The channel to use for the transfer + void *source; ///< Pointer to the source address, if applicable + void *dest; ///< Pointer to the destination address, if applicable + int len; ///< Number of bytes to transfer } mxc_dma_srcdst_t; /** @@ -148,12 +150,12 @@ typedef struct { * */ typedef struct { - int ch; ///< The channel to use for the transfer - mxc_dma_priority_t prio; ///< The DMA priority for the channel - unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer - mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout - mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer - unsigned int burst_size; ///< Number of bytes moved in a single burst + int ch; ///< The channel to use for the transfer + mxc_dma_priority_t prio; ///< The DMA priority for the channel + unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer + mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout + mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer + unsigned int burst_size; ///< Number of bytes moved in a single burst } mxc_dma_adv_config_t; /** @@ -161,7 +163,7 @@ typedef struct { * * @param dest Pointer to the destination of the copy */ -typedef void (*mxc_dma_complete_cb_t) (void* dest); +typedef void (*mxc_dma_complete_cb_t)(void *dest); /** * @brief The callback called on completion of a transfer, @@ -174,7 +176,7 @@ typedef void (*mxc_dma_complete_cb_t) (void* dest); * @return Returns the next transfer to be completed, or NULL * if no more transfers will be done */ -typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest); +typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); /* **** Function Prototypes **** */ /*************************/ @@ -185,7 +187,7 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest); * @details This initialization is required before using the DMA driver functions. * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init (void); +int MXC_DMA_Init(void); /** * @brief Request DMA channel @@ -196,7 +198,7 @@ int MXC_DMA_Init (void); * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel (void); +int MXC_DMA_AcquireChannel(void); /** * @brief Release DMA channel @@ -206,7 +208,7 @@ int MXC_DMA_AcquireChannel (void); * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ReleaseChannel (int ch); +int MXC_DMA_ReleaseChannel(int ch); /** * @brief Configure the DMA channel @@ -217,7 +219,7 @@ int MXC_DMA_ReleaseChannel (int ch); * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); /** * @brief Configure the DMA channel with more advanced parameters @@ -226,7 +228,7 @@ int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig); +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); /** * @brief Set channel source, destination, and count for the transfer @@ -237,7 +239,7 @@ int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig); * Guide for more information. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst); +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); /** * @brief Get channel source, destination, and count for transfer @@ -246,7 +248,7 @@ int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst); * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst); +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); /** * @brief Set channel reload source, destination, and count for the transfer @@ -257,7 +259,7 @@ int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst); * Guide for more information. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload); +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); /** * @brief Get channel reload source, destination, and count for transfer @@ -266,7 +268,7 @@ int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload); * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload); +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); /** * @brief Set channel interrupt callback @@ -290,7 +292,7 @@ int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload); * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR * otherwise */ -int MXC_DMA_SetCallback (int ch, void (*callback) (int, int)); +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); /** * @brief Set channel interrupt @@ -302,7 +304,7 @@ int MXC_DMA_SetCallback (int ch, void (*callback) (int, int)); * @param ctz Enable channel count to zero interrupt. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz); +int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); /** * @brief Enable channel interrupt @@ -312,7 +314,7 @@ int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz); * @param flags The flags to enable * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ChannelEnableInt (int ch, int flags); +int MXC_DMA_ChannelEnableInt(int ch, int flags); /** * @brief Disable channel interrupt @@ -320,14 +322,14 @@ int MXC_DMA_ChannelEnableInt (int ch, int flags); * @param flags The flags to disable * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ChannelDisableInt (int ch, int flags); +int MXC_DMA_ChannelDisableInt(int ch, int flags); /** * @brief Read channel interrupt flags * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise */ -int MXC_DMA_ChannelGetFlags (int ch); +int MXC_DMA_ChannelGetFlags(int ch); /** * @brief Clear channel interrupt flags @@ -335,7 +337,7 @@ int MXC_DMA_ChannelGetFlags (int ch); * @param flags The flags to clear * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ChannelClearFlags (int ch, int flags); +int MXC_DMA_ChannelClearFlags(int ch, int flags); /** * @brief Enable channel interrupt @@ -344,14 +346,14 @@ int MXC_DMA_ChannelClearFlags (int ch, int flags); * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_EnableInt (int ch); +int MXC_DMA_EnableInt(int ch); /** * @brief Disable channel interrupt * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_DisableInt (int ch); +int MXC_DMA_DisableInt(int ch); /** * @brief Start transfer @@ -359,14 +361,14 @@ int MXC_DMA_DisableInt (int ch); * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_Start (int ch); +int MXC_DMA_Start(int ch); /** * @brief Stop DMA transfer, irrespective of status (complete or in-progress) * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_Stop (int ch); +int MXC_DMA_Stop(int ch); /** * @brief Get a pointer to the DMA channel registers @@ -375,7 +377,7 @@ int MXC_DMA_Stop (int ch); * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise */ -mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch); +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function @@ -400,7 +402,7 @@ void MXC_DMA_Handler(); * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous @@ -413,7 +415,8 @@ int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callba * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver */ @@ -423,4 +426,4 @@ int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, m } #endif -#endif /* _DMA_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h index adafe86b0a4..ce7d144711a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h @@ -4,8 +4,8 @@ * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,10 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FLC_H_ -#define _FLC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_ /* **** Includes **** */ #include "flc_regs.h" @@ -58,10 +58,10 @@ extern "C" { /***** Definitions *****/ /// Bit mask that can be used to find the starting address of a page in flash -#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) +#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) /// Calculate the address of a page in flash from the page number -#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) +#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE)) /***** Function Prototypes *****/ @@ -77,14 +77,14 @@ int MXC_FLC_Init(); * with an erase or write operation. * @return If non-zero, flash operation is in progress */ -int MXC_FLC_Busy (void); +int MXC_FLC_Busy(void); /** * @brief Erases the entire flash array. * @note This function must be executed from RAM. * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_MassErase (void); +int MXC_FLC_MassErase(void); /** * @brief Erases the page of flash at the specified address. @@ -92,7 +92,7 @@ int MXC_FLC_MassErase (void); * @param address Any address within the page to erase. * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_PageErase (uint32_t address); +int MXC_FLC_PageErase(uint32_t address); /** * @brief Read Data out of Flash from an address @@ -102,7 +102,7 @@ int MXC_FLC_PageErase (uint32_t address); * @param[in] len The length of the buffer * */ -void MXC_FLC_Read (int address, void* buffer, int len); +void MXC_FLC_Read(int address, void *buffer, int len); /** * @brief Writes data to flash. @@ -113,7 +113,7 @@ void MXC_FLC_Read (int address, void* buffer, int len); * @return #E_NO_ERROR If function is successful. * @note make sure to disable ICC with ICC_Disable(); before Running this function */ -int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer); +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer); /** * @brief Writes 32 bits of data to flash. @@ -123,7 +123,7 @@ int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer); * @return #E_NO_ERROR If function is successful. * @note make sure to disable ICC with ICC_Disable(); before Running this function */ -int MXC_FLC_Write32 (uint32_t address, uint32_t data); +int MXC_FLC_Write32(uint32_t address, uint32_t data); /** * @brief Writes 128 bits of data to flash. @@ -133,27 +133,27 @@ int MXC_FLC_Write32 (uint32_t address, uint32_t data); * @return #E_NO_ERROR If function is successful. * @note make sure to disable ICC with ICC_Disable(); before Running this function */ -int MXC_FLC_Write128 (uint32_t address, uint32_t *data); +int MXC_FLC_Write128(uint32_t address, uint32_t *data); /** * @brief Enable flash interrupts * @param flags Interrupts to enable * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_EnableInt (uint32_t flags); +int MXC_FLC_EnableInt(uint32_t flags); /** * @brief Disable flash interrupts * @param flags Interrupts to disable * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_DisableInt (uint32_t flags); +int MXC_FLC_DisableInt(uint32_t flags); /** * @brief Retrieve flash interrupt flags * @return Interrupt flags registers */ -int MXC_FLC_GetFlags (void); +int MXC_FLC_GetFlags(void); /** * @brief Clear flash interrupt flags @@ -161,7 +161,7 @@ int MXC_FLC_GetFlags (void); * @param flags Flag bit(s) to clear * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_ClearFlags (uint32_t flags); +int MXC_FLC_ClearFlags(uint32_t flags); /** * @brief Unlock info block @@ -170,7 +170,7 @@ int MXC_FLC_ClearFlags (uint32_t flags); * * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_UnlockInfoBlock (uint32_t address); +int MXC_FLC_UnlockInfoBlock(uint32_t address); /** * @brief Lock info block @@ -178,7 +178,7 @@ int MXC_FLC_UnlockInfoBlock (uint32_t address); * @param[in] address The address in the info block that was written to * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_LockInfoBlock (uint32_t address); +int MXC_FLC_LockInfoBlock(uint32_t address); /**@} end of group flc */ @@ -186,4 +186,4 @@ int MXC_FLC_LockInfoBlock (uint32_t address); } #endif -#endif /* _FLC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h index 28b81a266e2..c24a72dbb3a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h @@ -3,8 +3,8 @@ * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _GPIO_H_ -#define _GPIO_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_ /* **** Includes **** */ #include "gpio_regs.h" @@ -62,27 +62,27 @@ extern "C" { * @ingroup gpio_port_pin * @{ */ -#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define +#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define /**@} end of gpio_port group*/ /** * @defgroup gpio_pin Pin Definitions * @ingroup gpio_port_pin * @{ */ -#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define -#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define -#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define -#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define -#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define -#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define -#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define -#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define -#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define -#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define -#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define -#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define -#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define -#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define +#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define +#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define +#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define +#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define +#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define +#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define +#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define +#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define +#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define +#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define +#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define +#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define +#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define +#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define /**@} end of gpio_pin group */ /**@} end of gpio_port_pin group */ @@ -94,65 +94,65 @@ extern "C" { * @param cbdata A void pointer to the data type as registered when * MXC_GPIO_RegisterCallback() was called. */ -typedef void (*mxc_gpio_callback_fn) (void *cbdata); +typedef void (*mxc_gpio_callback_fn)(void *cbdata); /** * @brief Enumeration type for the GPIO Function Type */ typedef enum { - MXC_GPIO_FUNC_IN, ///< GPIO Input - MXC_GPIO_FUNC_OUT, ///< GPIO Output - MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection - MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection - MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection - MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection + MXC_GPIO_FUNC_IN, ///< GPIO Input + MXC_GPIO_FUNC_OUT, ///< GPIO Output + MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection } mxc_gpio_func_t; /** * @brief Enumeration type for the voltage level on a given pin. */ typedef enum { - MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage - MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage + MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage + MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage } mxc_gpio_vssel_t; /** * @brief Enumeration type for the type of GPIO pad on a given pin. */ typedef enum { - MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down - MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up - MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down + MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down + MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up + MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down } mxc_gpio_pad_t; /** * @brief Structure type for configuring a GPIO port. */ typedef struct { - mxc_gpio_regs_t* port; ///< Pointer to GPIO regs - uint32_t mask; ///< Pin mask (multiple pins may be set) - mxc_gpio_func_t func; ///< Function type - mxc_gpio_pad_t pad; ///< Pad type - mxc_gpio_vssel_t vssel; ///< Voltage select + mxc_gpio_regs_t *port; ///< Pointer to GPIO regs + uint32_t mask; ///< Pin mask (multiple pins may be set) + mxc_gpio_func_t func; ///< Function type + mxc_gpio_pad_t pad; ///< Pad type + mxc_gpio_vssel_t vssel; ///< Voltage select } mxc_gpio_cfg_t; /** * @brief Enumeration type for the interrupt modes. */ typedef enum { - MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive - MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive + MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive + MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive } mxc_gpio_int_mode_t; /** * @brief Enumeration type for the interrupt polarity. */ typedef enum { - MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge - MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high - MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge - MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low - MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge + MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge + MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high + MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge + MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low + MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; /* **** Function Prototypes **** */ @@ -162,28 +162,28 @@ typedef enum { * @param portMask Mask for the port to be initialized * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Init (uint32_t portMask); +int MXC_GPIO_Init(uint32_t portMask); /** * @brief Shutdown GPIO. * @param portMask Mask for the port to be initialized * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Shutdown (uint32_t portMask); +int MXC_GPIO_Shutdown(uint32_t portMask); /** * @brief Reset GPIO. * @param portMask Mask for the port to be initialized * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Reset (uint32_t portMask); +int MXC_GPIO_Reset(uint32_t portMask); /** * @brief Configure GPIO pin(s). * @param cfg Pointer to configuration structure describing the pin. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg); +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg); /** * @brief Gets the pin(s) input state. @@ -191,21 +191,21 @@ int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg); * @param mask Mask of the pin(s) to read * @return The requested pin state. */ -uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask); +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Sets the pin(s) to a high level output. * @param port Pointer to the GPIO port registers * @param mask Mask of the pin(s) to set */ -void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Clears the pin(s) to a low level output. * @param port Pointer to the GPIO port registers * @param mask Mask of the pin(s) to clear */ -void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Gets the pin(s) output state. @@ -214,7 +214,7 @@ void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask); * @return The state of the requested pin. * */ -uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask); +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Write the pin(s) to a desired output level. @@ -223,14 +223,14 @@ uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask); * @param val Desired output level of the pin(s). This will be masked * with the configuration mask. */ -void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val); +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val); /** * @brief Toggles the the pin(s) output level. * @param port Pointer to the GPIO port registers * @param mask Mask of the pin(s) to toggle */ -void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Configure GPIO interrupt(s) @@ -238,7 +238,7 @@ void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask); * @param pol Requested interrupt polarity. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); /** * @brief Enables the specified GPIO interrupt @@ -246,14 +246,14 @@ int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); * @param mask Mask of the pin(s) to enable interrupts for * */ -void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Disables the specified GPIO interrupt. * @param port Pointer to the GPIO port registers * @param mask Mask of the pin(s) to disable interrupts for */ -void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Gets the interrupt(s) status on a GPIO port @@ -262,7 +262,7 @@ void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask); * * @return The requested interrupt status. */ -uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port); +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port); /** * @brief Gets the interrupt(s) status on a GPIO port @@ -270,7 +270,7 @@ uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port); * @param port Pointer to the port requested * @param flags The flags to clear */ -void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags); +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags); /** * @brief Registers a callback for the interrupt on a given port and pin. @@ -279,7 +279,8 @@ void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags); * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs. * */ -void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, + void *cbdata); /** * @brief GPIO IRQ Handler. @note If a callback is registered for a given @@ -288,7 +289,7 @@ void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn * @param port Number of the port that generated the interrupt service routine. * */ -void MXC_GPIO_Handler (unsigned int port); +void MXC_GPIO_Handler(unsigned int port); /** * @brief Set Voltage select for pins to VDDIO or VDDIOH @@ -299,7 +300,32 @@ void MXC_GPIO_Handler (unsigned int port); * * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask); + +/** + * @brief Enables GPIO pins to be used as a wakeup source. + * + * @param port The GPIO port + * @param mask Pins in the GPIO port that will be enabled as a wakeup source. + */ +void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Disables GPIO pins from being used as a wakeup source. + * + * @param port The GPIO port + * @param mask Pins in the GPIO port that will be disabled as a wakeup source. + */ +void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Returns the pins currently enabled as wakeup sources. + * + * @param port The GPIO port to check. + * + * @returns The value of the wake enable register. + */ +uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); /**@} end of group gpio */ @@ -307,4 +333,4 @@ int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t m } #endif -#endif /* _GPIO_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h index 9ad334617bf..95f5b3c803c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h @@ -3,8 +3,8 @@ * @brief I2S (Inter-Integrated Sound) driver function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,10 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _I2S_H_ -#define _I2S_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_ /* **** Includes **** */ #include "mxc_sys.h" @@ -62,7 +62,7 @@ typedef enum { } mxc_i2s_sys_map_t; typedef enum { - LEFT_JUSTIFIED= 0, + LEFT_JUSTIFIED = 0, RIGHT_JUSTIFIED = 1, } mxc_i2s_justify_t; @@ -77,21 +77,20 @@ typedef enum { AUDIO_IN = 2, } mxc_i2s_direction_t; - /** @brief I2S Configuration Struct */ typedef struct { - mxc_i2s_sys_map_t map; - mxc_i2s_justify_t justify; - mxc_i2s_audio_mode_t audio_mode; - mxc_i2s_direction_t audio_direction; - uint16_t sample_rate; - unsigned int start_immediately; - unsigned int dma_reload_en; - void *src_addr; - void *dst_addr; - uint32_t length; + mxc_i2s_sys_map_t map; + mxc_i2s_justify_t justify; + mxc_i2s_audio_mode_t audio_mode; + mxc_i2s_direction_t audio_direction; + uint16_t sample_rate; + unsigned int start_immediately; + unsigned int dma_reload_en; + void *src_addr; + void *dst_addr; + uint32_t length; } mxc_i2s_config_t; - + /* **** Function Prototypes **** */ /** @@ -101,62 +100,62 @@ typedef struct { * @param dma_ctz_cb Function pointer to Count-to-Zero callback function. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int)); +int MXC_I2S_Init(const mxc_i2s_config_t *config, void (*dma_ctz_cb)(int, int)); /** * @brief Release I2S * @details De-configures the I2S protocol and stops DMA request * @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise - */ + */ int MXC_I2S_Shutdown(void); /** * @brief Mute I2S Output * @details Sets I2S data to zero, continues sending clock and accessing DMA * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_Mute(void); /** * @brief Unmute I2S Output * @details Restores I2S data * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_Unmute(void); /** * @brief Pause I2S Output * @details Similar to mute, but stops FIFO and DMA access, clocks continue * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_Pause(void); /** * @brief Unpause I2S Output * @details Similar to mute, but restarts FIFO and DMA access * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_Unpause(void); /** * @brief Stops I2S Output * @details Similar to pause, but also halts clock * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_Stop(void); /** * @brief Starts I2S Output * @details Starts I2S Output, automatically called by configure if requested * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_Start(void); /** * @brief Clears DMA Interrupt Flags * @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_DMA_ClearFlags(void); /** @@ -167,7 +166,7 @@ int MXC_I2S_DMA_ClearFlags(void); * @details Sets the address to read/write data in memory and the length of * the transfer. The unused addr parameter is ignored. * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count); /** @@ -179,13 +178,12 @@ int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count); * (a CTZ event occurs) the src, dst, and count registers will be * set to these. The DMA reload flag clears after a reload occurs. * @return \c #E_NO_ERROR - */ + */ int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count); /**@} end of group i2s */ - #ifdef __cplusplus } #endif -#endif /* _I2S_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h index fb7a6bc0710..1e5b3a1995a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h @@ -3,8 +3,8 @@ * @brief Instruction Controller Cache(ICC) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _ICC_H_ -#define _ICC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_ /* **** Includes **** */ #include @@ -58,9 +58,9 @@ extern "C" { * @brief Enumeration type for the Cache ID Register */ typedef enum { - ICC_INFO_RELNUM, ///< Identifies the RTL release version - ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number - ICC_INFO_ID ///< Specifies the value of Cache ID + ICC_INFO_RELNUM, ///< Identifies the RTL release version + ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number + ICC_INFO_ID ///< Specifies the value of Cache ID } mxc_icc_info_t; /** @@ -68,22 +68,22 @@ typedef enum { * @param cid Enumeration type for Cache Id Register. * @retval Returns the contents of Cache Id Register. */ -int MXC_ICC_ID (mxc_icc_info_t cid); +int MXC_ICC_ID(mxc_icc_info_t cid); /** * @brief Enable the instruction cache controller. */ -void MXC_ICC_Enable (void); +void MXC_ICC_Enable(void); /** * @brief Disable the instruction cache controller. */ -void MXC_ICC_Disable (void); +void MXC_ICC_Disable(void); /** * @brief Flush the instruction cache controller. */ -void MXC_ICC_Flush (void); +void MXC_ICC_Flush(void); /**@} end of group icc */ @@ -91,4 +91,4 @@ void MXC_ICC_Flush (void); } #endif -#endif /* _ICC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h index ead39aea0a8..a92e07b9bd4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h @@ -3,9 +3,8 @@ * @brief Low power function prototypes and data types. */ - -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,16 +34,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $ - * $Revision: 38105 $ - * - *************************************************************************** */ + ******************************************************************************/ // Define to prevent redundant inclusion -#ifndef _LP_H_ -#define _LP_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_ /***** Includes *****/ +#include "gpio.h" #include "pwrseq_regs.h" #ifdef __cplusplus @@ -59,9 +56,9 @@ extern "C" { /** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */ typedef enum { - MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */ - MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */ - MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */ + MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */ + MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */ + MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */ } mxc_lp_ovr_t; /** @@ -163,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void); * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. * Call this function multiple times to enable pins on multiple ports. This function does not configure * the GPIO pins nor does it setup their interrupt functionality. - * @param port The port to configure as wakeup sources. - * @param mask The pins to configure as wakeup sources. + * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. */ -void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask); +void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins); /** * @brief Disables the selected GPIO port and its selected pins as a wake up source. * Call this function multiple times to disable pins on multiple ports. - * @param port The port to configure as wakeup sources. - * @param mask The pins to configure as wakeup sources. + * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. */ -void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask); +void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins); /** * @brief Enables the RTC alarm to wake up the device from any low power mode. @@ -327,7 +324,6 @@ void MXC_LP_EnableVCoreSVM(void); */ void MXC_LP_DisableVCoreSVM(void); - /** * @brief Enables VDDIO Power-On-Reset Monitor */ @@ -343,4 +339,4 @@ void MXC_LP_DisableVDDIOPorMonitor(void); } #endif -#endif /* _LP_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h index cc919767d6c..a74731f671d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h @@ -1,36 +1,35 @@ -/******************************************************************************* -* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a -* copy of this software and associated documentation files (the "Software"), -* to deal in the Software without restriction, including without limitation -* the rights to use, copy, modify, merge, publish, distribute, sublicense, -* and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included -* in all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES -* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -* OTHER DEALINGS IN THE SOFTWARE. -* -* Except as contained in this notice, the name of Maxim Integrated -* Products, Inc. shall not be used except as stated in the Maxim Integrated -* Products, Inc. Branding Policy. -* -* The mere transfer of this software does not imply any licenses -* of trade secrets, proprietary technology, copyrights, patents, -* trademarks, maskwork rights, or any other form of intellectual -* property whatsoever. Maxim Integrated Products, Inc. retains all -* ownership rights. -* -******************************************************************************** -*/ +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + ******************************************************************************/ /** * \file @@ -42,60 +41,64 @@ * prototypes. */ -#ifndef _MSR_H_ -#define _MSR_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_ + +#ifdef __cplusplus +extern "C" { +#endif /***** Definitions *****/ /// Number of tracks on a card #ifndef MSR_NUM_TRACKS -#define MSR_NUM_TRACKS 3 +#define MSR_NUM_TRACKS 3 #endif -#define MSR_MAX_SAMPLES 1536 +#define MSR_MAX_SAMPLES 1536 // Assuming nominal bit density of 210 bpi and 3.375 inch length -#define MSR_MAX_RAW_LEN_BITS (709) -#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8) +#define MSR_MAX_RAW_LEN_BITS (709) +#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8) #define MSR_MAX_RAW_LEN_HALFWORDS ((MSR_MAX_RAW_LEN_BITS + 15) / 16) /// Maximum size in bytes of decoded track characters (5-bit min to 8-bit max) -#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5) +#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5) /// Swipe direction: the card was swiped in the forward direction -#define MSR_FORWARD 0 +#define MSR_FORWARD 0 /// Swipe direction: the card was swiped in the reverse direction -#define MSR_REVERSE 1 +#define MSR_REVERSE 1 /// Error codes -#define MSR_ERR_OK 0x00 -#define MSR_ERR_BAD_LEN 0x01 -#define MSR_ERR_START_SEN 0x02 -#define MSR_ERR_END_SEN 0x04 -#define MSR_ERR_OUTLIER 0x08 -#define MSR_ERR_PARAM 0x10 -#define MSR_ERR_LRC 0x40 -#define MSR_ERR_PARITY 0x80 +#define MSR_ERR_OK 0x00 +#define MSR_ERR_BAD_LEN 0x01 +#define MSR_ERR_START_SEN 0x02 +#define MSR_ERR_END_SEN 0x04 +#define MSR_ERR_OUTLIER 0x08 +#define MSR_ERR_PARAM 0x10 +#define MSR_ERR_LRC 0x40 +#define MSR_ERR_PARITY 0x80 /// Structure to contain result of a track decode typedef struct { - uint8_t error_code; /**< Error code value */ - uint8_t parity_errs; /**< Number of characters with parity errors */ - uint8_t lrc; /**< LRC check value. A value of '0' indicates a - successful LRC check. Any other value should be - considered a failure. */ - uint8_t direction; /**< Swipe direction determined from decode */ - uint8_t len; /**< Number or decoded characters. This does not include - the sentinels or the LRC. */ + uint8_t error_code; ///< Error code value + uint8_t parity_errs; ///< Number of characters with parity errors + uint8_t lrc; ///< LRC check value. A value of '0' indicates a + /// successful LRC check. Any other value should be + /// considered a failure. + uint8_t direction; ///< Swipe direction determined from decode + uint8_t len; ///< Number or decoded characters. This does not include + /// the sentinels or the LRC. uint16_t speed; - uint8_t data[MSR_MAX_DEC_LEN]; /**< The decoded data */ + uint8_t data[MSR_MAX_DEC_LEN]; ///< The decoded data } msr_decoded_track_t; /// MSR sample fields typedef union { struct { uint16_t time : 9; - uint16_t amp : 7; + uint16_t amp : 7; }; uint16_t value; } msr_sample_t; @@ -112,25 +115,25 @@ typedef struct { * \brief Initializes magnetic card reader hardware * \returns #E_NO_ERROR if everything is successful */ -int msr_init (void); +int msr_init(void); /** * \brief Initializes specified track * \param track track number (1 to 3) */ -void msr_init_track (unsigned int track); +void msr_init_track(unsigned int track); /** * \brief Enables magnetic card reader * \pre The reader should be initialized by calling msr_init() and then * waiting at least 100 us before calling this function. */ -void msr_enable (void); +void msr_enable(void); /** * \brief Disables magnetic card reader */ -void msr_disable (void); +void msr_disable(void); /** * \brief Task used to execute driver functionality. @@ -139,7 +142,7 @@ void msr_disable (void); * when MSR interrupt servicing is disabled. * \returns 1 if all tracking reading is complete, 0 otherwise */ -int msr_task (void); +int msr_task(void); /** * \brief Decodes the specified track of data @@ -148,7 +151,7 @@ int msr_task (void); * \returns number of characters decoded * \note This function has significant stack usage. */ -unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded_track); +unsigned int msr_track_decode(unsigned int track, msr_decoded_track_t *decoded_track); /** * \brief Registers an application callback function @@ -158,7 +161,7 @@ unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded * function function with a NULL parameter. * \param func application callback function */ -void msr_set_complete_callback (void (*func) (void)); +void msr_set_complete_callback(void (*func)(void)); /** * \brief Retrieves the raw (undecoded) sample data for the specified track @@ -167,7 +170,10 @@ void msr_set_complete_callback (void (*func) (void)); * \param samples pointer to where the sample data will be copied * \returns number of samples retrieved */ -unsigned int mcr_get_track_samples (unsigned int track, msr_samples_t * samples); +unsigned int mcr_get_track_samples(unsigned int track, msr_samples_t *samples); -#endif /* _MSR_H_ */ +#ifdef __cplusplus +} +#endif +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h index b77a9b87647..aee4588ebd6 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h @@ -3,8 +3,8 @@ * @brief Assertion checks for debugging. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,15 +34,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_ASSERT_H_ -#define _MXC_ASSERT_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_ /* **** Includes **** */ - #ifdef __cplusplus extern "C" { #endif @@ -65,11 +64,10 @@ extern "C" { * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * defined. */ -#define MXC_ASSERT(expr) \ -if (!(expr)) \ -{ \ - mxc_assert(#expr, __FILE__, __LINE__); \ -} +#define MXC_ASSERT(expr) \ + if (!(expr)) { \ + mxc_assert(#expr, __FILE__, __LINE__); \ + } /** * Macro that generates an assertion with the message "FAIL". * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be @@ -98,7 +96,7 @@ if (!(expr)) \ * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * defined. */ -void mxc_assert (const char *expr, const char *file, int line); +void mxc_assert(const char *expr, const char *file, int line); /**@} end of group MXC_Assertions*/ @@ -106,4 +104,4 @@ void mxc_assert (const char *expr, const char *file, int line); } #endif -#endif /* _MXC_ASSERT_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h index d2db0f1a068..c4957b67e77 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h @@ -3,8 +3,8 @@ * @brief Asynchronous delay routines based on the SysTick Timer. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,17 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _DELAY_H_ -#define _DELAY_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif /** * @ingroup devicelibs @@ -54,21 +60,21 @@ * x = SEC(3) // 3 seconds -> x = 3,000,000 * \endcode */ -#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL) +#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL) /** * Macro used to specify a microsecond timing parameter in milliseconds. * \code * x = MSEC(3) // 3ms -> x = 3,000 * \endcode */ -#define MXC_DELAY_MSEC(ms) (ms * 1000UL) +#define MXC_DELAY_MSEC(ms) (ms * 1000UL) /** * Macro used to specify a microsecond timing parameter. * \code * x = USEC(3) // 3us -> x = 3 * \endcode */ -#define MXC_DELAY_USEC(us) (us) +#define MXC_DELAY_USEC(us) (us) /** * @brief The callback routine used by MXC_DelayAsync() when the delay is complete @@ -76,7 +82,7 @@ * * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_delay_complete_t) (int result); +typedef void (*mxc_delay_complete_t)(int result); /***** Function Prototypes *****/ @@ -88,7 +94,7 @@ typedef void (*mxc_delay_complete_t) (int result); * @param us microseconds to delay * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. */ -int MXC_Delay (unsigned long us); +int MXC_Delay(uint32_t us); /** * @brief Starts a non-blocking delay for the specified number of @@ -103,28 +109,32 @@ int MXC_Delay (unsigned long us); * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another * delay request. */ -int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback); +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback); /** * @brief Returns the status of a non-blocking delay request * @pre Start the asynchronous delay by calling MXC_Delay_start(). * @return #E_BUSY until the requested delay time has expired. */ -int MXC_DelayCheck (void); +int MXC_DelayCheck(void); /** * @brief Stops an asynchronous delay previously started. * @pre Start the asynchronous delay by calling MXC_Delay_start(). */ -void MXC_DelayAbort (void); +void MXC_DelayAbort(void); /** * @brief Processes the delay interrupt. * @details This function must be called from the SysTick IRQ or polled at a * rate greater than the SysTick overflow rate. */ -void MXC_DelayHandler (void); +void MXC_DelayHandler(void); /**@} end of group MXC_delay */ -#endif /* _DELAY_H_ */ +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h index d0be9b60789..5d80f0c3599 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h @@ -1,5 +1,5 @@ -/******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,46 +29,42 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * ******************************************************************************/ /** * @file mxc_device.h * @brief contains device and revision specific definitions */ - -#ifndef _MXC_DEVICE_H_ -#define _MXC_DEVICE_H_ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_ #include "max32660.h" #include "mxc_errors.h" - #ifndef TARGET - #error TARGET NOT DEFINED +#error TARGET NOT DEFINED #endif // Create a string definition for the TARGET #define STRING_ARG(arg) #arg #define STRING_NAME(name) STRING_ARG(name) -#if MBED_VERSION && MBED_VERSION < 51200 #define TARGET_NAME STRING_NAME(TARGET) -#endif // Define which revisions of the IP we are using #ifndef TARGET_REV - #error TARGET_REV NOT DEFINED +#error TARGET_REV NOT DEFINED #endif -#if(TARGET_REV == 0x4131) - // A1 - #define MXC_PBM_REV 0 - #define MXC_TMR_REV 0 - #define MXC_UART_REV 1 +#if (TARGET_REV == 0x4131) +// A1 +#define MXC_PBM_REV 0 +#define MXC_TMR_REV 0 +#define MXC_UART_REV 1 #else #error TARGET_REV NOT SUPPORTED -#endif // if(TARGET_REV == ...) +#endif // if(TARGET_REV == ...) -#endif /* _MXC_DEVICE_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h index f2afb9a7e90..38b76c5f919 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h @@ -3,8 +3,8 @@ * @brief List of common error return codes for Maxim Integrated libraries. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_ERRORS_H_ -#define _MXC_ERRORS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_ /** * @ingroup syscfg @@ -50,43 +50,45 @@ */ /** No Error */ -#define E_NO_ERROR 0 +#define E_NO_ERROR 0 /** No Error, success */ -#define E_SUCCESS 0 +#define E_SUCCESS 0 /** Pointer is NULL */ -#define E_NULL_PTR -1 +#define E_NULL_PTR -1 /** No such device */ -#define E_NO_DEVICE -2 +#define E_NO_DEVICE -2 /** Parameter not acceptable */ -#define E_BAD_PARAM -3 +#define E_BAD_PARAM -3 /** Value not valid or allowed */ -#define E_INVALID -4 +#define E_INVALID -4 /** Module not initialized */ -#define E_UNINITIALIZED -5 +#define E_UNINITIALIZED -5 /** Busy now, try again later */ -#define E_BUSY -6 +#define E_BUSY -6 /** Operation not allowed in current state */ -#define E_BAD_STATE -7 +#define E_BAD_STATE -7 /** Generic error */ -#define E_UNKNOWN -8 +#define E_UNKNOWN -8 /** General communications error */ -#define E_COMM_ERR -9 +#define E_COMM_ERR -9 /** Operation timed out */ -#define E_TIME_OUT -10 +#define E_TIME_OUT -10 /** Expected response did not occur */ -#define E_NO_RESPONSE -11 +#define E_NO_RESPONSE -11 /** Operations resulted in unexpected overflow */ -#define E_OVERFLOW -12 +#define E_OVERFLOW -12 /** Operations resulted in unexpected underflow */ -#define E_UNDERFLOW -13 +#define E_UNDERFLOW -13 /** Data or resource not available at this time */ -#define E_NONE_AVAIL -14 +#define E_NONE_AVAIL -14 /** Event was shutdown */ -#define E_SHUTDOWN -15 +#define E_SHUTDOWN -15 /** Event was aborted */ -#define E_ABORT -16 +#define E_ABORT -16 /** The requested operation is not supported */ -#define E_NOT_SUPPORTED -17 +#define E_NOT_SUPPORTED -17 +/** The requested operation is failed */ +#define E_FAIL -255 /**@} end of MXC_Error_Codes group */ -#endif /* _MXC_ERRORS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h index 76bbd083032..589940b7c7b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h @@ -3,8 +3,8 @@ * @brief Inter-integrated circuit (I2C) communications interface driver. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_I2C_H_ -#define _MXC_I2C_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_ #include #include "mxc_sys.h" @@ -69,7 +69,7 @@ typedef struct _i2c_req_t mxc_i2c_req_t; * @return 0 if the byte should not be acknowledged (NACK), non-zero to * acknowledge the byte. */ -typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte); +typedef int (*mxc_i2c_getAck_t)(mxc_i2c_regs_t *i2c, unsigned char byte); /** * @brief The callback routine used by the MXC_I2C_MasterTransactionAsync() @@ -80,7 +80,7 @@ typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte); * transmitted is not acknowledged, negative if error. * See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result); +typedef void (*mxc_i2c_complete_cb_t)(mxc_i2c_req_t *req, int result); /** * @brief The callback routine used by the I2C Read/Write FIFO DMA @@ -89,7 +89,7 @@ typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result); * @param len The length of data actually read/written * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result); +typedef void (*mxc_i2c_dma_complete_cb_t)(int len, int result); /** * @brief The information required to perform a complete I2C transaction as @@ -100,22 +100,22 @@ typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result); * MXC_I2C_MasterTransactionAsync() functions. */ struct _i2c_req_t { - mxc_i2c_regs_t* i2c; ///< Pointer to I2C registers (selects the + mxc_i2c_regs_t *i2c; ///< Pointer to I2C registers (selects the ///< I2C block used.) - unsigned int addr; ///< The 7-bit or 10-bit address of the slave. - unsigned char* tx_buf; ///< The buffer containing the bytes to write. - unsigned int tx_len; ///< The number of bytes to write. On return + unsigned int addr; ///< The 7-bit or 10-bit address of the slave. + unsigned char *tx_buf; ///< The buffer containing the bytes to write. + unsigned int tx_len; ///< The number of bytes to write. On return ///< from the function, this will be set to ///< the number of bytes actually transmitted. - unsigned char* rx_buf; ///< The buffer to read the data into. - unsigned int rx_len; ///< The number of bytes to read. On return + unsigned char *rx_buf; ///< The buffer to read the data into. + unsigned int rx_len; ///< The number of bytes to read. On return ///< from the function, this will be set to ///< the number of bytes actually received. - int restart; ///< Controls whether the transaction is + int restart; ///< Controls whether the transaction is ///< terminated with a stop or repeated start ///< condition. Use 0 for a stop, non-zero ///< for repeated start. - mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the + mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the ///< transaction is complete or an error has ///< occurred. This field may be set to NULL ///< if no indication is necessary. This @@ -134,18 +134,18 @@ struct _i2c_req_t { * application to handle these events. */ typedef enum { - MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master + MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master ///< requesting a write to the slave. - MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master + MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master ///< requesting a read from the slave. - MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its + MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its ///< threshold level. - MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its + MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its ///< threshold level. MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended. - MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the + MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the ///< transmit FIFO was empty. - MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive + MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive ///< FIFO was already full. } mxc_i2c_slave_event_t; @@ -165,9 +165,9 @@ typedef enum { * non-zero to not acknowledge. The return value is ignored for all * other event types. */ -typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c, - mxc_i2c_slave_event_t event, void* data); - +typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event, + void *data); + /***** Function Prototypes *****/ /* ************************************************************************* */ @@ -188,7 +188,7 @@ typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c, * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr); /** * @brief Set slave address for I2C instances acting as slaves on the bus. @@ -202,7 +202,7 @@ int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx); /** * @brief Disable and shutdown I2C peripheral. @@ -211,7 +211,7 @@ int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c); +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c); /** * @brief Set the frequency of the I2C interface. @@ -222,7 +222,7 @@ int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c); * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz); +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz); /** * @brief Get the frequency of the I2C interface. @@ -231,7 +231,7 @@ int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz); * * @return The I2C bus frequency in Hertz */ -unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c); /** * @brief Checks if the given I2C bus can be placed in sleep more. @@ -245,7 +245,7 @@ unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c); * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c); +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c); /** * @brief Enables or disables clock stretching by the slave. @@ -258,7 +258,7 @@ int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable); +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable); /** * @brief Determines if clock stretching has been enabled. @@ -267,7 +267,7 @@ int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable); * * @return Zero if clock stretching is disabled, non-zero otherwise */ -int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c); +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c); /* ************************************************************************* */ /* Low-level functions */ @@ -284,7 +284,7 @@ int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Start (mxc_i2c_regs_t* i2c); +int MXC_I2C_Start(mxc_i2c_regs_t *i2c); /** * @brief Generate a stop condition on the I2C bus. @@ -293,7 +293,7 @@ int MXC_I2C_Start (mxc_i2c_regs_t* i2c); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Stop (mxc_i2c_regs_t* i2c); +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c); /** * @brief Write a single byte to the I2C bus. @@ -310,7 +310,7 @@ int MXC_I2C_Stop (mxc_i2c_regs_t* i2c); * @return 0 if byte is acknowledged, 1 if not acknowledged, negative if * error. See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte); +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte); /** * @brief Read a single byte from the I2C bus. @@ -326,7 +326,7 @@ int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack); +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack); /** * @brief Read a single byte from the I2C bus. @@ -350,9 +350,8 @@ int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte, - mxc_i2c_getAck_t getAck); - +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck); + /** * @brief Write multiple bytes to the I2C bus. * @@ -370,7 +369,7 @@ int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte, * acknowledged, negative if error. See \ref MXC_Error_Codes for the * list of error return codes. */ -int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len); +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len); /** * @brief Read multiple bytes from the I2C bus. @@ -389,9 +388,8 @@ int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len) * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, - int ack); - +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); + /** * @brief Unloads bytes from the receive FIFO. * @@ -401,9 +399,8 @@ int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, * * @return The number of bytes actually read. */ -int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, - unsigned int len); - +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + /** * @brief Unloads bytes from the receive FIFO using DMA for longer reads. * @@ -416,9 +413,9 @@ int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, * * @return See \ref MXC_Error_Codes for a list of return values. */ -int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, - unsigned int len, mxc_i2c_dma_complete_cb_t callback); - +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + /** * @brief Get the number of bytes currently available in the receive FIFO. * @@ -426,7 +423,7 @@ int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, * * @return The number of bytes available. */ -int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c); +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c); /** * @brief Loads bytes into the transmit FIFO. @@ -437,9 +434,8 @@ int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c); * * @return The number of bytes actually written. */ -int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, - unsigned int len); - +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes. * @@ -451,9 +447,9 @@ int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, - unsigned int len, mxc_i2c_dma_complete_cb_t callback); - +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + /** * @brief Get the amount of free space available in the transmit FIFO. * @@ -461,21 +457,21 @@ int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, * * @return The number of bytes available. */ -int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c); +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c); /** * @brief Removes and discards all bytes currently in the receive FIFO. * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c); +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c); /** * @brief Removes and discards all bytes currently in the transmit FIFO. * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c); +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c); /** * @brief Get the presently set interrupt flags. @@ -486,7 +482,7 @@ void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c); * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); /** * @brief Clears the Interrupt Flags. @@ -495,7 +491,7 @@ int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *f * @param flags0 Flags to clear in the intfl0 interrupt register. * @param flags1 Flags to clear in the intfl1 interrupt register. */ -void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); /** * @brief Enable Interrupts. @@ -504,7 +500,7 @@ void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int * @param flags0 Interrupts to be enabled in int->en0 * @param flags1 Interrupts to be enabled in int->en1 */ -void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); /** * @brief Disable Interrupts. @@ -513,7 +509,7 @@ void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int f * @param flags0 Interrupts to be disabled in int->en0 * @param flags1 Interrupts to be disabled in int->en1 */ -void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); /** * @brief Enables the slave preload mode @@ -523,28 +519,28 @@ void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c); +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c); /** * @brief Disable the slave preload mode * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c); +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c); /** * @brief Enables the slave to respond to the general call address * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c); +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c); /** * @brief Prevents the slave from responding to the general call address * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c); +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c); /** * @brief Set the I2C Timeout @@ -558,7 +554,7 @@ void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout); +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout); /** * @brief Get the current I2C timeout @@ -567,7 +563,7 @@ void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout); * * @return The current timeout in uS */ -unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c); /** * @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle. @@ -593,7 +589,7 @@ unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries); +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries); /* ************************************************************************* */ /* Transaction level functions */ @@ -620,7 +616,7 @@ int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries); * acknowledged, negative if error. See \ref MXC_Error_Codes for the * list of error return codes. */ -int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req); +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req); /** * @brief Performs a non-blocking I2C Master transaction. @@ -647,7 +643,7 @@ int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req); +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req); /** * @brief Performs a non-blocking I2C Master transaction using DMA for reduced time @@ -675,7 +671,7 @@ int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req); +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req); /** * @brief Performs a blocking I2C Slave transaction. @@ -715,7 +711,7 @@ int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); /** * @brief Performs a non-blocking I2C Slave transaction. @@ -758,7 +754,7 @@ int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callb * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); /** * @brief Set the receive threshold level. @@ -781,7 +777,7 @@ int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); /** * @brief Get the current receive threshold level. @@ -790,7 +786,7 @@ int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); * * @return The receive threshold value (in bytes). */ -unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c); /** * @brief Set the transmit threshold level. @@ -814,7 +810,7 @@ unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); /** * @brief Get the current transmit threshold level. @@ -823,7 +819,17 @@ int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); * * @return The transmit threshold value (in bytes). */ -unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c); + +/** + * @brief Stop any asynchronous requests in progress. + * + * Stop any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be NOT executed. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c); /** * @brief Abort any asynchronous requests in progress. @@ -834,7 +840,7 @@ unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c); * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c); +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c); /** * @brief The processing function for asynchronous transactions. @@ -845,7 +851,7 @@ void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c); * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c); +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c); /** * @brief The processing function for DMA transactions. @@ -856,14 +862,12 @@ void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c); * @param ch DMA channel * @param error Error status */ -void MXC_I2C_DMACallback (int ch, int error); - +void MXC_I2C_DMACallback(int ch, int error); /**@} end of group i2c */ - #ifdef __cplusplus } #endif -#endif /* _MXC_I2C_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h index 455398a4de0..cd91bcd2b1b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h @@ -3,8 +3,8 @@ * @brief Exclusive access lock utility functions. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,16 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_LOCK_H_ -#define _MXC_LOCK_H_ - -// To enable disable this module -#define USE_LOCK_IN_DRIVERS 0 - -#if USE_LOCK_IN_DRIVERS +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ /* **** Includes **** */ #include "mxc_device.h" @@ -78,14 +73,14 @@ extern "C" { * * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. */ -int MXC_GetLock (uint32_t *lock, uint32_t value); +int MXC_GetLock(uint32_t *lock, uint32_t value); /** * @brief Free the given lock. * @param[in,out] lock Pointer to the variable used for the lock. When the lock * is free, the value pointed to by @p lock is set to zero. */ -void MXC_FreeLock (uint32_t *lock); +void MXC_FreeLock(uint32_t *lock); /**@} end of group mxc_lock_utilities */ @@ -93,12 +88,4 @@ void MXC_FreeLock (uint32_t *lock); } #endif - -#else // USE_LOCK_IN_DRIVERS - -#define MXC_GetLock(x, y) E_NO_ERROR -#define MXC_FreeLock(x) - -#endif // USE_LOCK_IN_DRIVERS - -#endif /* _MXC_LOCK_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h index 4fc112179c2..1d28443610c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h @@ -3,8 +3,8 @@ * @brief This file contains constant pin configurations for the peripherals. */ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,21 +34,16 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ - -#ifndef _MXC_PINS_H_ -#define _MXC_PINS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_ #include "gpio.h" /***** Global Variables *****/ -typedef enum { - MAP_A, - MAP_B, - MAP_C -} sys_map_t; +typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t; // Predefined GPIO Configurations extern const mxc_gpio_cfg_t gpio_cfg_swda; @@ -57,7 +52,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_swdb; extern const mxc_gpio_cfg_t gpio_cfg_i2c0; extern const mxc_gpio_cfg_t gpio_cfg_i2c1; - extern const mxc_gpio_cfg_t gpio_cfg_uart0; extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart1a; @@ -65,13 +59,9 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart1b; extern const mxc_gpio_cfg_t gpio_cfg_uart1c; extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; - extern const mxc_gpio_cfg_t gpio_cfg_spi0; -extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss; extern const mxc_gpio_cfg_t gpio_cfg_spi1a; -extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss; extern const mxc_gpio_cfg_t gpio_cfg_spi1b; -extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss; // Timers are only defined once, depending on package, each timer could be mapped to other pins extern const mxc_gpio_cfg_t gpio_cfg_tmr0; @@ -80,6 +70,4 @@ extern const mxc_gpio_cfg_t gpio_cfg_32kcal; extern const mxc_gpio_cfg_t gpio_cfg_i2s0a; extern const mxc_gpio_cfg_t gpio_cfg_i2s0b; - -#endif /* _MXC_PINS_H_ */ - +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h index fe4c440149c..6121e44de9e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h @@ -3,8 +3,8 @@ * @brief Serial Peripheral Interface (SPI) communications driver. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,9 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifndef _SPI_H_ -#define _SPI_H_ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_ /***** includes *******/ #include "spi_regs.h" @@ -46,6 +47,9 @@ #include "mxc_pins.h" #include "mxc_lock.h" +#ifdef __cplusplus +extern "C" { +#endif /***** Definitions *****/ @@ -76,10 +80,10 @@ * */ typedef enum { - SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex - SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex - SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex - SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex + SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex + SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex + SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex + SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex } mxc_spi_width_t; /** @@ -94,10 +98,10 @@ typedef enum { * */ typedef enum { - SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 - SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 - SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 - SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 + SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 + SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 + SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 + SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 } mxc_spi_mode_t; typedef struct _mxc_spi_req_t mxc_spi_req_t; @@ -108,7 +112,7 @@ typedef struct _mxc_spi_req_t mxc_spi_req_t; * @param req The details of the transaction. * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*spi_complete_cb_t) (void * req, int result); +typedef void (*spi_complete_cb_t)(void *req, int result); /** * @brief The information required to perform a complete SPI transaction @@ -117,23 +121,23 @@ typedef void (*spi_complete_cb_t) (void * req, int result); * @param "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. */ struct _mxc_spi_req_t { - mxc_spi_regs_t* spi; /// 8 bits, use two bytes per character ///< and pad the MSB of the upper byte with zeros - uint8_t *rxData; ///< Buffer to store received data For character sizes + uint8_t *rxData; ///< Buffer to store received data For character sizes ///< < 8 bits, pad the MSB of each byte with zeros. For ///< character sizes > 8 bits, use two bytes per character ///< and pad the MSB of the upper byte with zeros - uint32_t txLen; ///< Number of bytes to be sent from txData - uint32_t rxLen; ///< Number of bytes to be stored in rxData - uint32_t txCnt; ///< Number of bytes actually transmitted from txData - uint32_t rxCnt; ///< Number of bytes stored in rxData + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + uint32_t txCnt; ///< Number of bytes actually transmitted from txData + uint32_t rxCnt; ///< Number of bytes stored in rxData - spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete + spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete }; /* ************************************************************************* */ @@ -165,15 +169,12 @@ struct _mxc_spi_req_t { * @param hz The requested clock frequency. The actual clock frequency * will be returned by the function if successful. Used in * master mode only. - * @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is - * To upper layer firmware drive it. - * 1:Driver will drive SS pin, 0:Driver will NOT drive it * * @return If successful, the actual clock frequency is returned. Otherwise, see * \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz); /** * @brief Disable and shutdown SPI peripheral. @@ -182,7 +183,7 @@ int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int num * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_Shutdown (mxc_spi_regs_t* spi); +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); /** * @brief Checks if the given SPI bus can be placed in sleep mode. @@ -196,7 +197,16 @@ int MXC_SPI_Shutdown (mxc_spi_regs_t* spi); * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi); +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); + +/** + * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Frequency of the clock used as the bit rate generator + */ +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); /** * @brief Set the frequency of the SPI interface. @@ -209,9 +219,7 @@ int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi); * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz); - -int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi); +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); /** * @brief Get the frequency of the SPI interface. @@ -222,7 +230,7 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi); * * @return The SPI bus frequency in Hertz */ -unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); /** * @brief Sets the number of bits per character @@ -232,7 +240,7 @@ unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize); +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); /** * @brief Gets the number of bits per character @@ -241,8 +249,7 @@ int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi); - +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); /* ************************************************************************* */ /* Low-level functions */ @@ -258,7 +265,7 @@ int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx); +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); /** * @brief Gets the slave select (SS) line used for transmissions @@ -269,7 +276,7 @@ int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx); * * @return slave slect */ -int MXC_SPI_GetSlave (mxc_spi_regs_t* spi); +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); /** * @brief Sets the SPI width used for transmissions @@ -279,7 +286,7 @@ int MXC_SPI_GetSlave (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth); +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); /** * @brief Gets the SPI width used for transmissions @@ -288,7 +295,7 @@ int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth); * * @return Spi Width \ref mxc_spi_width_t */ -mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi); +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); /** * @brief Sets the spi mode using clock polarity and clock phase @@ -298,7 +305,7 @@ mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode); +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); /** * @brief Gets the spi mode @@ -307,7 +314,7 @@ int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode); * * @return mxc_spi_mode_t \ref mxc_spi_mode_t */ -mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi); +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); /** * @brief Starts a SPI Transmission @@ -321,7 +328,7 @@ mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi); +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); /** * @brief Checks the SPI Peripheral for an ongoing transmission @@ -332,7 +339,7 @@ int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi); * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetActive (mxc_spi_regs_t* spi); +int MXC_SPI_GetActive(mxc_spi_regs_t *spi); /** * @brief Aborts an ongoing SPI Transmission @@ -343,7 +350,7 @@ int MXC_SPI_GetActive (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi); +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); /** * @brief Unloads bytes from the receive FIFO. @@ -354,8 +361,7 @@ int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi); * * @return The number of bytes actually read. */ -unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len); +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); /** * @brief Get the number of bytes currently available in the receive FIFO. @@ -364,7 +370,7 @@ unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, * * @return The number of bytes available. */ -unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); /** * @brief Loads bytes into the transmit FIFO. @@ -375,8 +381,7 @@ unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi); * * @return The number of bytes actually written. */ -unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len); +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); /** * @brief Get the amount of free space available in the transmit FIFO. @@ -385,21 +390,21 @@ unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, * * @return The number of bytes available. */ -unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); /** * @brief Removes and discards all bytes currently in the receive FIFO. * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi); +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); /** * @brief Removes and discards all bytes currently in the transmit FIFO. * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi); +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); /** * @brief Set the receive threshold level. @@ -418,7 +423,7 @@ void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); /** * @brief Get the current receive threshold level. @@ -427,7 +432,7 @@ int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); * * @return The receive threshold value (in bytes). */ -unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); /** * @brief Set the transmit threshold level. @@ -446,7 +451,7 @@ unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); /** * @brief Get the current transmit threshold level. @@ -455,7 +460,7 @@ int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); * * @return The transmit threshold value (in bytes). */ -unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); /** * @brief Gets the interrupt flags that are currently set @@ -467,7 +472,7 @@ unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi); * * @return The interrupt flags */ -unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); /** * @brief Clears the interrupt flags that are currently set @@ -477,7 +482,7 @@ unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi); +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); /** * @brief Enables specific interrupts @@ -488,7 +493,7 @@ void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi); * @param spi Pointer to SPI registers (selects the SPI block used.) * @param mask The interrupts to be enabled */ -void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask); +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask); /** * @brief Disables specific interrupts @@ -499,7 +504,7 @@ void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask); * @param spi Pointer to SPI registers (selects the SPI block used.) * @param mask The interrupts to be disabled */ -void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask); +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask); /* ************************************************************************* */ /* Transaction level functions */ @@ -528,7 +533,7 @@ void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransaction (mxc_spi_req_t* req); +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); /** * @brief Setup an interrupt-driven SPI transaction @@ -540,7 +545,7 @@ int MXC_SPI_MasterTransaction (mxc_spi_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req); +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); /** * @brief Setup a DMA driven SPI transaction @@ -557,7 +562,7 @@ int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req); +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); /** * @brief Performs a blocking SPI transaction. @@ -574,7 +579,7 @@ int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req); +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); /** * @brief Setup an interrupt-driven SPI transaction @@ -586,7 +591,7 @@ int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req); +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); /** * @brief Setup a DMA driven SPI transaction @@ -603,7 +608,7 @@ int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req); +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); /** * @brief Sets the TX data to transmit as a 'dummy' byte @@ -616,7 +621,7 @@ int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData); +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); /** * @brief Abort any asynchronous requests in progress. @@ -627,7 +632,7 @@ int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData); * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi); +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); /** * @brief The processing function for asynchronous transactions. @@ -638,11 +643,11 @@ void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi); +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); /**@} end of group spi */ #ifdef __cplusplus } #endif -#endif /* _PT_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h index 29a791d4d48..b33976271ec 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h @@ -3,8 +3,8 @@ * @brief System level header file. */ -/******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,8 +36,8 @@ * ******************************************************************************/ -#ifndef _MXC_MXC_SYS_H_ -#define _MXC_MXC_SYS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_ #include "mxc_device.h" #include "gcr_regs.h" @@ -46,79 +46,211 @@ extern "C" { #endif +/** + * @defgroup mxc_sys System Configuration (MXC_SYS) + * @ingroup syscfg + * @details API for system configuration including clock source selection and entering critical sections of code. + * @{ + */ + /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ typedef enum { - MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ - MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ - MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ - MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */ - MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */ - MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */ - MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ - MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ - MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */ - MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ - MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ - MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ - MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ - MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ - MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */ + MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ + MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ + MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ + MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */ + MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */ + MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */ + MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ + MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */ + MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ + MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ + MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ + MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ + MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ + MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */ /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ - MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ + MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ } mxc_sys_reset_t; /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ typedef enum { - MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ - MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ - MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */ - MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ - MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ - MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ - MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ - MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */ - MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */ - MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */ - MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ + MXC_SYS_PERIPH_CLOCK_GPIO0 = + MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA = + MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ + MXC_SYS_PERIPH_CLOCK_SPI0 = + MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI1 = + MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ + MXC_SYS_PERIPH_CLOCK_UART0 = + MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ + MXC_SYS_PERIPH_CLOCK_UART1 = + MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ + MXC_SYS_PERIPH_CLOCK_I2C0 = + MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR0 = + MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR1 = + MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */ + MXC_SYS_PERIPH_CLOCK_TMR2 = + MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */ + MXC_SYS_PERIPH_CLOCK_I2C1 = + MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ - MXC_SYS_PERIPH_CLOCK_FLCD = (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */ - MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ + MXC_SYS_PERIPH_CLOCK_FLCD = + (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */ + MXC_SYS_PERIPH_CLOCK_ICACHE = + (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ } mxc_sys_periph_clock_t; /** @brief Enumeration to select System Clock source */ typedef enum { - MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */ - MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */ - MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ - MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */ + MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */ + MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */ + MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ + MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */ } mxc_sys_system_clock_t; +#define MXC_SYS_USN_LEN 8 + /***** Function Prototypes *****/ +typedef struct { + int ie_status; + int in_critical; +} mxc_crit_state_t; + +static mxc_crit_state_t _state = { .ie_status = 0xFFFFFFFF, .in_critical = 0 }; + +static inline void _mxc_crit_get_state() +{ +#ifndef __riscv + /* + On ARM M the 0th bit of the Priority Mask register indicates + whether interrupts are enabled or not. + + 0 = enabled + 1 = disabled + */ + uint32_t primask = __get_PRIMASK(); + _state.ie_status = (primask == 0); +#else + /* + On RISC-V bit position 3 (Machine Interrupt Enable) of the + mstatus register indicates whether interrupts are enabled. + + 0 = disabled + 1 = enabled + */ + uint32_t mstatus = get_mstatus(); + _state.ie_status = ((mstatus & (1 << 3)) != 0); +#endif +} + +/** + * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section. + * @details Ex: + * @code + * MXC_SYS_Crit_Enter(); + * printf("Hello critical section!\n"); + * MXC_SYS_Crit_Exit(); + * @endcode + * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way. + * @returns None + */ +static inline void MXC_SYS_Crit_Enter(void) +{ + _mxc_crit_get_state(); + if (_state.ie_status) + __disable_irq(); + _state.in_critical = 1; +} + +/** + * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter + * @returns None + */ +static inline void MXC_SYS_Crit_Exit(void) +{ + if (_state.ie_status) { + __enable_irq(); + } + _state.in_critical = 0; + _mxc_crit_get_state(); + /* + ^ Reset the state again to prevent edge case + where interrupts get disabled, then Crit_Exit() gets + called, which would inadvertently re-enable interrupts + from old state. + */ +} + +/** + * @brief Polls whether code is currently executing from a critical section. + * @returns 1 if code is currently in a critical section (interrupts are disabled). + * 0 if code is not in a critical section. + */ +static inline int MXC_SYS_In_Crit_Section(void) +{ + return _state.in_critical; +} + +// clang-format off +/** + * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro + * does not support nesting. + * @details + * Ex: + * \code + * MXC_CRITICAL( + * printf("Hello critical section!\n"); + * ) + * \endcode + * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after. + * @param code The code section to wrap. + */ +#define MXC_CRITICAL(code) {\ + MXC_SYS_Crit_Enter();\ + code;\ + MXC_SYS_Crit_Exit();\ +} +// clang-format on + +/** + * @brief Reads the device USN. + * @param usn Pointer to store the USN. + * @param len Length of the USN buffer + * @param part Which USN part you want (0, 1, 2) + * @returns E_NO_ERROR if everything is successful. + */ +int MXC_SYS_GetUSN(uint8_t *usn, int len, int part); + /** * @brief Determines if the selected peripheral clock is enabled. * @param clock Enumeration for desired clock. * @returns 0 is the clock is disabled, non 0 if the clock is enabled. */ -int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock); +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock); /** * @brief Disables the selected peripheral clock. * @param clock Enumeration for desired clock. */ -void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock); +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock); /** * @brief Enables the selected peripheral clock. * @param clock Enumeration for desired clock. */ -void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock); +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock); /** * @brief Enables the 32kHz oscillator * @param mxc_sys_cfg Not used, may be NULL. */ -void MXC_SYS_RTCClockEnable (void); +void MXC_SYS_RTCClockEnable(void); /** * @brief Disables the 32kHz oscillator @@ -131,37 +263,36 @@ int MXC_SYS_RTCClockDisable(); * @param clock The clock to enable * @return E_NO_ERROR if everything is successful */ -int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock); +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock); /** * @brief Disable System Clock Source * @param clock The clock to disable * @return E_NO_ERROR if everything is successful */ -int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock); +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock); /** * @brief Select the system clock. * @param clock Enumeration for desired clock. - * @param tmr Optional tmr pointer for timeout. NULL if undesired. * @returns E_NO_ERROR if everything is successful. */ -int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock); +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); /** * @brief Wait for a clock to enable with timeout * @param ready The clock to wait for * @return E_NO_ERROR if ready, E_TIME_OUT if timeout */ -int MXC_SYS_Clock_Timeout (uint32_t ready); +int MXC_SYS_Clock_Timeout(uint32_t ready); /** * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. * @param Enumeration for what to reset. Can reset multiple items at once. */ -void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset); +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset); #ifdef __cplusplus } #endif -#endif /* _MXC_MXC_SYS_H_*/ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h index 2320fc2fccc..b6c05edb11b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h @@ -3,8 +3,8 @@ * @brief Real Time Clock (RTC) functions and prototypes. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _RTC_H_ -#define _RTC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_ /* **** Includes **** */ #include @@ -56,33 +56,36 @@ extern "C" { * @{ */ +#define MXC_RTC_MAX_SSEC (0xFFF + 1) // 0xFFF = max ssec counter value +#define MXC_RTC_TRIM_TMR_IRQ MXC_F_TMR_INTR_IRQ + /* **** Definitions **** */ /** * @brief Bitmasks for each of the RTC's Frequency. */ typedef enum { - MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated) + MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated) MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, ///< 512Hz (Compensated) - MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz - MXC_RTC_F_32KHZ = 32, ///< 32Khz + MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz + MXC_RTC_F_32KHZ = 32, ///< 32Khz } mxc_rtc_freq_sel_t; /** * @brief Bitmasks for each of the RTC's interrupt enables. */ typedef enum { - MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable - MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable - MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable + MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable + MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable + MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable } mxc_rtc_int_en_t; /** * @brief Bitmasks for each of the RTC's interrupt flags. */ typedef enum { - MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag - MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag - MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag + MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag } mxc_rtc_int_fl_t; /** @@ -90,7 +93,7 @@ typedef enum { * @param ras 20-bit value 0-0xFFFFF * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SetTimeofdayAlarm (uint32_t ras); +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras); /** * @brief Set Sub-Second alarm value and enable interrupt, @@ -98,62 +101,62 @@ int MXC_RTC_SetTimeofdayAlarm (uint32_t ras); * @param rssa 32-bit value 0-0xFFFFFFFF * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SetSubsecondAlarm (uint32_t rssa); +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa); /** - * @brief Start the Real Time Clock + * @brief Start the Real Time Clock (Blocking function) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Start (void); +int MXC_RTC_Start(void); /** - * @brief Stop the Real Time Clock + * @brief Stop the Real Time Clock (Blocking function) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Stop (void); +int MXC_RTC_Stop(void); /** - * @brief Initialize the sec and ssec registers and enable RTC + * @brief Initialize the sec and ssec registers and enable RTC (Blocking function) * @param sec set the RTC Sec counter (32-bit) * @param ssec set the RTC Sub-second counter (8-bit) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Init (uint32_t sec, uint8_t ssec); +int MXC_RTC_Init(uint32_t sec, uint8_t ssec); /** - * @brief Allow generation of Square Wave on the SQW pin + * @brief Allow generation of Square Wave on the SQW pin (Blocking function) * @param fq Frequency output selection * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq); - +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq); + /** - * @brief Stop the generation of square wave + * @brief Stop the generation of square wave (Blocking function) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SquareWaveStop (void); +int MXC_RTC_SquareWaveStop(void); /** - * @brief Set Trim register value + * @brief Set Trim register value (Blocking function) * @param trm set the RTC Trim (8-bit, +/- 127) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Trim (int8_t trm); +int MXC_RTC_Trim(int8_t trm); /** - * @brief Enable Interurpts + * @brief Enable Interurpts (Blocking function) * @param mask The bitwise OR of interrupts to enable. * See #mxc_rtc_int_en_t for available choices. * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_EnableInt (uint32_t mask); +int MXC_RTC_EnableInt(uint32_t mask); /** - * @brief Disable Interurpts + * @brief Disable Interurpts (Blocking function) * @param mask The mask of interrupts to disable. * See #mxc_rtc_int_en_t for available choices. * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_DisableInt (uint32_t mask); +int MXC_RTC_DisableInt(uint32_t mask); /** * @brief Gets interrupt flags. @@ -161,7 +164,7 @@ int MXC_RTC_DisableInt (uint32_t mask); * currently set. See \ref mxc_rtc_int_fl_t for the list * of possible flags. */ -int MXC_RTC_GetFlags (void); +int MXC_RTC_GetFlags(void); /** * @brief Clear interrupt flags. @@ -169,19 +172,19 @@ int MXC_RTC_GetFlags (void); * See #mxc_rtc_int_fl_t for the list of possible flags. * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_ClearFlags (int flags); +int MXC_RTC_ClearFlags(int flags); /** - * @brief Get SubSecond + * @brief Get SubSecond or E_BUSY, see /ref MXC_ERROR_CODES * @retval Returns subsecond value */ -int MXC_RTC_GetSubSecond (void); +int MXC_RTC_GetSubSecond(void); /** - * @brief Get Second + * @brief Get Second or E_BUSY, see /ref MXC_ERROR_CODES * @retval returns second value */ -int MXC_RTC_GetSecond (void); +int MXC_RTC_GetSecond(void); /** * @brief Get the time using nuclear fusion. Or atomically. Something like that. @@ -189,11 +192,17 @@ int MXC_RTC_GetSecond (void); * @param subsec pointer to store subseconds value * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec); +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec); + +/** + * @brief Get RTC busy flag. + * @retval returns Success or E_BUSY, see /ref MXC_ERROR_CODES + */ +int MXC_RTC_GetBusyFlag(void); /**@} end of group rtc */ #ifdef __cplusplus } #endif -#endif /* _RTC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h index c6bcf2b39fd..e5df3e13a7b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h @@ -1,10 +1,10 @@ /** * @file spimss.h * @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types. - */ + */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,12 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ - + ******************************************************************************/ + /* Define to prevent redundant inclusion */ -#ifndef _SPIMSS_H_ -#define _SPIMSS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_ /* **** Includes **** */ #include "mxc_device.h" @@ -60,14 +59,13 @@ extern "C" { /* **** Definitions **** */ - /** * @brief Enumeration type for setting the number data lines to use for communication. */ -typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED - DUMMY_1, /**< NOT USED */ - DUMMY_2, /**< NOT USED */ - DUMMY_3, /**< NOT USED */ +typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED + DUMMY_1, /**< NOT USED */ + DUMMY_2, /**< NOT USED */ + DUMMY_3, /**< NOT USED */ } mxc_spimss_width_t; /** @@ -87,7 +85,7 @@ typedef struct mxc_spimss_req mxc_spimss_req_t; * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | * @note Callback will execute in interrupt context */ -typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code); +typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t *req, int error_code); /** * @brief Structure definition for an SPI Master Transaction request. @@ -95,16 +93,16 @@ typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code); * structure must remain allocated until the callback is completed. */ struct mxc_spimss_req { - uint8_t ssel; /**< Not Used*/ - uint8_t deass; /**< Not Used*/ - const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ - void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ - mxc_spimss_width_t width; /**< Not Used */ - unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ - unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ - unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ - unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ - mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */ + uint8_t ssel; /**< Not Used*/ + uint8_t deass; /**< Not Used*/ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + mxc_spimss_width_t width; /**< Not Used */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */ }; /* **** Function Prototypes **** */ @@ -115,12 +113,10 @@ struct mxc_spimss_req { * @param mode SPI mode for clock phase and polarity. * @param freq Desired clock frequency. * @param sys_cfg System configuration object - * @param drv_ssel 1 SSEL will be drive by driver - * 0 SSEL will NOT be drive by driver * * @return \c #E_NO_ERROR if successful, appropriate error otherwise */ -int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel); +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg); /** * @brief Shutdown SPI module. @@ -179,19 +175,6 @@ int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); */ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); -/** - * @brief Sets the TX data to transmit as a 'dummy' byte - * - * In single wire master mode, this data is transmitted on MOSI when performing - * an RX (MISO) only transaction. This defaults to 0. - * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param defaultTXData Data to shift out in RX-only transactions - * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. - */ -int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData); - /** * @brief Aborts an Asynchronous request * @@ -207,4 +190,4 @@ int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req); } #endif -#endif /* _SPIMSS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h index f60a0d8e29a..3ce9bf91b61 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h @@ -3,8 +3,8 @@ * @brief Timer (TMR) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _TMR_H_ -#define _TMR_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_ /* **** Includes **** */ #include "mxc_device.h" @@ -61,34 +61,38 @@ extern "C" { * @brief Timer prescaler values */ typedef enum { - TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1 - TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2 - TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4 - TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8 - TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16 - TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32 - TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64 - TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128 - TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256, ///< Divide input clock by 256 - TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512, ///< Divide input clock by 512 - TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024, ///< Divide input clock by 1024 - TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048, ///< Divide input clock by 2048 - TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096, ///< Divide input clock by 4096 - TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 ///< Divide input clock by 8192 + TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1 + TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2 + TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4 + TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8 + TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16 + TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32 + TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64 + TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128 + TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256 | MXC_F_TMR_CN_PRES3, ///< Divide input clock by 256 + TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512 | MXC_F_TMR_CN_PRES3, ///< Divide input clock by 512 + TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024 | + MXC_F_TMR_CN_PRES3, ///< Divide input clock by 1024 + TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048 | + MXC_F_TMR_CN_PRES3, ///< Divide input clock by 2048 + TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096 | + MXC_F_TMR_CN_PRES3, ///< Divide input clock by 4096 + TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 | + MXC_F_TMR_CN_PRES3 ///< Divide input clock by 8192 } mxc_tmr_pres_t; /** * @brief Timer modes */ typedef enum { - TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT - TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS - TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER - TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM - TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE - TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE - TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED - TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE + TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT + TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS + TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER + TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM + TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE + TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE + TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED + TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE } mxc_tmr_mode_t; /** @@ -96,46 +100,33 @@ typedef enum { * */ typedef enum { - TMR_BIT_MODE_32, ///< Timer Mode 32 bit - TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit - TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit + TMR_BIT_MODE_32, ///< Timer Mode 32 bit + TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit + TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit } mxc_tmr_bit_mode_t; /** * @brief Timer units of time enumeration */ typedef enum { - TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator - TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator - TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator - TMR_UNIT_SEC, ///< Second Unit Indicator + TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator + TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator + TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator + TMR_UNIT_SEC, ///< Second Unit Indicator } mxc_tmr_unit_t; -/** - * @brief Clock settings - * @note 8M and 32M clocks can be used for Timers 0,1,2 and 3 - * 32K and 80K clocks can only be used for Timers 4 and 5 - */ -typedef enum { - MXC_TMR_HFIO_CLK, ///< HFIO Clock - MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock - MXC_TMR_EXT_CLK, ///< External Clock -} mxc_tmr_clock_t; - /** * @brief Timer Configuration */ typedef struct { - mxc_tmr_pres_t pres; ///< Desired timer prescaler - mxc_tmr_mode_t mode; ///< Desired timer mode - mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits - mxc_tmr_clock_t clock; ///< Desired clock source - uint32_t cmp_cnt; ///< Compare register value in timer ticks - unsigned pol; ///< Polarity (0 or 1) + mxc_tmr_pres_t pres; ///< Desired timer prescaler + mxc_tmr_mode_t mode; ///< Desired timer mode + uint32_t cmp_cnt; ///< Compare register value in timer ticks + unsigned pol; ///< Polarity (0 or 1) } mxc_tmr_cfg_t; /* **** Definitions **** */ -typedef void (*mxc_tmr_complete_t) (int error); +typedef void (*mxc_tmr_complete_t)(int error); /* **** Function Prototypes **** */ @@ -146,25 +137,25 @@ typedef void (*mxc_tmr_complete_t) (int error); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg); +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); /** * @brief Shutdown timer module clock. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr); +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr); /** * @brief Start the timer counting. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_Start (mxc_tmr_regs_t* tmr); +void MXC_TMR_Start(mxc_tmr_regs_t *tmr); /** * @brief Stop the timer. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_Stop (mxc_tmr_regs_t* tmr); +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr); /** * @brief Set the value of the first transition in PWM mode @@ -173,65 +164,64 @@ void MXC_TMR_Stop (mxc_tmr_regs_t* tmr); * @note Will block until safe to change the period count. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm); +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm); /** * @brief Get the timer compare count. * @param tmr Pointer to timer module to initialize. * @return Returns the current compare count. */ -uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr); /** * @brief Get the timer capture count. * @param tmr Pointer to timer module to initialize. * @return Returns the most recent capture count. */ -uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr); /** * @brief Get the timer count. * @param tmr Pointer to timer module to initialize. * @return Returns the current count. */ -uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr); /** * @brief Calculate count for required frequency. * @param tmr Timer - * @param clock Clock source. * @param prescalar prescalar * @param frequency required frequency. * @return Returns the period count. */ -uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency); +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, uint32_t prescalar, uint32_t frequency); /** * @brief Clear the timer interrupt. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr); +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr); /** * @brief Get the timer interrupt status. * @param tmr Pointer to timer module to initialize. * @return Returns the interrupt status. 1 if interrupt has occured. */ -uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr); /** * @brief enable interupt * * @param tmr The timer */ -void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr); +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr); /** * @brief disable interupt * * @param tmr The timer */ -void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr); +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr); /** * @brief Set the timer compare count. @@ -239,14 +229,14 @@ void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr); * @param cmp_cnt New compare count. * @note In PWM Mode use this to set the value of the second transition. */ -void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); /** * @brief Set the timer count. * @param tmr Pointer to timer module to initialize. * @param cnt New count. */ -void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt); +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt); /** * @brief Dealay for a set periord of time measured in microseconds @@ -254,7 +244,7 @@ void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt); * @param tmr The timer * @param us microseconds to delay for */ -void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us); +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us); /** * @brief Start a timer that will time out after a certain number of microseconds @@ -263,7 +253,7 @@ void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us); * @param tmr The timer * @param us microseconds to time out after */ -void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us); /** * @brief Check on time out timer @@ -272,21 +262,21 @@ void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr); +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr); /** * @brief Stop the Timeout timer * * @param tmr The timer */ -void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr); +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr); /** * @brief Clear timeout timer back to zero * * @param tmr The timer */ -void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr); +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr); /** * @brief Get elapsed time of timeout timer @@ -295,7 +285,7 @@ void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr); * * @return Time that has elapsed in timeout timer */ -unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr); /** * @brief Amount of time remaining until timeour @@ -304,14 +294,14 @@ unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr); * * @return Time that is left until timeout */ -unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr); /** * @brief Start stopwatch * * @param tmr The timer */ -void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr); +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr); /** * @brief Stopwatch stop @@ -320,7 +310,7 @@ void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr); * * @return the time when the stopwatch is stopped. */ -unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr); /** * @brief Get time from timer @@ -332,7 +322,7 @@ unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); /**@} end of group tmr */ @@ -340,4 +330,4 @@ int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tm } #endif -#endif /* _TMR_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h index 35de287738a..27be4d5d73e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h @@ -3,8 +3,8 @@ * @brief (UART) communications driver. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_UART_H_ -#define _MXC_UART_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_ /***** Definitions *****/ #include "uart_regs.h" @@ -61,8 +61,8 @@ typedef struct _mxc_uart_req_t mxc_uart_req_t; * */ typedef enum { - MXC_UART_STOP_1, ///< UART Stop 1 clock cycle - MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) + MXC_UART_STOP_1, ///< UART Stop 1 clock cycle + MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) } mxc_uart_stop_t; /** @@ -70,19 +70,19 @@ typedef enum { * */ typedef enum { - MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled - MXC_UART_PARITY_EVEN, ///< UART Parity Even - MXC_UART_PARITY_ODD, ///< UART Parity Odd - MXC_UART_PARITY_MARK, ///< UART Parity Mark - MXC_UART_PARITY_SPACE, ///< UART Parity Space - MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based - MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based - MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based - MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based - MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based - MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based - MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based - MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based + MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN, ///< UART Parity Even + MXC_UART_PARITY_ODD, ///< UART Parity Odd + MXC_UART_PARITY_MARK, ///< UART Parity Mark + MXC_UART_PARITY_SPACE, ///< UART Parity Space + MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based + MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based + MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based + MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based + MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based + MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based + MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based + MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based } mxc_uart_parity_t; /** @@ -90,19 +90,18 @@ typedef enum { * */ typedef enum { - MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled - MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low - MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High + MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled + MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low + MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High } mxc_uart_flow_t; - /** * @brief The callback routine used to indicate the transaction has terminated. * * @param req The details of the transaction. * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result); +typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); /** * @brief The callback routine used to indicate the transaction has terminated. @@ -111,7 +110,7 @@ typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result); * @param num The number of characters actually copied * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int result); +typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); /** * @brief The information required to perform a complete UART transaction @@ -119,21 +118,21 @@ typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int re * @note This structure is used by blocking, async, and DMA based transactions. */ struct _mxc_uart_req_t { - mxc_uart_regs_t* uart; /// 8 bits, use two bytes per character ///< and pad the MSB of the upper byte with zeros - uint8_t *rxData; ///< Buffer to store received data For character sizes + uint8_t *rxData; ///< Buffer to store received data For character sizes ///< < 8 bits, pad the MSB of each byte with zeros. For ///< character sizes > 8 bits, use two bytes per character ///< and pad the MSB of the upper byte with zeros - uint32_t txLen; ///< Number of bytes to be sent from txData - uint32_t rxLen; ///< Number of bytes to be stored in rxData - uint32_t txCnt; ///< Number of bytes actually transmitted from txData - uint32_t rxCnt; ///< Number of bytes stored in rxData + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData + volatile uint32_t rxCnt; ///< Number of bytes stored in rxData - mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete + mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete }; /***** Function Prototypes *****/ @@ -163,7 +162,7 @@ struct _mxc_uart_req_t { * @return If successful, the actual clock frequency is returned. Otherwise, see * \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map); +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, sys_map_t map); /** * @brief Disable and shutdown UART peripheral. @@ -172,7 +171,7 @@ int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Shutdown (mxc_uart_regs_t* uart); +int MXC_UART_Shutdown(mxc_uart_regs_t *uart); /** * @brief Checks if the given UART bus can be placed in sleep more. @@ -186,7 +185,7 @@ int MXC_UART_Shutdown (mxc_uart_regs_t* uart); * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart); +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); /** * @brief Set the frequency of the UART interface. @@ -199,7 +198,7 @@ int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart); * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud); +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud); /** * @brief Get the frequency of the UART interface. @@ -210,7 +209,7 @@ int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud); * * @return The UART baud rate */ -int MXC_UART_GetFrequency (mxc_uart_regs_t* uart); +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); /** * @brief Sets the number of bits per character @@ -220,7 +219,7 @@ int MXC_UART_GetFrequency (mxc_uart_regs_t* uart); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize); +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); /** * @brief Sets the number of stop bits sent at the end of a character @@ -230,7 +229,7 @@ int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits); +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); /** * @brief Sets the type of parity generation used @@ -240,7 +239,7 @@ int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity); +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); /** * @brief Sets the flow control used @@ -251,7 +250,7 @@ int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); /** * @brief Sets the clock source for the baud rate generator @@ -265,7 +264,7 @@ int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int r * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes * for a list of return codes. */ -int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK); +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK); /** * @brief Enables or Disables the built-in null modem @@ -276,7 +275,7 @@ int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem); +int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem); /* ************************************************************************* */ /* Low-level functions */ @@ -289,7 +288,7 @@ int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SendBreak (mxc_uart_regs_t* uart); +int MXC_UART_SendBreak(mxc_uart_regs_t *uart); /** * @brief Checks the UART Peripheral for an ongoing transmission @@ -300,7 +299,7 @@ int MXC_UART_SendBreak (mxc_uart_regs_t* uart); * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_GetActive (mxc_uart_regs_t* uart); +int MXC_UART_GetActive(mxc_uart_regs_t *uart); /** * @brief Aborts an ongoing UART Transmission @@ -309,7 +308,7 @@ int MXC_UART_GetActive (mxc_uart_regs_t* uart); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart); +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); /** * @brief Reads the next available character. This function will block until a character @@ -319,7 +318,7 @@ int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart); * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart); +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); /** * @brief Writes a character on the UART. This function will block until the character @@ -330,7 +329,7 @@ int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character); +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character. If no character is available, this function @@ -340,7 +339,7 @@ int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character); * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart); +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); /** * @brief Writes a character on the UART. If the character cannot be written because the @@ -351,7 +350,7 @@ int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character); +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character @@ -364,7 +363,7 @@ int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character); * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len); +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); /** * @brief Writes a byte on the UART @@ -375,7 +374,7 @@ int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len); +int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len); /** * @brief Unloads bytes from the receive FIFO. @@ -386,9 +385,8 @@ int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len); * * @return The number of bytes actually read. */ -unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len); - +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); + /** * @brief Unloads bytes from the receive FIFO user DMA for longer reads. * @@ -399,9 +397,9 @@ unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback); - +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback); + /** * @brief Get the number of bytes currently available in the receive FIFO. * @@ -409,7 +407,7 @@ int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, * * @return The number of bytes available. */ -unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); /** * @brief Loads bytes into the transmit FIFO. @@ -420,9 +418,8 @@ unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart); * * @return The number of bytes actually written. */ -unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len); - +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); + /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes * @@ -433,9 +430,9 @@ unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback); - +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback); + /** * @brief Get the amount of free space available in the transmit FIFO. * @@ -443,7 +440,7 @@ int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, * * @return The number of bytes available. */ -unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart); /** * @brief Removes and discards all bytes currently in the receive FIFO. @@ -452,7 +449,7 @@ unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart); +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart); /** * @brief Removes and discards all bytes currently in the transmit FIFO. @@ -461,7 +458,7 @@ int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart); +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); /** * @brief Set the receive threshold level. @@ -480,7 +477,7 @@ int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes); +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current receive threshold level. @@ -489,7 +486,7 @@ int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes); * * @return The receive threshold value (in bytes). */ -unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); /** * @brief Set the transmit threshold level. @@ -508,7 +505,7 @@ unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes); +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current transmit threshold level. @@ -517,7 +514,7 @@ int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes); * * @return The transmit threshold value (in bytes). */ -unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); /** * @brief Gets the interrupt flags that are currently set @@ -529,7 +526,7 @@ unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart); * * @return The interrupt flags */ -unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); /** * @brief Clears the interrupt flags that are currently set @@ -542,7 +539,7 @@ unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags); +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); /** * @brief Enables specific interrupts @@ -555,7 +552,7 @@ int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask); +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Disables specific interrupts @@ -568,7 +565,7 @@ int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask); +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Gets the status flags that are currently set @@ -577,9 +574,9 @@ int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask); * * @return The status flags */ -unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); -int MXC_UART_Busy(mxc_uart_regs_t* uart); +int MXC_UART_Busy(mxc_uart_regs_t *uart); /* ************************************************************************* */ /* Transaction level functions */ @@ -596,7 +593,7 @@ int MXC_UART_Busy(mxc_uart_regs_t* uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_Transaction (mxc_uart_req_t* req); +int MXC_UART_Transaction(mxc_uart_req_t *req); /** * @brief Setup an interrupt-driven UART transaction @@ -608,7 +605,7 @@ int MXC_UART_Transaction (mxc_uart_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionAsync (mxc_uart_req_t* req); +int MXC_UART_TransactionAsync(mxc_uart_req_t *req); /** * @brief Setup a DMA driven UART transaction @@ -623,7 +620,7 @@ int MXC_UART_TransactionAsync (mxc_uart_req_t* req); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionDMA (mxc_uart_req_t* req); +int MXC_UART_TransactionDMA(mxc_uart_req_t *req); /** * @brief The processing function for DMA transactions. @@ -634,7 +631,7 @@ int MXC_UART_TransactionDMA (mxc_uart_req_t* req); * @param ch DMA channel * @param error Error status */ -void MXC_UART_DMACallback (int ch, int error); +void MXC_UART_DMACallback(int ch, int error); /** * @brief Async callback @@ -644,7 +641,9 @@ void MXC_UART_DMACallback (int ch, int error); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal); +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); +int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal); +int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal); /** * @brief stop any async callbacks @@ -653,7 +652,9 @@ int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncStop (mxc_uart_regs_t* uart); +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); +int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart); +int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart); /** * @brief Abort any asynchronous requests in progress. @@ -666,7 +667,9 @@ int MXC_UART_AsyncStop (mxc_uart_regs_t* uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AbortAsync (mxc_uart_regs_t* uart); +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); +int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart); +int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart); /** * @brief The processing function for asynchronous transactions. @@ -679,7 +682,25 @@ int MXC_UART_AbortAsync (mxc_uart_regs_t* uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart); +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); + +/** + * @brief Provide TXCount for asynchronous transactions.. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Returns transmit bytes (in FIFO). + */ +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); + +/** + * @brief Provide RXCount for asynchronous transactions.. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Returns receive bytes (in FIFO). + */ +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req); /**@} end of group uart */ @@ -687,4 +708,4 @@ int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart); } #endif -#endif /* _MXC_UART_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h index fc66d6731ab..421536f1d4a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h @@ -3,8 +3,8 @@ * @brief Watchdog timer (WDT) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _WDT_H_ -#define _WDT_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_ /* **** Includes **** */ #include @@ -60,22 +60,22 @@ extern "C" { /** @brief Watchdog period enumeration. Used to configure the period of the watchdog interrupt */ typedef enum { - MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31 - MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30 - MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29 - MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28 - MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27 - MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26 - MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25 - MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24 - MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23 - MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22 - MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21 - MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20 - MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19 - MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18 - MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17 - MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16 + MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31 + MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30 + MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29 + MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28 + MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27 + MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26 + MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25 + MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24 + MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23 + MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22 + MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21 + MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20 + MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19 + MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18 + MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17 + MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16 } mxc_wdt_period_t; /* **** Function Prototypes **** */ @@ -85,96 +85,96 @@ typedef enum { * @param wdt Pointer to the watchdog registers * @return See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_WDT_Init (mxc_wdt_regs_t* wdt); +int MXC_WDT_Init(mxc_wdt_regs_t *wdt); /** * @brief Shutdown the Watchdog Timer * @param wdt Pointer to the watchdog registers * @return See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt); +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt); /** * @brief Set the period of the watchdog interrupt. * @param wdt Pointer to watchdog registers. * @param period Enumeration of the desired watchdog period. */ -void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period); +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period); /** * @brief Set the period of the watchdog reset. * @param wdt Pointer to watchdog registers. * @param period Enumeration of the desired watchdog period. */ -void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period); +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period); /** * @brief Enable the watchdog timer. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_Enable (mxc_wdt_regs_t* wdt); +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt); /** * @brief Disable the watchdog timer. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_Disable (mxc_wdt_regs_t* wdt); +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt); /** * @brief Enable the watchdog interrupt. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt); +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt); /** * @brief Enable the watchdog reset. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt); +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt); /** * @brief Enable the watchdog interrupt. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt); +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt); /** * @brief Enable the watchdog reset. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt); +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt); /** * @brief Reset the watchdog timer. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt); +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt); /** * @brief Get the status of the reset flag. * @param wdt Pointer to watchdog registers. * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. */ -int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt); +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt); /** * @brief Clears the reset flag. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt); +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt); /** * @brief Get the status of the interrupt flag. * @param wdt Pointer to watchdog registers. * @returns 1 if the interrupt is pending, 0 otherwise. */ -int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt); +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt); /** * @brief Clears the interrupt flag. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt); +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt); /**@} end of group wdt */ @@ -182,4 +182,4 @@ void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt); } #endif -#endif /* _WDT_H_ */ \ No newline at end of file +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c index 02bd982ffe8..b1f4b45a250 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /****** Includes *******/ #include @@ -51,17 +51,17 @@ int MXC_DMA_Init(void) { - if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); - } - - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA); + if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + } + + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); } int MXC_DMA_AcquireChannel(void) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); } int MXC_DMA_ReleaseChannel(int ch) @@ -80,7 +80,7 @@ int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) } int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst) -{ +{ return MXC_DMA_RevA_SetSrcDst(srcdst); } @@ -99,14 +99,14 @@ int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst) return MXC_DMA_RevA_GetSrcReload(srcdst); } -int MXC_DMA_SetCallback(int ch, void(*callback)(int, int)) +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)) { return MXC_DMA_RevA_SetCallback(ch, callback); } int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) { - return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); + return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); } int MXC_DMA_ChannelEnableInt(int ch, int flags) @@ -131,12 +131,12 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags) int MXC_DMA_EnableInt(int ch) { - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); } int MXC_DMA_DisableInt(int ch) { - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); } int MXC_DMA_Start(int ch) @@ -149,23 +149,23 @@ int MXC_DMA_Stop(int ch) return MXC_DMA_RevA_Stop(ch); } -mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch) +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) { return MXC_DMA_RevA_GetCHRegs(ch); } void MXC_DMA_Handler(void) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); } -int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); } - diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c index 724453c8a62..2bd9e99d48c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,10 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM // Keil -#pragma diag_suppress 68 // integer conversion resulted in a change of sign -#endif + ******************************************************************************/ /****** Includes *******/ #include @@ -46,29 +43,26 @@ #include "dma_reva_regs.h" /***** Definitions *****/ -#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) +#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) typedef struct { - void* userCallback; // user given callback - void* dest; // memcpy destination + void *userCallback; // user given callback + void *dest; // memcpy destination } mxc_dma_highlevel_t; typedef struct { - unsigned int valid; // Flag to invalidate this resource - unsigned int instance; // Hardware instance of this DMA controller - unsigned int id; // Channel ID, which matches the index into the underlying hardware - mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel - void(*cb)(int, int); // Pointer to a callback function type + unsigned int valid; // Flag to invalidate this resource + unsigned int instance; // Hardware instance of this DMA controller + unsigned int id; // Channel ID, which matches the index into the underlying hardware + mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel + void (*cb)(int, int); // Pointer to a callback function type } mxc_dma_channel_t; /******* Globals *******/ -static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0}; +static unsigned int dma_initialized[MXC_DMA_INSTANCES] = { 0 }; static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS]; static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS]; - -#if USE_LOCK_IN_DRIVERS - static uint32_t dma_lock; -#endif +static uint32_t dma_lock; /****** Functions ******/ static void memcpy_callback(int ch, int error); @@ -79,59 +73,59 @@ int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma) int i, numCh, offset; #if TARGET_NUM == 32665 numCh = MXC_DMA_CH_OFFSET; - offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma); #else numCh = MXC_DMA_CHANNELS; offset = 0; #endif - - if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { + + if (dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) { return E_BAD_STATE; } - + #ifndef __riscv - /* Initialize mutex */ - MXC_FreeLock(&dma_lock); - - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } + /* Initialize mutex */ + MXC_FreeLock(&dma_lock); + + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } #endif - + /* Ensure all channels are disabled at start, clear flags, init handles */ dma->inten = 0; - - for(i = offset; i < (offset + numCh); i++) { + + for (i = offset; i < (offset + numCh); i++) { dma_resource[i].valid = 0; dma_resource[i].instance = 0; dma_resource[i].id = i; - dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]); + dma_resource[i].regs = (mxc_dma_reva_ch_regs_t *)&(dma->ch[(i % numCh)]); dma_resource[i].regs->ctrl = 0; dma_resource[i].regs->status = dma_resource[i].regs->status; - + dma_resource[i].cb = NULL; } - - dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++; + + dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]++; #ifndef __riscv - MXC_FreeLock(&dma_lock); + MXC_FreeLock(&dma_lock); #endif - + return E_NO_ERROR; } -int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma) +int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma) { int i, channel, numCh, offset; - + /* Check for initialization */ - if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { + if (!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) { return E_BAD_STATE; } - + #if TARGET_NUM == 32665 numCh = MXC_DMA_CH_OFFSET; - offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma); #else numCh = MXC_DMA_CHANNELS; offset = 0; @@ -139,15 +133,15 @@ int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma) #ifndef __riscv /* If DMA is locked return busy */ - if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { return E_BUSY; } #endif /* Default is no channel available */ channel = E_NONE_AVAIL; - - for(i = offset; i < (offset + numCh); i++) { - if(!dma_resource[i].valid) { + + for (i = offset; i < (offset + numCh); i++) { + if (!dma_resource[i].valid) { /* Found one */ channel = i; dma_resource[i].valid = 1; @@ -165,159 +159,142 @@ int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma) int MXC_DMA_RevA_ReleaseChannel(int ch) { - if(CHECK_HANDLE(ch)) { - if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + if (CHECK_HANDLE(ch)) { + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { return E_BUSY; } - + dma_resource[ch].valid = 0; dma_resource[ch].regs->ctrl = 0; dma_resource[ch].regs->status = dma_resource[ch].regs->status; MXC_FreeLock(&dma_lock); - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) { - if(CHECK_HANDLE(config.ch)) { + if (CHECK_HANDLE(config.ch)) { /* Designed to be safe, not speedy. Should not be called often */ dma_resource[config.ch].regs->ctrl = - ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) | - (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | - config.reqsel | - (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) | - (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS)); - } - else { + ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) | + (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | config.reqsel | + (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) | + (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS)); + } else { return E_BAD_PARAM; } - + return MXC_DMA_RevA_SetSrcDst(srcdst); } - int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) { - if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) { + if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) { dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here /* Designed to be safe, not speedy. Should not be called often */ dma_resource[advConfig.ch].regs->ctrl |= - ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | - advConfig.prio | advConfig.tosel | advConfig.pssel | - (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE)); - } - else { + ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio | + advConfig.tosel | advConfig.pssel | + (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & + MXC_F_DMA_REVA_CTRL_BURST_SIZE)); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst) { - if(CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source; - dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest; + if (CHECK_HANDLE(srcdst.ch)) { + dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source; + dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest; dma_resource[srcdst.ch].regs->cnt = srcdst.len; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - -int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst) +int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst) { if (CHECK_HANDLE(srcdst->ch)) { - srcdst->source = (void*) dma_resource[srcdst->ch].regs->src; - srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst; + srcdst->source = (void *)dma_resource[srcdst->ch].regs->src; + srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst; srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst) { - if(CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source; - dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest; - - if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) { + if (CHECK_HANDLE(srcdst.ch)) { + dma_resource[srcdst.ch].regs->srcrld = (unsigned int)srcdst.source; + dma_resource[srcdst.ch].regs->dstrld = (unsigned int)srcdst.dest; + + if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) { /* If channel is already running, set RLDEN to enable next reload */ dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len; - } - else { + } else { /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ dma_resource[srcdst.ch].regs->cntrld = srcdst.len; } - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - -int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst) +int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst) { if (CHECK_HANDLE(srcdst->ch)) { - srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld; - srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld; + srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld; + srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld; srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - -int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)) +int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int)) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { /* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */ dma_resource[ch].cb = callback; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) { - if(CHECK_HANDLE(ch)) { - if(chdis){ - dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE); - } - if(ctz){ - dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE); - } - } - else { + if (CHECK_HANDLE(ch)) { + if (chdis) { + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE); + } + if (ctz) { + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE); + } + } else { return E_BAD_PARAM; } return E_NO_ERROR; } - int MXC_DMA_RevA_GetChannelInterruptEn(int ch) { return E_NOT_SUPPORTED; @@ -325,119 +302,111 @@ int MXC_DMA_RevA_GetChannelInterruptEn(int ch) int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags) { - if(CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); - } - else { + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl |= + (flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE)); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags) { - if(CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); - } - else { + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl &= + ~(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE)); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch) { - if(CHECK_HANDLE(ch)) { - #if TARGET_NUM == 32665 + if (CHECK_HANDLE(ch)) { +#if TARGET_NUM == 32665 ch %= MXC_DMA_CH_OFFSET; - #endif - dma->inten |= (1 << ch); - } - else { +#endif + dma->inten |= (1 << ch); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch) { - if(CHECK_HANDLE(ch)) { - #if TARGET_NUM == 32665 + if (CHECK_HANDLE(ch)) { +#if TARGET_NUM == 32665 ch %= MXC_DMA_CH_OFFSET; - #endif - dma->inten &= ~(1 << ch); - } - else { +#endif + dma->inten &= ~(1 << ch); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ChannelGetFlags(int ch) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { return dma_resource[ch].regs->status; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags) { - if(CHECK_HANDLE(ch)) { - dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags - } - else { + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_Start(int ch) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch)); - - if(dma_resource[ch].regs->cntrld) { + + if (dma_resource[ch].regs->cntrld) { dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN); - } - else { + } else { dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN; } - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_Stop(int ch) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } -mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch) +mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch) { - if(CHECK_HANDLE(ch)) { - return(mxc_dma_ch_regs_t*) dma_resource[ch].regs; - } - else { + if (CHECK_HANDLE(ch)) { + return (mxc_dma_ch_regs_t *)dma_resource[ch].regs; + } else { return NULL; } } @@ -445,17 +414,21 @@ mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch) void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma) { int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES; - int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma); /* Do callback, if enabled */ - for(int i = offset; i < (offset + numCh); i++) { - if(CHECK_HANDLE(i)) { - if(dma->intfl &(0x1 << (i % numCh))) { - if(dma_resource[i].cb != NULL) { + for (int i = offset; i < (offset + numCh); i++) { + if (CHECK_HANDLE(i)) { + if (dma->intfl & (0x1 << (i % numCh))) { + if (dma_resource[i].cb != NULL) { dma_resource[i].cb(i, E_NO_ERROR); } - + MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i)); - break; + + // No need to check rest of the channels if no interrupt flags set. + if (dma->intfl == 0) { + break; + } } } } @@ -464,72 +437,76 @@ void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma) void memcpy_callback(int ch, int error) { mxc_dma_complete_cb_t callback; - callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback; - - if(error != E_NO_ERROR) { + callback = (mxc_dma_complete_cb_t)memcpy_resource[ch].userCallback; + + if (error != E_NO_ERROR) { callback(NULL); } - + callback(memcpy_resource[ch].dest); - + + // Release global objects and local resources callback = NULL; + memcpy_resource[ch].userCallback = NULL; + memcpy_resource[ch].dest = NULL; MXC_DMA_ReleaseChannel(ch); } -int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback) { int retval; mxc_dma_config_t config; mxc_dma_srcdst_t transfer; int channel; - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); - #else +#if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); +#else channel = MXC_DMA_AcquireChannel(); - #endif - - if(memcpy_resource[channel].userCallback != NULL) { +#endif + + if (memcpy_resource[channel].userCallback != NULL) { // We acquired a channel we haven't cleared yet MXC_DMA_ReleaseChannel(channel); return E_UNKNOWN; } - + transfer.ch = channel; transfer.source = src; transfer.dest = dest; transfer.len = len; - + config.ch = channel; config.reqsel = MXC_DMA_REQUEST_MEMTOMEM; config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_WORD; config.srcinc_en = 1; config.dstinc_en = 1; - + retval = MXC_DMA_ConfigChannel(config, transfer); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_EnableInt(channel); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + MXC_DMA_SetCallback(channel, memcpy_callback); - - memcpy_resource[channel].userCallback = (void*) callback; + + memcpy_resource[channel].userCallback = (void *)callback; memcpy_resource[channel].dest = dest; - + return MXC_DMA_Start(channel); } @@ -540,46 +517,47 @@ void transfer_callback(int ch, int error) // Call user callback for next transfer // determine whether to load into the transfer slot or reload slot // continue on or stop - while(1); + while (1) {} } -int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) +int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, + mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { int retval, channel; - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); - #else +#if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); +#else channel = MXC_DMA_AcquireChannel(); - #endif - - if(memcpy_resource[channel].userCallback != NULL) { +#endif + + if (memcpy_resource[channel].userCallback != NULL) { // We acquired a channel we haven't cleared yet MXC_DMA_ReleaseChannel(channel); return E_UNKNOWN; } - + retval = MXC_DMA_ConfigChannel(config, firstSrcDst); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_EnableInt(channel); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + MXC_DMA_SetCallback(channel, transfer_callback); - - memcpy_resource[channel].userCallback = (void*) callback; - + + memcpy_resource[channel].userCallback = (void *)callback; + return MXC_DMA_Start(channel); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h index b6d4d401423..bb254a21281 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_ /****** Includes *******/ #include "dma_reva_regs.h" @@ -41,7 +44,7 @@ /****** Functions ******/ int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma); -int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma); +int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma); int MXC_DMA_RevA_ReleaseChannel(int ch); int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); @@ -49,7 +52,7 @@ int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst); int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst); -int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)); +int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int)); int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags); int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags); @@ -59,7 +62,11 @@ int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch); int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch); int MXC_DMA_RevA_Start(int ch); int MXC_DMA_RevA_Stop(int ch); -mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch); +mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch); void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma); -int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback); -int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); +int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); +int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, + mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h index 96b9078731e..0cb0b1c40e9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _DMA_REVA_REGS_H_ #define _DMA_REVA_REGS_H_ @@ -86,14 +85,14 @@ extern "C" { * Structure type to access the DMA Registers. */ typedef struct { - __IO uint32_t ctrl; /**< \b 0x100: DMA CTRL Register */ - __IO uint32_t status; /**< \b 0x104: DMA STATUS Register */ - __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ - __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ - __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ - __IO uint32_t srcrld; /**< \b 0x114: DMA SRCRLD Register */ - __IO uint32_t dstrld; /**< \b 0x118: DMA DSTRLD Register */ - __IO uint32_t cntrld; /**< \b 0x11C: DMA CNTRLD Register */ + __IO uint32_t ctrl; /**< \b 0x000: DMA CTRL Register */ + __IO uint32_t status; /**< \b 0x004: DMA STATUS Register */ + __IO uint32_t src; /**< \b 0x008: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x00C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x010: DMA CNT Register */ + __IO uint32_t srcrld; /**< \b 0x014: DMA SRCRLD Register */ + __IO uint32_t dstrld; /**< \b 0x018: DMA DSTRLD Register */ + __IO uint32_t cntrld; /**< \b 0x01C: DMA CNTRLD Register */ } mxc_dma_reva_ch_regs_t; typedef struct { @@ -110,14 +109,14 @@ typedef struct { * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. * @{ */ - #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ - #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ - #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ - #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ - #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ - #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ - #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ - #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ + #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0100 */ + #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0104 */ + #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: 0x0108 */ + #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: 0x010C */ + #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: 0x0110 */ + #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: 0x0114 */ + #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: 0x0118 */ + #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: 0x011C */ #define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ #define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ #define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c index 5a38e3faf8d..767556994bc 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c @@ -1,10 +1,10 @@ /** - * @file flc.h - * @brief Flash Controler driver. + * @file flc_common.c + * @brief Common functions for the flash controller drivers. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -43,79 +42,78 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "flc.h" +#include "flc_common.h" #include "stdlib.h" //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // Length is number of 32-bit words -int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data) +int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data) { - volatile uint32_t* ptr; - - - for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) { + volatile uint32_t *ptr; + + for (ptr = (uint32_t *)address; ptr < (((uint32_t *)(address)) + length); ptr++, data++) { if (*ptr != *data) { return E_BAD_STATE; } } - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer) +int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer) { int err; uint32_t bytes_written; uint32_t current_data_32; - uint8_t* current_data = (uint8_t*) ¤t_data_32; - uint8_t* buffer8 = (uint8_t*)buffer; + uint8_t *current_data = (uint8_t *)¤t_data_32; + uint8_t *buffer8 = (uint8_t *)buffer; // Align the address to a word boundary and read/write if we have to if (address & 0x3) { - // Figure out how many bytes we have to write to round up the address bytes_written = 4 - (address & 0x3); - + // Save the data currently in the flash - memcpy(current_data, (void*)(address & (~0x3)), 4); - + memcpy(current_data, (void *)(address & (~0x3)), 4); + // Modify current_data to insert the data from buffer memcpy(¤t_data[4 - bytes_written], buffer8, bytes_written); - + // Write the modified data if ((err = MXC_FLC_Write32(address - (address % 4), current_data_32)) != E_NO_ERROR) { return err; } - + address += bytes_written; length -= bytes_written; buffer8 += bytes_written; } - + // Align the address to a 4-word (128bit) boundary while ((length >= 4) && ((address & 0xF) != 0)) { memcpy(current_data, buffer8, 4); if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { return err; } - + address += 4; length -= 4; buffer8 += 4; } - + if (length >= 16) { uint32_t buff128[4]; while (length >= 16) { @@ -123,48 +121,46 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer) if ((err = MXC_FLC_Write128(address, buff128)) != E_NO_ERROR) { return err; } - + address += 16; length -= 16; buffer8 += 16; } - } - + while (length >= 4) { memcpy(current_data, buffer8, 4); if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { return err; } - + address += 4; length -= 4; buffer8 += 4; } - + if (length > 0) { // Save the data currently in the flash - memcpy(current_data, (void*)(address), 4); - + memcpy(current_data, (void *)(address), 4); + // Modify current_data to insert the data from buffer memcpy(current_data, buffer8, length); - + if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { return err; } } - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -void MXC_FLC_Com_Read(int address, void* buffer, int len) +void MXC_FLC_Com_Read(int address, void *buffer, int len) { - memcpy(buffer, (void*) address, len); + memcpy(buffer, (void *)address, len); } - diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h index b612393416d..16d5759e28c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h @@ -1,11 +1,11 @@ /** - * @file flc.h - * @brief Flash Controller driver. + * @file flc_common.h + * @brief Common functions for the flash controller driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,9 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_ /* **** Includes **** */ #include "mxc_sys.h" @@ -54,19 +55,22 @@ extern "C" { /***** Definitions *****/ +/***** Function Prototypes *****/ +int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data); -/***** Function Prototypes *****/ +int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer); -int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data); +void MXC_FLC_Com_Read(int address, void *buffer, int len); -int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer); +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num); -void MXC_FLC_Com_Read (int address, void* buffer, int len); +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num); /**@} end of group flc */ - #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c index 7891e950e98..bb79c1c2b88 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c @@ -1,15 +1,15 @@ /** - * @file flc.h + * @file flc_me11.c * @brief Flash Controler driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * @@ -20,7 +20,7 @@ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * @@ -29,13 +29,12 @@ * Products, Inc. Branding Policy. * * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, + * of trade secrets, proprietary technology, copyrights, patents, * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -49,58 +48,72 @@ //****************************************************************************** void MXC_FLC_ME11_Flash_Operation(void) { + /* + This function should be called after modifying the contents of flash memory. + It flushes the instruction caches and line fill buffer. + + It should be called _afterwards_ because after flash is modified the cache + may contain instructions that may no longer be valid. _Before_ the + flash modifications the ICC may contain relevant cached instructions related to + the incoming flash instructions (especially relevant in the case of external memory), + and these instructions will be valid up until the point that the modifications are made. + + The line fill buffer is a FLC-related buffer that also may no longer be valid. + It's flushed by reading 2 pages of flash. + */ + /* Flush all instruction caches */ MXC_GCR->scon |= MXC_F_GCR_SCON_ICC0_FLUSH; - + /* Wait for flush to complete */ - while(MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) { - } + while (MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) {} + + // Clear the line fill buffer by reading 2 pages from flash + volatile uint32_t *line_addr; + volatile uint32_t __unused line; // __unused attribute removes warning + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE); + line = *line_addr; + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); + line = *line_addr; } //****************************************************************************** int MXC_FLC_ME11_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) { - - // flash base start from 0x00000000 - if ( addr < MXC_FLASH_MEM_SIZE ) { + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { *flc = MXC_FLC; - } - else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { *flc = MXC_FLC; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } //****************************************************************************** int MXC_FLC_ME11_GetPhysicalAddress(uint32_t addr, uint32_t *result) { - // flash base start from 0x00000000 - if ( addr < MXC_FLASH_MEM_SIZE ) { - *result = addr & (MXC_FLASH_MEM_SIZE-1); - } - else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { - *result = (addr & (MXC_INFO_MEM_SIZE-1)) + MXC_FLASH_MEM_SIZE; - } - else { + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { + *result = addr & (MXC_FLASH_MEM_SIZE - 1); + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + MXC_FLASH_MEM_SIZE; + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } //****************************************************************************** - int MXC_FLC_Init() { return E_NO_ERROR; } +//****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif @@ -109,197 +122,211 @@ int MXC_FLC_Busy(void) return MXC_FLC_RevA_Busy(); } +//****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -int MXC_FLC_ME11_PageErase(uint32_t address) +int MXC_FLC_PageErase(uint32_t address) { int err; uint32_t addr; mxc_flc_regs_t *flc = NULL; - + // Get FLC Instance - if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - - if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + + if ((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - - err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*) flc, addr); + + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr); // Flush the cache MXC_FLC_ME11_Flash_Operation(); - + return err; } +//****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_ME11_Write128(uint32_t address, uint32_t *data) +int MXC_FLC_Write128(uint32_t address, uint32_t *data) { int err; mxc_flc_regs_t *flc = NULL; uint32_t addr; - + // Address checked if it is 128-bit aligned - if(address & 0xF) { + if (address & 0xF) { return E_BAD_PARAM; } - + // Get FLC Instance - if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - - if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + + if ((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - - if((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*) flc, addr, data)) != E_NO_ERROR) { + + if ((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data)) != E_NO_ERROR) { return err; } - + // Flush the cache MXC_FLC_ME11_Flash_Operation(); - - if((err= MXC_FLC_Com_VerifyData(address, 4, data)) !=E_NO_ERROR) { + + if ((err = MXC_FLC_Com_VerifyData(address, 4, data)) != E_NO_ERROR) { return err; } - + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_ME11_Write32(uint32_t address, uint32_t data) +int MXC_FLC_Write32(uint32_t address, uint32_t data) { uint32_t addr, aligned; int err; mxc_flc_regs_t *flc = NULL; - + // Address checked if it is byte addressable - if(address & 0x3) { + if (address & 0x3) { return E_BAD_PARAM; } - + // Align address to 128-bit word aligned = address & 0xfffffff0; - + // Get FLC Instance - if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - - if((err = MXC_FLC_ME11_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { + + if ((err = MXC_FLC_ME11_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { return err; } - - return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*) flc, address, data, addr); - + + err = MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t *)flc, address, data, addr); + + // Flush the cache + MXC_FLC_ME11_Flash_Operation(); + + return err; } -int MXC_FLC_ME11_MassErase(void) +//****************************************************************************** +int MXC_FLC_MassErase(void) { int err; mxc_flc_regs_t *flc; - + flc = MXC_FLC; - err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*) flc); + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc); - if(err != E_NO_ERROR) { + if (err != E_NO_ERROR) { return err; } - + MXC_FLC_ME11_Flash_Operation(); - + return E_NO_ERROR; - - } -int MXC_FLC_ME11_UnlockInfoBlock(uint32_t address) + +//****************************************************************************** +int MXC_FLC_UnlockInfoBlock(uint32_t address) { int err; mxc_flc_regs_t *flc; - - if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + + if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - - return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*) flc, address); + + return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address); } -int MXC_FLC_ME11_LockInfoBlock(uint32_t address) + +//****************************************************************************** +int MXC_FLC_LockInfoBlock(uint32_t address) { int err; mxc_flc_regs_t *flc; - - if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + + if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - - return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*) flc, address); -} -/* ****************************************************************************** */ -int MXC_FLC_MassErase(void) -{ - return MXC_FLC_ME11_MassErase(); -} -int MXC_FLC_PageErase(uint32_t address) -{ - return MXC_FLC_ME11_PageErase(address); -} - -int MXC_FLC_Write32(uint32_t address, uint32_t data) -{ - return MXC_FLC_ME11_Write32(address, data); -} - -int MXC_FLC_Write128(uint32_t address, uint32_t *data) -{ - return MXC_FLC_ME11_Write128(address, data); + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address); } +//****************************************************************************** int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer) { return MXC_FLC_Com_Write(address, length, buffer); } -void MXC_FLC_Read(int address, void* buffer, int len) + +//****************************************************************************** +void MXC_FLC_Read(int address, void *buffer, int len) { MXC_FLC_Com_Read(address, buffer, len); } +//****************************************************************************** int MXC_FLC_EnableInt(uint32_t flags) { return MXC_FLC_RevA_EnableInt(flags); } +//****************************************************************************** int MXC_FLC_DisableInt(uint32_t flags) { return MXC_FLC_RevA_DisableInt(flags); } +//****************************************************************************** int MXC_FLC_GetFlags(void) { return MXC_FLC_RevA_GetFlags(); } +//****************************************************************************** int MXC_FLC_ClearFlags(uint32_t flags) { return MXC_FLC_RevA_ClearFlags(flags); } -int MXC_FLC_UnlockInfoBlock(uint32_t address) +//****************************************************************************** +int MXC_FLC_BlockPageWrite(uint32_t address) { - return MXC_FLC_ME11_UnlockInfoBlock(address); + /* MAX32660 does not support flash page read and write locks */ + return E_NOT_SUPPORTED; } -int MXC_FLC_LockInfoBlock(uint32_t address) +//****************************************************************************** +int MXC_FLC_BlockPageRead(uint32_t address) +{ + /* MAX32660 does not support flash page read and write locks */ + return E_NOT_SUPPORTED; +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num) +{ + /* MAX32660 does not support flash page read and write locks */ + return NULL; +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num) { - return MXC_FLC_ME11_LockInfoBlock(address); + /* MAX32660 does not support flash page read and write locks */ + return NULL; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c index 4e380c62ee4..befba39794c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c @@ -3,8 +3,8 @@ * @brief Flash Controler driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -53,50 +52,56 @@ /* **** Definitions **** */ /* **** Globals **** */ +#ifdef MXC_FLC0 +static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC0; +#else +static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC; +#endif /* **** Functions **** */ //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -static int MXC_busy_flc(mxc_flc_reva_regs_t* flc) +static int MXC_busy_flc(mxc_flc_reva_regs_t *flc) { - return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE)); + return (flc->ctrl & + (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE)); } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc) +static int MXC_prepare_flc(mxc_flc_reva_regs_t *flc) { /* Check if the flash controller is busy */ if (MXC_busy_flc(flc)) { return E_BUSY; } - + // Set flash clock divider to generate a 1MHz clock from the APB clock flc->clkdiv = SystemCoreClock / 1000000; - + /* Clear stale errors */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; } - + /* Unlock flash */ flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED; - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif @@ -105,60 +110,61 @@ int MXC_FLC_RevA_Busy(void) uint32_t flc_cn = 0; int i; mxc_flc_reva_regs_t *flc; - + for (i = 0; i < MXC_FLC_INSTANCES; i++) { - flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i); - flc_cn = MXC_busy_flc (flc); - + flc = (mxc_flc_reva_regs_t *)MXC_FLC_GET_FLC(i); + flc_cn = MXC_busy_flc(flc); + if (flc_cn != 0) { break; } } - + return flc_cn; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc) +int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc) { int err; - + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { return err; } - + /* Write mass erase code */ - flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL; - + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | + MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL; + /* Issue mass erase command */ flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME; - + /* Wait until flash operation is complete */ - while (MXC_busy_flc(flc)); - + while (MXC_busy_flc(flc)) {} + /* Lock flash */ flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; - + /* Check access violations */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; return E_BAD_STATE; } - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr) +int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr) { int err; @@ -167,108 +173,158 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr) } /* Write page erase code */ - flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE; + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | + MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE; /* Issue page erase command */ flc->addr = addr; flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE; - + /* Wait until flash operation is complete */ - while (MXC_FLC_Busy()); - + while (MXC_busy_flc(flc)) {} + /* Lock flash */ flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; - + /* Check access violations */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; return E_BAD_STATE; } - + return E_NO_ERROR; } +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data, + uint32_t physicalAddr) +{ + int err; + // Address checked if it is byte addressable + if (logicAddr & 0x3) { + return E_BAD_PARAM; + } + + // Check if the location trying to be written has 1's in to be written to 0's + if ((*(uint32_t *)logicAddr & data) != data) { + return E_BAD_STATE; + } + + // Align address to 32-bit word + logicAddr = logicAddr & 0xfffffffc; + + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { + return err; + } + + // write 32-bits + flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH; + + // write the data + flc->addr = logicAddr; + flc->data[0] = data; + flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; + + /* Wait until flash operation is complete */ + while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {} + while (MXC_busy_flc(flc)) {} + + /* Lock flash */ + flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; + + /* Check access violations */ + if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { + flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; + return E_BAD_STATE; + } + + return E_NO_ERROR; +} //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr) +int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data, + uint32_t physicalAddr) { int err, i = 0; uint32_t byte; - volatile uint32_t* ptr; - uint32_t current_data[4] = {0, 0, 0, 0}; - + volatile uint32_t *ptr; + uint32_t current_data[4] = { 0, 0, 0, 0 }; + // Address checked if it is byte addressable if (logicAddr & 0x3) { return E_BAD_PARAM; } - + // Check if the location trying to be written has 1's in to be written to 0's - if ((* (uint32_t*) logicAddr & data) != data) { + if ((*(uint32_t *)logicAddr & data) != data) { return E_BAD_STATE; } - + // Get byte idx within 128-bit word byte = (logicAddr & 0xf); // Align address to 128-bit word logicAddr = logicAddr & 0xfffffff0; - + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { return err; } - + // Get current data stored in flash - for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) { + for (ptr = (uint32_t *)logicAddr; ptr < (uint32_t *)(logicAddr + 16); ptr++, i++) { current_data[i] = *ptr; } - + // write the data flc->addr = physicalAddr; - + if (byte < 4) { current_data[0] = data; - } - else if (byte < 8) { + } else if (byte < 8) { current_data[1] = data; - } - else if (byte < 12) { + } else if (byte < 12) { current_data[2] = data; - } - else { + } else { current_data[3] = data; } - + return MXC_FLC_Write128(logicAddr, current_data); } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data) +int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data) { int err; - + // Address checked if it is 128-bit aligned if (addr & 0xF) { return E_BAD_PARAM; } - + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { return err; } - + // write 128-bits flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_WDTH; - + // write the data flc->addr = addr; flc->data[0] = data[0]; @@ -278,101 +334,152 @@ int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *da flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; /* Wait until flash operation is complete */ - while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){} - while (MXC_busy_flc (flc)){} - + while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {} + while (MXC_busy_flc(flc)) {} + /* Lock flash */ flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; - + /* Check access violations */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; return E_BAD_STATE; } - + return E_NO_ERROR; } +//****************************************************************************** +void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc) +{ + flc_int = flc; +} + +//****************************************************************************** +mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void) +{ + return flc_int; +} + //****************************************************************************** int MXC_FLC_RevA_EnableInt(uint32_t mask) { - mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); - + mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); + if (!mask) { /* No bits set? Wasn't something we can enable. */ return E_BAD_PARAM; } - + /* Apply enables and write back, preserving the flags */ - ((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr |= mask; - + flc_int->intr |= mask; + return E_NO_ERROR; } //****************************************************************************** int MXC_FLC_RevA_DisableInt(uint32_t mask) { - mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); - + mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); + if (!mask) { /* No bits set? Wasn't something we can disable. */ return E_BAD_PARAM; } - + /* Apply disables and write back, preserving the flags */ - ((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr &= ~mask; - + flc_int->intr &= ~mask; + return E_NO_ERROR; } //****************************************************************************** int MXC_FLC_RevA_GetFlags(void) { - return (((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF)); + return (flc_int->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF)); } //****************************************************************************** int MXC_FLC_RevA_ClearFlags(uint32_t mask) { mask &= (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF); - + if (!mask) { /* No bits set? Wasn't something we can clear. */ return E_BAD_PARAM; } - + /* Both flags are write zero clear */ - ((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr ^= mask; - + flc_int->intr ^= mask; + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) +int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { - if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { + if ((address < MXC_INFO_MEM_BASE) || + (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } /* Make sure the info block is locked */ flc->actrl = 0x1234; - + /* Write the unlock sequence */ flc->actrl = 0x3a7f5ca3; flc->actrl = 0xa1e34f20; flc->actrl = 0x9608b2c1; - + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) +int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { - if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { + if ((address < MXC_INFO_MEM_BASE) || + (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } - + flc->actrl = 0xDEADBEEF; return E_NO_ERROR; } + +//****************************************************************************** +int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base) +{ + uint32_t page_num; + page_num = address - bank_base; // Get page number in flash bank + page_num /= MXC_FLASH_PAGE_SIZE; + + volatile uint32_t *welr = MXC_FLC_GetWELR( + address, page_num); // Get pointer to WELR register containing corresponding page bit + + while (page_num > 31) { // Set corresponding bit in WELR register + page_num -= 32; + } + *welr = (1 << page_num); + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base) +{ + uint32_t page_num; + page_num = address - bank_base; // Get page number in flash bank + page_num /= MXC_FLASH_PAGE_SIZE; + + volatile uint32_t *rlr = MXC_FLC_GetRLR( + address, page_num); // Get pointer to RLR register containing corresponding page bit + + while (page_num > 31) { // Set corresponding bit in WELR register + page_num -= 32; + } + *rlr = (1 << page_num); + + return E_NO_ERROR; +} + /**@} end of group flc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h index 80c7083a65a..618828704b2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h @@ -1,10 +1,10 @@ /** - * @file flc.h - * @brief Flash Controler driver. + * @file flc_reva.h + * @brief Flash RevA Controller driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_ /* **** Includes **** */ #include @@ -43,6 +45,7 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "flc.h" +#include "flc_common.h" #include "flc_reva_regs.h" /** @@ -56,30 +59,44 @@ /* **** Functions **** */ -int MXC_FLC_RevA_Busy (void); +int MXC_FLC_RevA_Busy(void); -int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc); +int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc); -int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr); +int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr); -int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr); +int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, + uint32_t physicalAddr); -int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data); +int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, + uint32_t physicalAddr); -int MXC_FLC_RevA_EnableInt (uint32_t mask); +int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data); -int MXC_FLC_RevA_DisableInt (uint32_t mask); +void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc); -int MXC_FLC_RevA_GetFlags (void); +mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void); -int MXC_FLC_RevA_ClearFlags (uint32_t mask); +int MXC_FLC_RevA_EnableInt(uint32_t mask); -int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); +int MXC_FLC_RevA_DisableInt(uint32_t mask); -int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); -/**@} end of group flc */ +int MXC_FLC_RevA_GetFlags(void); + +int MXC_FLC_RevA_ClearFlags(uint32_t mask); + +int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address); +int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address); + +int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base); + +int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base); + +/**@} end of group flc */ #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h index 7a3fc60ea7a..bf6419f50c1 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FLC_REVA_REGS_H_ -#define _FLC_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,13 +45,13 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) - #pragma system_include +#pragma system_include #endif - + #if defined (__CC_ARM) - #pragma anon_unions +#pragma anon_unions #endif /// @cond /* @@ -104,13 +103,13 @@ typedef struct { * @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address. * @{ */ - #define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: 0x0000 */ - #define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: 0x0004 */ - #define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: 0x0008 */ - #define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: 0x0024 */ - #define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: 0x0028 */ - #define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: 0x0030 */ - #define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: 0x0040 */ +#define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: 0x0000 */ +#define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: 0x0004 */ +#define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: 0x0008 */ +#define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: 0x0024 */ +#define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: 0x0028 */ +#define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: 0x0030 */ +#define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: 0x0040 */ /**@} end of group flc_reva_registers */ /** @@ -119,8 +118,8 @@ typedef struct { * @brief Flash Write Address. * @{ */ - #define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ - #define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ +#define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ /**@} end of group FLC_REVA_ADDR_Register */ @@ -131,8 +130,8 @@ typedef struct { * MHz clock for Flash controller. * @{ */ - #define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ +#define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ /**@} end of group FLC_REVA_CLKDIV_Register */ @@ -142,39 +141,39 @@ typedef struct { * @brief Flash Control Register. * @{ */ - #define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ - #define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ +#define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ +#define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ - #define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ - #define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ +#define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ +#define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ - #define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ - #define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ +#define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ +#define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ - #define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ - #define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ +#define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ +#define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ - #define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ - #define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ - #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ - #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ - #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ - #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ - #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ - #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ +#define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ - #define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ - #define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ +#define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ +#define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ - #define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ - #define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ +#define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ - #define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ - #define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ - #define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ - #define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ - #define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ - #define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ +#define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ +#define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ +#define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ /**@} end of group FLC_REVA_CTRL_Register */ @@ -184,17 +183,17 @@ typedef struct { * @brief Flash Interrupt Register. * @{ */ - #define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ - #define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ +#define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ +#define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ - #define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ - #define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ +#define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ +#define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ - #define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ - #define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ +#define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ +#define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ - #define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ - #define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ +#define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ +#define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ /**@} end of group FLC_REVA_INTR_Register */ @@ -204,11 +203,11 @@ typedef struct { * @brief ECC Data Register. * @{ */ - #define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ - #define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ +#define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ +#define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ - #define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ - #define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ +#define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ +#define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ /**@} end of group FLC_REVA_ECCDATA_Register */ @@ -218,8 +217,8 @@ typedef struct { * @brief Flash Write Data. * @{ */ - #define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ /**@} end of group FLC_REVA_DATA_Register */ @@ -234,8 +233,8 @@ typedef struct { * this register is always zero. * @{ */ - #define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ - #define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ +#define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ /**@} end of group FLC_REVA_ACTRL_Register */ @@ -243,4 +242,4 @@ typedef struct { } #endif -#endif /* _FLC_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c index a2bd8b5da61..ba58087f359 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,17 +29,18 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include +#include "gpio_common.h" #include "mxc_device.h" #include "mxc_assert.h" #include "gpio.h" -#include /* **** Globals **** */ -static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void*); -static void* cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; +static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *); +static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; static uint8_t initialized = 0; /* **** Functions **** */ @@ -47,34 +48,35 @@ int MXC_GPIO_Common_Init(uint32_t portmask) { if (!initialized) { int i, j; - + for (i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) { // Initialize call back arrays for (j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) { callback[i][j] = NULL; } } - + initialized = 1; } - + return E_NO_ERROR; } -void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata) +void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, + void *cbdata) { uint32_t mask; unsigned int pin; - + mask = cfg->mask; pin = 0; - + while (mask) { if (mask & 1) { callback[MXC_GPIO_GET_IDX(cfg->port)][pin] = func; cbparam[MXC_GPIO_GET_IDX(cfg->port)][pin] = cbdata; } - + pin++; mask >>= 1; } @@ -84,23 +86,23 @@ void MXC_GPIO_Common_Handler(unsigned int port) { uint32_t stat; unsigned int pin; - + MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES); - - mxc_gpio_regs_t* gpio = MXC_GPIO_GET_GPIO(port); - + + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); + stat = MXC_GPIO_GetFlags(gpio); MXC_GPIO_ClearFlags(gpio, stat); - + pin = 0; - + while (stat) { if (stat & 1) { if (callback[port][pin]) { callback[port][pin](cbparam[port][pin]); } } - + pin++; stat >>= 1; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h index 28720d601dc..6c02acd5d34 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_ /* **** Includes **** */ #include "gpio_regs.h" +#include "gpio.h" #ifdef __cplusplus extern "C" { @@ -40,9 +44,10 @@ extern "C" { /* **** Function Prototypes **** */ -int MXC_GPIO_Common_Init (uint32_t portmask); -void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); -void MXC_GPIO_Common_Handler (unsigned int port); +int MXC_GPIO_Common_Init(uint32_t portmask); +void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, + void *cbdata); +void MXC_GPIO_Common_Handler(unsigned int port); /**@} end of group gpio */ @@ -50,3 +55,4 @@ void MXC_GPIO_Common_Handler (unsigned int port); } #endif +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c index 15de33f37b6..78c1e0fbf9c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,43 +29,41 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include #include "mxc_device.h" #include "mxc_assert.h" #include "mxc_errors.h" #include "gpio.h" #include "gpio_reva.h" #include "gpio_common.h" -#include #include "mxc_sys.h" /* **** Functions **** */ int MXC_GPIO_Init(uint32_t portmask) { - int retval = MXC_GPIO_Common_Init(portmask); - - if(portmask & MXC_GPIO_PORT_0) { + if (portmask & MXC_GPIO_PORT_0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - - return MXC_GPIO_Common_Init(portmask) + retval; + + return MXC_GPIO_Common_Init(portmask); } int MXC_GPIO_Shutdown(uint32_t portmask) { - if(portmask & MXC_GPIO_PORT_0) { + if (portmask & MXC_GPIO_PORT_0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - + return E_NO_ERROR; } int MXC_GPIO_Reset(uint32_t portmask) { - if(portmask & MXC_GPIO_PORT_0) { + if (portmask & MXC_GPIO_PORT_0) { MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); } @@ -75,99 +73,97 @@ int MXC_GPIO_Reset(uint32_t portmask) int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) { mxc_gpio_regs_t *gpio = cfg->port; - + // Set the GPIO type - switch(cfg->func) { + switch (cfg->func) { case MXC_GPIO_FUNC_IN: - gpio->out_en_clr = cfg->mask; - gpio->en0_set = cfg->mask; - gpio->en1_clr = cfg->mask; - gpio->en2_clr = cfg->mask; + gpio->out_en_clr = cfg->mask; + gpio->en0_set = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; break; - + case MXC_GPIO_FUNC_OUT: - gpio->out_en_set = cfg->mask; - gpio->en0_set = cfg->mask; - gpio->en1_clr = cfg->mask; - gpio->en2_clr = cfg->mask; + gpio->out_en_set = cfg->mask; + gpio->en0_set = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; break; - + case MXC_GPIO_FUNC_ALT1: - gpio->en0_clr = cfg->mask; - gpio->en1_clr = cfg->mask; - gpio->en2_clr = cfg->mask; + gpio->en0_clr = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; break; - + case MXC_GPIO_FUNC_ALT2: - gpio->en0_clr = cfg->mask; - gpio->en1_set = cfg->mask; - gpio->en2_clr = cfg->mask; + gpio->en0_clr = cfg->mask; + gpio->en1_set = cfg->mask; + gpio->en2_clr = cfg->mask; break; - + case MXC_GPIO_FUNC_ALT3: - gpio->en0_set = cfg->mask; - gpio->en1_set = cfg->mask; + gpio->en0_set = cfg->mask; + gpio->en1_set = cfg->mask; // gpio->en2_set |= cfg->mask; break; - + default: return E_BAD_PARAM; } - + // Configure the pad - switch(cfg->pad) { + switch (cfg->pad) { case MXC_GPIO_PAD_NONE: gpio->pad_cfg1 &= ~cfg->mask; break; - + case MXC_GPIO_PAD_PULL_UP: - gpio->pad_cfg1 |= cfg->mask; + gpio->pad_cfg1 |= cfg->mask; gpio->ps |= cfg->mask; break; - + case MXC_GPIO_PAD_PULL_DOWN: - gpio->pad_cfg1 |= cfg->mask; + gpio->pad_cfg1 |= cfg->mask; gpio->ps &= ~cfg->mask; break; - + default: return E_BAD_PARAM; } - + // Configure the vssel - MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); - - return E_NO_ERROR; + return MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); } uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) { - return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t*) port, mask); + return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask); } void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask); } void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask); } uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) { - return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t*) port, mask); + return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask); } void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) { - MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t*) port, mask, val); + MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val); } void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask); } int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) @@ -177,12 +173,12 @@ int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask); } void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask); } void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata) @@ -197,15 +193,30 @@ void MXC_GPIO_Handler(unsigned int port) void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) { - MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t*) port, flags); + MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags); } uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) { - return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t*) port); + return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port); } int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { - return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t*) port, vssel, mask); + return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask); +} + +void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask); +} + +void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask); +} + +uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port) +{ + return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c index 72fb8a170d6..4c70cf16391 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,173 +29,209 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include #include "mxc_device.h" #include "mxc_assert.h" #include "mxc_errors.h" #include "gpio.h" #include "gpio_reva.h" #include "gpio_common.h" -#include /* **** Functions **** */ -uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask) +uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask) { return (port->in & mask); } -void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_OutSet(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->out_set = mask; } -void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_OutClr(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->out_clr = mask; } -uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask) +uint32_t MXC_GPIO_RevA_OutGet(mxc_gpio_reva_regs_t *port, uint32_t mask) { return (port->out & mask); } -void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val) +void MXC_GPIO_RevA_OutPut(mxc_gpio_reva_regs_t *port, uint32_t mask, uint32_t val) { port->out = (port->out & ~mask) | (val & mask); } -void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_OutToggle(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->out ^= mask; } -int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol) +int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) { - mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t*) cfg->port; - + mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t *)cfg->port; + switch (pol) { case MXC_GPIO_INT_HIGH: - gpio->intpol &= ~cfg->mask; + gpio->intpol |= cfg->mask; gpio->dualedge &= ~cfg->mask; - gpio->intmode &= ~cfg->mask; + gpio->intmode &= ~cfg->mask; break; - - case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */ - gpio->intpol &= ~cfg->mask; - gpio->dualedge &= ~cfg->mask; - gpio->intmode |= cfg->mask; + + case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */ + gpio->intpol &= ~cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode |= cfg->mask; break; - - case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */ - gpio->intpol |= cfg->mask; - gpio->dualedge &= ~cfg->mask; - gpio->intmode &= ~cfg->mask; + + case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */ + gpio->intpol &= ~cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode &= ~cfg->mask; break; - - case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */ - gpio->intpol |= cfg->mask; + + case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */ + gpio->intpol |= cfg->mask; gpio->dualedge &= ~cfg->mask; - gpio->intmode |= cfg->mask; + gpio->intmode |= cfg->mask; break; - + case MXC_GPIO_INT_BOTH: - gpio->dualedge |= cfg->mask; - gpio->intmode |= cfg->mask; + gpio->dualedge |= cfg->mask; + gpio->intmode |= cfg->mask; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_EnableInt(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->inten_set = mask; } -void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->inten_clr = mask; } -void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags) +void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags) { - port->intfl_clr = flags; + port->intfl_clr = flags; } -uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port) +uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port) { return port->intfl; } -int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask) +int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { // Configure the vssel switch (vssel) { case MXC_GPIO_VSSEL_VDDIO: port->vssel &= ~mask; break; - + case MXC_GPIO_VSSEL_VDDIOH: port->vssel |= mask; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask) +int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask) { + //This is required for new devices going forward. + port->inen |= mask; + + //Switch to I/O mode first + port->en0_set = mask; + switch (func) { case MXC_GPIO_FUNC_IN: - port->outen_clr = mask; - port->en0_set = mask; - port->en1_clr = mask; - port->en2_clr = mask; + port->outen_clr = mask; + port->en0_set = mask; + port->en1_clr = mask; + port->en2_clr = mask; + port->en3_clr = mask; break; - + case MXC_GPIO_FUNC_OUT: - port->outen_set = mask; - port->en0_set = mask; - port->en1_clr = mask; - port->en2_clr = mask; + port->outen_set = mask; + port->en0_set = mask; + port->en1_clr = mask; + port->en2_clr = mask; + port->en3_clr = mask; break; - + case MXC_GPIO_FUNC_ALT1: - port->en0_clr = mask; - port->en1_clr = mask; - port->en2_clr = mask; + port->en3_clr = mask; + port->en2_clr = mask; + port->en1_clr = mask; + port->en0_clr = mask; break; - + case MXC_GPIO_FUNC_ALT2: - port->en0_clr = mask; - port->en1_set = mask; - port->en2_clr = mask; + port->en3_clr = mask; + port->en2_clr = mask; + port->en1_set = mask; + port->en0_clr = mask; break; - #if TARGET_NUM != 32650 +#if TARGET_NUM != 32650 case MXC_GPIO_FUNC_ALT3: - port->en0_clr = mask; - port->en1_clr = mask; - port->en2_set = mask; + port->en3_clr = mask; + port->en2_set = mask; + port->en1_clr = mask; + port->en0_clr = mask; break; - + case MXC_GPIO_FUNC_ALT4: - port->en0_clr = mask; - port->en1_set = mask; - port->en2_set = mask; + port->en3_clr = mask; + port->en2_set = mask; + port->en1_set = mask; + port->en0_clr = mask; break; - #endif + +#if TARGET_NUM == 32662 + case MXC_GPIO_FUNC_ALT5: + port->en3_set = mask; + port->en2_clr = mask; + port->en1_clr = mask; + port->en0_clr = mask; + break; +#endif +#endif default: return E_BAD_PARAM; } - return E_NO_ERROR; + return E_NO_ERROR; +} + +void MXC_GPIO_RevA_SetWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask) +{ + port->wken_set = mask; +} + +void MXC_GPIO_RevA_ClearWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask) +{ + port->wken_clr = mask; +} + +uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port) +{ + return port->wken; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h index b9c7b200d77..22f643710d2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_ /* **** Includes **** */ #include "gpio_reva_regs.h" @@ -38,36 +41,37 @@ extern "C" { #endif - - /** * @brief Enumeration type for the pullup strength on a given pin. */ typedef enum { - MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/ - MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/ + MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/ + MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/ } mxc_gpio_ps_t; /* **** Function Prototypes **** */ -uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask); -uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val); -void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask); -int MXC_GPIO_RevA_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); -void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags); -uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port); -#if TARGET_NUM != 32650 -int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); -#endif -int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask); +uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_OutSet(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_OutClr(mxc_gpio_reva_regs_t *port, uint32_t mask); +uint32_t MXC_GPIO_RevA_OutGet(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_OutPut(mxc_gpio_reva_regs_t *port, uint32_t mask, uint32_t val); +void MXC_GPIO_RevA_OutToggle(mxc_gpio_reva_regs_t *port, uint32_t mask); +int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); +void MXC_GPIO_RevA_EnableInt(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags); +uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port); +int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask); +int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask); +void MXC_GPIO_RevA_SetWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_ClearWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask); +uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port); /**@} end of group gpio */ #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h index 27a20b1094a..1433971d1fd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h @@ -1,10 +1,10 @@ /** - * @file gpio_regs.h - * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @file gpio_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _GPIO_REVA_REGS_H_ -#define _GPIO_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +45,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,616 +74,665 @@ extern "C" { /* **** Definitions **** */ /** - * @ingroup gpio - * @defgroup gpio_registers GPIO_Registers - * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @ingroup gpio_reva + * @defgroup gpio_reva_registers GPIO_REVA_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module. * @details Individual I/O for each GPIO */ /** - * @ingroup gpio_registers - * Structure type to access the GPIO Registers. + * @ingroup gpio_reva_registers + * Structure type to access the GPIO_REVA Registers. */ typedef struct { - __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ - __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ - __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ - __IO uint32_t outen; /**< \b 0x0C: GPIO OUTEN Register */ - __IO uint32_t outen_set; /**< \b 0x10: GPIO OUTEN_SET Register */ - __IO uint32_t outen_clr; /**< \b 0x14: GPIO OUTEN_CLR Register */ - __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ - __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ - __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ - __I uint32_t in; /**< \b 0x24: GPIO IN Register */ - __IO uint32_t intmode; /**< \b 0x28: GPIO INTMODE Register */ - __IO uint32_t intpol; /**< \b 0x2C: GPIO INTPOL Register */ - __IO uint32_t inen; /**< \b 0x30: GPIO INEN Register */ - __IO uint32_t inten; /**< \b 0x34: GPIO INTEN Register */ - __IO uint32_t inten_set; /**< \b 0x38: GPIO INTEN_SET Register */ - __IO uint32_t inten_clr; /**< \b 0x3C: GPIO INTEN_CLR Register */ - __I uint32_t intfl; /**< \b 0x40: GPIO INTFL Register */ + __IO uint32_t en0; /**< \b 0x00: GPIO_REVA EN0 Register */ + __IO uint32_t en0_set; /**< \b 0x04: GPIO_REVA EN0_SET Register */ + __IO uint32_t en0_clr; /**< \b 0x08: GPIO_REVA EN0_CLR Register */ + __IO uint32_t outen; /**< \b 0x0C: GPIO_REVA OUTEN Register */ + __IO uint32_t outen_set; /**< \b 0x10: GPIO_REVA OUTEN_SET Register */ + __IO uint32_t outen_clr; /**< \b 0x14: GPIO_REVA OUTEN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO_REVA OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO_REVA OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO_REVA OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO_REVA IN Register */ + __IO uint32_t intmode; /**< \b 0x28: GPIO_REVA INTMODE Register */ + __IO uint32_t intpol; /**< \b 0x2C: GPIO_REVA INTPOL Register */ + __IO uint32_t inen; /**< \b 0x30: GPIO_REVA INEN Register */ + __IO uint32_t inten; /**< \b 0x34: GPIO_REVA INTEN Register */ + __IO uint32_t inten_set; /**< \b 0x38: GPIO_REVA INTEN_SET Register */ + __IO uint32_t inten_clr; /**< \b 0x3C: GPIO_REVA INTEN_CLR Register */ + __I uint32_t intfl; /**< \b 0x40: GPIO_REVA INTFL Register */ __R uint32_t rsv_0x44; - __IO uint32_t intfl_clr; /**< \b 0x48: GPIO INTFL_CLR Register */ - __IO uint32_t wken; /**< \b 0x4C: GPIO WKEN Register */ - __IO uint32_t wken_set; /**< \b 0x50: GPIO WKEN_SET Register */ - __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ + __IO uint32_t intfl_clr; /**< \b 0x48: GPIO_REVA INTFL_CLR Register */ + __IO uint32_t wken; /**< \b 0x4C: GPIO_REVA WKEN Register */ + __IO uint32_t wken_set; /**< \b 0x50: GPIO_REVA WKEN_SET Register */ + __IO uint32_t wken_clr; /**< \b 0x54: GPIO_REVA WKEN_CLR Register */ __R uint32_t rsv_0x58; - __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ - __IO uint32_t padctrl0; /**< \b 0x60: GPIO PADCTRL0 Register */ - __IO uint32_t padctrl1; /**< \b 0x64: GPIO PADCTRL1 Register */ - __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ - __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ - __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ - __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ - __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ - __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ - __R uint32_t rsv_0x80_0xa7[10]; - __IO uint32_t hysen; /**< \b 0xA8: GPIO HYSEN Register */ - __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ - __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ - __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ - __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ + __IO uint32_t dualedge; /**< \b 0x5C: GPIO_REVA DUALEDGE Register */ + __IO uint32_t padctrl0; /**< \b 0x60: GPIO_REVA PADCTRL0 Register */ + __IO uint32_t padctrl1; /**< \b 0x64: GPIO_REVA PADCTRL1 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO_REVA EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO_REVA EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO_REVA EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO_REVA EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO_REVA EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO_REVA EN2_CLR Register */ + __IO uint32_t en3; /**< \b 0x80: GPIO_REVA EN3 Register */ + __IO uint32_t en3_set; /**< \b 0x84: GPIO_REVA EN3_SET Register */ + __IO uint32_t en3_clr; /**< \b 0x88: GPIO_REVA EN3_CLR Register */ + __R uint32_t rsv_0x8c_0xa7[7]; + __IO uint32_t hysen; /**< \b 0xA8: GPIO_REVA HYSEN Register */ + __IO uint32_t srsel; /**< \b 0xAC: GPIO_REVA SRSEL Register */ + __IO uint32_t ds0; /**< \b 0xB0: GPIO_REVA DS0 Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO_REVA DS1 Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO_REVA PS Register */ __R uint32_t rsv_0xbc; - __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ + __IO uint32_t vssel; /**< \b 0xC0: GPIO_REVA VSSEL Register */ } mxc_gpio_reva_regs_t; -/* Register offsets for module GPIO */ -/** - * @ingroup gpio_registers - * @defgroup GPIO_Register_Offsets Register Offsets - * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. - * @{ - */ - #define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ - #define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ - #define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ - #define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ - #define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ - #define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ - #define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ - #define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ - #define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ - #define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ - #define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ - #define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ - #define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ - #define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ - #define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ - #define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ - #define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ - #define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ - #define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ - #define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ - #define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ - #define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ - #define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ - #define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ - #define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ - #define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ - #define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ - #define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ - #define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ - #define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ - #define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ - #define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ - #define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ - #define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ - #define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ - #define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ -/**@} end of group gpio_registers */ - -/** - * @ingroup gpio_registers - * @defgroup GPIO_EN0 GPIO_EN0 +/* Register offsets for module GPIO_REVA */ +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_Register_Offsets Register Offsets + * @brief GPIO_REVA Peripheral Register Offsets from the GPIO_REVA Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO_REVA Base Address: 0x0000 */ +#define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO_REVA Base Address: 0x0004 */ +#define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO_REVA Base Address: 0x0008 */ +#define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO_REVA Base Address: 0x000C */ +#define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO_REVA Base Address: 0x0010 */ +#define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO_REVA Base Address: 0x0014 */ +#define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO_REVA Base Address: 0x0018 */ +#define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO_REVA Base Address: 0x001C */ +#define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO_REVA Base Address: 0x0020 */ +#define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO_REVA Base Address: 0x0024 */ +#define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO_REVA Base Address: 0x0028 */ +#define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO_REVA Base Address: 0x002C */ +#define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO_REVA Base Address: 0x0030 */ +#define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO_REVA Base Address: 0x0034 */ +#define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO_REVA Base Address: 0x0038 */ +#define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO_REVA Base Address: 0x003C */ +#define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO_REVA Base Address: 0x0040 */ +#define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO_REVA Base Address: 0x0048 */ +#define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO_REVA Base Address: 0x004C */ +#define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO_REVA Base Address: 0x0050 */ +#define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO_REVA Base Address: 0x0054 */ +#define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO_REVA Base Address: 0x005C */ +#define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO_REVA Base Address: 0x0060 */ +#define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO_REVA Base Address: 0x0064 */ +#define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO_REVA Base Address: 0x0068 */ +#define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO_REVA Base Address: 0x006C */ +#define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO_REVA Base Address: 0x0070 */ +#define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO_REVA Base Address: 0x0074 */ +#define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO_REVA Base Address: 0x0078 */ +#define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO_REVA Base Address: 0x007C */ +#define MXC_R_GPIO_REVA_EN3 ((uint32_t)0x00000080UL) /**< Offset from GPIO_REVA Base Address: 0x0080 */ +#define MXC_R_GPIO_REVA_EN3_SET ((uint32_t)0x00000084UL) /**< Offset from GPIO_REVA Base Address: 0x0084 */ +#define MXC_R_GPIO_REVA_EN3_CLR ((uint32_t)0x00000088UL) /**< Offset from GPIO_REVA Base Address: 0x0088 */ +#define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO_REVA Base Address: 0x00A8 */ +#define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO_REVA Base Address: 0x00AC */ +#define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO_REVA Base Address: 0x00B0 */ +#define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO_REVA Base Address: 0x00B4 */ +#define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO_REVA Base Address: 0x00B8 */ +#define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO_REVA Base Address: 0x00C0 */ +/**@} end of group gpio_reva_registers */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN0 GPIO_REVA_EN0 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one * GPIO pin on the associated port. * @{ */ - #define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_REVA_EN Position */ - #define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ - #define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ - #define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ - #define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ - #define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ +#define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ +#define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ +#define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ +#define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ +#define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ +#define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ -/**@} end of group GPIO_EN0_Register */ +/**@} end of group GPIO_REVA_EN0_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN0_SET GPIO_EN0_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN0_SET GPIO_REVA_EN0_SET * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this * register sets the bits in the same positions in GPIO_EN to 1, without affecting * other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ - #define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ -/**@} end of group GPIO_EN0_SET_Register */ +/**@} end of group GPIO_REVA_EN0_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN0_CLR GPIO_REVA_EN0_CLR * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this * register clears the bits in the same positions in GPIO_EN to 0, without * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ -/**@} end of group GPIO_EN0_CLR_Register */ +/**@} end of group GPIO_REVA_EN0_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUTEN GPIO_OUTEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUTEN GPIO_REVA_OUTEN * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one * GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ - #define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ - #define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ - #define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ - #define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ - #define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ +#define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ +#define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ +#define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ +#define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ +#define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ +#define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ -/**@} end of group GPIO_OUTEN_Register */ +/**@} end of group GPIO_REVA_OUTEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUTEN_SET GPIO_REVA_OUTEN_SET * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ - #define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ +#define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ -/**@} end of group GPIO_OUTEN_SET_Register */ +/**@} end of group GPIO_REVA_OUTEN_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUTEN_CLR GPIO_REVA_OUTEN_CLR * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ -/**@} end of group GPIO_OUTEN_CLR_Register */ +/**@} end of group GPIO_REVA_OUTEN_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUT GPIO_OUT + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUT GPIO_REVA_OUT * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the * associated port. This register can be written either directly, or by using the * GPIO_OUT_SET and GPIO_OUT_CLR registers. * @{ */ - #define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ - #define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ - #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ - #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ - #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ - #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ +#define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ +#define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ +#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ +#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ +#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ +#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ -/**@} end of group GPIO_OUT_Register */ +/**@} end of group GPIO_REVA_OUT_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUT_SET GPIO_REVA_OUT_SET * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits * in the same positions in GPIO_OUT to 1, without affecting other bits in that * register. * @{ */ - #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ - #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ - #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ - #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ - #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ - #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ +#define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ +#define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ +#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ +#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ +#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ +#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ -/**@} end of group GPIO_OUT_SET_Register */ +/**@} end of group GPIO_REVA_OUT_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUT_CLR GPIO_REVA_OUT_CLR * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the * bits in the same positions in GPIO_OUT to 0, without affecting other bits in * that register. * @{ */ - #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ - #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ +#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ +#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ -/**@} end of group GPIO_OUT_CLR_Register */ +/**@} end of group GPIO_REVA_OUT_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_IN GPIO_IN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_IN GPIO_REVA_IN * @brief GPIO Input Register. Read-only register to read from the logic states of the * GPIO pins on this port. * @{ */ - #define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ - #define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ +#define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ +#define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ -/**@} end of group GPIO_IN_Register */ +/**@} end of group GPIO_REVA_IN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTMODE GPIO_INTMODE + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTMODE GPIO_REVA_INTMODE * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt * mode setting for the associated GPIO pin on this port. * @{ */ - #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ - #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ - #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ - #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ - #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ - #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ +#define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ +#define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ +#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ +#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ +#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ +#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ -/**@} end of group GPIO_INTMODE_Register */ +/**@} end of group GPIO_REVA_INTMODE_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTPOL GPIO_INTPOL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTPOL GPIO_REVA_INTPOL * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the * interrupt polarity setting for one GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ - #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ - #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ - #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ - #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ - #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ +#define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ +#define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ +#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ +#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ +#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ +#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ -/**@} end of group GPIO_INTPOL_Register */ +/**@} end of group GPIO_REVA_INTPOL_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTEN GPIO_INTEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTEN GPIO_REVA_INTEN * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO * interrupt enable for the associated pin on the GPIO port. * @{ */ - #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_REVA_INTEN Position */ - #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ - #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ - #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ - #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ - #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ +#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ +#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ +#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ +#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ +#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ +#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ -/**@} end of group GPIO_INTEN_Register */ +/**@} end of group GPIO_REVA_INTEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTEN_SET GPIO_REVA_INTEN_SET * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits * in that register. * @{ */ - #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ - #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ - #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ - #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ - #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ - #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ +#define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ +#define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ +#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ +#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ +#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ +#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ -/**@} end of group GPIO_INTEN_SET_Register */ +/**@} end of group GPIO_REVA_INTEN_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTEN_CLR GPIO_REVA_INTEN_CLR * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting * other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ - #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ - #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ - #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ - #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ - #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ +#define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ +#define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ +#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ +#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ +#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ +#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ -/**@} end of group GPIO_INTEN_CLR_Register */ +/**@} end of group GPIO_REVA_INTEN_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTFL GPIO_INTFL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTFL GPIO_REVA_INTFL * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending * interrupt status for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ - #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ - #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ - #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ - #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ - #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ +#define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ +#define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ +#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ +#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ +#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ +#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ -/**@} end of group GPIO_INTFL_Register */ +/**@} end of group GPIO_REVA_INTFL_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTFL_CLR GPIO_REVA_INTFL_CLR * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits * in that register. * @{ */ - #define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ -/**@} end of group GPIO_INTFL_CLR_Register */ +/**@} end of group GPIO_REVA_INTFL_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_WKEN GPIO_WKEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_WKEN GPIO_REVA_WKEN * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup * enable for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ - #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ - #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_REVA_WKEN_DIS Value */ - #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_REVA_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ - #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ - #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ +#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ +#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ +#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ +#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ +#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ +#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ -/**@} end of group GPIO_WKEN_Register */ +/**@} end of group GPIO_REVA_WKEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_WKEN_SET GPIO_REVA_WKEN_SET * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in * that register. * @{ */ - #define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ - #define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ +#define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ -/**@} end of group GPIO_WKEN_SET_Register */ +/**@} end of group GPIO_REVA_WKEN_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_WKEN_CLR GPIO_REVA_WKEN_CLR * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ -/**@} end of group GPIO_WKEN_CLR_Register */ +/**@} end of group GPIO_REVA_WKEN_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_DUALEDGE GPIO_REVA_DUALEDGE * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual * edge mode for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ - #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ - #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ - #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ - #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ - #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ +#define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ +#define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ +#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ +#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ +#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ +#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ -/**@} end of group GPIO_DUALEDGE_Register */ +/**@} end of group GPIO_REVA_DUALEDGE_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_PADCTRL0 GPIO_REVA_PADCTRL0 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ - #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ - #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ - #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ - #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ - #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ - #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ - #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ +#define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ +#define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ +#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ +#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ +#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ +#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ +#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ +#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ -/**@} end of group GPIO_PADCTRL0_Register */ +/**@} end of group GPIO_REVA_PADCTRL0_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_PADCTRL1 GPIO_REVA_PADCTRL1 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ - #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ - #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ - #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ - #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ - #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ - #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ - #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ +#define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ +#define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ +#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ +#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ +#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ +#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ +#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ +#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ -/**@} end of group GPIO_PADCTRL1_Register */ +/**@} end of group GPIO_REVA_PADCTRL1_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN1 GPIO_EN1 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN1 GPIO_REVA_EN1 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ - #define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ - #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ - #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ - #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ - #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ +#define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ +#define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ +#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ +#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ +#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ +#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ -/**@} end of group GPIO_EN1_Register */ +/**@} end of group GPIO_REVA_EN1_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN1_SET GPIO_REVA_EN1_SET * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ - #define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ -/**@} end of group GPIO_EN1_SET_Register */ +/**@} end of group GPIO_REVA_EN1_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN1_CLR GPIO_REVA_EN1_CLR * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ -/**@} end of group GPIO_EN1_CLR_Register */ +/**@} end of group GPIO_REVA_EN1_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN2 GPIO_EN2 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN2 GPIO_REVA_EN2 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ - #define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ - #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ - #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ - #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ - #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ +#define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ +#define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ +#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ +#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ +#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ +#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ -/**@} end of group GPIO_EN2_Register */ +/**@} end of group GPIO_REVA_EN2_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN2_SET GPIO_REVA_EN2_SET * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ - #define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ -/**@} end of group GPIO_EN2_SET_Register */ +/**@} end of group GPIO_REVA_EN2_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN2_CLR GPIO_REVA_EN2_CLR * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this * register clears the bits in the same positions in GPIO_EN2 to 0, without * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_REVA_EN2_CLR_Register */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN3 GPIO_REVA_EN3 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS 0 /**< EN3_GPIO_EN3 Position */ +#define MXC_F_GPIO_REVA_EN3_GPIO_EN3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS)) /**< EN3_GPIO_EN3 Mask */ +#define MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY ((uint32_t)0x0UL) /**< EN3_GPIO_EN3_PRIMARY Value */ +#define MXC_S_GPIO_REVA_EN3_GPIO_EN3_PRIMARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_PRIMARY Setting */ +#define MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY ((uint32_t)0x1UL) /**< EN3_GPIO_EN3_SECONDARY Value */ +#define MXC_S_GPIO_REVA_EN3_GPIO_EN3_SECONDARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_SECONDARY Setting */ + +/**@} end of group GPIO_REVA_EN3_Register */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN3_SET GPIO_REVA_EN3_SET + * @brief GPIO Alternate Function 3 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN3 to 1, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_REVA_EN3_SET_ALL_POS 0 /**< EN3_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN3_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_SET_ALL_POS)) /**< EN3_SET_ALL Mask */ + +/**@} end of group GPIO_REVA_EN3_SET_Register */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN3_CLR GPIO_REVA_EN3_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN3 to 0, without + * affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_REVA_EN3_CLR_ALL_POS 0 /**< EN3_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN3_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_CLR_ALL_POS)) /**< EN3_CLR_ALL Mask */ -/**@} end of group GPIO_EN2_CLR_Register */ +/**@} end of group GPIO_REVA_EN3_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_HYSEN GPIO_HYSEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_HYSEN GPIO_REVA_HYSEN * @brief GPIO Input Hysteresis Enable. * @{ */ - #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ - #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ +#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ +#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ -/**@} end of group GPIO_HYSEN_Register */ +/**@} end of group GPIO_REVA_HYSEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_SRSEL GPIO_SRSEL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_SRSEL GPIO_REVA_SRSEL * @brief GPIO Slew Rate Enable Register. * @{ */ - #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ - #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ - #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ - #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ - #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ - #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ +#define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ +#define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ +#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ +#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ +#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ +#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ -/**@} end of group GPIO_SRSEL_Register */ +/**@} end of group GPIO_REVA_SRSEL_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_DS0 GPIO_DS0 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_DS0 GPIO_REVA_DS0 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ - #define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ - #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ - #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ - #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ - #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ +#define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ +#define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ +#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ +#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ +#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ +#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ -/**@} end of group GPIO_DS0_Register */ +/**@} end of group GPIO_REVA_DS0_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_DS1 GPIO_DS1 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_DS1 GPIO_REVA_DS1 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ - #define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ +#define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ +#define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ -/**@} end of group GPIO_DS1_Register */ +/**@} end of group GPIO_REVA_DS1_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_PS GPIO_PS + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_PS GPIO_REVA_PS * @brief GPIO Pull Select Mode. * @{ */ - #define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */ - #define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */ +#define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */ +#define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */ -/**@} end of group GPIO_PS_Register */ +/**@} end of group GPIO_REVA_PS_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_VSSEL GPIO_VSSEL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_VSSEL GPIO_REVA_VSSEL * @brief GPIO Voltage Select. * @{ */ - #define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ - #define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ +#define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ +#define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ -/**@} end of group GPIO_VSSEL_Register */ +/**@} end of group GPIO_REVA_VSSEL_Register */ #ifdef __cplusplus } #endif -#endif /* _GPIO_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c index 042207ec484..ffb3dcfb0b5 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c @@ -1,10 +1,10 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * @@ -15,7 +15,7 @@ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * @@ -24,12 +24,12 @@ * Products, Inc. Branding Policy. * * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, + * of trade secrets, proprietary technology, copyrights, patents, * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -42,7 +42,7 @@ #include "mxc_delay.h" #include "i2c_regs.h" #include "dma_regs.h" -#include "mxc_i2c.h" +#include "i2c.h" #include "i2c_reva.h" /* **** Definitions **** */ @@ -382,6 +382,16 @@ unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); } +void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AsyncStop((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AbortAsync((mxc_i2c_reva_regs_t *)i2c); +} + void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) { MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index 572ca6f0cb2..a9bd8110da9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -40,7 +40,7 @@ #include "mxc_sys.h" #include "mxc_delay.h" #include "i2c_regs.h" -#include "mxc_i2c.h" +#include "i2c.h" #include "i2c_reva.h" #include "dma.h" @@ -66,9 +66,8 @@ void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, - mxc_i2c_reva_slave_handler_t callback, - unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t *int_en, int *retVal); /* ************************************************************************* */ /* Control/Configuration functions */ @@ -145,8 +144,8 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz) return E_NULL_PTR; } - if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) { - // We're going to enable high speed + if (hz > MXC_I2C_REVA_FASTPLUS_SPEED && hz <= MXC_I2C_REVA_HIGH_SPEED) { + // Enable high speed mode int hsLowClks, hsHiClks; // Calculate the period of SCL and set up 33% duty cycle @@ -164,7 +163,17 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz) return E_BAD_PARAM; } + hsLowClks = (hsLowClks << MXC_F_I2C_REVA_HSCLK_LO_POS) & MXC_F_I2C_REVA_HSCLK_LO; + hsHiClks = (hsHiClks << MXC_F_I2C_REVA_HSCLK_HI_POS) & MXC_F_I2C_REVA_HSCLK_HI; + + i2c->hsclk = (hsLowClks | hsHiClks); + + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_HS_EN; + hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz + + } else if (hz > MXC_I2C_REVA_HIGH_SPEED) { + return E_BAD_PARAM; } // Calculate the period of SCL, 50% duty cycle @@ -805,7 +814,7 @@ int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req) i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {} // Wait for Transaction to finish } @@ -1017,9 +1026,12 @@ void MXC_I2C_RevA_DMACallback(int ch, int error) int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) { - unsigned int interruptEnables = interruptCheck; int retVal = E_NO_ERROR; + uint32_t int_en[2]; + int_en[0] = interruptCheck; + int_en[1] = 0; + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } @@ -1050,8 +1062,8 @@ int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_h // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - while (interruptEnables > 0) { - interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); + while (int_en[0] > 0 || int_en[1] > 0) { + MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &retVal); } return retVal; @@ -1270,9 +1282,8 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum) } } -unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, - mxc_i2c_reva_slave_handler_t callback, - unsigned int interruptEnables, int *retVal) +void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t *int_en, int *retVal) { uint32_t tFlags = i2c->intfl0; *retVal = E_NO_ERROR; @@ -1294,9 +1305,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - if (!(interruptEnables & - (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | - MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + if (!(int_en[0] & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | + MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // (fires anytime a stop/start is detected out of sequence). if (tFlags & MXC_I2C_REVA_ERROR) { @@ -1310,11 +1320,12 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { + if (int_en[0] & MXC_F_I2C_REVA_INTFL0_RX_THD || int_en[1] & MXC_F_I2C_REVA_INTFL1_RX_OV) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { if (callback != NULL) { callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); @@ -1332,8 +1343,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, } } - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | - MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + if (int_en[0] & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) || + int_en[1] & MXC_F_I2C_REVA_INTFL1_TX_UN) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (callback != NULL) { callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); @@ -1358,7 +1369,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, } i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } @@ -1371,7 +1383,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, } i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } @@ -1383,8 +1396,10 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | - MXC_I2C_REVA_ERROR; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; + + int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE | MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV; } if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { @@ -1394,8 +1409,9 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | - MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | + MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN; } if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { @@ -1404,19 +1420,23 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | - MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; + + int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | + MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN; } else { if (callback != NULL) { callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | - MXC_I2C_REVA_ERROR; + int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE | + MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV; } } else if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; @@ -1429,17 +1449,17 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c); - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - - return interruptEnables; } void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck) { int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int slaveRetVal; + uint32_t int_en[2]; if (i2cNum < 0) { return; @@ -1449,6 +1469,13 @@ void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck MXC_I2C_RevA_MasterAsyncHandler(i2cNum); } else { mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; - i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); + + int_en[0] = i2c->inten0; + int_en[1] = i2c->inten1; + + MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &slaveRetVal); + + i2c->inten0 = int_en[0]; + i2c->inten1 = int_en[1]; } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h index aa41e2c5761..74080f4bc36 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ @@ -51,7 +51,7 @@ #define MXC_I2C_REVA_STD_MODE 100000 #define MXC_I2C_REVA_FAST_SPEED 400000 #define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 -#define MXC_I2C_REVA_HS_MODE 3400000 +#define MXC_I2C_REVA_HIGH_SPEED 3400000 #define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF #define MXC_I2C_REVA_INTFL1_MASK 0x00000007 @@ -163,9 +163,8 @@ void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, - mxc_i2c_reva_slave_handler_t callback, - unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t *int_en, int *retVal); void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); void MXC_I2C_RevA_DMACallback(int ch, int error); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h index 49a434116ff..17e75c8b853 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c index 7a2c66485bb..7764fa929b4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -38,6 +38,7 @@ #include "mxc_sys.h" #include "icc.h" #include "icc_reva.h" +#include "icc_common.h" void MXC_ICC_Com_Flush(void) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h index 72e18408385..e6b1b751f69 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_ /* **** Includes **** */ #include "mxc_sys.h" @@ -48,3 +51,5 @@ void MXC_ICC_Com_Flush(void); #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c index f5565a426a4..aa60013442c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -42,22 +42,22 @@ /* **** Functions **** */ -int MXC_ICC_ID (mxc_icc_info_t cid) +int MXC_ICC_ID(mxc_icc_info_t cid) { - return MXC_ICC_RevA_ID ((mxc_icc_reva_regs_t*) MXC_ICC, cid); + return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)MXC_ICC, cid); } -void MXC_ICC_Enable (void) +void MXC_ICC_Enable(void) { - MXC_ICC_RevA_Enable ((mxc_icc_reva_regs_t*) MXC_ICC); + MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)MXC_ICC); } -void MXC_ICC_Disable (void) +void MXC_ICC_Disable(void) { - MXC_ICC_RevA_Disable ((mxc_icc_reva_regs_t*) MXC_ICC); + MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)MXC_ICC); } -void MXC_ICC_Flush (void) +void MXC_ICC_Flush(void) { MXC_ICC_Com_Flush(); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c index 5852ec4dd55..2984a8f8737 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -38,6 +38,7 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "icc.h" +#include "icc_reva.h" #include "icc_reva_regs.h" /* **** Definitions **** */ @@ -45,27 +46,27 @@ /* **** Globals **** */ /* **** Functions **** */ -static int MXC_ICC_Ready(mxc_icc_reva_regs_t* icc) +static int MXC_ICC_Ready(mxc_icc_reva_regs_t *icc) { return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY); } -int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid) +int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid) { - if(icc == NULL) { + if (icc == NULL) { return E_NULL_PTR; } - switch(cid) { + switch (cid) { case ICC_INFO_RELNUM: return ((icc->info & MXC_F_ICC_REVA_INFO_RELNUM) >> MXC_F_ICC_REVA_INFO_RELNUM_POS); - + case ICC_INFO_PARTNUM: return ((icc->info & MXC_F_ICC_REVA_INFO_PARTNUM) >> MXC_F_ICC_REVA_INFO_PARTNUM_POS); - + case ICC_INFO_ID: return ((icc->info & MXC_F_ICC_REVA_INFO_ID) >> MXC_F_ICC_REVA_INFO_ID_POS); - + default: return E_BAD_PARAM; } @@ -76,15 +77,15 @@ void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc) // Invalidate cache and wait until ready icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; icc->invalidate = 1; - - while(!(MXC_ICC_Ready(icc))); - + + while (!(MXC_ICC_Ready(icc))) {} + // Enable Cache icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN; - while(!(MXC_ICC_Ready(icc))); + while (!(MXC_ICC_Ready(icc))) {} } -void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t* icc) +void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc) { // Disable Cache icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h index 9cda9cdcaa9..bc3aeeef20d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software");, + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_ /* **** Includes **** */ #include "mxc_device.h" @@ -45,6 +48,8 @@ /* **** Functions **** */ -int MXC_ICC_RevA_ID (mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid); -void MXC_ICC_RevA_Enable (mxc_icc_reva_regs_t* icc); -void MXC_ICC_RevA_Disable (mxc_icc_reva_regs_t* icc); +int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid); +void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc); +void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h index dcdcad947e6..ac77603ac23 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _ICC_REVA_REGS_H_ -#define _ICC_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +45,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -101,10 +100,10 @@ typedef struct { * @brief ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address. * @{ */ - #define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: 0x0000 */ - #define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: 0x0004 */ - #define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: 0x0100 */ - #define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: 0x0700 */ +#define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: 0x0000 */ +#define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: 0x0004 */ +#define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: 0x0100 */ +#define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: 0x0700 */ /**@} end of group icc_reva_registers */ /** @@ -113,14 +112,14 @@ typedef struct { * @brief Cache ID Register. * @{ */ - #define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ - #define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ +#define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ - #define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ - #define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ +#define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ - #define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ - #define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ +#define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ /**@} end of group ICC_REVA_INFO_Register */ @@ -130,11 +129,11 @@ typedef struct { * @brief Memory Configuration Register. * @{ */ - #define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ - #define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ +#define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ - #define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ - #define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ +#define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ /**@} end of group ICC_REVA_SZ_Register */ @@ -144,11 +143,11 @@ typedef struct { * @brief Cache Control and Status Register. * @{ */ - #define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ - #define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ +#define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ /**@} end of group ICC_REVA_CTRL_Register */ @@ -156,4 +155,5 @@ typedef struct { } #endif -#endif /* _ICC_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c index 7f7d7ae7f6f..5f0514de2ae 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c @@ -3,8 +3,8 @@ * @brief Low power functions */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,14 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ - + ******************************************************************************/ /***** Includes *****/ #include "lp.h" #include "pwrseq_regs.h" -#include "mxc_errors.h" #include "gcr_regs.h" #include "mxc_device.h" #include "mxc_errors.h" @@ -56,7 +53,7 @@ void MXC_LP_ClearWakeStatus(void) MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF; /* These flags are slow to clear, so block until they do */ - while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en)); + while (MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en)) {} } void MXC_LP_EnableSRAM3(void) @@ -153,66 +150,65 @@ void MXC_LP_EnableRTCAlarmWakeup(void) { MXC_GCR->pm |= MXC_F_GCR_PM_RTCWK_EN; } - + void MXC_LP_DisableRTCAlarmWakeup(void) { MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN; } -void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask) +void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins) { MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN; - //switch(port) + //switch(wu_pins->port) //{ - /*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break; + /*case 0:*/ MXC_PWRSEQ->lpwk_en |= wu_pins->mask; //break; //} } -void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask) +void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins) { - //switch(port) + //switch(wu_pins->port) //{ - /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break; + /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; //break; //} - - if(MXC_PWRSEQ->lpwk_en == 0) - { + + if (MXC_PWRSEQ->lpwk_en == 0) { MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN; } } void MXC_LP_EnterSleepMode(void) -{ - // Clear SLEEPDEEP bit +{ + // Clear SLEEPDEEP bit SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - // Go into Sleep mode and wait for an interrupt to wake the processor + // Go into Sleep mode and wait for an interrupt to wake the processor __WFI(); } void MXC_LP_EnterDeepSleepMode(void) -{ - // Set SLEEPDEEP bit +{ + // Set SLEEPDEEP bit SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - // Auto-powerdown 96 MHz oscillator when in deep sleep + // Auto-powerdown 96 MHz oscillator when in deep sleep MXC_GCR->pm |= MXC_F_GCR_PM_HFIOPD; - // Go into Deepsleep mode and wait for an interrupt to wake the processor + // Go into Deepsleep mode and wait for an interrupt to wake the processor __WFI(); } void MXC_LP_EnterBackupMode(void) -{ +{ MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; - while(1); + while (1) {} } void MXC_LP_EnterShutdownMode(void) { MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN; - while(1); + while (1) {} } int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr) @@ -221,28 +217,29 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr) int error; // Ensure part is operating from internal LDO for core power - if(MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_LDO_DIS) { + if (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_LDO_DIS) { return E_BAD_STATE; } // Select the 8KHz nanoring (no guarantee 32KHz is attached) as system clock source current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; - if(current_clock == MXC_SYS_CLOCK_HIRC) { + if (current_clock == MXC_SYS_CLOCK_HIRC) { error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_NANORING); - if(error != E_NO_ERROR) { + if (error != E_NO_ERROR) { return error; } } // Set flash wait state for any clock so its not to low after clock changes. - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS); // Set the OVR bits MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR); MXC_PWRSEQ->lp_ctrl |= ovr; // Set LVE bit - if(ovr == MXC_LP_OVR_0_9) { + if (ovr == MXC_LP_OVR_0_9) { MXC_FLC->ctrl |= MXC_F_FLC_CTRL_LVE; } else { @@ -250,11 +247,11 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr) } // Revert the clock to original state if it was HIRC - if(current_clock == MXC_SYS_CLOCK_HIRC) { - error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); - if(error != E_NO_ERROR) { - return error; - } + if (current_clock == MXC_SYS_CLOCK_HIRC) { + error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); + if (error != E_NO_ERROR) { + return error; + } } // Update SystemCoreClock variable @@ -264,132 +261,162 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr) div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; // Set Flash Wait States - if(ovr == MXC_LP_OVR_0_9) { - if(div == 0) { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + if (ovr == MXC_LP_OVR_0_9) { + if (div == 0) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); } else { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); } - } else if(ovr == MXC_LP_OVR_1_0) { - if(div == 0) { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + } else if (ovr == MXC_LP_OVR_1_0) { + if (div == 0) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); } else { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); } } else { - if(div == 0) { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS); - - } else if(div == 1) { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + if (div == 0) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + + } else if (div == 1) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); } else { - MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | + (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); } } // Caller must perform peripheral reset return E_NO_ERROR; - } -void MXC_LP_EnableSRamRet0(void){ +void MXC_LP_EnableSRamRet0(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0; } - -void MXC_LP_DisableSRamRet0(void){ + +void MXC_LP_DisableSRamRet0(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0; } -void MXC_LP_EnableSRamRet1(void){ +void MXC_LP_EnableSRamRet1(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1; } - -void MXC_LP_DisableSRamRet1(void){ + +void MXC_LP_DisableSRamRet1(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1; } -void MXC_LP_EnableSRamRet2(void){ +void MXC_LP_EnableSRamRet2(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2; } - -void MXC_LP_DisableSRamRet2(void){ + +void MXC_LP_DisableSRamRet2(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2; } -void MXC_LP_EnableSRamRet3(void){ +void MXC_LP_EnableSRamRet3(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3; } - -void MXC_LP_DisableSRamRet3(void){ + +void MXC_LP_DisableSRamRet3(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3; } -void MXC_LP_EnableBlockDetect(void){ - MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; +void MXC_LP_EnableBlockDetect(void) +{ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; } -void MXC_LP_DisableBlockDetect(void){ - MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; +void MXC_LP_DisableBlockDetect(void) +{ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; } -void MXC_LP_EnableRamRetReg(void){ +void MXC_LP_EnableRamRetReg(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN; } -void MXC_LP_DisableRamRetReg(void){ +void MXC_LP_DisableRamRetReg(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN; } -void MXC_LP_EnableFastWk(void){ +void MXC_LP_EnableFastWk(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN; } -void MXC_LP_DisableFastWk(void){ +void MXC_LP_DisableFastWk(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN; } -void MXC_LP_EnableBandGap(void){ +void MXC_LP_EnableBandGap(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF; } -void MXC_LP_DisableBandGap(void){ +void MXC_LP_DisableBandGap(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF; } -void MXC_LP_EnableVCorePORSignal(void){ +void MXC_LP_EnableVCorePORSignal(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS; } -void MXC_LP_DisableVCorePORSignal(void){ +void MXC_LP_DisableVCorePORSignal(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS; } -void MXC_LP_EnableLDO(void){ +void MXC_LP_EnableLDO(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS; } -void MXC_LP_DisableLDO(void){ +void MXC_LP_DisableLDO(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS; } -void MXC_LP_EnableVCoreSVM(void){ +void MXC_LP_EnableVCoreSVM(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS; } -void MXC_LP_DisableVCoreSVM(void){ +void MXC_LP_DisableVCoreSVM(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS; } -void MXC_LP_EnableVDDIOPorMonitoF(void){ +void MXC_LP_EnableVDDIOPorMonitoF(void) +{ MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS; } -void MXC_LP_DisableVDDIOPorMonitor(void){ +void MXC_LP_DisableVDDIOPorMonitor(void) +{ MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c index 8dedda1a5fe..3b85639ce05 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ #include "mxc_device.h" #include "rtc_regs.h" @@ -43,77 +43,109 @@ /* ***** Functions ***** */ -int MXC_RTC_EnableInt (uint32_t mask) +int MXC_RTC_EnableInt(uint32_t mask) { - return MXC_RTC_RevA_EnableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask); + return MXC_RTC_RevA_EnableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); } -int MXC_RTC_DisableInt (uint32_t mask) +int MXC_RTC_DisableInt(uint32_t mask) { - return MXC_RTC_RevA_DisableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask); + return MXC_RTC_RevA_DisableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); } -int MXC_RTC_SetTimeofdayAlarm (uint32_t ras) +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras) { - return MXC_RTC_RevA_SetTimeofdayAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, ras); + return MXC_RTC_RevA_SetTimeofdayAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, ras); } -int MXC_RTC_SetSubsecondAlarm (uint32_t rssa) +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa) { - return MXC_RTC_RevA_SetSubsecondAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, rssa); + return MXC_RTC_RevA_SetSubsecondAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, rssa); } -int MXC_RTC_Start (void) +int MXC_RTC_Start(void) { - return MXC_RTC_RevA_Start ((mxc_rtc_reva_regs_t*) MXC_RTC); + return MXC_RTC_RevA_Start((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_Stop (void) +int MXC_RTC_Stop(void) { - return MXC_RTC_RevA_Stop ((mxc_rtc_reva_regs_t*) MXC_RTC); + return MXC_RTC_RevA_Stop((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_Init (uint32_t sec, uint8_t ssec) +int MXC_RTC_Init(uint32_t sec, uint8_t ssec) { // Enable clock MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; - - return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec); + + return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_RTSS)); +} + +int MXC_RTC_SquareWave(mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +{ + MXC_GPIO_Config(&gpio_cfg_32kcal); + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, sqe, ft); +} + +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq) +{ + MXC_GPIO_Config(&gpio_cfg_32kcal); + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, + fq); } -int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +int MXC_RTC_SquareWaveStop(void) { - MXC_GPIO_Config (&gpio_cfg_32kcal); - - return MXC_RTC_RevA_SquareWave ((mxc_rtc_reva_regs_t*) MXC_RTC, sqe, ft); + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, + MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0); } -int MXC_RTC_Trim (int8_t trm) +int MXC_RTC_Trim(int8_t trm) { - return MXC_RTC_RevA_Trim ((mxc_rtc_reva_regs_t*) MXC_RTC, trm); + return MXC_RTC_RevA_Trim((mxc_rtc_reva_regs_t *)MXC_RTC, trm); } -int MXC_RTC_GetFlags (void) +int MXC_RTC_GetFlags(void) { - return MXC_RTC_RevA_GetFlags(); + return MXC_RTC_RevA_GetFlags((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_ClearFlags (int flags) +int MXC_RTC_ClearFlags(int flags) { - return MXC_RTC_RevA_ClearFlags (flags); + return MXC_RTC_RevA_ClearFlags((mxc_rtc_reva_regs_t *)MXC_RTC, flags); +} + +int MXC_RTC_GetSubSecond(void) +{ + MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} + + return MXC_RTC_RevA_GetSubSecond((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_GetSecond(void) +{ + MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} + + return MXC_RTC_RevA_GetSecond((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_GetSubSecond (void) +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec) { - return MXC_RTC_RevA_GetSubSecond(); + return MXC_RTC_RevA_GetTime((mxc_rtc_reva_regs_t *)MXC_RTC, sec, subsec); } -int MXC_RTC_GetSecond (void) +int MXC_RTC_GetBusyFlag(void) { - return MXC_RTC_RevA_GetSecond(); + return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec) +int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr) { - return MXC_RTC_RevA_GetTime (sec, subsec); + /* MAX32660 does not have a clock source which can + be used as the reference clock for the trim function */ + return E_NOT_SUPPORTED; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c index 6719a4bc433..60594191c77 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,346 +29,395 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ +#include #include -#include "mxc_device.h" -#include "rtc.h" -#include "mxc_sys.h" -#include "mxc_delay.h" + #include "gpio_regs.h" +#include "mxc_delay.h" +#include "mxc_device.h" #include "mxc_errors.h" +#include "mxc_sys.h" +#include "rtc.h" #include "rtc_reva.h" +#include "tmr.h" #if TARGET_NUM == 32650 - #include "pwrseq_regs.h" +#include "pwrseq_regs.h" #endif -int MXC_RTC_CheckBusy(void) +void MXC_RTC_Wait_BusyToClear(void) { - // Time-out transfer if it takes > BUSY_TIMEOUT microseconds - MXC_DelayAsync(MXC_DELAY_USEC(MXC_BUSY_TIMEOUT), NULL); + while (MXC_RTC_REVA_IS_BUSY) {} +} - while (MXC_RTC_REVA_IS_BUSY) { - if (MXC_DelayCheck() != E_BUSY) { - return E_BUSY; - } +int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc) +{ + if (MXC_RTC_REVA_IS_BUSY) { + return E_BUSY; } - - MXC_DelayAbort(); return E_SUCCESS; } -int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask) +int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask) { - mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); - + mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); + if (!mask) { /* No bits set? Wasn't something we can enable. */ return E_BAD_PARAM; } - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - + + MXC_RTC_Wait_BusyToClear(); + rtc->ctrl |= mask; - + + /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/ + mask &= ~MXC_RTC_INT_EN_READY; + + if (mask) { + MXC_RTC_Wait_BusyToClear(); + } return E_SUCCESS; } -int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask) +int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask) { - mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); - + mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); + if (!mask) { /* No bits set? Wasn't something we can enable. */ return E_BAD_PARAM; } - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - + + MXC_RTC_Wait_BusyToClear(); + rtc->ctrl &= ~mask; - + + /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/ + mask &= ~MXC_RTC_INT_EN_READY; + + if (mask) { + MXC_RTC_Wait_BusyToClear(); + } return E_SUCCESS; } -int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras) +int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras) { // ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0); - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + rtc->toda = (ras << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS) & MXC_F_RTC_REVA_TODA_TOD_ALARM; - + return E_SUCCESS; } -int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa) +int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa) { // ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0); - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + rtc->sseca = (rssa << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_REVA_SSECA_SSEC_ALARM; - + return E_SUCCESS; } -int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc) +int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc) { - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + + MXC_RTC_Wait_BusyToClear(); + // Can only write if WE=1 and BUSY=0 - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1 - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... - + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1 + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + return E_SUCCESS; } -int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc) +int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc) { - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + + MXC_RTC_Wait_BusyToClear(); + // Can only write if WE=1 and BUSY=0 - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0 - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... - + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0 + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + return E_SUCCESS; } -int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec) +int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec) { - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg. - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - + + rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg. + + MXC_RTC_Wait_BusyToClear(); + rtc->ssec = ssec; - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - + + MXC_RTC_Wait_BusyToClear(); + rtc->sec = sec; - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... - + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + return E_SUCCESS; } -int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, + mxc_rtc_freq_sel_t ft) { - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers - - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + + MXC_RTC_Wait_BusyToClear(); + if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) { - if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected... - rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin - } - else { // if 1Hz, 512Hz, 4KHz output is selected - - rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl &= ~ MXC_F_RTC_REVA_CTRL_SQW_SEL; - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave, - } - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock - } - else { // Turn off the square wave output on the pin - - rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; + if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected... + rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin + } else { // if 1Hz, 512Hz, 4KHz output is selected + rtc->oscctrl &= + ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_SEL; + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave, } - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output - } - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock + } else { // Turn off the square wave output on the pin + rtc->oscctrl &= + ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output } - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register - + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register + return E_SUCCESS; } -int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trim) +int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trim) { - - if (MXC_RTC_CheckBusy()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - MXC_SETFIELD (rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS); - - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register - + + MXC_RTC_Wait_BusyToClear(); + + MXC_SETFIELD(rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS); + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register + return E_SUCCESS; } -int MXC_RTC_RevA_GetFlags(void) +int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc) { - return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY); + return rtc->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY); } -int MXC_RTC_RevA_ClearFlags(int flags) +int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags) { - if (MXC_RTC_CheckBusy()) { - return E_BUSY; - } - - MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY)); - + rtc->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY)); + return E_SUCCESS; } -int MXC_RTC_RevA_GetSubSecond(void) +int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { + return E_BUSY; + } + #if TARGET_NUM == 32650 int ssec; - if(ChipRevision > 0xA1){ - ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF); - }else{ - ssec = MXC_RTC->ssec; + if (ChipRevision > 0xA1) { + ssec = ((MXC_PWRSEQ->ctrl >> 12) & 0xF00) | (rtc->ssec & 0xFF); + } else { + ssec = rtc->ssec; } - return ssec; + return ssec; #else - return MXC_RTC->ssec; + return rtc->ssec; #endif } -int MXC_RTC_RevA_GetSecond(void) +int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc) { - return MXC_RTC->sec; + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { + return E_BUSY; + } + + return rtc->sec; } -int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec) +int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec) { - uint32_t temp_sec; - + uint32_t temp_sec = 0; + if (sec == NULL || subsec == NULL) { return E_NULL_PTR; } - + do { // Check if an update is about to happen. - if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { return E_BUSY; } - + // Read the seconds count. - temp_sec = MXC_RTC_RevA_GetSecond(); - + temp_sec = MXC_RTC_RevA_GetSecond(rtc); + + if (temp_sec == E_BUSY) { + return E_BUSY; + } + // Check if an update is about to happen. - if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { return E_BUSY; } - + // Read the sub-seconds count. - *subsec = MXC_RTC_RevA_GetSubSecond(); - + *subsec = MXC_RTC_RevA_GetSubSecond(rtc); + // Check if an update is about to happen. - if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { return E_BUSY; } - + // Read the seconds count. - *sec = MXC_RTC_RevA_GetSecond(); - + *sec = MXC_RTC_RevA_GetSecond(rtc); + // Repeat until a steady state is reached. - } - while (temp_sec != *sec); - + } while (temp_sec != *sec); + return E_NO_ERROR; } + +int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr) +{ + int err, ppm = 0; + uint32_t sec = 0, ssec = 0, ctrl = 0; + uint32_t sec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 }; + uint32_t ssec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 }; + bool rtc_en = true; + + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_EN)) { // If RTC not enable, initialize it + rtc_en = false; + while ((sec = MXC_RTC_RevA_GetSecond(rtc)) < 0) {} + // Save state + while ((ssec = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {} + while (rtc->ctrl & MXC_F_RTC_CTRL_BUSY) {} + ctrl = rtc->ctrl; + + if ((err = MXC_RTC_Init(0, 0)) != E_NO_ERROR) { + return err; + } + MXC_RTC_Start(); + } + + MXC_TMR_ClearFlags(tmr); + MXC_TMR_Start(tmr); // Sample the RTC ticks in MXC_RTC_REVA_TRIM_PERIODS number of periods + while ((sec_sample[0] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {} + while ((ssec_sample[0] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {} + + for (int i = 1; i < (MXC_RTC_REVA_TRIM_PERIODS + 1); i++) { + while (!(MXC_TMR_GetFlags(tmr) & MXC_RTC_TRIM_TMR_IRQ)) {} + // Wait for time trim period to elapse + + while ((sec_sample[i] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {} + // Take time sample + while ((ssec_sample[i] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {} + + MXC_TMR_ClearFlags(tmr); + } + + MXC_TMR_Stop(tmr); // Shutdown timer + MXC_TMR_Shutdown(tmr); + + if (!rtc_en) { // If RTC wasn't enabled entering the function, restore state + MXC_RTC_Stop(); + + while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {} + MXC_SETFIELD(rtc->ssec, MXC_F_RTC_REVA_SSEC_SSEC, (ssec << MXC_F_RTC_REVA_SSEC_SSEC_POS)); + while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {} + MXC_SETFIELD(rtc->sec, MXC_F_RTC_REVA_SEC_SEC, (sec << MXC_F_RTC_REVA_SEC_SEC_POS)); + while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {} + rtc->ctrl = ctrl; + } + + for (int i = 0; i < MXC_RTC_REVA_TRIM_PERIODS; + i++) { // Get total error in RTC ticks over MXC_RTC_REVA_TRIM_PERIODS number of sample periods + if (sec_sample[i] < sec_sample[i + 1]) { + ppm += MXC_RTC_REVA_TICKS_PER_PERIOD - + ((MXC_RTC_MAX_SSEC - ssec_sample[i]) + ssec_sample[i + 1]); + } else { + ppm += MXC_RTC_REVA_TICKS_PER_PERIOD - (ssec_sample[i + 1] - ssec_sample[i]); + } + } + + ppm /= MXC_RTC_REVA_TRIM_PERIODS; + ppm = PPM(ppm); // Convert total error to PPM and set trim + if (ppm < -128 || ppm > 127) { + return E_OVERFLOW; + } + + return MXC_RTC_RevA_Trim(rtc, (int8_t)ppm); // Set Trim +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h index b8d216ea522..b6f93255af7 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,38 +29,51 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_ + +#include "gpio.h" +#include "mxc_delay.h" #include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_sys.h" #include "rtc_reva_regs.h" #include "rtc.h" -#include "mxc_sys.h" -#include "mxc_delay.h" -#include "gpio.h" -#include "mxc_errors.h" +#include "tmr.h" typedef enum { MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled - MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled + MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled } mxc_rtc_reva_sqwave_en_t; #define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL) -#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) -#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE) +#define MXC_RTC_REVA_IS_BUSY (MXC_F_RTC_REVA_CTRL_BUSY & MXC_RTC->ctrl) +#define MXC_RTC_REVA_IS_ENABLED (MXC_F_RTC_REVA_CTRL_RTCE & MXC_RTC->ctrl) + +#define MXC_RTC_REVA_TRIM_PERIODS 5 +#define MXC_RTC_REVA_TICKS_PER_PERIOD (MXC_RTC_MAX_SSEC / MXC_RTC_REVA_TRIM_PERIODS) +#define PPM(ppm) ((ppm * 1000000) / 4096) + +#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit -#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit +int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec); +int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask); +int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask); +int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras); +int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa); +int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, + mxc_rtc_freq_sel_t ft); +int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trm); +int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags); +int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec); +int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr); -int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec); -int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask); -int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask); -int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras); -int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa); -int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc); -int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc); -int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft); -int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trm); -int MXC_RTC_RevA_GetFlags (void); -int MXC_RTC_RevA_ClearFlags (int flags); -int MXC_RTC_RevA_GetSubSecond (void); -int MXC_RTC_RevA_GetSecond (void); -int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec); +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h index 584b929568b..f71a8c51519 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _RTC_REVA_REGS_H_ #define _RTC_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c index c973b7be32b..00ac830cf37 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c @@ -1,10 +1,10 @@ -/* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * @@ -15,7 +15,7 @@ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * @@ -24,12 +24,12 @@ * Products, Inc. Branding Policy. * * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, + * of trade secrets, proprietary technology, copyrights, patents, * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -43,210 +43,215 @@ #include "dma.h" /* **** Functions **** */ -int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned drv_ssel) +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz) { - - if(numSlaves > MXC_SPI_SS_INSTANCES) { + int spi_num; + + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + + if (numSlaves > MXC_SPI_SS_INSTANCES) { return E_BAD_PARAM; } - + // Check if frequency is too high - if(hz > PeripheralClock) { + if (hz > PeripheralClock) { return E_BAD_PARAM; } - + // Configure GPIO for spi - if(spi == MXC_SPI0) { + if (spi == MXC_SPI0) { MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI0; - while(MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0); + while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0) {} MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI0D); MXC_GPIO_Config(&gpio_cfg_spi0); - } - else { + } else { return E_NO_DEVICE; } - - return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel); + + return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, + ssPolarity, hz); } -int MXC_SPI_Shutdown(mxc_spi_regs_t* spi) -{ - if(spi != MXC_SPI0) { - return E_NO_DEVICE; - } +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); - MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t*) spi); - // - MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D); + MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t *)spi); + + if (spi == MXC_SPI0) { + MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D); + } else { + return E_INVALID; + } return E_NO_ERROR; } -int MXC_SPI_ReadyForSleep(mxc_spi_regs_t* spi) +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi) +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) { - if(spi == MXC_SPI0) { + if (spi == MXC_SPI0) { return PeripheralClock; - } - else { + } else { return E_BAD_PARAM; } return E_NO_ERROR; } -int MXC_SPI_SetFrequency(mxc_spi_regs_t* spi, unsigned int hz) +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz) { - return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t*) spi, hz); + return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t *)spi, hz); } -unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetDataSize(mxc_spi_regs_t* spi, int dataSize) +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize) { - return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t*) spi, dataSize); + return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t *)spi, dataSize); } -int MXC_SPI_GetDataSize(mxc_spi_regs_t* spi) +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetSlave(mxc_spi_regs_t* spi, int ssIdx) +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx) { - return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t*) spi, ssIdx); + return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t *)spi, ssIdx); } -int MXC_SPI_GetSlave(mxc_spi_regs_t* spi) +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetWidth(mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth) +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth) { - return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t)spiWidth); + return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t *)spi, spiWidth); } -mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi) +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi) { - return(mxc_spi_width_t) MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t*) spi); + return (mxc_spi_width_t)MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode) +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode) { - return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t)spiMode); + return MXC_SPI_RevA_SetMode((mxc_spi_reva_regs_t *)spi, spiMode); } -mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi) +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi) { - return (mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_StartTransmission(mxc_spi_regs_t* spi) +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_GetActive(mxc_spi_regs_t* spi) +int MXC_SPI_GetActive(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi) +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t *)spi); } -unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) { - return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len); + return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); } -unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi); } -unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) { - return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len); + return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); } -unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t* spi) +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t* spi) +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetRXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes) +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) { - return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t*) spi, numBytes); + return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); } -unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetTXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes) +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) { - return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t*) spi, numBytes); + return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); } -unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t *)spi); } -unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_ClearFlags(mxc_spi_regs_t* spi) +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_EnableInt(mxc_spi_regs_t* spi, unsigned int mask) +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask) { - MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t*) spi, mask); + MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t *)spi, mask); } -void MXC_SPI_DisableInt(mxc_spi_regs_t* spi, unsigned int mask) +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask) { - MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t*) spi, mask); + MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t *)spi, mask); } -int MXC_SPI_MasterTransaction(mxc_spi_req_t* req) +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req) { - return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t* req) +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) { - return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req) +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) { int reqselTx = -1; int reqselRx = -1; @@ -255,9 +260,9 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - - if(req->txData != NULL) { - switch(spi_num) { + + if (req->txData != NULL) { + switch (spi_num) { case 0: reqselTx = MXC_DMA_REQUEST_SPI0TX; break; @@ -267,12 +272,12 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req) break; default: - return E_BAD_PARAM; + return E_BAD_PARAM; } } - if(req->rxData != NULL) { - switch(spi_num) { + if (req->rxData != NULL) { + switch (spi_num) { case 0: reqselRx = MXC_DMA_REQUEST_SPI0RX; break; @@ -286,20 +291,21 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req) } } - return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA); + return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, + MXC_DMA); } -int MXC_SPI_SlaveTransaction(mxc_spi_req_t* req) +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) { - return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t* req) +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) { - return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req) +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) { int reqselTx = -1; int reqselRx = -1; @@ -308,9 +314,9 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - - if(req->txData != NULL) { - switch(spi_num) { + + if (req->txData != NULL) { + switch (spi_num) { case 0: reqselTx = MXC_DMA_REQUEST_SPI0TX; break; @@ -324,8 +330,8 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req) } } - if(req->rxData != NULL) { - switch(spi_num) { + if (req->rxData != NULL) { + switch (spi_num) { case 0: reqselRx = MXC_DMA_REQUEST_SPI0RX; break; @@ -333,26 +339,26 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req) case 1: reqselRx = MXC_DMA_REQUEST_SPI1RX; break; - + default: return E_BAD_PARAM; } } - return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA); + return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA); } -int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t* spi, unsigned int defaultTXData) +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) { - return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t*) spi, defaultTXData); + return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t *)spi, defaultTXData); } -void MXC_SPI_AbortAsync(mxc_spi_regs_t* spi) +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_AsyncHandler(mxc_spi_regs_t* spi) +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t *)spi); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index fa62a84fc4c..c7a9667341c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,13 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM //Keil -#pragma diag_suppress 188 // enumerated type mixed with another type -#pragma diag_suppress 68 // integer conversion resulted in a change of sign -#endif - - + ******************************************************************************/ #include #include @@ -46,7 +40,7 @@ #include "mxc_lock.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "mxc_spi.h" +#include "spi.h" #include "spi_reva.h" #include "dma_reva.h" @@ -59,320 +53,390 @@ typedef struct { unsigned defaultTXData; int channelTx; int channelRx; - unsigned drv_ssel; + int mtMode; + int mtFirstTrans; + bool txrx_req; + uint8_t req_done; + uint8_t async; } spi_req_reva_state_t; -/* states whether to use call back or not */ -uint8_t async; - static spi_req_reva_state_t states[MXC_SPI_INSTANCES]; -static uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); -static uint32_t MXC_SPI_RevA_TransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); -static uint32_t MXC_SPI_RevA_SlaveTransHandler (mxc_spi_reva_req_t *req); -static void MXC_SPI_RevA_SwapByte (uint8_t * arr, size_t length); -static int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req); - +static uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); +static uint32_t MXC_SPI_RevA_TransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); +static uint32_t MXC_SPI_RevA_SlaveTransHandler(mxc_spi_reva_req_t *req); +static void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length); +static int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req); -int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned drv_ssel) +int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz) { int spi_num; - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + states[spi_num].req = NULL; states[spi_num].last_size = 0; states[spi_num].ssDeassert = 1; states[spi_num].defaultTXData = 0; - states[spi_num].drv_ssel = drv_ssel; - + states[spi_num].mtMode = 0; + states[spi_num].mtFirstTrans = 0; + states[spi_num].channelTx = E_NO_DEVICE; + states[spi_num].channelRx = E_NO_DEVICE; + spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN); - spi->sstime = ( (0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) | - (0x1 << MXC_F_SPI_REVA_SSTIME_POST_POS) | - (0x1 << MXC_F_SPI_REVA_SSTIME_INACT_POS)); - + spi->sstime = + ((0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) | (0x1 << MXC_F_SPI_REVA_SSTIME_POST_POS) | + (0x1 << MXC_F_SPI_REVA_SSTIME_INACT_POS)); + //set master if (masterMode) { spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_MST_MODE; + } else { + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_MST_MODE); } - else { - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_MST_MODE); + + MXC_SPI_SetFrequency((mxc_spi_regs_t *)spi, hz); + + if (ssPolarity > (MXC_F_SPI_REVA_CTRL2_SS_POL >> MXC_F_SPI_REVA_CTRL2_SS_POL_POS)) { + return E_BAD_PARAM; } - - MXC_SPI_SetFrequency ((mxc_spi_regs_t*) spi, hz); - + //set slave select polarity - spi->ctrl2 |= ( (!!ssPolarity) << MXC_F_SPI_REVA_CTRL2_SS_POL_POS); - + spi->ctrl2 |= (ssPolarity << MXC_F_SPI_REVA_CTRL2_SS_POL_POS); + // Clear the interrupts spi->intfl = spi->intfl; - - // Driver will drive SS pin? - if (states[spi_num].drv_ssel) { + + if (numSlaves == 1) { spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; } + if (numSlaves == 2) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); + } + + if (numSlaves == 3) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); + } + + if (numSlaves == 4) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + } + //set quad mode if (quadModeUsed) { spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD; } - + return E_NO_ERROR; } -int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi) { int spi_num; - mxc_spi_reva_req_t * temp_req; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - + mxc_spi_reva_req_t *temp_req; + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + //disable and clear interrupts spi->inten = 0; spi->intfl = spi->intfl; - + // Disable SPI and FIFOS - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); - spi->dma &= ~ (MXC_F_SPI_REVA_DMA_TX_FIFO_EN | MXC_F_SPI_REVA_DMA_RX_FIFO_EN); - + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); + spi->dma &= ~(MXC_F_SPI_REVA_DMA_TX_FIFO_EN | MXC_F_SPI_REVA_DMA_RX_FIFO_EN); + //call all of the pending callbacks for this spi - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + if (states[spi_num].req != NULL) { //save the request temp_req = states[spi_num].req; - MXC_FreeLock((uint32_t*)(uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)(uint32_t *)&states[spi_num].req); + // Callback if not NULL if (states[spi_num].req->completeCB != NULL) { states[spi_num].req->completeCB(temp_req, E_SHUTDOWN); } - } - + // Clear registers spi->ctrl0 = 0; spi->ctrl1 = 0; spi->ctrl2 = 0; spi->sstime = 0; - + + // release any acquired DMA channels + if (states[spi_num].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelTx); + states[spi_num].channelTx = E_NO_DEVICE; + } + if (states[spi_num].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelRx); + states[spi_num].channelRx = E_NO_DEVICE; + } + return E_NO_ERROR; } -int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - - if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY || (spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) || (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL)) { + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + + if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY || (spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) || + (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL)) { return E_BUSY; - } - else { + } else { return E_NO_ERROR; } } -int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz) +int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz) { int hi_clk, lo_clk, scale; uint32_t freq_div; - + // Check if frequency is too high if (hz > PeripheralClock) { return E_BAD_PARAM; } - + // Set the clock high and low - freq_div = MXC_SPI_GetPeripheralClock((mxc_spi_regs_t*) spi); - #if TARGET_NUM == 32570 || TARGET_NUM == 32680 - freq_div = (freq_div / hz / 2); - #else + freq_div = MXC_SPI_GetPeripheralClock((mxc_spi_regs_t *)spi); freq_div = (freq_div / hz); - #endif hi_clk = freq_div / 2; lo_clk = freq_div / 2; scale = 0; - + if (freq_div % 2) { hi_clk += 1; } - + while (hi_clk >= 16 && scale < 8) { hi_clk /= 2; lo_clk /= 2; - scale ++; + scale++; } - + if (scale == 8) { lo_clk = 15; hi_clk = 15; } - - MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_LO, (lo_clk << MXC_F_SPI_REVA_CLKCTRL_LO_POS)); - MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_HI, (hi_clk << MXC_F_SPI_REVA_CLKCTRL_HI_POS)); - MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_CLKDIV, (scale << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)); - + + MXC_SETFIELD(spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_LO, + (lo_clk << MXC_F_SPI_REVA_CLKCTRL_LO_POS)); + MXC_SETFIELD(spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_HI, + (hi_clk << MXC_F_SPI_REVA_CLKCTRL_HI_POS)); + MXC_SETFIELD(spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_CLKDIV, + (scale << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)); + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetFrequency(mxc_spi_reva_regs_t *spi) { - if (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) < 0) { + if (MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) < 0) { return E_BAD_PARAM; } - + unsigned scale, lo_clk, hi_clk; - + scale = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_CLKDIV) >> MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS; - hi_clk= (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_HI) >> MXC_F_SPI_REVA_CLKCTRL_HI_POS; - lo_clk= (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_LO) >> MXC_F_SPI_REVA_CLKCTRL_LO_POS; - + hi_clk = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_HI) >> MXC_F_SPI_REVA_CLKCTRL_HI_POS; + lo_clk = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_LO) >> MXC_F_SPI_REVA_CLKCTRL_LO_POS; + return (PeripheralClock / (1 << scale)) / (lo_clk + hi_clk); } -int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize) +int MXC_SPI_RevA_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize) { int spi_num; - + // HW has problem with these two character sizes if (dataSize == 1 || dataSize > 16) { return E_BAD_PARAM; } - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + // Setup the character size - if (! (spi->stat & MXC_F_SPI_REVA_STAT_BUSY) && states[spi_num].ssDeassert == 1) { + if (!(spi->stat & MXC_F_SPI_REVA_STAT_BUSY) && states[spi_num].ssDeassert == 1) { //disable spi to change transfer size - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); // set bit size states[spi_num].last_size = dataSize; - + if (dataSize < 16) { - MXC_SETFIELD (spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, dataSize << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); - } - - else { - MXC_SETFIELD (spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, 0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); //may not be neccessary + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, + dataSize << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); + } else { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, + 0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); //may not be neccessary } - + //enable spi to change transfer size spi->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); - } - else { + } else { return E_BAD_STATE; } - + return E_NO_ERROR; } -int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_GetDataSize(mxc_spi_reva_regs_t *spi) { int spi_num; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - + if (!(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_NUMBITS)) { return 16; } - + return (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_NUMBITS) >> MXC_F_SPI_REVA_CTRL2_NUMBITS_POS; } -int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx) +int MXC_SPI_RevA_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode) +{ + int spi_num; + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + + if ((mtMode != 0) && (mtMode != 1)) { + return E_BAD_PARAM; + } + + if (states[spi_num].mtMode == 1) { + if (mtMode == 0) { + // exiting MT Mode: release any acquired DMA channels + if (states[spi_num].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelTx); + states[spi_num].channelTx = E_NO_DEVICE; + } + if (states[spi_num].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelRx); + states[spi_num].channelRx = E_NO_DEVICE; + } + } + } else if (mtMode == 1) { + // entering MT Mode: set first transaction + states[spi_num].mtFirstTrans = 1; + } + + states[spi_num].mtMode = mtMode; + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_GetMTMode(mxc_spi_reva_regs_t *spi) { int spi_num; - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + + return states[spi_num].mtMode; +} + +int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx) +{ + int spi_num; + // HW has problem with these two character sizes if (ssIdx >= MXC_SPI_SS_INSTANCES) { return E_BAD_PARAM; } - + //check if in master mode - if (! (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE)) { + if (!(spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE)) { return E_BAD_STATE; } - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - if (states[spi_num].drv_ssel) { - // Setup the slave select - // Activate chosen SS pin - spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; - } + + // Setup the slave select + // Activate chosen SS pin + spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; + // Deactivate all unchosen pins + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | + ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); return E_NO_ERROR; } -int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_GetSlave(mxc_spi_reva_regs_t *spi) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - return ( (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_SS_ACTIVE) >> MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) >> 1; + + return ((spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_SS_ACTIVE) >> MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) >> + 1; } -int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth) +int MXC_SPI_RevA_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth) { int spi_num; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - spi->ctrl2 &= ~ (MXC_F_SPI_REVA_CTRL2_THREE_WIRE | MXC_F_SPI_REVA_CTRL2_DATA_WIDTH); - + + spi->ctrl2 &= ~(MXC_F_SPI_REVA_CTRL2_THREE_WIRE | MXC_F_SPI_REVA_CTRL2_DATA_WIDTH); + switch (spiWidth) { - case SPI_REVA_WIDTH_3WIRE: spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_THREE_WIRE; break; - + case SPI_REVA_WIDTH_STANDARD: spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_MONO; break; - + case SPI_REVA_WIDTH_DUAL: spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL; break; - + case SPI_REVA_WIDTH_QUAD: spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD; break; } - + return E_NO_ERROR; } -mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi) +mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth(mxc_spi_reva_regs_t *spi) { if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) { return SPI_REVA_WIDTH_3WIRE; } - + if (spi->ctrl2 & MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL) { return SPI_REVA_WIDTH_DUAL; } - + if (spi->ctrl2 & MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD) { return SPI_REVA_WIDTH_QUAD; } - + return SPI_REVA_WIDTH_STANDARD; } -int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode) +int MXC_SPI_RevA_SetMode(mxc_spi_reva_regs_t *spi, mxc_spi_reva_mode_t spiMode) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - switch(spiMode) { + switch (spiMode) { case SPI_REVA_MODE_0: spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPHA; spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPOL; @@ -380,42 +444,40 @@ int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode) case SPI_REVA_MODE_1: spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPHA; - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; break; case SPI_REVA_MODE_2: - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPOL; break; case SPI_REVA_MODE_3: - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; break; default: - break; + break; } return E_NO_ERROR; } -mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi) +mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode(mxc_spi_reva_regs_t *spi) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPHA) { - if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPHA) { + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { return SPI_REVA_MODE_3; - } - else { + } else { return SPI_REVA_MODE_2; } - } - else { - if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { + } else { + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { return SPI_REVA_MODE_1; } } @@ -423,572 +485,591 @@ mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi) return SPI_REVA_MODE_0; } -int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_StartTransmission(mxc_spi_reva_regs_t *spi) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - if (MXC_SPI_GetActive ((mxc_spi_regs_t*) spi) == E_BUSY) { + + if (MXC_SPI_GetActive((mxc_spi_regs_t *)spi) == E_BUSY) { return E_BUSY; } - + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_START; - + return E_NO_ERROR; } -int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_GetActive(mxc_spi_reva_regs_t *spi) { if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_AbortTransmission(mxc_spi_reva_regs_t *spi) { int spi_num; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); // Disable interrupts, clear the flags spi->inten = 0; spi->intfl = spi->intfl; - + // Reset the SPI17Y to cancel the on ongoing transaction - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); spi->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); - + // Unlock this SPI - mxc_spi_reva_req_t * temp = states[spi_num].req; - MXC_FreeLock ((uint32_t*) &states[spi_num].req); - + mxc_spi_reva_req_t *temp = states[spi_num].req; + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL if (temp->completeCB != NULL) { temp->completeCB(states[spi_num].req, E_ABORT); } - + + // release any acquired DMA channels + if (states[spi_num].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelTx); + states[spi_num].channelTx = E_NO_DEVICE; + } + if (states[spi_num].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelRx); + states[spi_num].channelRx = E_NO_DEVICE; + } + if (states[spi_num].mtMode == 1) { + states[spi_num].mtFirstTrans = 1; + } + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_RevA_ReadRXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, + unsigned int len) { - unsigned rx_avail,bits; - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + unsigned rx_avail, bits; + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (!bytes || !len) { return 0; } - - rx_avail = MXC_SPI_GetRXFIFOAvailable ((mxc_spi_regs_t*) spi); - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) spi); - + + rx_avail = MXC_SPI_GetRXFIFOAvailable((mxc_spi_regs_t *)spi); + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)spi); + if (len > rx_avail) { len = rx_avail; } - + if (bits > 8) { - len &= ~(unsigned) 0x1; + len &= ~(unsigned)0x1; } - + unsigned cnt = 0; - + if (bits <= 8 || len >= 2) { // Read from the FIFO while (len) { if (len > 3) { - memcpy(& ((uint8_t*) bytes) [cnt], (void*) &spi->fifo32, 4); + memcpy((uint8_t *)(&bytes[cnt]), (void *)(&spi->fifo32), 4); len -= 4; cnt += 4; - } - else if (len > 1) { - memcpy(& ((uint8_t*) bytes) [cnt], (void*) &spi->fifo16[0], 2); + } else if (len > 1) { + memcpy((uint8_t *)(&bytes[cnt]), (void *)(&spi->fifo16[0]), 2); len -= 2; cnt += 2; - - } - else { - ((uint8_t*) bytes) [cnt++] = spi->fifo8[0]; + + } else { + ((uint8_t *)bytes)[cnt++] = spi->fifo8[0]; len -= 1; } - + // Don't read less than 2 bytes if we are using greater than 8 bit characters if (len == 1 && bits > 8) { break; } } } - + return cnt; } -unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetRXFIFOAvailable(mxc_spi_reva_regs_t *spi) { return (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL) >> MXC_F_SPI_REVA_DMA_RX_LVL_POS; } -unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_RevA_WriteTXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, + unsigned int len) { - unsigned tx_avail,bits; - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + unsigned tx_avail, bits; + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (!bytes || !len) { return 0; } - - tx_avail = MXC_SPI_GetTXFIFOAvailable ((mxc_spi_regs_t*) spi); - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) spi); - + + tx_avail = MXC_SPI_GetTXFIFOAvailable((mxc_spi_regs_t *)spi); + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)spi); + if (len > tx_avail) { len = tx_avail; } - + if (bits > 8) { - len &= ~(unsigned) 0x1; + len &= ~(unsigned)0x1; } - + unsigned cnt = 0; - + while (len) { if (len > 3) { - memcpy((void*) &spi->fifo32, & ((uint8_t*) bytes) [cnt], 4); - + memcpy((void *)(&spi->fifo32), (uint8_t *)(&bytes[cnt]), 4); + len -= 4; cnt += 4; - - } - else if (len > 1) { - memcpy((void*) &spi->fifo16[0], & ((uint8_t*) bytes) [cnt], 2); - + + } else if (len > 1) { + memcpy((void *)(&spi->fifo16[0]), (uint8_t *)(&bytes[cnt]), 2); + len -= 2; cnt += 2; - - } - else if (bits <= 8) { - spi->fifo8[0] = ((uint8_t*) bytes) [cnt++]; + + } else if (bits <= 8) { + spi->fifo8[0] = ((uint8_t *)bytes)[cnt++]; len--; } - } - + return cnt; } -unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetTXFIFOAvailable(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - return MXC_SPI_FIFO_DEPTH - ((spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) >> MXC_F_SPI_REVA_DMA_TX_LVL_POS); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + return MXC_SPI_FIFO_DEPTH - + ((spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) >> MXC_F_SPI_REVA_DMA_TX_LVL_POS); } -void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_ClearRXFIFO(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->dma |= MXC_F_SPI_REVA_DMA_RX_FLUSH; } -void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_ClearTXFIFO(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->dma |= MXC_F_SPI_REVA_DMA_TX_FLUSH; } -int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes) +int MXC_SPI_RevA_SetRXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (numBytes > 32) { return E_BAD_PARAM; } - - MXC_SETFIELD (spi->dma, MXC_F_SPI_REVA_DMA_RX_THD_VAL, numBytes << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS); - + + MXC_SETFIELD(spi->dma, MXC_F_SPI_REVA_DMA_RX_THD_VAL, + numBytes << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS); + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetRXThreshold(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); return (spi->dma & MXC_F_SPI_REVA_DMA_RX_THD_VAL) >> MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS; } -int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes) +int MXC_SPI_RevA_SetTXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (numBytes > 32) { return E_BAD_PARAM; } - - MXC_SETFIELD (spi->dma, MXC_F_SPI_REVA_DMA_TX_THD_VAL, numBytes << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS); - + + MXC_SETFIELD(spi->dma, MXC_F_SPI_REVA_DMA_TX_THD_VAL, + numBytes << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS); + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetTXThreshold(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); return (spi->dma & MXC_F_SPI_REVA_DMA_TX_THD_VAL) >> MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS; } -unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetFlags(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); return spi->intfl; } -void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_ClearFlags(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->intfl = spi->intfl; } -void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int intEn) +void MXC_SPI_RevA_EnableInt(mxc_spi_reva_regs_t *spi, unsigned int intEn) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->inten |= intEn; } -void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int intDis) +void MXC_SPI_RevA_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int intDis) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - spi->inten &= ~ (intDis); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + spi->inten &= ~(intDis); } -int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req) +int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req) { int spi_num; uint8_t bits; - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)(req->spi)); + MXC_ASSERT(spi_num >= 0); + MXC_ASSERT(req->ssIdx < MXC_SPI_SS_INSTANCES); + if ((!req) || ((req->txData == NULL) && (req->rxData == NULL))) { return E_BAD_PARAM; } - + // Setup the number of characters to transact if (req->txLen > (MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR >> MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS)) { return E_BAD_PARAM; } - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); - MXC_ASSERT (spi_num >= 0); - MXC_ASSERT (req->ssIdx < MXC_SPI_SS_INSTANCES); - - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); req->txCnt = 0; req->rxCnt = 0; - + states[spi_num].req = req; states[spi_num].started = 0; - + states[spi_num].req_done = 0; // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). if (states[spi_num].ssDeassert == 1) { - (req->spi)->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); } - + //if master if ((req->spi)->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) { // Setup the slave select - MXC_SPI_SetSlave ((mxc_spi_regs_t*) req->spi, req->ssIdx); - + MXC_SPI_SetSlave((mxc_spi_regs_t *)req->spi, req->ssIdx); } - + if (req->rxData != NULL && req->rxLen > 0) { - MXC_SETFIELD ( (req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR, - req->rxLen << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS); + MXC_SETFIELD((req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR, + req->rxLen << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS); (req->spi)->dma |= MXC_F_SPI_REVA_DMA_RX_FIFO_EN; + } else { + (req->spi)->ctrl1 &= ~(MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR); + (req->spi)->dma &= ~(MXC_F_SPI_REVA_DMA_RX_FIFO_EN); } - else { - (req->spi)->ctrl1 &= ~ (MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR); - (req->spi)->dma &= ~ (MXC_F_SPI_REVA_DMA_RX_FIFO_EN); - } - + // Must use TXFIFO and NUM in full duplex//start editing here - if ((mxc_spi_reva_width_t) MXC_SPI_GetWidth ((mxc_spi_regs_t*) req->spi) == SPI_REVA_WIDTH_STANDARD - && ! ( ( (req->spi)->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) >> MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) { + if ((mxc_spi_reva_width_t)MXC_SPI_GetWidth((mxc_spi_regs_t *)req->spi) == + SPI_REVA_WIDTH_STANDARD && + !(((req->spi)->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) >> + MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) { if (req->txData == NULL) { // Must have something to send, so we'll use the rx_data buffer initialized to 0. //SPI_SetDefaultTXData(spi, 0); - memset(req->rxData, states[spi_num].defaultTXData, (bits > 8 ? req->rxLen << 1 : req->rxLen)); + memset(req->rxData, states[spi_num].defaultTXData, + (bits > 8 ? req->rxLen << 1 : req->rxLen)); req->txData = req->rxData; req->txLen = req->rxLen; } } - - if(req->txData != NULL && req->txLen > 0) { - MXC_SETFIELD ( (req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR, - req->txLen << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS); + + if (req->txData != NULL && req->txLen > 0) { + MXC_SETFIELD((req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR, + req->txLen << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS); (req->spi)->dma |= MXC_F_SPI_REVA_DMA_TX_FIFO_EN; - } - else { + } else { (req->spi)->ctrl1 &= ~(MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR); (req->spi)->dma &= ~(MXC_F_SPI_REVA_DMA_TX_FIFO_EN); } - + + if ((req->txData != NULL && req->txLen) && (req->rxData != NULL && req->rxLen)) { + states[spi_num].txrx_req = true; + } else { + states[spi_num].txrx_req = false; + } (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_TX_FLUSH | MXC_F_SPI_REVA_DMA_RX_FLUSH); (req->spi)->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); - + states[spi_num].ssDeassert = req->ssDeassert; // Clear master done flag (req->spi)->intfl = MXC_F_SPI_REVA_INTFL_MST_DONE; - - + return E_NO_ERROR; } -uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) +uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) { uint32_t retval; int spi_num; - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + // Leave slave select asserted at the end of the transaction if (!req->ssDeassert) { spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; } - + retval = MXC_SPI_RevA_TransHandler(spi, req); - + if (!states[spi_num].started) { - MXC_SPI_StartTransmission ((mxc_spi_regs_t*) spi); + MXC_SPI_StartTransmission((mxc_spi_regs_t *)spi); states[spi_num].started = 1; } - + // Deassert slave select at the end of the transaction if (req->ssDeassert) { spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; } - + return retval; } -uint32_t MXC_SPI_RevA_SlaveTransHandler (mxc_spi_reva_req_t *req) +uint32_t MXC_SPI_RevA_SlaveTransHandler(mxc_spi_reva_req_t *req) { return MXC_SPI_RevA_TransHandler(req->spi, req); } -uint32_t MXC_SPI_RevA_TransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) +uint32_t MXC_SPI_RevA_TransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) { int remain, spi_num; uint32_t int_en = 0; uint32_t tx_length = 0, rx_length = 0; uint8_t bits; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - if (spi_num < 0) { - MXC_ASSERT(0); - } + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); - //MXC_F_SPI_REVA_CTRL2_NUMBITS data bits // Read/write 2x number of bytes if larger character size if (bits > 8) { tx_length = req->txLen * 2; rx_length = req->rxLen * 2; - } - else { + } else { tx_length = req->txLen; rx_length = req->rxLen; } - + if (req->txData != NULL) { - - req->txCnt += MXC_SPI_WriteTXFIFO ((mxc_spi_regs_t*) spi, & (req->txData[req->txCnt]),tx_length - req->txCnt); + req->txCnt += MXC_SPI_WriteTXFIFO((mxc_spi_regs_t *)spi, &(req->txData[req->txCnt]), + tx_length - req->txCnt); } - + remain = tx_length - req->txCnt; - + // Set the TX interrupts // Write the FIFO //starting here if (remain) { if (remain > MXC_SPI_FIFO_DEPTH) { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) spi,MXC_SPI_FIFO_DEPTH); - } - else { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) spi,remain); + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)spi, MXC_SPI_FIFO_DEPTH); + } else { + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)spi, remain); } - + int_en |= MXC_F_SPI_REVA_INTEN_TX_THD; - } // Break out if we've transmitted all the bytes and not receiving if ((req->rxData == NULL) && (req->txCnt == tx_length)) { spi->inten = 0; int_en = 0; - MXC_FreeLock((uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL - if (async && req->completeCB != NULL) { + if (states[spi_num].async && req->completeCB != NULL) { req->completeCB(req, E_NO_ERROR); } } // Read the RX FIFO if (req->rxData != NULL) { - - req->rxCnt += MXC_SPI_ReadRXFIFO ((mxc_spi_regs_t*) spi,& (req->rxData[req->rxCnt]),rx_length - req->rxCnt); - - + req->rxCnt += MXC_SPI_ReadRXFIFO((mxc_spi_regs_t *)spi, &(req->rxData[req->rxCnt]), + rx_length - req->rxCnt); + remain = rx_length - req->rxCnt; - + if (remain) { if (remain > MXC_SPI_FIFO_DEPTH) { - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) spi, 2); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)spi, 2); + } else { + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)spi, remain - 1); } - else { - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) spi, remain - 1); - } - + int_en |= MXC_F_SPI_REVA_INTEN_RX_THD; } - + // Break out if we've received all the bytes and we're not transmitting if ((req->txData == NULL) && (req->rxCnt == rx_length)) { spi->inten = 0; int_en = 0; - MXC_FreeLock((uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL - if (async && req->completeCB != NULL) { + if (states[spi_num].async && req->completeCB != NULL) { req->completeCB(req, E_NO_ERROR); } } } // Break out once we've transmitted and received all of the data - if ((req->rxCnt == rx_length) && (req->txCnt == tx_length)) { + if ((req->rxCnt == rx_length) && (req->txCnt == tx_length)) { spi->inten = 0; int_en = 0; - MXC_FreeLock((uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL - if (async && req->completeCB != NULL) { + if (states[spi_num].async && req->completeCB != NULL) { req->completeCB(req, E_NO_ERROR); } } - + return int_en; } -int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_MasterTransaction(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - async = 0; - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 0; + //call master transHandler - while (MXC_SPI_RevA_MasterTransHandler(req->spi, req) != 0); - - while (!((req->spi)->intfl & MXC_F_SPI_REVA_INTFL_MST_DONE)); - + while (MXC_SPI_RevA_MasterTransHandler(req->spi, req) != 0) {} + + while (!((req->spi)->intfl & MXC_F_SPI_REVA_INTFL_MST_DONE)) {} + return E_NO_ERROR; } -int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_MasterTransactionAsync(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - async = 1; - - MXC_SPI_EnableInt ((mxc_spi_regs_t*) req->spi, MXC_SPI_RevA_MasterTransHandler (req->spi,req)); - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 1; + + MXC_SPI_EnableInt((mxc_spi_regs_t *)req->spi, MXC_SPI_RevA_MasterTransHandler(req->spi, req)); + return E_NO_ERROR; } -int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma) +int MXC_SPI_RevA_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma) { int spi_num; - uint8_t channel,error,bits; + uint8_t error, bits; mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; - mxc_dma_adv_config_t advConfig = {0, 0, 0, 0, 0, 0}; + mxc_dma_adv_config_t advConfig = { 0, 0, 0, 0, 0, 0 }; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)(req->spi)); + MXC_ASSERT(spi_num >= 0); if (req->txData == NULL && req->rxData == NULL) { return E_BAD_PARAM; } - if ((error = MXC_SPI_RevA_TransSetup (req)) != E_NO_ERROR) { + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - // Leave slave select asserted at the end of the transaction - if (!req->ssDeassert) { - req->spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + // for non-MT mode do this setup every time, for MT mode only first time + if ((states[spi_num].mtMode == 0) || + ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { +#if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); +#else + MXC_DMA_Init(); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(); +#endif + + if ((states[spi_num].channelTx < 0) || (states[spi_num].channelRx < 0)) { + states[spi_num].channelTx = E_NO_DEVICE; + states[spi_num].channelRx = E_NO_DEVICE; + return E_NO_DEVICE; + } + + states[spi_num].mtFirstTrans = 0; + + MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA_DMACallback); + MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt(states[spi_num].channelTx); + MXC_DMA_EnableInt(states[spi_num].channelRx); + + // Configure SS for per-transaction or always on + if (req->ssDeassert) { + req->spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } else { + req->spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } - - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); - + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); + MXC_SPI_RevA_TransHandler(req->spi, req); - + if (bits <= 8) { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 1); //set threshold to 1 byte - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); //set threshold to 0 bytes - } - else { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 2); - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); - } - - #if TARGET_NUM == 32665 - MXC_DMA_Init(dma); - #else - MXC_DMA_Init(); - #endif - + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 1); //set threshold to 1 byte + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); //set threshold to 0 bytes + } else { + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 2); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); + } + //tx if (req->txData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif - config.reqsel = reqselTx; - config.ch = channel; - advConfig.ch = channel; + config.ch = states[spi_num].channelTx; + advConfig.ch = states[spi_num].channelTx; advConfig.burst_size = 2; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - + config.srcinc_en = 1; config.dstinc_en = 0; - - srcdst.ch = channel; - srcdst.source = & (req->txData[req->txCnt]); - + + srcdst.ch = states[spi_num].channelTx; + srcdst.source = &(req->txData[req->txCnt]); + if (bits > 8) { srcdst.len = (req->txLen * 2) - req->txCnt; - } - else { + } else { srcdst.len = (req->txLen) - req->txCnt; } - - states[spi_num].channelTx = channel; - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelTx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelTx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; if (bits > 8) { @@ -996,335 +1077,313 @@ int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, in //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 1 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } } - - if (req->rxData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif + if (req->rxData != NULL) { config.reqsel = reqselRx; - config.ch = channel; + config.ch = states[spi_num].channelRx; config.srcinc_en = 0; config.dstinc_en = 1; - advConfig.ch = channel; + advConfig.ch = states[spi_num].channelRx; advConfig.burst_size = 1; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - - - srcdst.ch = channel; + + srcdst.ch = states[spi_num].channelRx; srcdst.dest = req->rxData; - + if (bits <= 8) { srcdst.len = req->rxLen; - } - else { + } else { srcdst.len = req->rxLen * 2; } - - states[spi_num].channelRx = channel; - - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelRx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelRx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; if (bits > 8) { MXC_DMA_AdvConfigChannel(advConfig); //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 0 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } - } - + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_DMA_TX_EN | MXC_F_SPI_REVA_DMA_DMA_RX_EN); - - + if (!states[spi_num].started) { - MXC_SPI_StartTransmission ((mxc_spi_regs_t*) req->spi); + MXC_SPI_StartTransmission((mxc_spi_regs_t *)req->spi); states[spi_num].started = 1; } - - // Deassert slave select at the end of the transaction - if (req->ssDeassert) { - req->spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; - } - + return E_NO_ERROR; } -int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_SlaveTransaction(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - - async = 0; - - while (MXC_SPI_RevA_SlaveTransHandler(req) != 0); - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 0; + + while (MXC_SPI_RevA_SlaveTransHandler(req) != 0) {} + return E_NO_ERROR; } -int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_SlaveTransactionAsync(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - async = 1; - - MXC_SPI_EnableInt ((mxc_spi_regs_t*) req->spi,MXC_SPI_RevA_SlaveTransHandler (req)); - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 1; + + MXC_SPI_EnableInt((mxc_spi_regs_t *)req->spi, MXC_SPI_RevA_SlaveTransHandler(req)); + return E_NO_ERROR; } -int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma) +int MXC_SPI_RevA_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma) { int spi_num; - uint8_t channel, error, bits; + uint8_t error, bits; mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; - mxc_dma_adv_config_t advConfig = {0, 0, 0, 0, 0, 0}; - + mxc_dma_adv_config_t advConfig = { 0, 0, 0, 0, 0, 0 }; + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)(req->spi)); + MXC_ASSERT(spi_num >= 0); + if (req->txData == NULL && req->rxData == NULL) { return E_BAD_PARAM; } - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); - + + // for non-MT mode do this setup every time, for MT mode only first time + if ((states[spi_num].mtMode == 0) || + ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { +#if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); +#else + MXC_DMA_Init(); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(); +#endif + + if ((states[spi_num].channelTx < 0) || (states[spi_num].channelRx < 0)) { + states[spi_num].channelTx = E_NO_DEVICE; + states[spi_num].channelRx = E_NO_DEVICE; + return E_NO_DEVICE; + } + + states[spi_num].mtFirstTrans = 0; + + MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA_DMACallback); + MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt(states[spi_num].channelTx); + MXC_DMA_EnableInt(states[spi_num].channelRx); + } + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); + MXC_SPI_RevA_TransHandler(req->spi, req); - + if (bits <= 8) { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 1); - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); - } - else { - - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 2); - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); - } - - #if TARGET_NUM == 32665 - MXC_DMA_Init(dma); - #else - MXC_DMA_Init(); - #endif - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); - MXC_ASSERT (spi_num >= 0); - + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 1); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); + } else { + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 2); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); + } + //tx if (req->txData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif - config.reqsel = reqselTx; - config.ch = channel; - advConfig.ch = channel; + config.ch = states[spi_num].channelTx; + advConfig.ch = states[spi_num].channelTx; advConfig.burst_size = 2; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - + config.srcinc_en = 1; config.dstinc_en = 0; - - srcdst.ch = channel; - srcdst.source = & (req->txData[req->txCnt]); - + + srcdst.ch = states[spi_num].channelTx; + srcdst.source = &(req->txData[req->txCnt]); + if (bits > 8) { srcdst.len = (req->txLen * 2) - req->txCnt; - } - else { + } else { srcdst.len = (req->txLen) - req->txCnt; } - - states[spi_num].channelTx = channel; - - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelTx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelTx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; - + if (bits > 8) { MXC_DMA_AdvConfigChannel(advConfig); //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 1 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } } - - if (req->rxData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif + if (req->rxData != NULL) { config.reqsel = reqselRx; - config.ch = channel; + config.ch = states[spi_num].channelRx; config.srcinc_en = 0; config.dstinc_en = 1; - advConfig.ch = channel; + advConfig.ch = states[spi_num].channelRx; advConfig.burst_size = 1; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - - - srcdst.ch = channel; + + srcdst.ch = states[spi_num].channelRx; srcdst.dest = req->rxData; - + if (bits <= 8) { srcdst.len = req->rxLen; - } - else { + } else { srcdst.len = req->rxLen * 2; } - - states[spi_num].channelRx = channel; - - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelRx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelRx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; - + if (bits > 8) { MXC_DMA_AdvConfigChannel(advConfig); //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 0 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } } - + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_DMA_TX_EN | MXC_F_SPI_REVA_DMA_DMA_RX_EN); - + return E_NO_ERROR; } void MXC_SPI_RevA_DMACallback(int ch, int error) { - mxc_spi_reva_req_t * temp_req; - - for (int i = 0; i < MXC_SPI_INSTANCES; i ++) { - if (states[i].channelTx == ch) { - //save the request - temp_req = states[i].req; - MXC_FreeLock((uint32_t*) &states[i].req); - // Callback if not NULL - if (temp_req->completeCB != NULL) { - temp_req->completeCB(temp_req, E_NO_ERROR); - } - break; - } - - else if (states[i].channelRx == ch) { - //save the request - temp_req = states[i].req; - MXC_FreeLock((uint32_t*) &states[i].req); - - if (MXC_SPI_GetDataSize ((mxc_spi_regs_t*) temp_req->spi) > 8) { - MXC_SPI_RevA_SwapByte (temp_req->rxData, temp_req->rxLen); + mxc_spi_reva_req_t *temp_req; + + for (int i = 0; i < MXC_SPI_INSTANCES; i++) { + if (states[i].req != NULL) { + if (states[i].channelTx == ch) { + states[i].req_done++; + } else if (states[i].channelRx == ch) { + states[i].req_done++; + //save the request + temp_req = states[i].req; + + if (MXC_SPI_GetDataSize((mxc_spi_regs_t *)temp_req->spi) > 8) { + MXC_SPI_RevA_SwapByte(temp_req->rxData, temp_req->rxLen); + } } - // Callback if not NULL - if (temp_req->completeCB != NULL) { - temp_req->completeCB(temp_req, E_NO_ERROR); - } - - break; + if (!states[i].txrx_req || (states[i].txrx_req && states[i].req_done == 2)) { + //save the request + temp_req = states[i].req; + MXC_FreeLock((uint32_t *)&states[i].req); + // Callback if not NULL + if (temp_req->completeCB != NULL) { + temp_req->completeCB(temp_req, E_NO_ERROR); + } + if (states[i].mtMode == 0) { + // release any acquired DMA channels + if (states[i].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[i].channelTx); + states[i].channelTx = E_NO_DEVICE; + } + if (states[i].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[i].channelRx); + states[i].channelRx = E_NO_DEVICE; + } + } + break; + } } } } -int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData) +int MXC_SPI_RevA_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); states[spi_num].defaultTXData = defaultTXData; return E_NO_ERROR; } -void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_AbortAsync(mxc_spi_reva_regs_t *spi) { - MXC_SPI_AbortTransmission ((mxc_spi_regs_t*) spi); + MXC_SPI_AbortTransmission((mxc_spi_regs_t *)spi); } -void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_AsyncHandler(mxc_spi_reva_regs_t *spi) { int spi_num; unsigned rx_avail; uint32_t flags; - + // Clear the interrupt flags spi->inten = 0; flags = spi->intfl; spi->intfl = flags; - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + // Figure out if this SPI has an active request - if ( (states[spi_num].req != NULL) && (flags)) { - if ( (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) >> MXC_F_SPI_REVA_CTRL0_MST_MODE_POS) { + if ((states[spi_num].req != NULL) && (flags)) { + if ((spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) >> MXC_F_SPI_REVA_CTRL0_MST_MODE_POS) { do { - spi->inten = MXC_SPI_RevA_MasterTransHandler(spi, states[spi_num].req); + spi->inten = MXC_SPI_RevA_MasterTransHandler(spi, states[spi_num].req); rx_avail = MXC_SPI_RevA_GetRXFIFOAvailable(spi); - } - while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); - - } - else { + } while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); + + } else { do { spi->inten = MXC_SPI_RevA_SlaveTransHandler(states[spi_num].req); rx_avail = MXC_SPI_RevA_GetRXFIFOAvailable(spi); - } - while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); - + } while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); } } } //call in DMA IRQHANDLER with rxData for transmissions with bits > 8 -void MXC_SPI_RevA_SwapByte(uint8_t* arr, size_t length) +void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length) { MXC_ASSERT(arr != NULL); - - for (size_t i = 0 ; i < (length * 2); i+=2) { + + for (size_t i = 0; i < (length * 2); i += 2) { uint8_t tmp = arr[i]; arr[i] = arr[i + 1]; arr[i + 1] = tmp; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h index 50291087412..bfc190d66ad 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_ #include #include @@ -41,9 +44,13 @@ #include "mxc_delay.h" #include "spi_regs.h" #include "spi_reva_regs.h" -#include "mxc_spi.h" +#include "spi.h" #include "dma.h" +#ifdef __cplusplus +extern "C" { +#endif + typedef enum { SPI_REVA_WIDTH_3WIRE, SPI_REVA_WIDTH_STANDARD, @@ -52,7 +59,7 @@ typedef enum { } mxc_spi_reva_width_t; typedef enum { - SPI_REVA_MODE_0, + SPI_REVA_MODE_0, SPI_REVA_MODE_1, SPI_REVA_MODE_2, SPI_REVA_MODE_3, @@ -61,58 +68,68 @@ typedef enum { typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t; struct _mxc_spi_reva_req_t { - mxc_spi_reva_regs_t* spi; - int ssIdx; - int ssDeassert; - uint8_t *txData; - uint8_t *rxData; - uint32_t txLen; - uint32_t rxLen; - uint32_t txCnt; - uint32_t rxCnt; - spi_complete_cb_t completeCB; + mxc_spi_reva_regs_t *spi; + int ssIdx; + int ssDeassert; + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; + uint32_t rxLen; + uint32_t txCnt; + uint32_t rxCnt; + spi_complete_cb_t completeCB; }; -int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); -int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz); -unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize); -int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx); -int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth); -mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode); -mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi); -unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, +int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz); +int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz); +unsigned int MXC_SPI_RevA_GetFrequency(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize); +int MXC_SPI_RevA_GetDataSize(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode); +int MXC_SPI_RevA_GetMTMode(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx); +int MXC_SPI_RevA_GetSlave(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth); +mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetMode(mxc_spi_reva_regs_t *spi, mxc_spi_reva_mode_t spiMode); +mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_StartTransmission(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_GetActive(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_AbortTransmission(mxc_spi_reva_regs_t *spi); +unsigned int MXC_SPI_RevA_ReadRXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, + unsigned int len); +unsigned int MXC_SPI_RevA_WriteTXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, unsigned int len); -unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, - unsigned int len); -unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi); -unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes); -unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes); -unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi); -unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask); -void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int mask); -int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma); -int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma); -void MXC_SPI_RevA_DMACallback (int ch, int error); -int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData); -void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi); +unsigned int MXC_SPI_RevA_GetTXFIFOAvailable(mxc_spi_reva_regs_t *spi); +unsigned int MXC_SPI_RevA_GetRXFIFOAvailable(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_ClearRXFIFO(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_ClearTXFIFO(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetRXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes); +unsigned int MXC_SPI_RevA_GetRXThreshold(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetTXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes); +unsigned int MXC_SPI_RevA_GetTXThreshold(mxc_spi_reva_regs_t *spi); +unsigned int MXC_SPI_RevA_GetFlags(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_ClearFlags(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_EnableInt(mxc_spi_reva_regs_t *spi, unsigned int mask); +void MXC_SPI_RevA_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int mask); +int MXC_SPI_RevA_MasterTransaction(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_MasterTransactionAsync(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma); +int MXC_SPI_RevA_SlaveTransaction(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_SlaveTransactionAsync(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma); +void MXC_SPI_RevA_DMACallback(int ch, int error); +int MXC_SPI_RevA_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData); +void MXC_SPI_RevA_AbortAsync(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_AsyncHandler(mxc_spi_reva_regs_t *spi); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h index 9dab65ee108..0601b8c0a98 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _SPI_REVA_REGS_H_ #define _SPI_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c index 04ee66236c4..75d1fcd3f68 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c @@ -3,8 +3,8 @@ * @brief Inter-Integrated Sound (I2S) driver implementation. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -51,61 +50,59 @@ #include "spimss_regs.h" #define I2S_CHANNELS 2 -#define I2S_WIDTH 16 +#define I2S_WIDTH 16 int dma_channel = -1; -int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int)) +int MXC_I2S_Init(const mxc_i2s_config_t *config, void (*dma_ctz_cb)(int, int)) { - if(config->map == I2S_MAP_A) { - MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins - } - else if(config->map == I2S_MAP_B) { + if (config->map == I2S_MAP_A) { + MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins + } else if (config->map == I2S_MAP_B) { MXC_GPIO_Config(&gpio_cfg_spi1b); - } - else { + } else { return E_BAD_PARAM; } - - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 clock used for SPIMSS - return MXC_I2S_RevA_Init((mxc_spimss_reva_regs_t*) MXC_SPIMSS, config, dma_ctz_cb); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 clock used for SPIMSS + + return MXC_I2S_RevA_Init((mxc_spimss_reva_regs_t *)MXC_SPIMSS, config, dma_ctz_cb); } int MXC_I2S_Shutdown(void) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 used for SPIMSS - return MXC_I2S_RevA_Shutdown((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 used for SPIMSS + return MXC_I2S_RevA_Shutdown((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_Mute(void) { - return MXC_I2S_RevA_Mute((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + return MXC_I2S_RevA_Mute((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_Unmute(void) { - return MXC_I2S_RevA_Unmute((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + return MXC_I2S_RevA_Unmute((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_Pause(void) { - return MXC_I2S_RevA_Pause((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + return MXC_I2S_RevA_Pause((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_Unpause(void) { - return MXC_I2S_RevA_Unpause((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + return MXC_I2S_RevA_Unpause((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_Stop(void) { - return MXC_I2S_RevA_Stop((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + return MXC_I2S_RevA_Stop((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_Start(void) { - return MXC_I2S_RevA_Start((mxc_spimss_reva_regs_t*) MXC_SPIMSS); + return MXC_I2S_RevA_Start((mxc_spimss_reva_regs_t *)MXC_SPIMSS); } int MXC_I2S_DMA_ClearFlags(void) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c index f992e44a707..2de3670444e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c @@ -3,11 +3,11 @@ * @brief Inter-Integrated Sound(I2S) driver implementation. */ -/* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -51,11 +50,13 @@ #include "spimss_reva.h" #define I2S_CHANNELS 2 -#define I2S_WIDTH 16 +#define I2S_WIDTH 16 -static int dma_channel = -1; +static int tx_dma_channel = -1; +static int rx_dma_channel = -1; -int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int)) +int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config, + void (*dma_ctz_cb)(int, int)) { unsigned int baud; uint16_t clkdiv; @@ -67,123 +68,135 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co /* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */ spimss->ctrl = MXC_F_SPIMSS_REVA_CTRL_MMEN; - spimss->mode = MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO; - spimss->dma = MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8; + spimss->mode = MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO; + + spimss->dma = (1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) | /* TX DMA request FIFO level */ + MXC_F_SPIMSS_DMA_TX_FIFO_CLR | /* Clear TX FIFO */ + (1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) | /* RX DMA request FIFO level */ + MXC_F_SPIMSS_DMA_RX_FIFO_CLR; /* Clear RX FIFO */ /* Setup I2S register from i2s_cfg_t */ - spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS | - config->audio_mode << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS; + spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS | + config->audio_mode << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS; /* Determine divisor for baud rate generator */ baud = config->sample_rate * I2S_CHANNELS * I2S_WIDTH; - if((PeripheralClock / 4) < baud) { + if ((PeripheralClock / 4) < baud) { return E_BAD_PARAM; } - clkdiv = PeripheralClock / (2 * baud); // Peripheral clock in system_max*****.h + clkdiv = PeripheralClock / (2 * baud); // Peripheral clock in system_max*****.h - if(clkdiv < 2) { + if (clkdiv < 2) { return E_BAD_PARAM; } spimss->brg = clkdiv; /* Prepare SPIMSS DMA register for DMA setup */ - if(dma_ctz_cb == NULL) { + if (dma_ctz_cb == NULL) { ctz_en = 0; } else { ctz_en = 1; } /* Initialize DMA */ - if(config->audio_direction % 2) { + if (config->audio_direction % 2) { spimss->dma |= MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR; - if((err = MXC_DMA_Init()) != E_NO_ERROR) { - if(err != E_BAD_STATE) { + if ((err = MXC_DMA_Init()) != E_NO_ERROR) { + if (err != E_BAD_STATE) { return err; } } - if((err = MXC_DMA_AcquireChannel()) < 0) { + if ((err = MXC_DMA_AcquireChannel()) < 0) { return err; } - dma_channel = err; + tx_dma_channel = err; - dma_config.ch = dma_channel; + dma_config.ch = tx_dma_channel; - dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD; - dma_config.dstwd = MXC_DMA_WIDTH_WORD; - #if TARGET_NUM == 32650 + dma_config.srcwd = MXC_DMA_WIDTH_WORD; + dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD; +#if TARGET_NUM == 32650 dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSTX; - #endif - +#endif +#if TARGET_NUM == 32660 + dma_config.reqsel = MXC_DMA_REQUEST_SPI1TX; +#endif + dma_config.srcinc_en = 1; dma_config.dstinc_en = 0; - srcdst.ch = dma_channel; + srcdst.ch = tx_dma_channel; srcdst.source = config->src_addr; + srcdst.dest = NULL; srcdst.len = config->length; MXC_DMA_ConfigChannel(dma_config, srcdst); - MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1); + MXC_DMA_SetChannelInterruptEn(tx_dma_channel, 0, 1); - MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST; - MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS); + MXC_DMA->ch[tx_dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST; + MXC_DMA->ch[tx_dma_channel].cfg |= (3 << MXC_F_DMA_CFG_BRST_POS); - if(ctz_en) { - MXC_DMA_SetCallback(dma_channel, dma_ctz_cb); - MXC_DMA_EnableInt(dma_channel); + if (ctz_en) { + MXC_DMA_SetCallback(tx_dma_channel, dma_ctz_cb); + MXC_DMA_EnableInt(tx_dma_channel); } } - if(config->audio_direction / 2) { - spimss->dma = MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR; - if((err = MXC_DMA_Init()) != E_NO_ERROR) { - if(err != E_BAD_STATE) { //DMA already initialized + if (config->audio_direction / 2) { + spimss->dma |= MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR; + if ((err = MXC_DMA_Init()) != E_NO_ERROR) { + if (err != E_BAD_STATE) { //DMA already initialized return err; } } - if((err = MXC_DMA_AcquireChannel()) < 0) { + if ((err = MXC_DMA_AcquireChannel()) < 0) { return err; } - dma_channel = err; + rx_dma_channel = err; - dma_config.ch = dma_channel; - - dma_config.srcwd = MXC_DMA_WIDTH_WORD; - dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD; - #if TARGET_NUM == 32650 + dma_config.ch = rx_dma_channel; + + dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD; + dma_config.dstwd = MXC_DMA_WIDTH_WORD; +#if TARGET_NUM == 32650 dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSRX; - #endif +#endif +#if TARGET_NUM == 32660 + dma_config.reqsel = MXC_DMA_REQUEST_SPI1RX; +#endif dma_config.srcinc_en = 0; dma_config.dstinc_en = 1; - srcdst.ch = dma_channel; + srcdst.ch = rx_dma_channel; + srcdst.source = NULL; srcdst.dest = config->dst_addr; srcdst.len = config->length; MXC_DMA_ConfigChannel(dma_config, srcdst); - MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1); + MXC_DMA_SetChannelInterruptEn(rx_dma_channel, 0, 1); - MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST; - MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS); + MXC_DMA->ch[rx_dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST; + MXC_DMA->ch[rx_dma_channel].cfg |= (3 << MXC_F_DMA_CFG_BRST_POS); - if(ctz_en) { - MXC_DMA_SetCallback(dma_channel, dma_ctz_cb); - MXC_DMA_EnableInt(dma_channel); + if (ctz_en) { + MXC_DMA_SetCallback(rx_dma_channel, dma_ctz_cb); + MXC_DMA_EnableInt(rx_dma_channel); } } MXC_I2S_DMA_SetAddrCnt(config->src_addr, config->dst_addr, config->length); - if(config->dma_reload_en) { + if (config->dma_reload_en) { MXC_I2S_DMA_SetReload(config->src_addr, config->dst_addr, config->length); } - if(config->start_immediately) { + if (config->start_immediately) { return MXC_I2S_Start(); } return E_NO_ERROR; @@ -191,12 +204,28 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss) { + int retTx = E_NO_ERROR; + int retRx = E_NO_ERROR; + spimss->ctrl = 0; spimss->i2s_ctrl = 0; spimss->brg = 0; spimss->mode = 0; spimss->dma = 0; - return MXC_DMA_ReleaseChannel(dma_channel); + + if (tx_dma_channel != -1) { + retTx = MXC_DMA_ReleaseChannel(tx_dma_channel); + } + + if (rx_dma_channel != -1) { + retRx = MXC_DMA_ReleaseChannel(rx_dma_channel); + } + + if (retTx != E_NO_ERROR) { + return retTx; + } else { + return retRx; + } } int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss) @@ -225,40 +254,125 @@ int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss) int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss) { + int retTx = E_NO_ERROR; + int retRx = E_NO_ERROR; + spimss->ctrl &= ~MXC_F_SPIMSS_REVA_CTRL_ENABLE; spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN; - return MXC_DMA_Stop(dma_channel); + + if (tx_dma_channel != -1) { + retTx = MXC_DMA_Stop(tx_dma_channel); + } + if (rx_dma_channel != -1) { + retRx = MXC_DMA_Stop(rx_dma_channel); + } + + if (retTx != E_NO_ERROR) { + return retTx; + } else { + return retRx; + } } int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss) { + int retTx = E_NO_ERROR; + int retRx = E_NO_ERROR; + spimss->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN; - return MXC_DMA_Start(dma_channel); + + if (tx_dma_channel != -1) { + retTx = MXC_DMA_Start(tx_dma_channel); + } + if (rx_dma_channel != -1) { + retRx = MXC_DMA_Start(rx_dma_channel); + } + + if (retTx != E_NO_ERROR) { + return retTx; + } else { + return retRx; + } } int MXC_I2S_RevA_DMA_ClearFlags(void) { - int flags = MXC_DMA_ChannelGetFlags(dma_channel); - return MXC_DMA_ChannelClearFlags(dma_channel, flags); + int retTx = E_NO_ERROR; + int retRx = E_NO_ERROR; + + int flags; + + if (tx_dma_channel != -1) { + flags = MXC_DMA_ChannelGetFlags(tx_dma_channel); + retTx = MXC_DMA_ChannelClearFlags(tx_dma_channel, flags); + } + if (rx_dma_channel != -1) { + flags = MXC_DMA_ChannelGetFlags(rx_dma_channel); + retRx = MXC_DMA_ChannelClearFlags(rx_dma_channel, flags); + } + + if (retTx != E_NO_ERROR) { + return retTx; + } else { + return retRx; + } } int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count) { + int retTx = E_NO_ERROR; + int retRx = E_NO_ERROR; + mxc_dma_srcdst_t srcdst; - srcdst.ch = dma_channel; - srcdst.source = src_addr; - srcdst.dest = dst_addr; - srcdst.len = count; - return MXC_DMA_SetSrcDst(srcdst); + + if (tx_dma_channel != -1) { + srcdst.ch = tx_dma_channel; + srcdst.source = src_addr; + srcdst.dest = dst_addr; + srcdst.len = count; + retTx = MXC_DMA_SetSrcDst(srcdst); + } + if (rx_dma_channel != -1) { + srcdst.ch = rx_dma_channel; + srcdst.source = src_addr; + srcdst.dest = dst_addr; + srcdst.len = count; + retRx = MXC_DMA_SetSrcDst(srcdst); + } + + if (retTx != E_NO_ERROR) { + return retTx; + } else { + return retRx; + } } int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count) { + int retTx = E_NO_ERROR; + int retRx = E_NO_ERROR; + mxc_dma_srcdst_t srcdst; - srcdst.ch = dma_channel; - srcdst.source = src_addr; - srcdst.dest = dst_addr; - srcdst.len = count; - return MXC_DMA_SetSrcReload(srcdst); + + if (tx_dma_channel != -1) { + srcdst.ch = tx_dma_channel; + srcdst.source = src_addr; + srcdst.dest = dst_addr; + srcdst.len = count; + retTx = MXC_DMA_SetSrcReload(srcdst); + } + if (rx_dma_channel != -1) { + srcdst.ch = rx_dma_channel; + srcdst.source = src_addr; + srcdst.dest = dst_addr; + srcdst.len = count; + retRx = MXC_DMA_SetSrcReload(srcdst); + } + + if (retTx != E_NO_ERROR) { + return retTx; + } else { + return retRx; + } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h index 84e7c753dc2..8e57634b0a7 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_ #include #include @@ -37,9 +40,8 @@ #include "i2s.h" #include "spimss_reva_regs.h" - - -int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req, void (*dma_ctz_cb)(int, int)); +int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req, + void (*dma_ctz_cb)(int, int)); int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss); int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss); int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss); @@ -50,3 +52,5 @@ int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss); int MXC_I2S_RevA_DMA_ClearFlags(void); int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count); int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c index d69d258c5f6..cf7adfe1cf2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -42,11 +42,17 @@ #include "spimss_reva_regs.h" #include "spimss_reva.h" - /* **** Functions **** */ +/* **** Functions **** */ /* ************************************************************************** */ -int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel) +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg) { + int spi_num; + + spi_num = MXC_SPIMSS_GET_IDX(spi); + + MXC_ASSERT(spi_num >= 0); + if (mode > 3) { return E_BAD_PARAM; } @@ -59,73 +65,67 @@ int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const // Configure GPIO for spimss if (spi == MXC_SPIMSS) { MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI1; - while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1); - MXC_GCR->pclk_dis0 &= ~ (MXC_F_GCR_PCLK_DIS0_SPI1D); - if(sys_cfg == MAP_A){ - MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen - }else if(sys_cfg == MAP_B){ - MXC_GPIO_Config(&gpio_cfg_spi1b); // SPI1B chosen - }else{ + while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1) {} + MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI1D); + if (sys_cfg == MAP_A) { + MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen + } else if (sys_cfg == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_spi1b); // SPI1B chosen + } else { return E_BAD_PARAM; } } else { return E_NO_DEVICE; } - return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t*) spi, mode, freq, drv_ssel); + return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq); } /* ************************************************************************* */ int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi) { - if(spi != MXC_SPIMSS) { - return E_NO_DEVICE; - } + int spi_num; + spi_num = MXC_SPIMSS_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); - MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t*) spi); - // - MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D); + MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t *)spi); + if (spi == MXC_SPIMSS) { + MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D); + } return E_NO_ERROR; } /* ************************************************************************** */ -void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ +void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ { - MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t*) spi); + MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t *)spi); } /* ************************************************************************** */ int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) { - return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); + return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req); } - /* ************************************************************************** */ int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) { - return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); + return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req); } /* ************************************************************************** */ int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) { - return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); + return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t *)spi, + (spimss_reva_req_t *)req); } /* ************************************************************************** */ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) { - return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); -} - -/* ************************************************************************* */ -int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData) -{ - return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData); + return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req); } - /* ************************************************************************* */ int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req) { - return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t*) req); + return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t *)req); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c index cafa7d0b13d..b58537356e6 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c @@ -1,11 +1,11 @@ - /** +/** * @file spimss.c * @brief This file contains the function implementations for the * Serial Peripheral Interface (SPIMSS) peripheral module. */ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,9 +35,8 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - **************************************************************************** */ - + ******************************************************************************/ + /* **** Includes **** */ #include #include @@ -55,48 +54,46 @@ /* **** Definitions **** */ - - /* **** Globals **** */ typedef struct { spimss_reva_req_t *req; - unsigned defaultTXData; - unsigned drv_ssel; } spimss_reva_req_state_t; static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES]; - /* **** Functions **** */ -static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master); -static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, + int master); +static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, + spimss_reva_req_t *req); static uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); -static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, + spimss_reva_req_t *req); /* ************************************************************************** */ -int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel) +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq) { int spi_num; unsigned int spimss_clk; - unsigned int pol, pha; // Polarity and phase of the clock (SPI mode) + unsigned int pol, pha; // Polarity and phase of the clock (SPI mode) - spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); states[spi_num].req = NULL; - states[spi_num].defaultTXData = 0; - states[spi_num].drv_ssel = drv_ssel; - spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start) + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start) - // Set the bit rate + // Set the bit rate spimss_clk = PeripheralClock; spi->brg = (spimss_clk / freq) >> 1; // Set the mode - pol = mode >> 1; // Get the polarity out of the mode input value - pha = mode & 1; // Get the phase out of the mode input value + pol = mode >> 1; // Get the polarity out of the mode input value + pha = mode & 1; // Get the phase out of the mode input value - spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity - - spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase + spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | + (pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity + + spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | + (pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase spi->int_fl &= ~(MXC_F_SPIMSS_REVA_INT_FL_IRQ); @@ -109,22 +106,21 @@ int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi) spimss_reva_req_t *temp_req; // Disable and turn off the SPI transaction. - spi->ctrl = 0; // Interrupts, SPI transaction all turned off + spi->ctrl = 0; // Interrupts, SPI transaction all turned off spi->int_fl = 0; - spi->mode = 0; + spi->mode = 0; // Reset FIFO counters - spi->dma &= ~(MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT); + spi->dma &= ~(MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT | MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT); // Call all of the pending callbacks for this SPI - spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); if (states[spi_num].req != NULL) { - // Save the request temp_req = states[spi_num].req; // Unlock this SPI - MXC_FreeLock((uint32_t*)&states[spi_num].req); + MXC_FreeLock((uint32_t *)&states[spi_num].req); // Callback if not NULL if (temp_req->callback != NULL) { @@ -142,17 +138,17 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r { int spi_num; - spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation - // of SPI Start is disabled. + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation + // of SPI Start is disabled. - spi->mode |= MXC_F_SPIMSS_REVA_MODE_TX_LJ; // Making sure data is left - // justified. + spi->mode |= MXC_F_SPIMSS_REVA_MODE_TX_LJ; // Making sure data is left + // justified. if ((req->tx_data == NULL) && (req->rx_data == NULL)) { return -1; } - spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); MXC_ASSERT(spi_num >= 0); if (req->len == 0) { @@ -162,50 +158,41 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r req->tx_num = 0; req->rx_num = 0; - if (MXC_GetLock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) { + if (MXC_GetLock((uint32_t *)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) { return E_BUSY; } if (master) { // Enable master mode - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master. - if (states[spi_num].drv_ssel) { - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output. - } + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master. + spi->mode |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SSEL pin is an output. } else { // Enable slave mode - spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave. - spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input. + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave. + spi->mode &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SSEL pin is an input. } // Setup the character size - if (req->bits <16) { - MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); - + if (req->bits < 16) { + MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS, + req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); + } else { - MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); - + MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS, + 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); } - if (req->tx_data == NULL) { - // Must have something to send, so we'll use the rx_data buffer initialized to 0. - memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len)); - req->tx_data = req->rx_data; - } + // Setup the slave select + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, + // to get the line ready for active low later // Clear the TX and RX FIFO spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR); - if (states[spi_num].drv_ssel) { - // Setup the slave select - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, - // to get the line ready for active low later - } - return E_NO_ERROR; } /* ************************************************************************** */ -void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ +void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ { int spi_num; uint32_t flags; @@ -213,23 +200,22 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ flags = spi->int_fl; spi->int_fl = flags; - spi->int_fl|= 0x80; // clear interrupt + spi->int_fl |= 0x80; // clear interrupt - spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); int_enable = 0; if (states[spi_num].req != NULL) { - if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) { + if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) { int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, states[spi_num].req); - + } else { - int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, states[spi_num].req); + int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, states[spi_num].req); } } - if (int_enable==1) { - spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE ); - + if (int_enable == 1) { + spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE); } } @@ -237,48 +223,43 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) { int error; - int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { return error; } - + req->callback = NULL; - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI - if (states[spi_num].drv_ssel) { - spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. - } + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI - while (MXC_SPIMSS_RevA_MasterTransHandler(spi,req)!=0) { - ; - } + while (MXC_SPIMSS_RevA_MasterTransHandler(spi, req) != 0) {} - if (states[spi_num].drv_ssel) { - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; - } - spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... - // stop the transmission... + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; + + spi->ctrl &= + ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... + // stop the transmission... return E_NO_ERROR; } - /* ************************************************************************** */ int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) { int error; - - if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req,0)) != E_NO_ERROR) { + + if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 0)) != E_NO_ERROR) { return error; } - while (MXC_SPIMSS_RevA_SlaveTransHandler(spi,req)!=0) { - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI - while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {} - } + while (MXC_SPIMSS_RevA_SlaveTransHandler(spi, req) != 0) { + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {} + } - spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... - // stop the transmission... + spi->ctrl &= + ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... + // stop the transmission... return E_NO_ERROR; } @@ -287,20 +268,21 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re { int error; uint8_t int_enable; - int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); - if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1) )!= E_NO_ERROR) { - return error; + // Clear state for next transaction + MXC_SPIMSS_AbortAsync((mxc_spimss_req_t *)req); + + if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { + return error; } - int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi,req); + int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, req); - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI - if (states[spi_num].drv_ssel) { - spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. - } + spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. - if (int_enable==1) { + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + + if (int_enable == 1) { spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); } @@ -316,12 +298,12 @@ int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req return error; } - int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi,req); + int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, req); - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI - if (int_enable==1) { // Trigger a SPI Interrupt - spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE ); + if (int_enable == 1) { // Trigger a SPI Interrupt + spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE); } return E_NO_ERROR; @@ -334,8 +316,8 @@ uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_ uint32_t retval; if (!start_set) { - start_set = 1; - retval = MXC_SPIMSS_RevA_TransHandler(spi,req); + start_set = 1; + retval = MXC_SPIMSS_RevA_TransHandler(spi, req); } return retval; @@ -344,7 +326,7 @@ uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_ /* ************************************************************************** */ uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) { - return MXC_SPIMSS_RevA_TransHandler(spi,req); + return MXC_SPIMSS_RevA_TransHandler(spi, req); } /* ************************************************************************** */ @@ -352,40 +334,88 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r { unsigned tx_avail, rx_avail; int remain, spi_num; - uint32_t int_en =0; - uint32_t length =req->len; + uint32_t int_en = 0; + uint32_t length = req->len; - spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); - if (spi_num < 0) { - MXC_ASSERT(0); - } + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); + + // Read the RX FIFO + if (req->rx_data != NULL) { + // Wait for there to be data in the RX FIFO + rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> + MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS); + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + + // Read from the FIFO + while (rx_avail) { + // Don't read less than 2 bytes if we are using greater than 8 bit characters + if (req->bits > 8) { + ((uint16_t *)req->rx_data)[req->rx_num++] = spi->data; + rx_avail -= 1; + + } else { + ((uint8_t *)req->rx_data)[req->rx_num++] = spi->data; + rx_avail -= 1; + } + rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> + MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS); + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + } + + remain = length - req->rx_num; + if (remain) { + if (remain > MXC_SPIMSS_FIFO_DEPTH) { + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | + ((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)); + } else { + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | + ((remain - 1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)); + } + + int_en = 1; + } + + // Break out if we've received all the bytes and we're not transmitting + if ((req->tx_data == NULL) && (req->rx_num == length)) { + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); + int_en = 0; + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + } // Note:- spi->dma shows the FIFO TX count and FIFO RX count in // Words, while the calculation below is in bytes. if (req->tx_data != NULL) { - if (req->tx_num < length) { - // Calculate how many bytes we can write to the FIFO (tx_avail holds that value) - tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes + tx_avail = + MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >> + MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes if ((length - req->tx_num) < tx_avail) { - tx_avail = (length - req->tx_num); // This is for the last spin + tx_avail = (length - req->tx_num); // This is for the last spin } if (req->bits > 8) { tx_avail &= ~(unsigned)0x1; } // Write the FIFO while (tx_avail) { - if (req->bits >8) { - spi->data = ((uint16_t*)req->tx_data)[req->tx_num++]; + if (req->bits > 8) { + spi->data = ((uint16_t *)req->tx_data)[req->tx_num++]; - tx_avail -= 1; + tx_avail -= 1; } else { - spi->data = ((uint8_t*)req->tx_data)[req->tx_num++]; - tx_avail -=1; + spi->data = ((uint8_t *)req->tx_data)[req->tx_num++]; + tx_avail -= 1; } - } } @@ -394,10 +424,13 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r // If there are values remaining to be transmitted, this portion will get // executed and int_en set, to indicate that this must spin and come back again... if (remain) { - if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum, - spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); - } else { // only one more tx round will be done... Transfer whatever remains, - spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); + if (remain > + MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum, + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | + ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); + } else { // only one more tx round will be done... Transfer whatever remains, + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | + ((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); } int_en = 1; // This will act as a trigger for the next round... } @@ -406,7 +439,7 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r if ((req->rx_data == NULL) && (req->tx_num == length)) { spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); int_en = 0; - MXC_FreeLock((uint32_t*)&states[spi_num].req); + MXC_FreeLock((uint32_t *)&states[spi_num].req); // Callback if not NULL if (req->callback != NULL) { req->callback(req, E_NO_ERROR); @@ -414,50 +447,11 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r } } - // Read the RX FIFO - // Wait for there to be data in the RX FIFO - uint16_t rx_data; - - rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS); - if ((length - req->rx_num) < rx_avail) { - rx_avail = (length - req->rx_num); - } - - // Read from the FIFO - while (rx_avail) { - rx_data = spi->data; - rx_avail -= 1; - - if (req->rx_data != NULL) { - if (req->bits>8) { - ((uint16_t*)req->rx_data)[req->rx_num] = rx_data; - } else { - ((uint8_t*)req->rx_data)[req->rx_num] = rx_data; - } - } - req->rx_num++; // assume read one byte - - rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS); - if ((length - req->rx_num) < rx_avail) { - rx_avail = (length - req->rx_num); - } - } - - remain = length - req->rx_num; - if (remain) { - if (remain > MXC_SPIMSS_FIFO_DEPTH) { - spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)); - } else { - spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)); - } - int_en = 1; - } - // Break out once we've transmitted and received all of the data if ((req->rx_num == length) && (req->tx_num == length)) { spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); int_en = 0; - MXC_FreeLock((uint32_t*)&states[spi_num].req); + MXC_FreeLock((uint32_t *)&states[spi_num].req); // Callback if not NULL if (req->callback != NULL) { req->callback(req, E_NO_ERROR); @@ -467,15 +461,6 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r return int_en; } -/* ************************************************************************* */ -int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData) -{ - int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - states[spi_num].defaultTXData = defaultTXData; - return E_NO_ERROR; -} - /* ************************************************************************* */ int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req) { @@ -490,17 +475,16 @@ int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req) // Find the request, set to NULL for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) { if (req == states[spi_num].req) { - - spi =(mxc_spimss_reva_regs_t *) MXC_SPIMSS_GET_SPI(spi_num); + spi = (mxc_spimss_reva_regs_t *)MXC_SPIMSS_GET_SPI(spi_num); // Disable interrupts, clear the flags spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); // Disable and turn off the SPI transaction. - spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Unlock this SPI - MXC_FreeLock((uint32_t*)&states[spi_num].req); + MXC_FreeLock((uint32_t *)&states[spi_num].req); // Callback if not NULL if (req->callback != NULL) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h index eb3323d7d7f..a2d1cfd83c8 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_ #include #include @@ -44,13 +47,13 @@ #include "spimss_reva_regs.h" #include "spimss.h" - /** +/** * @brief Enumeration type for setting the number data lines to use for communication. */ -typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED - DUMMY_1_RevA, /**< NOT USED */ - DUMMY_2_RevA, /**< NOT USED */ - DUMMY_3_RevA, /**< NOT USED */ +typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED + DUMMY_1_RevA, /**< NOT USED */ + DUMMY_2_RevA, /**< NOT USED */ + DUMMY_3_RevA, /**< NOT USED */ } spimss_reva_width_t; /** @@ -71,7 +74,7 @@ typedef struct spimss_reva_req spimss_reva_req_t; * @note Callback will execute in interrupt context * @addtogroup spi_async */ -typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t * req, int error_code); +typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t *req, int error_code); /** * @brief Structure definition for an SPI Master Transaction request. @@ -80,25 +83,25 @@ typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t * req, int error_code) * @addtogroup spi_async */ struct spimss_reva_req { - uint8_t ssel; /**< Not Used*/ - uint8_t deass; /**< Not Used*/ - const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ - void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ - spimss_reva_width_t width; /**< Not Used */ - unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ - unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ - unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ - unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ - spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */ + uint8_t ssel; /**< Not Used*/ + uint8_t deass; /**< Not Used*/ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + spimss_reva_width_t width; /**< Not Used */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */ }; - -int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel); +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq); int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi); void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi); int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); -int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData); int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h index f0281426ca0..a002e4efde2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _SPIMSS_REVA_REGS_H_ #define _SPIMSS_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c index 7f3c9131b59..f356cc6813f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -42,7 +41,7 @@ /* **** Functions **** */ /* ************************************************************************** */ -__weak void mxc_assert(const char* expr, const char* file, int line) +__weak void mxc_assert(const char *expr, const char *file, int line) { while (1) {} } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c index 88963b51731..df60f7e5fef 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -41,7 +40,7 @@ #ifdef __riscv -int MXC_Delay(unsigned long us) +int MXC_Delay(uint32_t us) { // Check if there is nothing to do if (us == 0) { @@ -51,18 +50,18 @@ int MXC_Delay(unsigned long us) // Calculate number of cycles needed. uint32_t ticks = (MXC_SYS_RiscVClockRate() / 1000000) * us; - CSR_SetPCMR(0); // Turn off counter - CSR_SetPCCR(0); // Clear counter register - CSR_SetPCER(1); // Enable counting of cycles - CSR_SetPCMR(3); // Turn on counter + CSR_SetPCMR(0); // Turn off counter + CSR_SetPCCR(0); // Clear counter register + CSR_SetPCER(1); // Enable counting of cycles + CSR_SetPCMR(3); // Turn on counter - while(CSR_GetPCCR() < ticks) { + while (CSR_GetPCCR() < ticks) { // Wait for counter to reach the tick count. } return E_NO_ERROR; } -int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback) +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback) { return E_NOT_SUPPORTED; } @@ -72,9 +71,7 @@ int MXC_DelayCheck(void) return E_NOT_SUPPORTED; } -void MXC_DelayAbort(void) -{ -} +void MXC_DelayAbort(void) {} #else @@ -84,7 +81,7 @@ static uint32_t endtick; static uint32_t ctrl_save; static mxc_delay_complete_t cbFunc; -static void MXC_DelayInit(unsigned long us); +static void MXC_DelayInit(uint32_t us); extern void SysTick_Handler(void); /* ************************************************************************** */ @@ -101,10 +98,9 @@ void MXC_DelayHandler(void) // Decrement overflow flag if delay is still ongoing if (overflows > 0) { overflows--; - } - else { + } else { MXC_DelayAbort(); - + if (cbFunc != NULL) { cbFunc(E_NO_ERROR); cbFunc = NULL; @@ -114,16 +110,16 @@ void MXC_DelayHandler(void) } /* ************************************************************************** */ -static void MXC_DelayInit(unsigned long us) +static void MXC_DelayInit(uint32_t us) { uint32_t starttick, reload, ticks, lastticks; - + // Record the current tick value and clear the overflow flag starttick = SysTick->VAL; - + // Save the state of control register (and clear the overflow flag) ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk; - + // If the SysTick is not running, configure and start it if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; @@ -131,53 +127,51 @@ static void MXC_DelayInit(unsigned long us) SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; starttick = SysTick_VAL_CURRENT_Msk; reload = SysTick_LOAD_RELOAD_Msk + 1; - } - else { + } else { reload = SysTick->LOAD + 1; // get the current reload value } - + // Calculate the total number of ticks to delay - ticks = (uint32_t)(((uint64_t) us * (uint64_t) SystemCoreClock) / 1000000); - + ticks = (uint32_t)(((uint64_t)us * (uint64_t)SystemCoreClock) / 1000000); + // How many overflows of the SysTick will occur overflows = ticks / reload; - + // How many remaining ticks after the last overflow lastticks = ticks % reload; - + // Check if there will be another overflow due to the current value of the SysTick if (lastticks >= starttick) { overflows++; endtick = reload - (lastticks - starttick); - } - else { + } else { endtick = starttick - lastticks; } } /* ************************************************************************** */ -int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback) +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback) { cbFunc = callback; - + // Check if timeout currently ongoing if (overflows > 0) { return E_BUSY; } - + // Check if there is nothing to do if (us == 0) { return E_NO_ERROR; } - + // Calculate the necessary delay and start the timer MXC_DelayInit(us); - + // Enable SysTick interrupt if necessary if (overflows > 0) { SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; } - + return E_NO_ERROR; } @@ -190,22 +184,22 @@ int MXC_DelayCheck(void) cbFunc(E_NO_ERROR); cbFunc = NULL; } - + return E_NO_ERROR; } - + // Check the global values if ((overflows == 0) && (SysTick->VAL <= endtick)) { MXC_DelayAbort(); - + if (cbFunc != NULL) { cbFunc(E_NO_ERROR); cbFunc = NULL; } - + return E_NO_ERROR; } - + return E_BUSY; } @@ -216,27 +210,27 @@ void MXC_DelayAbort(void) cbFunc(E_ABORT); cbFunc = NULL; } - + SysTick->CTRL = ctrl_save; overflows = -1; } /* ************************************************************************** */ -int MXC_Delay(unsigned long us) +int MXC_Delay(uint32_t us) { // Check if timeout currently ongoing if (overflows > 0) { return E_BUSY; } - + // Check if there is nothing to do if (us == 0) { return E_NO_ERROR; } - + // Calculate the necessary delay and start the timer MXC_DelayInit(us); - + // Wait for the number of overflows while (overflows > 0) { // If SysTick interrupts are enabled, COUNTFLAG will never be set here and @@ -246,12 +240,12 @@ int MXC_Delay(unsigned long us) overflows--; } } - + // Wait for the counter value - while (SysTick->VAL > endtick); - + while (SysTick->VAL > endtick) {} + MXC_DelayAbort(); return E_NO_ERROR; } -#endif // __riscv \ No newline at end of file +#endif // __riscv diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index f8f199439ad..459df723f14 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,37 +29,33 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include "mxc_device.h" #include "mxc_lock.h" -#if USE_LOCK_IN_DRIVERS - #ifndef __riscv /* ************************************************************************** */ -int MXC_GetLock(uint32_t* lock, uint32_t value) +int MXC_GetLock(uint32_t *lock, uint32_t value) { do { - // Return if the lock is taken by a different thread - if (__LDREXW((volatile unsigned long*) lock) != 0) { + if (__LDREXW((volatile uint32_t *)lock) != 0) { return E_BUSY; } - + // Attempt to take the lock - } - while (__STREXW(value, (volatile unsigned long*) lock) != 0); - + } while (__STREXW(value, (volatile uint32_t *)lock) != 0); + // Do not start any other memory access until memory barrier is complete __DMB(); - + return E_NO_ERROR; } /* ************************************************************************** */ -void MXC_FreeLock(uint32_t* lock) +void MXC_FreeLock(uint32_t *lock) { // Ensure memory operations complete before releasing lock __DMB(); @@ -67,17 +63,15 @@ void MXC_FreeLock(uint32_t* lock) } #else // __riscv /* ************************************************************************** */ -int MXC_GetLock(uint32_t* lock, uint32_t value) -{ - #warning "Unimplemented for RISCV" +int MXC_GetLock(uint32_t *lock, uint32_t value) +{ +#warning "Unimplemented for RISCV" return E_NO_ERROR; } /* ************************************************************************** */ -void MXC_FreeLock(uint32_t* lock) +void MXC_FreeLock(uint32_t *lock) { - #warning "Unimplemented for RISCV" +#warning "Unimplemented for RISCV" } #endif - -#endif // USE_LOCK_IN_DRIVERS diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c index afe7258983c..14be089aff0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c @@ -3,8 +3,8 @@ * @brief This file contains constant pin configurations for the peripherals. */ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - **************************************************************************** */ + ******************************************************************************/ #include "gpio.h" #include "mxc_device.h" @@ -43,34 +42,55 @@ /***** Definitions *****/ /***** Global Variables *****/ -const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; - -const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; - +const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10|MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_VSSEL_VDDIO }; -//SPI0 -const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -// SPI1A -const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -//SPI1B -const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), + MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), + MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi0 = { + MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE +}; +const mxc_gpio_cfg_t gpio_cfg_spi1a = { + MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE +}; +const mxc_gpio_cfg_t gpio_cfg_spi1b = { + MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE +}; // Timers are only defined once, depending on package, each timer could be mapped to other pins -const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; +const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO }; -const mxc_gpio_cfg_t gpio_cfg_i2s0a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_i2s0b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_i2s0a = { + MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE +}; +const mxc_gpio_cfg_t gpio_cfg_i2s0b = { + MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE +}; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c index 128f439ff98..8dbc9ef8cee 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /** * @file mxc_sys.c @@ -45,6 +44,7 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "mxc_delay.h" +#include "flc.h" #include "gcr_regs.h" #include "fcr_regs.h" @@ -54,48 +54,98 @@ */ /* **** Definitions **** */ -#define MXC_SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1) +#define MXC_SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1) /* **** Globals **** */ /* **** Functions **** */ /* ************************************************************************** */ -int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock) +int MXC_SYS_GetUSN(uint8_t *usn, int len, int part) +{ + if (len != MXC_SYS_USN_LEN) { + return E_BAD_PARAM; + } + + uint32_t infoblock[6]; + + MXC_FLC_UnlockInfoBlock(0x0000); + infoblock[0] = *(uint32_t *)MXC_INFO_MEM_BASE; + infoblock[1] = *(uint32_t *)(MXC_INFO_MEM_BASE + 4); + infoblock[2] = *(uint32_t *)(MXC_INFO_MEM_BASE + 8); + infoblock[3] = *(uint32_t *)(MXC_INFO_MEM_BASE + 12); + infoblock[4] = *(uint32_t *)(MXC_INFO_MEM_BASE + 16); + infoblock[5] = *(uint32_t *)(MXC_INFO_MEM_BASE + 20); + MXC_FLC_LockInfoBlock(0x0000); + + if (part == 0) { + usn[0] = (infoblock[0] & 0x000000FF); + usn[1] = (infoblock[0] & 0x0000FF00) >> 8; + usn[2] = (infoblock[0] & 0x00FF0000) >> 16; + usn[3] = (infoblock[0] & 0x3F000000) >> 24; + usn[3] |= (infoblock[1] & 0x00000003) << 30; + usn[4] = (infoblock[1] & 0x000003FC) >> 2; + usn[5] = (infoblock[1] & 0x0003FC00) >> 10; + usn[6] = (infoblock[1] & 0x03FC0000) >> 18; + usn[7] = (infoblock[1] & 0x3C000000) >> 26; + } else if (part == 1) { + usn[0] = (infoblock[2] & 0x000000FF); + usn[1] = (infoblock[2] & 0x0000FF00) >> 8; + usn[2] = (infoblock[2] & 0x00FF0000) >> 16; + usn[3] = (infoblock[2] & 0xFF000000) >> 24; + usn[4] = (infoblock[3] & 0x000000FF); + usn[5] = (infoblock[3] & 0x0000FF00) >> 8; + usn[6] = (infoblock[3] & 0x00FF0000) >> 16; + usn[7] = (infoblock[3] & 0xFF000000) >> 24; + } else if (part == 2) { + usn[0] = (infoblock[4] & 0x000000FF); + usn[1] = (infoblock[4] & 0x0000FF00) >> 8; + usn[2] = (infoblock[4] & 0x00FF0000) >> 16; + usn[3] = (infoblock[4] & 0xFF000000) >> 24; + usn[4] = (infoblock[5] & 0x000000FF); + usn[5] = (infoblock[5] & 0x0000FF00) >> 8; + usn[6] = (infoblock[5] & 0x00FF0000) >> 16; + usn[7] = (infoblock[5] & 0xFF000000) >> 24; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */ if (clock > 31) { clock -= 32; - return ! (MXC_GCR->pclk_dis1 & (0x1 << clock)); - } - else { - return ! (MXC_GCR->pclk_dis0 & (0x1 << clock)); + return !(MXC_GCR->pclk_dis1 & (0x1 << clock)); + } else { + return !(MXC_GCR->pclk_dis0 & (0x1 << clock)); } } /* ************************************************************************** */ -void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock) +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */ if (clock > 31) { clock -= 32; MXC_GCR->pclk_dis1 |= (0x1 << clock); - } - else { + } else { MXC_GCR->pclk_dis0 |= (0x1 << clock); } } /* ************************************************************************** */ -void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock) +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */ if (clock > 31) { clock -= 32; - MXC_GCR->pclk_dis1 &= ~ (0x1 << clock); - } - else { - MXC_GCR->pclk_dis0 &= ~ (0x1 << clock); + MXC_GCR->pclk_dis1 &= ~(0x1 << clock); + } else { + MXC_GCR->pclk_dis0 &= ~(0x1 << clock); } } /* ************************************************************************** */ @@ -105,38 +155,36 @@ void MXC_SYS_RTCClockEnable() } /* ************************************************************************** */ -int MXC_SYS_RTCClockDisable (void) +int MXC_SYS_RTCClockDisable(void) { /* Check that the RTC is not the system clock source */ if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) != MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) { MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; return E_NO_ERROR; - } - else { + } else { return E_BAD_STATE; } } /******************************************************************************/ -int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock) +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) { switch (clock) { case MXC_SYS_CLOCK_HIRC: MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN; - return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY); + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC_RDY); break; - + case MXC_SYS_CLOCK_HFXIN: MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; - return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY); + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_X32K_RDY); break; - + case MXC_SYS_CLOCK_NANORING: - // MXC_GCR->clk_ctrl |= MXC_F_GCR_CLKCTRL_EXTCLK_EN; - // return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY); - return E_NOT_SUPPORTED; + // 80khz nanoring is always enabled + return E_NO_ERROR; break; - + default: return E_BAD_PARAM; break; @@ -144,146 +192,135 @@ int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock) } /******************************************************************************/ -int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock) +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) { uint32_t current_clock; - + current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; - + // Don't turn off the clock we're running on if (clock == current_clock) { return E_BAD_PARAM; } - + switch (clock) { case MXC_SYS_CLOCK_HIRC: MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC_EN; break; - + case MXC_SYS_CLOCK_HFXIN: MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; break; - + case MXC_SYS_CLOCK_NANORING: - // MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLKCTRL_EXTCLK_EN; + // 80khz nanoring is always enabled return E_BAD_PARAM; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } /* ************************************************************************** */ -int MXC_SYS_Clock_Timeout (uint32_t ready) +int MXC_SYS_Clock_Timeout(uint32_t ready) { // Start timeout, wait for ready - MXC_DelayAsync (MXC_SYS_CLOCK_TIMEOUT, NULL); - + MXC_DelayAsync(MXC_SYS_CLOCK_TIMEOUT, NULL); + do { if (MXC_GCR->clk_ctrl & ready) { MXC_DelayAbort(); return E_NO_ERROR; } - } - while (MXC_DelayCheck() == E_BUSY); - + } while (MXC_DelayCheck() == E_BUSY); + return E_TIME_OUT; } /* ************************************************************************** */ -int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock) +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) { uint32_t current_clock; - + // Save the current system clock current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; - + switch (clock) { case MXC_SYS_CLOCK_HIRC: - + // Enable HIRC clock - if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) { - + if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) { MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN; - + // Check if HIRC clock is ready - if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY) != E_NO_ERROR) { + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC_RDY) != E_NO_ERROR) { return E_TIME_OUT; } } - + // Set HIRC clock as System Clock - MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC); - + MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC); + break; - + case MXC_SYS_CLOCK_HFXIN: - + // Enable HFXtal clock - if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_X32K_EN)) { - MXC_GCR->clk_ctrl |=MXC_F_GCR_CLK_CTRL_X32K_EN; - + if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_X32K_EN)) { + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; + // Check if HFXtal clock is ready - if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY) != E_NO_ERROR) { + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_X32K_RDY) != E_NO_ERROR) { return E_TIME_OUT; } } - + // Set HFXtal clock as System Clock - MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN); - + MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN); + break; - + case MXC_SYS_CLOCK_NANORING: - // Enable HIRC clock - // if(!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLKCTRL_EXTCLK_EN)) { - // MXC_GCR->clk_ctrl |=MXC_F_GCR_CLKCTRL_EXTCLK_EN; - - // // Check if HIRC clock is ready - // if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY) != E_NO_ERROR) { - // return E_TIME_OUT; - // } - // } - - // Set HIRC clock as System Clock - // MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); - MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING); - + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_LIRC8K_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + + MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, + MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING); + break; - + default: return E_BAD_PARAM; } - + // Wait for system clock to be ready - if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) { - + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) { // Restore the old system clock if timeout - MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock); - + MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock); + return E_TIME_OUT; } - + // Update the system core clock SystemCoreClockUpdate(); - + return E_NO_ERROR; } - /* ************************************************************************** */ -void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset) +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) { /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 for the rstr1 register. */ if (reset > 31) { reset -= 32; MXC_GCR->rst1 = (0x1 << reset); - } - else { + while (MXC_GCR->rst1 & (0x1 << reset)) {} + } else { MXC_GCR->rst0 = (0x1 << reset); + while (MXC_GCR->rst0 & (0x1 << reset)) {} } } /**@} end of mxc_sys */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c index d0b6b1e4a06..e886118568d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -39,92 +39,92 @@ /* **** Functions **** */ -void MXC_TMR_Common_Delay(mxc_tmr_regs_t* tmr, unsigned long us) +void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us) { // Return immediately if delay is 0 if (!us) { return; } - + MXC_TMR_TO_Start(tmr, us); - + while (MXC_TMR_TO_Check(tmr) != E_TIME_OUT) {} } -int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t* tmr) +int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr) { if (MXC_TMR_GetFlags(tmr)) { return E_TIME_OUT; } - + return E_NO_ERROR; } -void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t* tmr) +void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr) { MXC_TMR_Stop(tmr); MXC_TMR_SetCount(tmr, 0x0); } -void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t* tmr) +void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr) { MXC_TMR_ClearFlags(tmr); MXC_TMR_SetCount(tmr, 0x0); } -unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr) { uint32_t remaining_ticks, remaining_time; mxc_tmr_unit_t units; - + remaining_ticks = MXC_TMR_GetCompare(tmr) - MXC_TMR_GetCount(tmr); MXC_TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units); - + switch (units) { case TMR_UNIT_NANOSEC: default: return (remaining_time / 1000); - + case TMR_UNIT_MICROSEC: return (remaining_time); - + case TMR_UNIT_MILLISEC: return (remaining_time * 1000); - + case TMR_UNIT_SEC: return (remaining_time * 1000000); } } -void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t* tmr) +void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr) { MXC_TMR_TO_Start(tmr, 0xFFFFFFFF); } -unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr) { unsigned int elapsed = MXC_TMR_TO_Elapsed(tmr); MXC_TMR_TO_Stop(tmr); return elapsed; } -unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t *tmr) { uint32_t elapsed; mxc_tmr_unit_t units; - MXC_TMR_GetTime (tmr, tmr->cnt, &elapsed, &units); - + MXC_TMR_GetTime(tmr, tmr->cnt, &elapsed, &units); + switch (units) { case TMR_UNIT_NANOSEC: default: return (elapsed / 1000); - + case TMR_UNIT_MICROSEC: return (elapsed); - + case TMR_UNIT_MILLISEC: return (elapsed * 1000); - + case TMR_UNIT_SEC: return (elapsed * 1000000); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h index 487716d928a..517e1e22134 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_ /* **** Includes **** */ #include @@ -37,12 +40,14 @@ #include "tmr.h" /* **** Functions **** */ -void MXC_TMR_Common_Delay (mxc_tmr_regs_t *tmr, unsigned long us); -void MXC_TMR_Common_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); -int MXC_TMR_Common_TO_Check (mxc_tmr_regs_t *tmr); -void MXC_TMR_Common_TO_Stop (mxc_tmr_regs_t *tmr); -void MXC_TMR_Common_TO_Clear (mxc_tmr_regs_t *tmr); -unsigned int MXC_TMR_Common_TO_Elapsed (mxc_tmr_regs_t *tmr); -unsigned int MXC_TMR_Common_TO_Remaining (mxc_tmr_regs_t *tmr); -void MXC_TMR_Common_SW_Start (mxc_tmr_regs_t *tmr); -unsigned int MXC_TMR_Common_SW_Stop (mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us); +void MXC_TMR_Common_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us); +int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c index 54a0ecd4768..d11ce346b6c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c @@ -1,10 +1,10 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * @@ -15,7 +15,7 @@ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * @@ -24,61 +24,44 @@ * Products, Inc. Branding Policy. * * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, + * of trade secrets, proprietary technology, copyrights, patents, * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ #include "tmr.h" #include "tmr_reva.h" #include "tmr_common.h" -int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg) +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) { int tmr_id = MXC_TMR_GET_IDX(tmr); MXC_ASSERT(tmr_id >= 0); - - switch(cfg->clock){ - case MXC_TMR_EXT_CLK: - MXC_GPIO_Config(&gpio_cfg_32kcal); - break; - - case MXC_TMR_HFIO_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_HIRC); - break; - - case MXC_TMR_NANORING_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_NANORING); - break; - - default: - return E_BAD_PARAM; - break; - } //enable peripheral clock and configure gpio pins - switch(tmr_id) { + switch (tmr_id) { case 0: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0); - while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0); + while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0) {} MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0); MXC_GPIO_Config(&gpio_cfg_tmr0); break; case 1: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER1); - while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1); + while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1) {} MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1); break; case 2: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER2); - while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2); + while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2) {} MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2); break; } - MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t*) tmr, cfg); + + MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t *)tmr, cfg); return E_NO_ERROR; } @@ -87,11 +70,11 @@ void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr) int tmr_id = MXC_TMR_GET_IDX(tmr); MXC_ASSERT(tmr_id >= 0); - MXC_TMR_RevA_Shutdown((mxc_tmr_reva_regs_t*) tmr); - + MXC_TMR_RevA_Shutdown((mxc_tmr_reva_regs_t *)tmr); + // System settigns //diasble peripheral clock - switch(tmr_id) { + switch (tmr_id) { case 0: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0); break; @@ -106,91 +89,77 @@ void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr) } } -void MXC_TMR_Start(mxc_tmr_regs_t* tmr) +void MXC_TMR_Start(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevA_Start((mxc_tmr_reva_regs_t*) tmr); + MXC_TMR_RevA_Start((mxc_tmr_reva_regs_t *)tmr); } -void MXC_TMR_Stop(mxc_tmr_regs_t* tmr) +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevA_Stop((mxc_tmr_reva_regs_t*) tmr); + MXC_TMR_RevA_Stop((mxc_tmr_reva_regs_t *)tmr); } -int MXC_TMR_SetPWM(mxc_tmr_regs_t* tmr, uint32_t pwm) +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm) { - return MXC_TMR_RevA_SetPWM((mxc_tmr_reva_regs_t*) tmr, pwm); + return MXC_TMR_RevA_SetPWM((mxc_tmr_reva_regs_t *)tmr, pwm); } -uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevA_GetCompare((mxc_tmr_reva_regs_t*) tmr); + return MXC_TMR_RevA_GetCompare((mxc_tmr_reva_regs_t *)tmr); } -uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t*) tmr); + return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t *)tmr); } -uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency) +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, uint32_t prescalar, uint32_t frequency) { - uint32_t retVal, clkFreq; - switch(clock) { - case MXC_TMR_HFIO_CLK: - clkFreq = PeripheralClock; - break; - case MXC_TMR_NANORING_CLK: - clkFreq = 80000; - break; - case MXC_TMR_EXT_CLK: - clkFreq = HFX_FREQ; - break; - default: - clkFreq = PeripheralClock; - break; - } - if(frequency == 0) { + uint32_t retVal; + + if (frequency == 0) { return 0; - } - else { - retVal = clkFreq / (prescalar * frequency); + } else { + retVal = PeripheralClock / (prescalar * frequency); return retVal; } return retVal; } -uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevA_GetCount((mxc_tmr_reva_regs_t*) tmr); + return MXC_TMR_RevA_GetCount((mxc_tmr_reva_regs_t *)tmr); } -void MXC_TMR_ClearFlags(mxc_tmr_regs_t* tmr) +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevA_ClearFlags((mxc_tmr_reva_regs_t*) tmr); + MXC_TMR_RevA_ClearFlags((mxc_tmr_reva_regs_t *)tmr); } -uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevA_GetFlags((mxc_tmr_reva_regs_t*) tmr); + return MXC_TMR_RevA_GetFlags((mxc_tmr_reva_regs_t *)tmr); } void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt) { - MXC_TMR_RevA_SetCompare((mxc_tmr_reva_regs_t*) tmr, cmp_cnt); + MXC_TMR_RevA_SetCompare((mxc_tmr_reva_regs_t *)tmr, cmp_cnt); } void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt) { - MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t*) tmr, cnt); + MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t *)tmr, cnt); } -void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us) +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us) { MXC_TMR_Common_Delay(tmr, us); } -void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us) +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us) { - MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t*) tmr, us); + MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t *)tmr, us); } int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr) @@ -230,5 +199,5 @@ unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr) int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) { - return MXC_TMR_RevA_GetTime((mxc_tmr_reva_regs_t*) tmr, ticks, time, units); + return MXC_TMR_RevA_GetTime((mxc_tmr_reva_regs_t *)tmr, ticks, time, units); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c index 87e71618f1b..5f71de2bb73 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,10 +29,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include +#include #include "mxc_assert.h" #include "tmr.h" #include "tmr_reva.h" @@ -41,72 +42,72 @@ #include "mxc_lock.h" /* **** Functions **** */ -void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg) +void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t *cfg) { // Clear interrupt flag tmr->intr = MXC_F_TMR_REVA_INTR_IRQ; - + // Set the prescaler - switch(cfg->pres) { + switch (cfg->pres) { case TMR_PRES_1: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1); break; - + case TMR_PRES_2: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV2); break; - + case TMR_PRES_4: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4); break; - + case TMR_PRES_8: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8); break; - + case TMR_PRES_16: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16); break; - + case TMR_PRES_32: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32); break; - + case TMR_PRES_64: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV64); break; - + case TMR_PRES_128: tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); break; - + case TMR_PRES_256: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + tmr->cn &= ~(MXC_S_TMR_REVA_CN_PRES_DIV1); break; - + case TMR_PRES_512: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4); break; - + case TMR_PRES_1024: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8); break; - + case TMR_PRES_2048: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16); break; - + case TMR_PRES_4096: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32); break; default: - tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1); break; } @@ -119,186 +120,168 @@ void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg) void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); // Disable timer and clear settings tmr->cn = 0; } -void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr) +void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); tmr->cn |= MXC_F_TMR_REVA_CN_TEN; } -void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr) +void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); tmr->cn &= ~MXC_F_TMR_REVA_CN_TEN; } -int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm) +int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t *tmr, uint32_t pwm) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } - - if(pwm > (tmr->cmp)) { + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); + + if (pwm > (tmr->cmp)) { return E_BAD_PARAM; } - + tmr->pwm = pwm; - + return E_NO_ERROR; } -uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr) +uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); return tmr->cmp; } -uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr) +uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); - return tmr->pwm;//check this + return tmr->pwm; //check this } -uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr) +uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); return tmr->cnt; } -void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr) +void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); tmr->intr = MXC_F_TMR_REVA_INTR_IRQ; } -uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr) +uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); return tmr->intr; } void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); tmr->cmp = cmp_cnt; } void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); - if (tmr_id < 0) { - MXC_ASSERT(0); - } - + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); + MXC_ASSERT(tmr_id >= 0); + tmr->cnt = cnt; } -void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us) +void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, uint32_t us) { uint64_t ticks; int clk_shift = 0; - - ticks = (uint64_t) us * (uint64_t) PeripheralClock / (uint64_t) 1000000; - - while(ticks > 0xFFFFFFFFUL) { + mxc_tmr_cfg_t cfg; + + ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000; + + while (ticks > 0xFFFFFFFFUL) { ticks >>= 1; ++clk_shift; } - - mxc_tmr_pres_t prescale = (mxc_tmr_pres_t) clk_shift << MXC_F_TMR_REVA_CN_PRES_POS; - mxc_tmr_cfg_t cfg = {0, 0, 0, 0}; // = (mxc_tmr_cfg_t) {.pres=0, .mode=0, .cmp_cnt=0, .pol=0}; - + + mxc_tmr_pres_t prescale = (mxc_tmr_pres_t)clk_shift << MXC_F_TMR_REVA_CN_PRES_POS; + + memset(&cfg, 0, sizeof(mxc_tmr_cfg_t)); + // Initialize the timer in one-shot mode cfg.pres = prescale; cfg.mode = TMR_MODE_ONESHOT; cfg.cmp_cnt = ticks; cfg.pol = 0; - - MXC_TMR_Stop((mxc_tmr_regs_t*) tmr); - MXC_TMR_Init((mxc_tmr_regs_t*) tmr, &cfg); - MXC_TMR_ClearFlags((mxc_tmr_regs_t*) tmr); - MXC_TMR_Start((mxc_tmr_regs_t*) tmr); + + MXC_TMR_Stop((mxc_tmr_regs_t *)tmr); + MXC_TMR_Init((mxc_tmr_regs_t *)tmr, &cfg); + MXC_TMR_ClearFlags((mxc_tmr_regs_t *)tmr); + MXC_TMR_Start((mxc_tmr_regs_t *)tmr); } -int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) +int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, + mxc_tmr_unit_t *units) { uint64_t temp_time = 0; uint32_t timerClock = PeripheralClock; - uint32_t prescale = ((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS) - |(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) <<3); - - temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000000); - - if(!(temp_time & 0xffffffff00000000)) { + uint32_t prescale = + ((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS) | + (((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) << 3); + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000); + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_NANOSEC; return E_NO_ERROR; } - - temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000); - - if(!(temp_time & 0xffffffff00000000)) { + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000); + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_MICROSEC; return E_NO_ERROR; } - - temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / timerClock; - - if(!(temp_time & 0xffffffff00000000)) { + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock; + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_MILLISEC; return E_NO_ERROR; } - - temp_time = (uint64_t) ticks * (1 <<(prescale & 0xF)) / timerClock; - - if(!(temp_time & 0xffffffff00000000)) { + + temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock; + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_SEC; return E_NO_ERROR; } - + return E_INVALID; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h index 9b83bc03e62..43fddd31076 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_ /* **** Includes **** */ #include @@ -41,18 +44,20 @@ #include "tmr_reva_regs.h" /* **** Functions **** */ -void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg); +void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t *cfg); void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr); -void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr); -void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr); -int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm); -uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr); -uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr); -uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr); -void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr); -uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr); +void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t *tmr); +void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t *tmr); +int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t *tmr, uint32_t pwm); +uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t *tmr); +uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t *tmr); +uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t *tmr); +void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t *tmr); +uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t *tmr); void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt); void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt); -void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us); -int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); +void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, uint32_t us); +int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, + mxc_tmr_unit_t *units); +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h index 10b768de178..7006c198825 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _TMR_REVA_REGS_H_ #define _TMR_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c index 77b23e70f63..692126bbebb 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,25 +29,25 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "uart_common.h" #include "uart.h" -int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t* uart) +int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart) { // Wait until FIFO has a character ready. - while (MXC_UART_GetRXFIFOAvailable(uart) < 1); - + while (MXC_UART_GetRXFIFOAvailable(uart) < 1) {} + // Read the character using the non-blocking function. return MXC_UART_ReadCharacterRaw(uart); } -int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character) +int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) { // Wait until FIFO has space for the character. - while (MXC_UART_GetTXFIFOAvailable(uart) < 1); - + while (MXC_UART_GetTXFIFOAvailable(uart) < 1) {} + // Write the character using the non-blocking function. return MXC_UART_WriteCharacterRaw(uart, character); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h index dbe87010567..d1e95ec1493 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_ #include "uart_regs.h" -int MXC_UART_Common_ReadCharacter (mxc_uart_regs_t* uart); -int MXC_UART_Common_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character); +int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart); +int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c index 4cf00221e45..e7db0c8f0d5 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "uart.h" #include "mxc_device.h" @@ -39,335 +39,374 @@ #include "uart_common.h" #include "dma.h" -void MXC_UART_DMACallback (int ch, int error) +void MXC_UART_DMACallback(int ch, int error) { - return MXC_UART_RevA_DMACallback (ch, error); + MXC_UART_RevA_DMACallback(ch, error); } -int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal) +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) { - return MXC_UART_RevA_AsyncCallback ((mxc_uart_reva_regs_t*) uart, retVal); + return MXC_UART_RevA_AsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); } -int MXC_UART_AsyncStop (mxc_uart_regs_t* uart) +int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal) { - return MXC_UART_RevA_AsyncStop ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_TxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); } -int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map) +int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevA_RxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); +} + +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_AsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_TxAsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_RxAsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, sys_map_t map) { int retval; - - retval = MXC_UART_Shutdown (uart); - + + retval = MXC_UART_Shutdown(uart); + if (retval) { return retval; } - - switch (MXC_UART_GET_IDX (uart)) { + + switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_GPIO_Config (&gpio_cfg_uart0); - MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_UART0); + MXC_GPIO_Config(&gpio_cfg_uart0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); break; - + case 1: - switch (map) { - case MAP_A: - MXC_GPIO_Config (&gpio_cfg_uart1a); - break; - case MAP_B: - MXC_GPIO_Config (&gpio_cfg_uart1b); - break; - case MAP_C: - MXC_GPIO_Config (&gpio_cfg_uart1c); - break; - } - MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_UART1); + switch (map) { + case MAP_A: + MXC_GPIO_Config(&gpio_cfg_uart1a); + break; + case MAP_B: + MXC_GPIO_Config(&gpio_cfg_uart1b); + break; + case MAP_C: + MXC_GPIO_Config(&gpio_cfg_uart1c); + break; + } + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART1); break; default: return E_BAD_PARAM; break; } - - return MXC_UART_RevA_Init (((mxc_uart_reva_regs_t*) uart), baud); + + return MXC_UART_RevA_Init(((mxc_uart_reva_regs_t *)uart), baud); } -int MXC_UART_Shutdown (mxc_uart_regs_t* uart) +int MXC_UART_Shutdown(mxc_uart_regs_t *uart) { - switch (MXC_UART_GET_IDX (uart)) { + switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_SYS_Reset_Periph (MXC_SYS_RESET0_UART0); - MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_UART0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART0); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); break; - + case 1: - MXC_SYS_Reset_Periph (MXC_SYS_RESET0_UART1); - MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_UART1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART1); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); break; - + default: return E_BAD_PARAM; - break; + break; } - + return E_NO_ERROR; } -int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart) +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ReadyForSleep ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_ReadyForSleep((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud) +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud) { - return MXC_UART_RevA_SetFrequency ((mxc_uart_reva_regs_t*) uart, baud); + return MXC_UART_RevA_SetFrequency((mxc_uart_reva_regs_t *)uart, baud); } -int MXC_UART_GetFrequency (mxc_uart_regs_t* uart) +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetFrequency ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_GetFrequency((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize) +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) { - return MXC_UART_RevA_SetDataSize ((mxc_uart_reva_regs_t*) uart, dataSize); + return MXC_UART_RevA_SetDataSize((mxc_uart_reva_regs_t *)uart, dataSize); } -int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits) +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) { - return MXC_UART_RevA_SetStopBits ((mxc_uart_reva_regs_t*) uart, stopBits); + return MXC_UART_RevA_SetStopBits((mxc_uart_reva_regs_t *)uart, stopBits); } -int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity) +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) { - return MXC_UART_RevA_SetParity ((mxc_uart_reva_regs_t*) uart, parity); + return MXC_UART_RevA_SetParity((mxc_uart_reva_regs_t *)uart, parity); } -int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) { - switch (MXC_UART_GET_IDX (uart)) { + switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_GPIO_Config (&gpio_cfg_uart0_flow); + MXC_GPIO_Config(&gpio_cfg_uart0_flow); break; - + case 1: - MXC_GPIO_Config (&gpio_cfg_uart1_flow); + MXC_GPIO_Config(&gpio_cfg_uart1_flow); break; } - - return MXC_UART_RevA_SetFlowCtrl ((mxc_uart_reva_regs_t*) uart, flowCtrl, rtsThreshold); + + return MXC_UART_RevA_SetFlowCtrl((mxc_uart_reva_regs_t *)uart, flowCtrl, rtsThreshold); } -int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK) +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK) { - return MXC_UART_RevA_SetClockSource ((mxc_uart_reva_regs_t*) uart, usePCLK); + return MXC_UART_RevA_SetClockSource((mxc_uart_reva_regs_t *)uart, usePCLK); } -int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem) +int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem) { - return MXC_UART_RevA_SetNullModem ((mxc_uart_reva_regs_t*) uart, nullModem); + return MXC_UART_RevA_SetNullModem((mxc_uart_reva_regs_t *)uart, nullModem); } -int MXC_UART_SendBreak (mxc_uart_regs_t* uart) +int MXC_UART_SendBreak(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_SendBreak ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_SendBreak((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_GetActive (mxc_uart_regs_t* uart) +int MXC_UART_GetActive(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetActive ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_GetActive((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart) +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_AbortTransmission ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_AbortTransmission((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart) +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ReadCharacterRaw ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_ReadCharacterRaw((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character) +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_RevA_WriteCharacterRaw ((mxc_uart_reva_regs_t*) uart, character); + return MXC_UART_RevA_WriteCharacterRaw((mxc_uart_reva_regs_t *)uart, character); } -int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart) +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) { - return MXC_UART_Common_ReadCharacter (uart); + return MXC_UART_Common_ReadCharacter(uart); } -int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character) +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_Common_WriteCharacter (uart, character); + return MXC_UART_Common_WriteCharacter(uart, character); } -int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len) +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) { - return MXC_UART_RevA_Read ((mxc_uart_reva_regs_t*) uart, buffer, len); + return MXC_UART_RevA_Read((mxc_uart_reva_regs_t *)uart, buffer, len); } -int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len) +int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len) { - return MXC_UART_RevA_Write ((mxc_uart_reva_regs_t*) uart, byte, len); + return MXC_UART_RevA_Write((mxc_uart_reva_regs_t *)uart, byte, len); } -unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len) +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevA_ReadRXFIFO ((mxc_uart_reva_regs_t*) uart, bytes, len); - + return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback) +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; - int uart_num = MXC_UART_GET_IDX (uart); - - // Only UART 0, 1 and 2 are supported for DMA transaction + int uart_num = MXC_UART_GET_IDX(uart); + + // Only UART 0, 1 and 2 are supported for DMA transaction switch (uart_num) { case 0: config.reqsel = MXC_DMA_REQUEST_UART0RX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_UART1RX; break; - + default: return E_BAD_PARAM; break; } - return MXC_UART_RevA_ReadRXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } -unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetRXFIFOAvailable ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_GetRXFIFOAvailable((mxc_uart_reva_regs_t *)uart); } -unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len) +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevA_WriteTXFIFO ((mxc_uart_reva_regs_t*) uart, bytes, len); + return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback) +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; - int uart_num = MXC_UART_GET_IDX (uart); + int uart_num = MXC_UART_GET_IDX(uart); - // Only UART 0, 1 and 2 are supported for DMA transaction + // Only UART 0, 1 and 2 are supported for DMA transaction switch (uart_num) { case 0: config.reqsel = MXC_DMA_REQUEST_UART0TX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_UART1TX; break; - + default: return E_BAD_PARAM; break; } - return MXC_UART_RevA_WriteTXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); +} + +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_GetTXFIFOAvailable((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_ClearRXFIFO((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_ClearTXFIFO((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) +{ + return MXC_UART_RevA_SetRXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); } -unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetTXFIFOAvailable ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_GetRXThreshold((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart) +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return MXC_UART_RevA_ClearRXFIFO ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_SetTXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); } -int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ClearTXFIFO ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_GetTXThreshold((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes) +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_SetRXThreshold ((mxc_uart_reva_regs_t*) uart, numBytes); + return MXC_UART_RevA_GetFlags((mxc_uart_reva_regs_t *)uart); } -unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart) +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) { - return MXC_UART_RevA_GetRXThreshold ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_ClearFlags((mxc_uart_reva_regs_t *)uart, flags); } -int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes) +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevA_SetTXThreshold ((mxc_uart_reva_regs_t*) uart, numBytes); + return MXC_UART_RevA_EnableInt((mxc_uart_reva_regs_t *)uart, mask); } -unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart) +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevA_GetTXThreshold ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_DisableInt((mxc_uart_reva_regs_t *)uart, mask); } -unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetFlags ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_GetStatus((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags) +int MXC_UART_Busy(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ClearFlags ((mxc_uart_reva_regs_t*) uart, flags); + return MXC_UART_RevA_Busy((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask) +int MXC_UART_Transaction(mxc_uart_req_t *req) { - return MXC_UART_RevA_EnableInt ((mxc_uart_reva_regs_t*) uart, mask); + return MXC_UART_RevA_Transaction((mxc_uart_reva_req_t *)req); } -int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask) +int MXC_UART_TransactionAsync(mxc_uart_req_t *req) { - return MXC_UART_RevA_DisableInt ((mxc_uart_reva_regs_t*) uart, mask); + return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req); } -unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart) +int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevA_GetStatus ((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, MXC_DMA); } -int MXC_UART_Busy(mxc_uart_regs_t* uart) +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_Busy((mxc_uart_reva_regs_t*) uart); + return MXC_UART_RevA_AbortAsync((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_Transaction (mxc_uart_req_t* req) +int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_Transaction ((mxc_uart_reva_req_t*) req); + return MXC_UART_RevA_TxAbortAsync((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_TransactionAsync (mxc_uart_req_t* req) +int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_TransactionAsync ((mxc_uart_reva_req_t*) req); + return MXC_UART_RevA_RxAbortAsync((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_TransactionDMA (mxc_uart_req_t* req) +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_TransactionDMA ((mxc_uart_reva_req_t*) req, MXC_DMA); + return MXC_UART_RevA_AsyncHandler((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_AbortAsync (mxc_uart_regs_t* uart) +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) { - return MXC_UART_RevA_AbortAsync ((mxc_uart_reva_regs_t*) uart); + return req->txCnt; } -int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart) +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) { - return MXC_UART_RevA_AsyncHandler ((mxc_uart_reva_regs_t*) uart); + return req->rxCnt; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 79ede5fc845..7f07b08fb66 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include "mxc_device.h" @@ -39,16 +39,17 @@ #include "dma.h" /* **** Definitions **** */ -#define MXC_UART_REVA_ERRINT_EN (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | \ - MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ - MXC_F_UART_REVA_INT_EN_RX_OVERRUN) +#define MXC_UART_REVA_ERRINT_EN \ + (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ + MXC_F_UART_REVA_INT_EN_RX_OVERRUN) -#define MXC_UART_REVA_ERRINT_FL (MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR | \ - MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR | \ - MXC_F_UART_REVA_INT_FL_RX_OVERRUN) +#define MXC_UART_REVA_ERRINT_FL \ + (MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR | MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR | \ + MXC_F_UART_REVA_INT_FL_RX_OVERRUN) /* **** Variable Declaration **** */ -static void* AsyncRequests[MXC_UART_INSTANCES]; +static void *TxAsyncRequests[MXC_UART_INSTANCES]; +static void *RxAsyncRequests[MXC_UART_INSTANCES]; // Structure to save DMA state typedef struct { @@ -64,999 +65,1176 @@ uart_reva_req_state_t states[MXC_UART_INSTANCES]; /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_UART_RevA_Init (mxc_uart_reva_regs_t* uart, unsigned int baud) +int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud) { int err; // Initialize UART // Set RX threshold to 1 byte - if ((err = (MXC_UART_SetRXThreshold ((mxc_uart_regs_t*) uart, 1))) != E_NO_ERROR) { + if ((err = (MXC_UART_SetRXThreshold((mxc_uart_regs_t *)uart, 1))) != E_NO_ERROR) { return err; } // Set TX threshold to 2 byte - if ((err = (MXC_UART_SetTXThreshold ((mxc_uart_regs_t*) uart, 2))) != E_NO_ERROR) { + if ((err = (MXC_UART_SetTXThreshold((mxc_uart_regs_t *)uart, 2))) != E_NO_ERROR) { return err; - } - + } + // Set Datasize to 8 bits - if ((err = (MXC_UART_SetDataSize ((mxc_uart_regs_t*) uart, 8))) != E_NO_ERROR) { + if ((err = (MXC_UART_SetDataSize((mxc_uart_regs_t *)uart, 8))) != E_NO_ERROR) { return err; - } - - if ((err = (MXC_UART_SetParity ((mxc_uart_regs_t*) uart, MXC_UART_PARITY_DISABLE))) != E_NO_ERROR) { + } + + if ((err = (MXC_UART_SetParity((mxc_uart_regs_t *)uart, MXC_UART_PARITY_DISABLE))) != + E_NO_ERROR) { return err; } - - if ((err = (MXC_UART_SetStopBits ((mxc_uart_regs_t*) uart, MXC_UART_STOP_1))) != E_NO_ERROR) { + + if ((err = (MXC_UART_SetStopBits((mxc_uart_regs_t *)uart, MXC_UART_STOP_1))) != E_NO_ERROR) { return err; } - + uart->ctrl |= MXC_F_UART_REVA_CTRL_ENABLE; - - MXC_UART_SetFrequency ((mxc_uart_regs_t*) uart, baud); + + MXC_UART_SetFrequency((mxc_uart_regs_t *)uart, baud); return E_NO_ERROR; } -int MXC_UART_RevA_ReadyForSleep (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_ReadyForSleep(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - - if (AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)] != NULL) { + + if (TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] != NULL) { return E_BUSY; } - - return MXC_UART_GetActive ((mxc_uart_regs_t*) uart); + + /* We can sleep if waiting for RX Async */ + + return MXC_UART_GetActive((mxc_uart_regs_t *)uart); } -int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud) +int MXC_UART_RevA_SetFrequency(mxc_uart_reva_regs_t *uart, unsigned int baud) { float uartDiv; int periphClock; int prescale; int decimalDiv; - - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (uart->ctrl & MXC_F_UART_REVA_CTRL_CLKSEL) { #ifdef IBRO_FREQ periphClock = IBRO_FREQ; #else return E_BAD_PARAM; #endif - } - else { + } else { periphClock = PeripheralClock; } - - uartDiv = (float) periphClock / baud; - + + uartDiv = (float)periphClock / baud; + // Find the largest value of prescale that keeps div > 1 - for (prescale = 8; prescale < 128; prescale = prescale << 1) { - if (uartDiv / (float) prescale < 1) { + for (prescale = 8; prescale <= 128; prescale = prescale << 1) { + if (uartDiv / (float)prescale < 1) { prescale = prescale >> 1; break; } } - + + if (prescale > 128) { + prescale = 128; + } + if (prescale < 8) { return E_BAD_PARAM; } - + uartDiv /= prescale; - decimalDiv = (int)((uartDiv - (int) uartDiv) * 128); - + decimalDiv = (int)((uartDiv - (int)uartDiv) * 128); + // Work around for Jira Bug: ME10-650 if (decimalDiv > 3) { decimalDiv -= 3; - } - else { + } else { decimalDiv += 3; } - + switch (prescale) { case 8: prescale = 4; break; - + case 16: prescale = 3; break; - + case 32: prescale = 2; break; - + case 64: prescale = 1; break; - + case 128: prescale = 0; break; - + default: return E_UNKNOWN; break; } - + prescale <<= MXC_F_UART_REVA_BAUD0_FACTOR_POS; decimalDiv <<= MXC_F_UART_REVA_BAUD1_DBAUD_POS; - - MXC_SETFIELD (uart->baud0, MXC_F_UART_REVA_BAUD0_FACTOR, prescale); - MXC_SETFIELD (uart->baud0, MXC_F_UART_REVA_BAUD0_IBAUD, (((int) uartDiv) << MXC_F_UART_REVA_BAUD0_IBAUD_POS)); - MXC_SETFIELD (uart->baud1, MXC_F_UART_REVA_BAUD1_DBAUD, decimalDiv); - - return MXC_UART_GetFrequency ((mxc_uart_regs_t*) uart); + + MXC_SETFIELD(uart->baud0, MXC_F_UART_REVA_BAUD0_FACTOR, prescale); + MXC_SETFIELD(uart->baud0, MXC_F_UART_REVA_BAUD0_IBAUD, + (((int)uartDiv) << MXC_F_UART_REVA_BAUD0_IBAUD_POS)); + MXC_SETFIELD(uart->baud1, MXC_F_UART_REVA_BAUD1_DBAUD, decimalDiv); + + return MXC_UART_GetFrequency((mxc_uart_regs_t *)uart); } -int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_GetFrequency(mxc_uart_reva_regs_t *uart) { int periphClock = 0; float uartDiv = 0; float decimalDiv = 0; - + if (uart->ctrl & MXC_F_UART_REVA_CTRL_CLKSEL) { #ifdef IBRO_FREQ periphClock = IBRO_FREQ; #else return E_BAD_PARAM; #endif - } - else { + } else { periphClock = PeripheralClock; } - + uartDiv += uart->baud0 & MXC_F_UART_REVA_BAUD0_IBAUD; decimalDiv = uart->baud1 & MXC_F_UART_REVA_BAUD1_DBAUD; // Based on work around for Jira Bug: ME10-650 - // No way to tell if the SetFrequency function added or + // No way to tell if the SetFrequency function added or // subtracted 3 in this range - if(decimalDiv > 3 && decimalDiv <= 6) { - decimalDiv -= 3; - } - else { - decimalDiv += 3; + if (decimalDiv > 3 && decimalDiv <= 6) { + decimalDiv -= 3; + } else { + decimalDiv += 3; } - uartDiv += decimalDiv / (float)128; + uartDiv += decimalDiv / 128.0; uartDiv *= (1 << (7 - (uart->baud0 & MXC_F_UART_REVA_BAUD0_FACTOR))); - return (int) ( (float) periphClock / uartDiv); + return (int)((float)periphClock / uartDiv); } -int MXC_UART_RevA_SetDataSize (mxc_uart_reva_regs_t* uart, int dataSize) +int MXC_UART_RevA_SetDataSize(mxc_uart_reva_regs_t *uart, int dataSize) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (dataSize < 5 || dataSize > 8) { return E_BAD_PARAM; } - + dataSize = (dataSize - 5) << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS; - - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_CHAR_SIZE, dataSize); - + + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_CHAR_SIZE, dataSize); + return E_NO_ERROR; } -int MXC_UART_RevA_SetStopBits (mxc_uart_reva_regs_t* uart, mxc_uart_stop_t stopBits) +int MXC_UART_RevA_SetStopBits(mxc_uart_reva_regs_t *uart, mxc_uart_stop_t stopBits) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + switch (stopBits) { case MXC_UART_STOP_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, 0 << MXC_F_UART_REVA_CTRL_STOPBITS_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, + 0 << MXC_F_UART_REVA_CTRL_STOPBITS_POS); break; - + case MXC_UART_STOP_2: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, 1 << MXC_F_UART_REVA_CTRL_STOPBITS_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, + 1 << MXC_F_UART_REVA_CTRL_STOPBITS_POS); break; - + default: return E_BAD_PARAM; break; } - + return E_NO_ERROR; } -int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parity) +int MXC_UART_RevA_SetParity(mxc_uart_reva_regs_t *uart, mxc_uart_parity_t parity) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + switch (parity) { case MXC_UART_PARITY_DISABLE: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 0 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS ); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 0 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); break; - + case MXC_UART_PARITY_EVEN: case MXC_UART_PARITY_EVEN_0: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_EVEN_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_ODD: case MXC_UART_PARITY_ODD_0: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_ODD_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_MARK: case MXC_UART_PARITY_MARK_0: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_MARK_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_SPACE: case MXC_UART_PARITY_SPACE_0: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + case MXC_UART_PARITY_SPACE_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, + 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); break; - + default: return E_BAD_PARAM; break; } - + return E_NO_ERROR; } -int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +int MXC_UART_RevA_SetFlowCtrl(mxc_uart_reva_regs_t *uart, mxc_uart_flow_t flowCtrl, + int rtsThreshold) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + switch (flowCtrl) { case MXC_UART_FLOW_DIS: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 0 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, + 0 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); break; - + case MXC_UART_FLOW_EN_LOW: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, 0 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, + 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, + 0 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS); break; - + case MXC_UART_FLOW_EN_HIGH: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, 1 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, + 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, + 1 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS); break; - + default: return E_BAD_PARAM; break; } - + if (rtsThreshold < 1 || rtsThreshold > MXC_UART_FIFO_DEPTH) { return E_BAD_PARAM; } - - rtsThreshold <<= MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; - MXC_SETFIELD (uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH, rtsThreshold); - + + rtsThreshold <<= MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH_POS; + MXC_SETFIELD(uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH, rtsThreshold); + return E_NO_ERROR; } -int MXC_UART_RevA_SetClockSource (mxc_uart_reva_regs_t* uart, int usePCLK) +int MXC_UART_RevA_SetClockSource(mxc_uart_reva_regs_t *uart, int usePCLK) { - int baudRate; + int baudRate; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - - baudRate = MXC_UART_GetFrequency ((mxc_uart_regs_t*) uart); - if(baudRate < 0) { // return error code - return baudRate; + + baudRate = MXC_UART_GetFrequency((mxc_uart_regs_t *)uart); + if (baudRate < 0) { // return error code + return baudRate; } if (usePCLK) { - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 0 << MXC_F_UART_REVA_CTRL_CLKSEL_POS); - } - else { - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 1 << MXC_F_UART_REVA_CTRL_CLKSEL_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 0 << MXC_F_UART_REVA_CTRL_CLKSEL_POS); + } else { + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 1 << MXC_F_UART_REVA_CTRL_CLKSEL_POS); } - return MXC_UART_SetFrequency ((mxc_uart_regs_t*) uart, baudRate); + return MXC_UART_SetFrequency((mxc_uart_regs_t *)uart, baudRate); } -int MXC_UART_RevA_SetNullModem (mxc_uart_reva_regs_t* uart, int nullModem) +int MXC_UART_RevA_SetNullModem(mxc_uart_reva_regs_t *uart, int nullModem) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + nullModem = (nullModem > 0) << MXC_F_UART_REVA_CTRL_NULL_MODEM_POS; - - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_NULL_MODEM, nullModem); - + + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_NULL_MODEM, nullModem); + return E_NO_ERROR; } -int MXC_UART_RevA_SendBreak (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_SendBreak(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_BREAK, 1 << MXC_F_UART_REVA_CTRL_BREAK_POS); - + + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_BREAK, 1 << MXC_F_UART_REVA_CTRL_BREAK_POS); + return E_NO_ERROR; } -int MXC_UART_RevA_GetActive (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_GetActive(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (uart->status & (MXC_F_UART_REVA_STATUS_TX_BUSY | MXC_F_UART_REVA_STATUS_RX_BUSY)) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_UART_RevA_AbortTransmission (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_AbortTransmission(mxc_uart_reva_regs_t *uart) { - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*) uart); + MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)uart); return E_NO_ERROR; } -int MXC_UART_RevA_ReadCharacterRaw (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_ReadCharacterRaw(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (uart->status & MXC_F_UART_REVA_STATUS_RX_EMPTY) { return E_UNDERFLOW; } - + return uart->fifo; } -int MXC_UART_RevA_WriteCharacterRaw (mxc_uart_reva_regs_t* uart, uint8_t character) +int MXC_UART_RevA_WriteCharacterRaw(mxc_uart_reva_regs_t *uart, uint8_t character) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + // Return error if the FIFO is full if (uart->status & MXC_F_UART_REVA_STATUS_TX_FULL) { return E_OVERFLOW; } - + uart->fifo = character; - + return E_NO_ERROR; } -int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len) +int MXC_UART_RevA_Read(mxc_uart_reva_regs_t *uart, uint8_t *buffer, int *len) { int read = 0; int retVal; - + for (; read < *len; read++) { - retVal = MXC_UART_ReadCharacter ((mxc_uart_regs_t*) uart); - + retVal = MXC_UART_ReadCharacter((mxc_uart_regs_t *)uart); + if (retVal < 0) { *len = read; return retVal; - } - else { + } else { buffer[read] = retVal; } } - + *len = read; return E_NO_ERROR; } -int MXC_UART_RevA_Write (mxc_uart_reva_regs_t* uart, uint8_t* byte, int* len) +int MXC_UART_RevA_Write(mxc_uart_reva_regs_t *uart, uint8_t *byte, int *len) { int written = 0; int retVal; - + for (; written < *len; written++) { - retVal = MXC_UART_WriteCharacter ((mxc_uart_regs_t*) uart, byte[written]); - + retVal = MXC_UART_WriteCharacter((mxc_uart_regs_t *)uart, byte[written]); + if (retVal != E_NO_ERROR) { *len = written; return retVal; } } - + *len = written; return E_NO_ERROR; } -unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, unsigned int len) +unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes, + unsigned int len) { unsigned int read = 0; - + for (; read < len; read++) { if (uart->status & MXC_F_UART_REVA_STATUS_RX_EMPTY) { break; } - + bytes[read] = uart->fifo; } - + return read; } -int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) +int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; mxc_dma_srcdst_t srcdst; - - int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); - + + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); + if (uart_num < 0) { return E_BAD_PARAM; } - + if (bytes == NULL) { return E_NULL_PTR; } - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 0; config.dstinc_en = 1; - + srcdst.ch = channel; srcdst.dest = bytes; srcdst.len = len; - - + states[uart_num].channelRx = channel; - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_UART_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); uart->dma |= MXC_F_UART_REVA_DMA_RXDMA_EN; - + return E_NO_ERROR; } -unsigned int MXC_UART_RevA_GetRXFIFOAvailable (mxc_uart_reva_regs_t* uart) +unsigned int MXC_UART_RevA_GetRXFIFOAvailable(mxc_uart_reva_regs_t *uart) { - return (uart->status & MXC_F_UART_REVA_STATUS_RX_FIFO_CNT) >> MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS; + return (uart->status & MXC_F_UART_REVA_STATUS_RX_FIFO_CNT) >> + MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS; } -unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, unsigned int len) +unsigned int MXC_UART_RevA_WriteTXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes, + unsigned int len) { unsigned int written = 0; - + for (; written < len; written++) { if (uart->status & MXC_F_UART_REVA_STATUS_TX_FULL) { break; } - + uart->fifo = bytes[written]; } - + return written; } -unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) +unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, + mxc_dma_config_t config) { uint8_t channel; mxc_dma_srcdst_t srcdst; - - int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); - + + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); + if (uart_num < 0) { return E_BAD_PARAM; } - + if (bytes == NULL) { return E_NULL_PTR; } - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; srcdst.source = bytes; srcdst.len = len; - - + states[uart_num].channelTx = channel; - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_UART_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); - + uart->dma |= MXC_F_UART_REVA_DMA_TXDMA_EN; - + return E_NO_ERROR; } -unsigned int MXC_UART_RevA_GetTXFIFOAvailable (mxc_uart_reva_regs_t* uart) +unsigned int MXC_UART_RevA_GetTXFIFOAvailable(mxc_uart_reva_regs_t *uart) { - int txCnt = (uart->status & MXC_F_UART_REVA_STATUS_TX_FIFO_CNT) >> MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS; + int txCnt = (uart->status & MXC_F_UART_REVA_STATUS_TX_FIFO_CNT) >> + MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS; return MXC_UART_FIFO_DEPTH - txCnt; } -int MXC_UART_RevA_ClearRXFIFO (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_ClearRXFIFO(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } uart->ctrl |= MXC_F_UART_REVA_CTRL_RX_FLUSH; - - while (uart->ctrl & MXC_F_UART_REVA_CTRL_RX_FLUSH); + + while (uart->ctrl & MXC_F_UART_REVA_CTRL_RX_FLUSH) {} return E_NO_ERROR; } -int MXC_UART_RevA_ClearTXFIFO (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_ClearTXFIFO(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } uart->ctrl |= MXC_F_UART_REVA_CTRL_TX_FLUSH; - - while (uart->ctrl & MXC_F_UART_REVA_CTRL_TX_FLUSH); + + while (uart->ctrl & MXC_F_UART_REVA_CTRL_TX_FLUSH) {} return E_NO_ERROR; } -int MXC_UART_RevA_SetRXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes) +int MXC_UART_RevA_SetRXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (numBytes < 1 || numBytes > MXC_UART_FIFO_DEPTH) { return E_BAD_PARAM; } - + numBytes <<= MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; - MXC_SETFIELD (uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH, numBytes); - + MXC_SETFIELD(uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH, numBytes); + return E_NO_ERROR; } -unsigned int MXC_UART_RevA_GetRXThreshold (mxc_uart_reva_regs_t* uart) +unsigned int MXC_UART_RevA_GetRXThreshold(mxc_uart_reva_regs_t *uart) { - return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH) >> MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; + return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH) >> + MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; } -int MXC_UART_RevA_SetTXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes) +int MXC_UART_RevA_SetTXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (numBytes < 1 || numBytes > MXC_UART_FIFO_DEPTH) { return E_BAD_PARAM; } - + numBytes <<= MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS; - MXC_SETFIELD (uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH, numBytes); - + MXC_SETFIELD(uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH, numBytes); + return E_NO_ERROR; } -unsigned int MXC_UART_RevA_GetTXThreshold (mxc_uart_reva_regs_t* uart) +unsigned int MXC_UART_RevA_GetTXThreshold(mxc_uart_reva_regs_t *uart) { - return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH) >> MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS; + return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH) >> + MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS; } -unsigned int MXC_UART_RevA_GetFlags (mxc_uart_reva_regs_t* uart) +unsigned int MXC_UART_RevA_GetFlags(mxc_uart_reva_regs_t *uart) { return uart->int_fl; } -int MXC_UART_RevA_ClearFlags (mxc_uart_reva_regs_t* uart, unsigned int flags) +int MXC_UART_RevA_ClearFlags(mxc_uart_reva_regs_t *uart, unsigned int flags) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + uart->int_fl = flags; - + return E_NO_ERROR; } -int MXC_UART_RevA_EnableInt (mxc_uart_reva_regs_t* uart, unsigned int intEn) +int MXC_UART_RevA_EnableInt(mxc_uart_reva_regs_t *uart, unsigned int intEn) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + uart->int_en |= intEn; - + return E_NO_ERROR; } -int MXC_UART_RevA_DisableInt (mxc_uart_reva_regs_t* uart, unsigned int intDis) +int MXC_UART_RevA_DisableInt(mxc_uart_reva_regs_t *uart, unsigned int intDis) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + uart->int_en &= ~intDis; - + return E_NO_ERROR; } -unsigned int MXC_UART_RevA_GetStatus (mxc_uart_reva_regs_t* uart) +unsigned int MXC_UART_RevA_GetStatus(mxc_uart_reva_regs_t *uart) { return uart->status; } -int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t *uart) { - int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t*) uart); // Holds the current index of tx_states + int uart_num = + MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); // Holds the current index of tx_states MXC_ASSERT(uart_num >= 0); - if ((uart->status & MXC_F_UART_REVA_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_REVA_STATUS_RX_BUSY)) { + if ((uart->status & MXC_F_UART_REVA_STATUS_TX_BUSY) || + (uart->status & MXC_F_UART_REVA_STATUS_RX_BUSY)) { return E_BUSY; } // Check to see if there are any ongoing transactions and the UART has room in its FIFO - if ((states[uart_num].req == NULL) && - !(uart->status & MXC_F_UART_REVA_STATUS_TX_FULL)) { - + if ((states[uart_num].req == NULL) && !(uart->status & MXC_F_UART_REVA_STATUS_TX_FULL)) { return E_NO_ERROR; } return E_BUSY; } -int MXC_UART_RevA_Transaction (mxc_uart_reva_req_t* req) +int MXC_UART_RevA_Transaction(mxc_uart_reva_req_t *req) { unsigned int numToWrite, numToRead; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart)) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)) < 0) { return E_BAD_PARAM; } - - MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - - MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart)); - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); - + + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + + MXC_UART_ClearRXFIFO((mxc_uart_regs_t *)(req->uart)); + MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)(req->uart)); + req->txCnt = 0; req->rxCnt = 0; - + if (req->rxLen) { if (req->rxData == NULL) { return E_BAD_PARAM; } } - + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; } - - numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); - + + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], + numToWrite); + while (req->txCnt < req->txLen) { - while ( !(MXC_UART_GetFlags ((mxc_uart_regs_t*)(req->uart)) & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH)); - - numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH); + while (!(MXC_UART_GetFlags((mxc_uart_regs_t *)(req->uart)) & + MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH)) {} + + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : + numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), + &req->txData[req->txCnt], numToWrite); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), + MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH); } } - + if (req->rxLen) { - numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); - + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt], + numToRead); + while (req->rxCnt < req->rxLen) { - while ( !(MXC_UART_GetFlags ((mxc_uart_regs_t*)(req->uart)) & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH)); - - numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); + while (!(MXC_UART_GetFlags((mxc_uart_regs_t *)(req->uart)) & + MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH)) {} + + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), + &req->rxData[req->rxCnt], numToRead); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), + MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); } } - + return E_NO_ERROR; } -int MXC_UART_RevA_TransactionAsync (mxc_uart_reva_req_t* req) +int MXC_UART_RevA_TransactionAsync(mxc_uart_reva_req_t *req) { unsigned int numToWrite, numToRead; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart)) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)) < 0) { return E_BAD_PARAM; } - - MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - - MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart)); - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); - - req->txCnt = 0; - req->rxCnt = 0; - + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; } - - MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH); - numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); + + req->txCnt = 0; + + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH); + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], + numToWrite); + TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req; } - + if (req->rxLen) { - // All error interrupts are related to RX - MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_UART_REVA_ERRINT_EN); - if (req->rxData == NULL) { - MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); return E_BAD_PARAM; } - - MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH); - numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); - } - - AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart))] = (void *) req; + + req->rxCnt = 0; + + // All error interrupts are related to RX + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_UART_REVA_ERRINT_EN); + + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH); + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt], + numToRead); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); + RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req; + } + return E_NO_ERROR; } -int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma) +int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) { - int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart)); - + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + if (uart_num < 0) { return E_BAD_PARAM; } - + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; } } - + if (req->rxLen) { if (req->rxData == NULL) { return E_BAD_PARAM; } } - - MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); - - MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart)); - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); - - (req->uart)->dma |= (1 << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS); // Set RX DMA threshold to 1 byte - (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes - - #if TARGET_NUM == 32665 + + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + + MXC_UART_ClearRXFIFO((mxc_uart_regs_t *)(req->uart)); + MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)(req->uart)); + + (req->uart)->dma |= + (1 << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS); // Set RX DMA threshold to 1 byte + (req->uart)->dma |= + (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes + +#if TARGET_NUM == 32665 MXC_DMA_Init(dma); - #else +#else MXC_DMA_Init(); - #endif - +#endif + //tx - if ( (req->txData != NULL) && (req->txLen)) { - #if TARGET_NUM == 32665 - if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { + if ((req->txData != NULL) && (req->txLen)) { +#if TARGET_NUM == 32665 + if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, + NULL) != E_NO_ERROR) { return E_BAD_PARAM; } - #else - if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*)(req->uart), req->txData, req->txLen, NULL) != E_NO_ERROR) { +#else + if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), req->txData, req->txLen, + NULL) != E_NO_ERROR) { return E_BAD_PARAM; } - #endif +#endif } - - if ( (req->rxData != NULL) && (req->rxLen)) { - #if TARGET_NUM == 32665 - if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { + + if ((req->rxData != NULL) && (req->rxLen)) { +#if TARGET_NUM == 32665 + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, + NULL) != E_NO_ERROR) { return E_BAD_PARAM; } - #else - if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*)(req->uart), req->rxData, req->rxLen, NULL) != E_NO_ERROR) { +#else + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) != + E_NO_ERROR) { return E_BAD_PARAM; } - #endif +#endif } - + return E_NO_ERROR; } -void MXC_UART_RevA_DMACallback (int ch, int error) +void MXC_UART_RevA_DMACallback(int ch, int error) { - mxc_uart_reva_req_t * temp_req; - - for (int i = 0; i < MXC_UART_INSTANCES; i ++) { + mxc_uart_reva_req_t *temp_req; + + for (int i = 0; i < MXC_UART_INSTANCES; i++) { if (states[i].channelTx == ch) { //save the request temp_req = states[i].req; // Callback if not NULL if (temp_req->callback != NULL) { - temp_req->callback((mxc_uart_req_t*)temp_req, E_NO_ERROR); - } + temp_req->callback((mxc_uart_req_t *)temp_req, E_NO_ERROR); + } break; - } - - else if (states[i].channelRx == ch) { + } else if (states[i].channelRx == ch) { //save the request temp_req = states[i].req; // Callback if not NULL if (temp_req->callback != NULL) { - temp_req->callback((mxc_uart_req_t*)temp_req, E_NO_ERROR); - } + temp_req->callback((mxc_uart_req_t *)temp_req, E_NO_ERROR); + } break; } } } -int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal) +int MXC_UART_RevA_RxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal) +{ + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { + return E_BAD_PARAM; + } + + mxc_uart_reva_req_t *req = + (mxc_uart_reva_req_t *)RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)]; + + if (req->callback != NULL) { + req->callback((mxc_uart_req_t *)req, retVal); + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_TxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - mxc_uart_reva_req_t* req = (mxc_uart_reva_req_t*) AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)]; - + mxc_uart_reva_req_t *req = + (mxc_uart_reva_req_t *)TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)]; + if (req->callback != NULL) { - req->callback ((mxc_uart_req_t*) req, retVal); + req->callback((mxc_uart_req_t *)req, retVal); + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AsyncCallback(mxc_uart_reva_regs_t *uart, int retVal) +{ + int retvalTx, retvalRx; + bool reqMatch; + + // If the requests are identical, only call one callback + if (TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] == + RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)]) { + reqMatch = TRUE; + } else { + reqMatch = FALSE; + } + + retvalTx = MXC_UART_RevA_TxAsyncCallback(uart, retVal); + + if (!reqMatch) { + retvalRx = MXC_UART_RevA_RxAsyncCallback(uart, retVal); + } else { + retvalRx = E_NO_ERROR; + } + + if (retvalTx != E_NO_ERROR) { + return retvalTx; + } + + if (retvalRx != E_NO_ERROR) { + return retvalRx; } - + return E_NO_ERROR; } -int MXC_UART_RevA_AsyncStop (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_TxAsyncStop(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - MXC_UART_DisableInt ((mxc_uart_regs_t*) uart, 0xFFFFFFFF); - AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)] = NULL; + MXC_UART_DisableInt((mxc_uart_regs_t *)uart, MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH); + TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] = NULL; return E_NO_ERROR; } -int MXC_UART_RevA_AbortAsync (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_RxAsyncStop(mxc_uart_reva_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_ABORT); - MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart); + MXC_UART_DisableInt((mxc_uart_regs_t *)uart, + (MXC_UART_REVA_ERRINT_EN | MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH)); + RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] = NULL; + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AsyncStop(mxc_uart_reva_regs_t *uart) +{ + int uartNum; + + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { + return E_BAD_PARAM; + } + + uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); + + mxc_uart_reva_req_t *req = (mxc_uart_reva_req_t *)TxAsyncRequests[uartNum]; + + if (req != NULL) { + MXC_UART_TxAsyncStop((mxc_uart_regs_t *)uart); + } + + req = (mxc_uart_reva_req_t *)RxAsyncRequests[uartNum]; + + if (req != NULL) { + MXC_UART_RxAsyncStop((mxc_uart_regs_t *)uart); + } return E_NO_ERROR; } -int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart) +int MXC_UART_RevA_TxAbortAsync(mxc_uart_reva_regs_t *uart) { - int uartNum = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); + int uartNum; + + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { + return E_BAD_PARAM; + } + + uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); + + mxc_uart_reva_req_t *req = (mxc_uart_reva_req_t *)TxAsyncRequests[uartNum]; + + if (req != NULL) { + MXC_UART_TxAsyncCallback((mxc_uart_regs_t *)uart, E_ABORT); + MXC_UART_TxAsyncStop((mxc_uart_regs_t *)uart); + } + + return E_NO_ERROR; +} +int MXC_UART_RevA_RxAbortAsync(mxc_uart_reva_regs_t *uart) +{ + int uartNum; + + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { + return E_BAD_PARAM; + } + + uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); + + mxc_uart_reva_req_t *req = (mxc_uart_reva_req_t *)RxAsyncRequests[uartNum]; + + if (req != NULL) { + MXC_UART_RxAsyncCallback((mxc_uart_regs_t *)uart, E_ABORT); + MXC_UART_RxAsyncStop((mxc_uart_regs_t *)uart); + } + + return E_NO_ERROR; +} +int MXC_UART_RevA_AbortAsync(mxc_uart_reva_regs_t *uart) +{ + int retvalTx, retvalRx; + + retvalTx = MXC_UART_RevA_TxAbortAsync(uart); + + retvalRx = MXC_UART_RevA_RxAbortAsync(uart); + + if (retvalTx != E_NO_ERROR) { + return retvalTx; + } + + if (retvalRx != E_NO_ERROR) { + return retvalRx; + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AsyncHandler(mxc_uart_reva_regs_t *uart) +{ + int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); unsigned int flags, numToWrite, numToRead; - mxc_uart_reva_req_t* req; - - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + mxc_uart_reva_req_t *req; + + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - - req = (mxc_uart_reva_req_t*) AsyncRequests[uartNum]; - - flags = MXC_UART_GetFlags ((mxc_uart_regs_t*) uart); - + + flags = MXC_UART_GetFlags((mxc_uart_regs_t *)uart); + if (flags & MXC_UART_REVA_ERRINT_FL & uart->int_en) { - MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_COMM_ERR); - MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart); + MXC_UART_AsyncCallback((mxc_uart_regs_t *)uart, E_COMM_ERR); + MXC_UART_AsyncStop((mxc_uart_regs_t *)uart); return E_INVALID; } - - if ( (flags & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH) && (req->txLen)) { - numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH); - } - - if ( (flags & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH) && (req->rxLen)) { - numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); - numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); - - if ( (req->rxLen - req->rxCnt) < MXC_UART_GetRXThreshold ((mxc_uart_regs_t*)(req->uart))) { - MXC_UART_SetRXThreshold ((mxc_uart_regs_t*)(req->uart), req->rxLen - req->rxCnt); + + req = (mxc_uart_reva_req_t *)TxAsyncRequests[uartNum]; + + if ((flags & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH) && (req != NULL) && (req->txLen)) { + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], + numToWrite); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH); + } + + if (req->txCnt == req->txLen) { + MXC_UART_TxAsyncCallback((mxc_uart_regs_t *)uart, E_NO_ERROR); + MXC_UART_TxAsyncStop((mxc_uart_regs_t *)uart); + } + + req = (mxc_uart_reva_req_t *)RxAsyncRequests[uartNum]; + + if ((flags & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH) && (req != NULL) && (req->rxLen)) { + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt], + numToRead); + + if ((req->rxLen - req->rxCnt) < MXC_UART_GetRXThreshold((mxc_uart_regs_t *)(req->uart))) { + MXC_UART_SetRXThreshold((mxc_uart_regs_t *)(req->uart), req->rxLen - req->rxCnt); } - - MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); + + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); } - - if ( (req->rxCnt == req->rxLen) && (req->txCnt == req->txLen)) { - MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_NO_ERROR); - MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart); + + if (req->rxCnt == req->rxLen) { + MXC_UART_RxAsyncCallback((mxc_uart_regs_t *)uart, E_NO_ERROR); + MXC_UART_RxAsyncStop((mxc_uart_regs_t *)uart); } - + return E_NO_ERROR; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h index f563d36492a..bba25f14aed 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_ #include "mxc_device.h" #include "mxc_assert.h" @@ -40,61 +43,73 @@ typedef struct _mxc_uart_reva_req_t mxc_uart_reva_req_t; struct _mxc_uart_reva_req_t { - mxc_uart_reva_regs_t* uart; - uint8_t *txData; - uint8_t *rxData; - uint32_t txLen; - uint32_t rxLen; - uint32_t txCnt; - uint32_t rxCnt; + mxc_uart_reva_regs_t *uart; + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; + uint32_t rxLen; + uint32_t txCnt; + uint32_t rxCnt; mxc_uart_complete_cb_t callback; }; -int MXC_UART_RevA_Init (mxc_uart_reva_regs_t* uart, unsigned int baud); -int MXC_UART_RevA_Shutdown (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_ReadyForSleep (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud); -int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_SetDataSize (mxc_uart_reva_regs_t* uart, int dataSize); -int MXC_UART_RevA_SetStopBits (mxc_uart_reva_regs_t* uart, mxc_uart_stop_t stopBits); -int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parity); -int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); -int MXC_UART_RevA_SetClockSource (mxc_uart_reva_regs_t* uart, int usePCLK); -int MXC_UART_RevA_SetNullModem (mxc_uart_reva_regs_t* uart, int nullModem); -int MXC_UART_RevA_SendBreak (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_GetActive (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_AbortTransmission (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_ReadCharacterRaw (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_WriteCharacterRaw (mxc_uart_reva_regs_t* uart, uint8_t character); -int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len); -int MXC_UART_RevA_Write (mxc_uart_reva_regs_t* uart, uint8_t* byte, int* len); -unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, +int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud); +int MXC_UART_RevA_Shutdown(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_ReadyForSleep(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_SetFrequency(mxc_uart_reva_regs_t *uart, unsigned int baud); +int MXC_UART_RevA_GetFrequency(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_SetDataSize(mxc_uart_reva_regs_t *uart, int dataSize); +int MXC_UART_RevA_SetStopBits(mxc_uart_reva_regs_t *uart, mxc_uart_stop_t stopBits); +int MXC_UART_RevA_SetParity(mxc_uart_reva_regs_t *uart, mxc_uart_parity_t parity); +int MXC_UART_RevA_SetFlowCtrl(mxc_uart_reva_regs_t *uart, mxc_uart_flow_t flowCtrl, + int rtsThreshold); +int MXC_UART_RevA_SetClockSource(mxc_uart_reva_regs_t *uart, int usePCLK); +int MXC_UART_RevA_SetNullModem(mxc_uart_reva_regs_t *uart, int nullModem); +int MXC_UART_RevA_SendBreak(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_GetActive(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_AbortTransmission(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_ReadCharacterRaw(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_WriteCharacterRaw(mxc_uart_reva_regs_t *uart, uint8_t character); +int MXC_UART_RevA_Read(mxc_uart_reva_regs_t *uart, uint8_t *buffer, int *len); +int MXC_UART_RevA_Write(mxc_uart_reva_regs_t *uart, uint8_t *byte, int *len); +unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes, + unsigned int len); +int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); +unsigned int MXC_UART_RevA_GetRXFIFOAvailable(mxc_uart_reva_regs_t *uart); +unsigned int MXC_UART_RevA_WriteTXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes, unsigned int len); -int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); -unsigned int MXC_UART_RevA_GetRXFIFOAvailable (mxc_uart_reva_regs_t* uart); -unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, - unsigned int len); -unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); -unsigned int MXC_UART_RevA_GetTXFIFOAvailable (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_ClearRXFIFO (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_ClearTXFIFO (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_SetRXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes); -unsigned int MXC_UART_RevA_GetRXThreshold (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_SetTXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes); -unsigned int MXC_UART_RevA_GetTXThreshold (mxc_uart_reva_regs_t* uart); -unsigned int MXC_UART_RevA_GetFlags (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_ClearFlags (mxc_uart_reva_regs_t* uart, unsigned int flags); -int MXC_UART_RevA_EnableInt (mxc_uart_reva_regs_t* uart, unsigned int mask); -int MXC_UART_RevA_DisableInt (mxc_uart_reva_regs_t* uart, unsigned int mask); -unsigned int MXC_UART_RevA_GetStatus (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_Transaction (mxc_uart_reva_req_t* req); -int MXC_UART_RevA_TransactionAsync (mxc_uart_reva_req_t* req); -int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma); -int MXC_UART_RevA_AbortAsync (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_AsyncStop (mxc_uart_reva_regs_t* uart); -int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal); -void MXC_UART_RevA_DMACallback (int ch, int error); +unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, + mxc_dma_config_t config); +unsigned int MXC_UART_RevA_GetTXFIFOAvailable(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_ClearRXFIFO(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_ClearTXFIFO(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_SetRXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes); +unsigned int MXC_UART_RevA_GetRXThreshold(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_SetTXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes); +unsigned int MXC_UART_RevA_GetTXThreshold(mxc_uart_reva_regs_t *uart); +unsigned int MXC_UART_RevA_GetFlags(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_ClearFlags(mxc_uart_reva_regs_t *uart, unsigned int flags); +int MXC_UART_RevA_EnableInt(mxc_uart_reva_regs_t *uart, unsigned int mask); +int MXC_UART_RevA_DisableInt(mxc_uart_reva_regs_t *uart, unsigned int mask); +unsigned int MXC_UART_RevA_GetStatus(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_Transaction(mxc_uart_reva_req_t *req); +int MXC_UART_RevA_TransactionAsync(mxc_uart_reva_req_t *req); +int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma); +int MXC_UART_RevA_TxAbortAsync(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_RxAbortAsync(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_AbortAsync(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_AsyncHandler(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_TxAsyncStop(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_RxAsyncStop(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_AsyncStop(mxc_uart_reva_regs_t *uart); +int MXC_UART_RevA_AsyncCallback(mxc_uart_reva_regs_t *uart, int retVal); +int MXC_UART_RevA_TxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal); +int MXC_UART_RevA_RxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal); +void MXC_UART_RevA_DMACallback(int ch, int error); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h index bc1acb7f532..c210967610d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _UART_REVA_REGS_H_ #define _UART_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c index 2b6f245b588..982fbbd12cc 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c index 15a05eca5f3..2d98ef2af9a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -42,90 +42,88 @@ /* **** Functions **** */ -int MXC_WDT_Init (mxc_wdt_regs_t* wdt) +int MXC_WDT_Init(mxc_wdt_regs_t *wdt) { if (wdt == MXC_WDT0) { return E_NO_ERROR; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } -int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt) +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) { if (wdt == MXC_WDT0) { return E_NO_ERROR; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } -void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period) +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period) { - MXC_WDT_RevA_SetIntPeriod ((mxc_wdt_reva_regs_t*) wdt,period); + MXC_WDT_RevA_SetIntPeriod((mxc_wdt_reva_regs_t *)wdt, period); } -void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period) +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period) { - MXC_WDT_RevA_SetResetPeriod ((mxc_wdt_reva_regs_t*) wdt,period); + MXC_WDT_RevA_SetResetPeriod((mxc_wdt_reva_regs_t *)wdt, period); } -void MXC_WDT_Enable (mxc_wdt_regs_t* wdt) +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_Enable ((mxc_wdt_reva_regs_t*) wdt); + MXC_WDT_RevA_Enable((mxc_wdt_reva_regs_t *)wdt); } -void MXC_WDT_Disable (mxc_wdt_regs_t* wdt) +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_Disable ((mxc_wdt_reva_regs_t*) wdt); + MXC_WDT_RevA_Disable((mxc_wdt_reva_regs_t *)wdt); } -void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt) +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_EnableInt ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_ENABLE); + MXC_WDT_RevA_EnableInt((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_ENABLE); } -void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt) +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_EnableReset ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_ENABLE); + MXC_WDT_RevA_EnableReset((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_ENABLE); } -void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt) +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_EnableInt ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_DISABLE); + MXC_WDT_RevA_EnableInt((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_DISABLE); } -void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt) +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_EnableReset ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_DISABLE); + MXC_WDT_RevA_EnableReset((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_DISABLE); } -void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt) +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_ResetTimer ((mxc_wdt_reva_regs_t*) wdt); + MXC_WDT_RevA_ResetTimer((mxc_wdt_reva_regs_t *)wdt); } -int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt) +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt) { - return MXC_WDT_RevA_GetResetFlag ((mxc_wdt_reva_regs_t*) wdt); + return MXC_WDT_RevA_GetResetFlag((mxc_wdt_reva_regs_t *)wdt); } -void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt) +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_ClearResetFlag ((mxc_wdt_reva_regs_t*) wdt); + MXC_WDT_RevA_ClearResetFlag((mxc_wdt_reva_regs_t *)wdt); } -int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt) +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt) { - return MXC_WDT_RevA_GetIntFlag ((mxc_wdt_reva_regs_t*) wdt); + return MXC_WDT_RevA_GetIntFlag((mxc_wdt_reva_regs_t *)wdt); } -void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt) +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevA_ClearIntFlag ((mxc_wdt_reva_regs_t*) wdt); + MXC_WDT_RevA_ClearIntFlag((mxc_wdt_reva_regs_t *)wdt); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c index 7a623e768d8..40893d084f9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -41,69 +41,68 @@ /* **** Functions **** */ -void MXC_WDT_RevA_SetIntPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period) +void MXC_WDT_RevA_SetIntPeriod(mxc_wdt_reva_regs_t *wdt, mxc_wdt_period_t period) { MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_INT_PERIOD, period); } -void MXC_WDT_RevA_SetResetPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period) +void MXC_WDT_RevA_SetResetPeriod(mxc_wdt_reva_regs_t *wdt, mxc_wdt_period_t period) { - MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_RST_PERIOD, (period << (MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS - MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS))); + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_RST_PERIOD, + (period + << (MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS - MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS))); } -void MXC_WDT_RevA_Enable(mxc_wdt_reva_regs_t* wdt) +void MXC_WDT_RevA_Enable(mxc_wdt_reva_regs_t *wdt) { wdt->ctrl |= MXC_F_WDT_REVA_CTRL_WDT_EN; } -void MXC_WDT_RevA_Disable(mxc_wdt_reva_regs_t* wdt) +void MXC_WDT_RevA_Disable(mxc_wdt_reva_regs_t *wdt) { wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_WDT_EN); - } -void MXC_WDT_RevA_EnableInt(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable) +void MXC_WDT_RevA_EnableInt(mxc_wdt_reva_regs_t *wdt, mxc_wdt_reva_en_t enable) { - if(enable) { + if (enable) { wdt->ctrl |= MXC_F_WDT_REVA_CTRL_INT_EN; - } - else { + } else { wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_INT_EN); } } -void MXC_WDT_RevA_EnableReset(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable) +void MXC_WDT_RevA_EnableReset(mxc_wdt_reva_regs_t *wdt, mxc_wdt_reva_en_t enable) { - if(enable) { + if (enable) { wdt->ctrl |= MXC_F_WDT_REVA_CTRL_RST_EN; - } - else { + } else { wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_RST_EN); } } -void MXC_WDT_RevA_ResetTimer(mxc_wdt_reva_regs_t* wdt) +void MXC_WDT_RevA_ResetTimer(mxc_wdt_reva_regs_t *wdt) { wdt->rst = 0x00A5; wdt->rst = 0x005A; } -int MXC_WDT_RevA_GetResetFlag(mxc_wdt_reva_regs_t* wdt) +int MXC_WDT_RevA_GetResetFlag(mxc_wdt_reva_regs_t *wdt) { return !!(wdt->ctrl & MXC_F_WDT_REVA_CTRL_RST_FLAG); } -void MXC_WDT_RevA_ClearResetFlag(mxc_wdt_reva_regs_t* wdt) +void MXC_WDT_RevA_ClearResetFlag(mxc_wdt_reva_regs_t *wdt) { wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_RST_FLAG); } -int MXC_WDT_RevA_GetIntFlag(mxc_wdt_reva_regs_t* wdt) +int MXC_WDT_RevA_GetIntFlag(mxc_wdt_reva_regs_t *wdt) { return !!(wdt->ctrl & MXC_F_WDT_REVA_CTRL_INT_FLAG); } -void MXC_WDT_RevA_ClearIntFlag(mxc_wdt_reva_regs_t* wdt) +void MXC_WDT_RevA_ClearIntFlag(mxc_wdt_reva_regs_t *wdt) { wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_INT_FLAG); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h index 6185d35a4ce..ef68cb1a812 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software");, + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_WDT_WDT_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_WDT_WDT_REVA_H_ /* **** Includes **** */ #include "mxc_device.h" @@ -46,14 +49,16 @@ typedef enum { } mxc_wdt_reva_en_t; /* **** Functions **** */ -void MXC_WDT_RevA_SetIntPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period); -void MXC_WDT_RevA_SetResetPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period); -void MXC_WDT_RevA_Enable(mxc_wdt_reva_regs_t* wdt); -void MXC_WDT_RevA_Disable(mxc_wdt_reva_regs_t* wdt); -void MXC_WDT_RevA_EnableInt(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable); -void MXC_WDT_RevA_EnableReset(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable); -void MXC_WDT_RevA_ResetTimer(mxc_wdt_reva_regs_t* wdt); -int MXC_WDT_RevA_GetResetFlag(mxc_wdt_reva_regs_t* wdt); -void MXC_WDT_RevA_ClearResetFlag(mxc_wdt_reva_regs_t* wdt); -int MXC_WDT_RevA_GetIntFlag(mxc_wdt_reva_regs_t* wdt); -void MXC_WDT_RevA_ClearIntFlag(mxc_wdt_reva_regs_t* wdt); +void MXC_WDT_RevA_SetIntPeriod(mxc_wdt_reva_regs_t *wdt, mxc_wdt_period_t period); +void MXC_WDT_RevA_SetResetPeriod(mxc_wdt_reva_regs_t *wdt, mxc_wdt_period_t period); +void MXC_WDT_RevA_Enable(mxc_wdt_reva_regs_t *wdt); +void MXC_WDT_RevA_Disable(mxc_wdt_reva_regs_t *wdt); +void MXC_WDT_RevA_EnableInt(mxc_wdt_reva_regs_t *wdt, mxc_wdt_reva_en_t enable); +void MXC_WDT_RevA_EnableReset(mxc_wdt_reva_regs_t *wdt, mxc_wdt_reva_en_t enable); +void MXC_WDT_RevA_ResetTimer(mxc_wdt_reva_regs_t *wdt); +int MXC_WDT_RevA_GetResetFlag(mxc_wdt_reva_regs_t *wdt); +void MXC_WDT_RevA_ClearResetFlag(mxc_wdt_reva_regs_t *wdt); +int MXC_WDT_RevA_GetIntFlag(mxc_wdt_reva_regs_t *wdt); +void MXC_WDT_RevA_ClearIntFlag(mxc_wdt_reva_regs_t *wdt); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_WDT_WDT_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h index eba132af176..b80806513b5 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _WDT_REVA_REGS_H_ #define _WDT_REVA_REGS_H_ From bb0eba5794de7ea905fae37de6845ed435dea104 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Mon, 15 May 2023 13:25:23 +0300 Subject: [PATCH 03/16] Apply MAX32660 delta Update mbed hal function as per of SDK update Signed-off-by: Sadik.Ozer --- .../Device/Maxim/MAX32660/Include/dma_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/fcr_regs.h | 4 +- .../Device/Maxim/MAX32660/Include/flc_regs.h | 8 +-- .../Device/Maxim/MAX32660/Include/gcr_regs.h | 8 +-- .../Device/Maxim/MAX32660/Include/gpio_regs.h | 13 ++-- .../Device/Maxim/MAX32660/Include/i2c_regs.h | 4 +- .../Device/Maxim/MAX32660/Include/icc_regs.h | 8 +-- .../Maxim/MAX32660/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/spi_regs.h | 6 +- .../Maxim/MAX32660/Include/spimss_regs.h | 8 +-- .../Device/Maxim/MAX32660/Include/tmr_regs.h | 4 +- .../Device/Maxim/MAX32660/Include/uart_regs.h | 4 +- .../Device/Maxim/MAX32660/Include/wdt_regs.h | 4 +- .../Maxim/MAX32660/Source/system_max32660.c | 53 +++++--------- .../PeriphDrivers/Include/MAX32660/lp.h | 12 ++-- .../Include/MAX32660/mxc_device.h | 2 + .../PeriphDrivers/Include/MAX32660/mxc_lock.h | 12 ++++ .../PeriphDrivers/Include/MAX32660/mxc_pins.h | 3 + .../PeriphDrivers/Include/MAX32660/mxc_spi.h | 6 +- .../PeriphDrivers/Include/MAX32660/mxc_sys.h | 2 +- .../PeriphDrivers/Include/MAX32660/spimss.h | 15 +++- .../PeriphDrivers/Include/MAX32660/tmr.h | 13 ++++ .../PeriphDrivers/Source/FLC/flc_me11.c | 6 +- .../PeriphDrivers/Source/I2C/i2c_me11.c | 2 +- .../PeriphDrivers/Source/I2C/i2c_reva.c | 2 +- .../PeriphDrivers/Source/LP/lp_me11.c | 17 ++--- .../PeriphDrivers/Source/SPI/spi_me11.c | 4 +- .../PeriphDrivers/Source/SPI/spi_reva.c | 61 +++++++++------- .../PeriphDrivers/Source/SPI/spi_reva.h | 4 +- .../PeriphDrivers/Source/SPIMSS/spimss_me11.c | 11 ++- .../PeriphDrivers/Source/SPIMSS/spimss_reva.c | 69 +++++++++++++------ .../PeriphDrivers/Source/SPIMSS/spimss_reva.h | 3 +- .../PeriphDrivers/Source/SYS/mxc_lock.c | 4 ++ .../PeriphDrivers/Source/SYS/pins_me11.c | 21 +++--- .../PeriphDrivers/Source/UART/uart_reva.c | 2 +- .../TARGET_Maxim/TARGET_MAX32660/lp_ticker.c | 4 +- .../TARGET_Maxim/TARGET_MAX32660/us_ticker.c | 4 +- 37 files changed, 231 insertions(+), 184 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h index 8f4eee91655..2b5d236eeb9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -99,7 +97,7 @@ typedef struct { typedef struct { __IO uint32_t int_en; /**< \b 0x000: DMA INT_EN Register */ __I uint32_t int_fl; /**< \b 0x004: DMA INT_FL Register */ - __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t rsv_0x8_0xff[62]; __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h index ff3389c449b..fdfb8cc2378 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h index 18d474a7434..931fff37a77 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -89,9 +87,9 @@ typedef struct { __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ - __R uint32_t rsv_0xc_0x23[6]; + __I uint32_t rsv_0xc_0x23[6]; __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ - __R uint32_t rsv_0x28_0x2f[2]; + __I uint32_t rsv_0x28_0x2f[2]; __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ } mxc_flc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h index d21a6d77a80..2dc5b6ba511 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -90,11 +88,11 @@ typedef struct { __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ __IO uint32_t clk_ctrl; /**< \b 0x08: GCR CLK_CTRL Register */ __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ - __R uint32_t rsv_0x10_0x23[5]; + __I uint32_t rsv_0x10_0x23[5]; __IO uint32_t pclk_dis0; /**< \b 0x24: GCR PCLK_DIS0 Register */ __IO uint32_t mem_ctrl; /**< \b 0x28: GCR MEM_CTRL Register */ __IO uint32_t mem_zctrl; /**< \b 0x2C: GCR MEM_ZCTRL Register */ - __R uint32_t rsv_0x30_0x3f[4]; + __I uint32_t rsv_0x30_0x3f[4]; __IO uint32_t sys_stat; /**< \b 0x40: GCR SYS_STAT Register */ __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ __IO uint32_t pclk_dis1; /**< \b 0x48: GCR PCLK_DIS1 Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h index f791e4cfd43..96613b6313a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -102,13 +99,13 @@ typedef struct { __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ - __I uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ - __R uint32_t rsv_0x44; + __IO uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ + __I uint32_t rsv_0x44; __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ - __R uint32_t rsv_0x58; + __I uint32_t rsv_0x58; __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ __IO uint32_t pad_cfg1; /**< \b 0x60: GPIO PAD_CFG1 Register */ __IO uint32_t pad_cfg2; /**< \b 0x64: GPIO PAD_CFG2 Register */ @@ -118,13 +115,13 @@ typedef struct { __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ - __R uint32_t rsv_0x80_0xa7[10]; + __I uint32_t rsv_0x80_0xa7[10]; __IO uint32_t is; /**< \b 0xA8: GPIO IS Register */ __IO uint32_t sr; /**< \b 0xAC: GPIO SR Register */ __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ - __R uint32_t rsv_0xbc; + __I uint32_t rsv_0xbc; __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ } mxc_gpio_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h index d370b74064d..d713e4d4e5c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h index 3ef38ffa969..2dc1b58136e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -88,9 +86,9 @@ extern "C" { typedef struct { __I uint32_t cache_id; /**< \b 0x0000: ICC CACHE_ID Register */ __I uint32_t mem_size; /**< \b 0x0004: ICC MEM_SIZE Register */ - __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t rsv_0x8_0xff[62]; __IO uint32_t cache_ctrl; /**< \b 0x0100: ICC CACHE_CTRL Register */ - __R uint32_t rsv_0x104_0x6ff[383]; + __I uint32_t rsv_0x104_0x6ff[383]; __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ } mxc_icc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h index 95dbebaa069..3d9ca43447e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -89,7 +87,7 @@ typedef struct { __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ - __R uint32_t rsv_0xc_0x3f[13]; + __I uint32_t rsv_0xc_0x3f[13]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ } mxc_pwrseq_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h index 35f8aec9842..759cbe94450 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -92,7 +90,7 @@ typedef struct { __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ __IO uint32_t ss_time; /**< \b 0x10: SPI SS_TIME Register */ __IO uint32_t clk_cfg; /**< \b 0x14: SPI CLK_CFG Register */ - __R uint32_t rsv_0x18; + __I uint32_t rsv_0x18; __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ __IO uint32_t int_fl; /**< \b 0x20: SPI INT_FL Register */ __IO uint32_t int_en; /**< \b 0x24: SPI INT_EN Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h index d5638e3e6ed..53e7b1fd3b2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -87,11 +85,11 @@ extern "C" { */ typedef struct { __IO uint16_t data; /**< \b 0x00: SPIMSS DATA Register */ - __R uint16_t rsv_0x2; + __I uint16_t rsv_0x2; __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ __IO uint32_t int_fl; /**< \b 0x08: SPIMSS INT_FL Register */ __IO uint32_t mode; /**< \b 0x0C: SPIMSS MODE Register */ - __R uint32_t rsv_0x10; + __I uint32_t rsv_0x10; __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h index b1073ea226b..bca94126c7a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h index 6eeec71d086..cad0f3409b3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h index 67f72795be2..d1f414711a2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index 3565907b90f..e4db445ea6d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -46,7 +46,6 @@ #include "wdt_regs.h" #include "mxc_sys.h" -extern void (*const __isr_vector[])(void); uint32_t SystemCoreClock = HIRC96_FREQ; __weak void SystemCoreClockUpdate(void) @@ -76,7 +75,7 @@ __weak void SystemCoreClockUpdate(void) } // Get the clock divider - div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; + div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS; SystemCoreClock = base_freq >> div; } @@ -91,7 +90,12 @@ __weak void SystemCoreClockUpdate(void) */ __weak int PreInit(void) { - /* Do nothing */ + /* Switch system clock to HIRC, 96 MHz*/ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); + + /* Enable cache here to reduce boot time */ + MXC_ICC_Enable(); + return 0; } @@ -102,6 +106,12 @@ __weak int Board_Init(void) return 0; } +/* Override this function for early platform initialization */ +__weak void low_level_init(void) +{ + /* Do nothing */ +} + /* This function is called just before control is transferred to main(). * * You may over-ride this function in your program by defining a custom @@ -110,23 +120,16 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { - /* Configure the interrupt controller to use the application vector table in */ - /* the application space */ - /* IAR & Keil must set vector table after all memory initialization. */ - SCB->VTOR = (uint32_t)__isr_vector; - - MXC_WDT0->ctrl &= - ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ + MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ +#if (__FPU_PRESENT == 1) /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ /* Grant full access, per "Table B3-24 CPACR bit assignments". */ /* DDI0403D "ARMv7-M Architecture Reference Manual" */ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); - - /* Switch system clock to HIRC */ - MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); +#endif /* Disable clocks to peripherals by default to reduce power */ MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA); @@ -140,26 +143,6 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); - Board_Init(); -} - -#if defined(__CC_ARM) -/* Global variable initialization does not occur until post scatterload in Keil tools.*/ - -/* External function called after our post scatterload function implementation. */ -extern void $Super$$__main_after_scatterload(void); - -/** - * @brief Initialization function for SystemCoreClock and Board_Init. - * @details $Sub$$__main_after_scatterload is called during system startup in the Keil - * toolset. Global variable and static variable space must be set up by the compiler - * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init - * require global memory for variable storage and are called from this function in - * the Keil tool chain. - */ -void $Sub$$__main_after_scatterload(void) -{ - SystemInit(); - $Super$$__main_after_scatterload(); + /* Early platform initialization */ + low_level_init(); } -#endif /* __CC_ARM */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h index a92e07b9bd4..d47f2bade87 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h @@ -160,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void); * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. * Call this function multiple times to enable pins on multiple ports. This function does not configure * the GPIO pins nor does it setup their interrupt functionality. - * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the - * structure are used. The func and pad fields are ignored. + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins); +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Disables the selected GPIO port and its selected pins as a wake up source. * Call this function multiple times to disable pins on multiple ports. - * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the - * structure are used. The func and pad fields are ignored. + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins); +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Enables the RTC alarm to wake up the device from any low power mode. diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h index 5d80f0c3599..b652db2c67d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h @@ -49,7 +49,9 @@ // Create a string definition for the TARGET #define STRING_ARG(arg) #arg #define STRING_NAME(name) STRING_ARG(name) +#if MBED_VERSION && MBED_VERSION < 51200 #define TARGET_NAME STRING_NAME(TARGET) +#endif // Define which revisions of the IP we are using #ifndef TARGET_REV diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h index cd91bcd2b1b..450ea27a581 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h @@ -40,6 +40,9 @@ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ +// To enable disable this module +#define USE_LOCK_IN_DRIVERS 0 + /* **** Includes **** */ #include "mxc_device.h" @@ -47,6 +50,8 @@ extern "C" { #endif +#if USE_LOCK_IN_DRIVERS + /** * @ingroup syscfg * @defgroup mxc_lock_utilities Exclusive Access Locks @@ -88,4 +93,11 @@ void MXC_FreeLock(uint32_t *lock); } #endif +#else // USE_LOCK_IN_DRIVERS + +#define MXC_GetLock(x, y) E_NO_ERROR +#define MXC_FreeLock(x) + +#endif // USE_LOCK_IN_DRIVERS + #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h index 1d28443610c..f7e4e654b36 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h @@ -60,8 +60,11 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart1c; extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; extern const mxc_gpio_cfg_t gpio_cfg_spi0; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss; extern const mxc_gpio_cfg_t gpio_cfg_spi1a; +extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss; extern const mxc_gpio_cfg_t gpio_cfg_spi1b; +extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss; // Timers are only defined once, depending on package, each timer could be mapped to other pins extern const mxc_gpio_cfg_t gpio_cfg_tmr0; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h index 6121e44de9e..8090125c17f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h @@ -169,12 +169,14 @@ struct _mxc_spi_req_t { * @param hz The requested clock frequency. The actual clock frequency * will be returned by the function if successful. Used in * master mode only. - * + * @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is + * To upper layer firmware drive it. + * 1:Driver will drive SS pin, 0:Driver will NOT drive it * @return If successful, the actual clock frequency is returned. Otherwise, see * \ref MXC_Error_Codes for a list of return codes. */ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz); + unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); /** * @brief Disable and shutdown SPI peripheral. diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h index b33976271ec..57b3dff9c48 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h @@ -122,7 +122,7 @@ typedef struct { int in_critical; } mxc_crit_state_t; -static mxc_crit_state_t _state = { .ie_status = 0xFFFFFFFF, .in_critical = 0 }; +static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 }; static inline void _mxc_crit_get_state() { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h index e5df3e13a7b..86637941c37 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h @@ -116,7 +116,7 @@ struct mxc_spimss_req { * * @return \c #E_NO_ERROR if successful, appropriate error otherwise */ -int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg); +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel); /** * @brief Shutdown SPI module. @@ -175,6 +175,19 @@ int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); */ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData); + /** * @brief Aborts an Asynchronous request * diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h index 3ce9bf91b61..cf9d5a0f267 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h @@ -115,12 +115,25 @@ typedef enum { TMR_UNIT_SEC, ///< Second Unit Indicator } mxc_tmr_unit_t; +/** + * @brief Clock settings + * @note 8M and 32M clocks can be used for Timers 0,1,2 and 3 + * 32K and 80K clocks can only be used for Timers 4 and 5 + */ +typedef enum { + MXC_TMR_HFIO_CLK, ///< HFIO Clock + MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock + MXC_TMR_EXT_CLK, ///< External Clock +} mxc_tmr_clock_t; + /** * @brief Timer Configuration */ typedef struct { mxc_tmr_pres_t pres; ///< Desired timer prescaler mxc_tmr_mode_t mode; ///< Desired timer mode + mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits + mxc_tmr_clock_t clock; ///< Desired clock source uint32_t cmp_cnt; ///< Compare register value in timer ticks unsigned pol; ///< Polarity (0 or 1) } mxc_tmr_cfg_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c index bb79c1c2b88..89f8b7e7666 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c @@ -70,11 +70,11 @@ void MXC_FLC_ME11_Flash_Operation(void) // Clear the line fill buffer by reading 2 pages from flash volatile uint32_t *line_addr; - volatile uint32_t __unused line; // __unused attribute removes warning - line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE); - line = *line_addr; + volatile uint32_t line; // __unused attribute removes warning line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); line = *line_addr; + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + (2 * MXC_FLASH_PAGE_SIZE)); + line = *line_addr; } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c index ffb3dcfb0b5..113988d48b8 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c @@ -42,7 +42,7 @@ #include "mxc_delay.h" #include "i2c_regs.h" #include "dma_regs.h" -#include "i2c.h" +#include "mxc_i2c.h" #include "i2c_reva.h" /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index a9bd8110da9..f6f7fed0567 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -40,7 +40,7 @@ #include "mxc_sys.h" #include "mxc_delay.h" #include "i2c_regs.h" -#include "i2c.h" +#include "mxc_i2c.h" #include "i2c_reva.h" #include "dma.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c index 5f0514de2ae..0082a449341 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c @@ -156,23 +156,24 @@ void MXC_LP_DisableRTCAlarmWakeup(void) MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN; } -void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins) +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask) { MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN; - //switch(wu_pins->port) + //switch(port) //{ - /*case 0:*/ MXC_PWRSEQ->lpwk_en |= wu_pins->mask; //break; + /*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break; //} } -void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins) +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask) { - //switch(wu_pins->port) + //switch(port) //{ - /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; //break; + /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break; //} - - if (MXC_PWRSEQ->lpwk_en == 0) { + + if(MXC_PWRSEQ->lpwk_en == 0) + { MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN; } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c index 00ac830cf37..1177229102e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c @@ -44,7 +44,7 @@ /* **** Functions **** */ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz) + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; @@ -71,7 +71,7 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, - ssPolarity, hz); + ssPolarity, hz, drv_ssel); } int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index c7a9667341c..82a54ee2447 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -40,7 +40,7 @@ #include "mxc_lock.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "spi.h" +#include "mxc_spi.h" #include "spi_reva.h" #include "dma_reva.h" @@ -58,6 +58,7 @@ typedef struct { bool txrx_req; uint8_t req_done; uint8_t async; + unsigned drv_ssel; } spi_req_reva_state_t; static spi_req_reva_state_t states[MXC_SPI_INSTANCES]; @@ -69,7 +70,7 @@ static void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length); static int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req); int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz) + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; @@ -84,6 +85,7 @@ int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed states[spi_num].mtFirstTrans = 0; states[spi_num].channelTx = E_NO_DEVICE; states[spi_num].channelRx = E_NO_DEVICE; + states[spi_num].drv_ssel = drv_ssel; spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN); spi->sstime = @@ -109,22 +111,25 @@ int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed // Clear the interrupts spi->intfl = spi->intfl; - if (numSlaves == 1) { - spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; - } + // Driver will drive SS pin? + if (states[spi_num].drv_ssel) { + if (numSlaves == 1) { + spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; + } - if (numSlaves == 2) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); - } + else if (numSlaves == 2) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); + } - if (numSlaves == 3) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | - MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); - } + else if (numSlaves == 3) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); + } - if (numSlaves == 4) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | - MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + else if (numSlaves == 4) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + } } //set quad mode @@ -364,12 +369,14 @@ int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx) MXC_ASSERT(spi_num >= 0); (void)spi_num; - // Setup the slave select - // Activate chosen SS pin - spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; - // Deactivate all unchosen pins - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | - ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + if (states[spi_num].drv_ssel) { + // Setup the slave select + // Activate chosen SS pin + spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; + // Deactivate all unchosen pins + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | + ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + } return E_NO_ERROR; } @@ -823,8 +830,10 @@ uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_ spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); // Leave slave select asserted at the end of the transaction - if (!req->ssDeassert) { - spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + if (states[spi_num].drv_ssel) { + if (!req->ssDeassert) { + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } retval = MXC_SPI_RevA_TransHandler(spi, req); @@ -835,8 +844,10 @@ uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_ } // Deassert slave select at the end of the transaction - if (req->ssDeassert) { - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + if (states[spi_num].drv_ssel) { + if (req->ssDeassert) { + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } return retval; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h index bfc190d66ad..6f46c8562d6 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h @@ -44,7 +44,7 @@ #include "mxc_delay.h" #include "spi_regs.h" #include "spi_reva_regs.h" -#include "spi.h" +#include "mxc_spi.h" #include "dma.h" #ifdef __cplusplus @@ -81,7 +81,7 @@ struct _mxc_spi_reva_req_t { }; int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz); + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi); int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi); int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c index cf7adfe1cf2..ea47b23dfc2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c @@ -45,7 +45,7 @@ /* **** Functions **** */ /* ************************************************************************** */ -int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg) +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel) { int spi_num; @@ -78,7 +78,7 @@ int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const return E_NO_DEVICE; } - return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq); + return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq, drv_ssel); } /* ************************************************************************* */ int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi) @@ -124,6 +124,13 @@ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) { return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req); } + +/* ************************************************************************* */ +int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData) +{ + return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData); +} + /* ************************************************************************* */ int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c index b58537356e6..241fe171954 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c @@ -57,6 +57,8 @@ /* **** Globals **** */ typedef struct { spimss_reva_req_t *req; + unsigned defaultTXData; + unsigned drv_ssel; } spimss_reva_req_state_t; static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES]; @@ -71,7 +73,7 @@ static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); /* ************************************************************************** */ -int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq) +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel) { int spi_num; unsigned int spimss_clk; @@ -79,6 +81,8 @@ int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned fr spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); states[spi_num].req = NULL; + states[spi_num].defaultTXData = 0; + states[spi_num].drv_ssel = drv_ssel; spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start) // Set the bit rate @@ -164,10 +168,12 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r if (master) { // Enable master mode spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master. - spi->mode |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SSEL pin is an output. + if (states[spi_num].drv_ssel) { + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output. + } } else { // Enable slave mode spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave. - spi->mode &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SSEL pin is an input. + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input. } // Setup the character size @@ -180,14 +186,22 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS, 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); } - - // Setup the slave select - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, - // to get the line ready for active low later + + if (req->tx_data == NULL) { + // Must have something to send, so we'll use the rx_data buffer initialized to 0. + memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len)); + req->tx_data = req->rx_data; + } // Clear the TX and RX FIFO spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR); + if (states[spi_num].drv_ssel) { + // Setup the slave select + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, + // to get the line ready for active low later + } + return E_NO_ERROR; } @@ -223,6 +237,7 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) { int error; + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { return error; @@ -230,16 +245,18 @@ int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t * req->callback = NULL; - spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + if (states[spi_num].drv_ssel) { + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. + } while (MXC_SPIMSS_RevA_MasterTransHandler(spi, req) != 0) {} - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; - - spi->ctrl &= - ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... - // stop the transmission... + if (states[spi_num].drv_ssel) { + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; + } + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... + // stop the transmission... return E_NO_ERROR; } @@ -268,9 +285,7 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re { int error; uint8_t int_enable; - - // Clear state for next transaction - MXC_SPIMSS_AbortAsync((mxc_spimss_req_t *)req); + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { return error; @@ -278,9 +293,10 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, req); - spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. - - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + if (states[spi_num].drv_ssel) { + spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. + } if (int_enable == 1) { spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); @@ -339,6 +355,10 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); + if (spi_num < 0) { + MXC_ASSERT(0); + } + // Read the RX FIFO if (req->rx_data != NULL) { // Wait for there to be data in the RX FIFO @@ -461,6 +481,15 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r return int_en; } +/* ************************************************************************* */ +int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData) +{ + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + states[spi_num].defaultTXData = defaultTXData; + return E_NO_ERROR; +} + /* ************************************************************************* */ int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h index a2d1cfd83c8..5d179fefaed 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h @@ -95,13 +95,14 @@ struct spimss_reva_req { spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */ }; -int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq); +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel); int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi); void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi); int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData); int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req); #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index 459df723f14..734196f11a9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -35,6 +35,8 @@ #include "mxc_device.h" #include "mxc_lock.h" +#if USE_LOCK_IN_DRIVERS + #ifndef __riscv /* ************************************************************************** */ int MXC_GetLock(uint32_t *lock, uint32_t value) @@ -75,3 +77,5 @@ void MXC_FreeLock(uint32_t *lock) #warning "Unimplemented for RISCV" } #endif + +#endif // USE_LOCK_IN_DRIVERS \ No newline at end of file diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c index 14be089aff0..a122971501e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c @@ -67,18 +67,15 @@ const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_P const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi0 = { - MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE -}; -const mxc_gpio_cfg_t gpio_cfg_spi1a = { - MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE -}; -const mxc_gpio_cfg_t gpio_cfg_spi1b = { - MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE -}; +//SPI0 +const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +// SPI1A +const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +//SPI1B +const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; // Timers are only defined once, depending on package, each timer could be mapped to other pins const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 7f07b08fb66..7a3f47ef77c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -230,7 +230,7 @@ int MXC_UART_RevA_GetFrequency(mxc_uart_reva_regs_t *uart) decimalDiv += 3; } - uartDiv += decimalDiv / 128.0; + uartDiv += decimalDiv / (float)128; uartDiv *= (1 << (7 - (uart->baud0 & MXC_F_UART_REVA_BAUD0_FACTOR))); return (int)((float)periphClock / uartDiv); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c index 315352b172c..864d27b016a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c @@ -162,9 +162,7 @@ void lp_ticker_init(void) unsigned int count; cfg.pres = LP_TIMER_PRESCALE; - cfg.mode = TMR_MODE_COMPARE; - cfg.bitMode = TMR_BIT_MODE_32; - cfg.clock = MXC_TMR_HFIO_CLK; + cfg.mode = TMR_MODE_COMPARE; cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(LP_TIMER); cfg.pol = 0; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c index 539751c609a..daa15bcaa70 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c @@ -49,9 +49,7 @@ void us_ticker_init(void) unsigned int count; cfg.pres = US_TIMER_PRESCALE; - cfg.mode = TMR_MODE_COMPARE; - cfg.bitMode = TMR_BIT_MODE_32; - cfg.clock = MXC_TMR_HFIO_CLK; + cfg.mode = TMR_MODE_COMPARE; cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(US_TIMER); cfg.pol = 0; From 9458dc3c7c9fef76183c9c3f53dc81ef26794d17 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Mon, 22 May 2023 16:48:03 +0800 Subject: [PATCH 04/16] M2354: Fix debug failure in Mbed Studio In Mbed Studio, debugging, based on pyOCD, requires Mbed OS application code starting on the sector boundary. Modification list: 1. Update TF-M import assets with MCUboot header padding to sector aligned 2. Following above, change header size argument (-H) in wrapper.py command line 3. Following below, fix min-write-size (--align) to 4 (per flash_area_align()) in wrapper.py command line https://docs.mcuboot.com/design.html#image-trailer Related issue: https://github.com/ARMmbed/mbed-os/issues/15417 --- .../COMPONENT_TFM_S_FW/README.md | 1 + .../partition/flash_layout.h | 2 ++ .../partition/region_defs.h | 31 ++++++++++++++++-- .../COMPONENT_TFM_S_FW/s_veneers.o | Bin 644 -> 644 bytes .../COMPONENT_TFM_S_FW/tfm_s.axf | Bin 448472 -> 442328 bytes .../COMPONENT_TFM_S_FW/tfm_s.bin | Bin 323872 -> 314656 bytes targets/TARGET_NUVOTON/scripts/NUVOTON.py | 4 +-- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md index 5b03c916e63..20196bcb4d5 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md @@ -136,6 +136,7 @@ Below summarize the copy paths from TF-M into Mbed: - trusted-firmware-m/cmake_build/install/outputs/NUVOTON/M2354/tfm_s.bin → tfm_s.bin - trusted-firmware-m/cmake_build/install/interface/lib/s_veneers.o → s_veneers.o - trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/flash_layout.h → partition/flash_layout.h +- trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/partition_M2354.h → partition/partition_M2354_im.h - trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/region_defs.h → partition/region_defs.h - trusted-firmware-m/cmake_build/install/image_signing/layout_files/signing_layout_s.o → partition/signing_layout_s_preprocessed.h - trusted-firmware-m/cmake_build/install/image_signing/layout_files/signing_layout_ns.o → partition/signing_layout_ns_preprocessed.h diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h index 97561f51a97..582d855ee61 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h @@ -2,6 +2,8 @@ * Copyright (c) 2017-2020 Arm Limited. All rights reserved. * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h index a1441a8dc22..704e73e7485 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h @@ -2,6 +2,8 @@ * Copyright (c) 2017-2020 Arm Limited. All rights reserved. * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at @@ -69,12 +71,35 @@ * by the bootloader. */ #ifdef BL2 -#define BL2_HEADER_SIZE (0x400) /* 1 KB */ -#define BL2_TRAILER_SIZE (0x800) /* 2 KB */ +#define BL2_HEADER_SIZE (0x1000) /* 4 KB */ +/* Evaluate image trailer size for 'SWAP' upgrade strategy + * + * Check the link below for necessary trailer size: + * https://www.mcuboot.com/documentation/design/ + * + * With the formula: + * Swap status (BOOT_MAX_IMG_SECTORS * min-write-size * 3) + * + * Where for the platform: + * BOOT_MAX_IMG_SECTORS = 512 (= 1MiB / 2KiB) + * min-write-size = 4 bytes (per flash_area_align()) + * Swap status = 512 * 4 * 3 = 6KiB + * + * 6KiB plus other fields for image trailer plus TLV, we reserve 8KiB in total. + * + * Notes for above estimation: + * 1. In image signing such as bl2/ext/mcuboot/CMakeLists.txt, `--align` must fix to 4 and `--max-sectors` must specify as 512 to catch trailer size overrun error. + * 2. 2KiB is taken from smaller of internal/external Flash's sector sizes. + * 3. Continuing above, SDH Flash's sector size should have adapted to larger from 512 bytes. + * 4. BL2_TRAILER_SIZE must include TLV area, though not mentioned. + * 5. For consistency, BL2_TRAILER_SIZE doesn't change across 'OVERWRITE_ONLY' and "SWAP" upgrade strategies. + * 6. For consistency, (BL2_HEADER_SIZE + BL2_TRAILER_SIZE) doesn't change across w/ and w/o BL2. + */ +#define BL2_TRAILER_SIZE (0x2000) /* 8 KB */ #else /* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */ #define BL2_HEADER_SIZE (0x0) -#define BL2_TRAILER_SIZE (0x800) +#define BL2_TRAILER_SIZE (0x3000) #endif /* BL2 */ #define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/s_veneers.o b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/s_veneers.o index c963835056bf7e9b24239f77a26747c901081ffe..da13cd5e8fb89260ccc82530b8d73c0017a7b50e 100644 GIT binary patch delta 157 zcmZo+ZDF0@S$~I(frEj8L5Shwe)+$B-o4_hX delta 157 zcmZo+ZDF0@S^tHNfrEj8L5Shwe diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf 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'full', "--align", - '1', + '4', # Reasons for removing padding and boot magic option "--pad": # 1. PSA FWU API psa_fwu_install() will be responsible for writing boot magic to enable upgradeable. # 2. The image size gets smaller instead of slot size. #"--pad", "--pad-header", "-H", - '0x400', + '0x1000', "--overwrite-only", "-s", 'auto', # Or modified_timestamp From 79acfb85d45b52fdb5f2166c0344939a5e1558be Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Tue, 23 May 2023 23:25:52 +0300 Subject: [PATCH 05/16] Do not clear interrupt flag during initialization This causes issue for repeaded initialization while using BufferedSerial mode Signed-off-by: Sadik.Ozer --- targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c | 3 --- targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c index 66678832356..57758550c5c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c @@ -213,9 +213,6 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) MBED_ASSERT(0); } - // Clear pending interrupts - obj->uart->int_fl = obj->uart->int_fl; - // Set TX Almost Empty level to interrupt when empty obj->uart->ctrl1 = (MXC_F_UART_THRESH_CTRL_RX_FIFO_DEFAULT_THRESH_VAL | MXC_F_UART_THRESH_CTRL_TX_FIFO_DEFAULT_THRESH_VAL); diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c index 8554dce187e..5bcdc06ec21 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c @@ -218,9 +218,6 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) MBED_ASSERT(0); } - // Clear pending interrupts - obj->uart->int_fl = obj->uart->int_fl; - // Set TX Almost Empty level to interrupt when empty MXC_UART_SetRXThreshold(obj->uart, 1); From cfa0b6498510b5a83daf7847ebcb6dcdceceadbb Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Tue, 23 May 2023 23:35:55 +0300 Subject: [PATCH 06/16] MAX32660, MAX32670 UART performance improvement Signed-off-by: Sadik.Ozer --- .../TARGET_Maxim/TARGET_MAX32660/serial_api.c | 84 +++++++------- .../TARGET_Maxim/TARGET_MAX32670/serial_api.c | 104 +++++++++--------- 2 files changed, 94 insertions(+), 94 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c index 57758550c5c..7452f21e836 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c @@ -67,6 +67,35 @@ static serial_t *objs[MXC_UART_INSTANCES]; static void usurp_pin(PinName, int); +//****************************************************************************** +void uart_handler(serial_t *obj) +{ + // clear interrupts + volatile uint32_t flags = obj->uart->int_fl; + + if (flags & UART_ER_IE) { + // clear error flags + obj->uart->int_fl = UART_ER_IE; + } + + if (flags & UART_RX_IE) { + obj->uart->int_fl = UART_RX_IE; + if (obj && irq_handler) { + irq_handler(obj->id, RxIrq); + } + } + + if (flags & UART_TX_IE) { + obj->uart->int_fl = UART_TX_IE; + if (obj && irq_handler) { + irq_handler(obj->id, TxIrq); + } + } +} + +void uart0_handler(void) { uart_handler(objs[0]); } +void uart1_handler(void) { uart_handler(objs[1]); } + //****************************************************************************** void serial_init(serial_t *obj, PinName tx, PinName rx) { @@ -106,6 +135,19 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) MXC_UART_Init (obj->uart, DEFAULT_BAUD, obj->map); //MBED_ASSERT(retval == E_NO_ERROR); + + switch (obj->index) { + case 0: + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + break; + case 1: + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + break; + } + + return; } void serial_free(serial_t *obj) @@ -158,35 +200,6 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b } } -//****************************************************************************** -void uart_handler(serial_t *obj) -{ - // clear interrupts - volatile uint32_t flags = obj->uart->int_fl; - - if (flags & UART_ER_IE) { - // clear error flags - obj->uart->int_fl = UART_ER_IE; - } - - if (flags & UART_RX_IE) { - obj->uart->int_fl = UART_RX_IE; - if (obj && irq_handler) { - irq_handler(obj->id, RxIrq); - } - } - - if (flags & UART_TX_IE) { - obj->uart->int_fl = UART_TX_IE; - if (obj && irq_handler) { - irq_handler(obj->id, TxIrq); - } - } -} - -void uart0_handler(void) { uart_handler(objs[0]); } -void uart1_handler(void) { uart_handler(objs[1]); } - //****************************************************************************** void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { @@ -200,19 +213,6 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) MBED_ASSERT(obj->index < MXC_UART_INSTANCES); objs[obj->index] = obj; - switch (obj->index) { - case 0: - NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); - NVIC_EnableIRQ(UART0_IRQn); - break; - case 1: - NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); - NVIC_EnableIRQ(UART1_IRQn); - break; - default: - MBED_ASSERT(0); - } - // Set TX Almost Empty level to interrupt when empty obj->uart->ctrl1 = (MXC_F_UART_THRESH_CTRL_RX_FIFO_DEFAULT_THRESH_VAL | MXC_F_UART_THRESH_CTRL_TX_FIFO_DEFAULT_THRESH_VAL); diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c index 5bcdc06ec21..76abac7ef7a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c @@ -63,6 +63,37 @@ static serial_t *objs[MXC_UART_INSTANCES]; static void usurp_pin(PinName, int); +//****************************************************************************** +void uart_handler(serial_t *obj) +{ + // clear interrupts + volatile uint32_t flags = obj->uart->int_fl; + + if (flags & UART_ER_IE) { + // clear error flags + obj->uart->int_fl = UART_ER_IE; + } + + if (flags & UART_RX_IE) { + obj->uart->int_fl = UART_RX_IE; + if (obj && irq_handler) { + irq_handler(obj->id, RxIrq); + } + } + + if (flags & UART_TX_IE) { + obj->uart->int_fl = UART_TX_IE; + if (obj && irq_handler) { + irq_handler(obj->id, TxIrq); + } + } +} + +void uart0_handler(void) { uart_handler(objs[0]); } +void uart1_handler(void) { uart_handler(objs[1]); } +void uart2_handler(void) { uart_handler(objs[2]); } +void uart3_handler(void) { uart_handler(objs[3]); } + //****************************************************************************** void serial_init(serial_t *obj, PinName tx, PinName rx) { @@ -101,6 +132,27 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) MXC_UART_Init (obj->uart, DEFAULT_BAUD, MXC_UART_APB_CLK, obj->map); //MBED_ASSERT(retval == E_NO_ERROR); + + switch (obj->index) { + case 0: + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + break; + case 1: + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + break; + case 2: + NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler); + NVIC_EnableIRQ(UART2_IRQn); + break; + case 3: + NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler); + NVIC_EnableIRQ(UART3_IRQn); + break; + } + + return; } void serial_free(serial_t *obj) @@ -153,37 +205,6 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b } } -//****************************************************************************** -void uart_handler(serial_t *obj) -{ - // clear interrupts - volatile uint32_t flags = obj->uart->int_fl; - - if (flags & UART_ER_IE) { - // clear error flags - obj->uart->int_fl = UART_ER_IE; - } - - if (flags & UART_RX_IE) { - obj->uart->int_fl = UART_RX_IE; - if (obj && irq_handler) { - irq_handler(obj->id, RxIrq); - } - } - - if (flags & UART_TX_IE) { - obj->uart->int_fl = UART_TX_IE; - if (obj && irq_handler) { - irq_handler(obj->id, TxIrq); - } - } -} - -void uart0_handler(void) { uart_handler(objs[0]); } -void uart1_handler(void) { uart_handler(objs[1]); } -void uart2_handler(void) { uart_handler(objs[2]); } -void uart3_handler(void) { uart_handler(objs[3]); } - //****************************************************************************** void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { @@ -197,27 +218,6 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) MBED_ASSERT(obj->index < MXC_UART_INSTANCES); objs[obj->index] = obj; - switch (obj->index) { - case 0: - NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); - NVIC_EnableIRQ(UART0_IRQn); - break; - case 1: - NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); - NVIC_EnableIRQ(UART1_IRQn); - break; - case 2: - NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler); - NVIC_EnableIRQ(UART2_IRQn); - break; - case 3: - NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler); - NVIC_EnableIRQ(UART3_IRQn); - break; - default: - MBED_ASSERT(0); - } - // Set TX Almost Empty level to interrupt when empty MXC_UART_SetRXThreshold(obj->uart, 1); From 23031501cdb7787331e5cd8c76d4731653664fae Mon Sep 17 00:00:00 2001 From: alrvid <126816223+alrvid@users.noreply.github.com> Date: Wed, 14 Jun 2023 23:29:38 +0200 Subject: [PATCH 07/16] Handle negative values passed to close() Calling close() with negative numbers causes out-of-bounds indexing of the filehandles array. For example, this can happen if open() returns an error and the value is later passed to close(). --- platform/source/mbed_retarget.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index f052eec9302..bab741c1920 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -678,6 +678,11 @@ extern "C" int PREFIX(_close)(FILEHANDLE fh) #if !MBED_CONF_PLATFORM_STDIO_MINIMAL_CONSOLE_ONLY extern "C" int close(int fildes) { + if (fildes < 0) + { + errno = EBADF; + return -1; + } FileHandle *fhc = mbed_file_handle(fildes); filehandles[fildes] = NULL; if (fhc == NULL) { From aee2542f591e26d53341733640d0e6ed67ffaa0b Mon Sep 17 00:00:00 2001 From: alrvid <126816223+alrvid@users.noreply.github.com> Date: Thu, 15 Jun 2023 15:38:55 +0200 Subject: [PATCH 08/16] Moved a { to the same line as if Moved a { to the same line as if --- platform/source/mbed_retarget.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index bab741c1920..aa274d2634c 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -678,8 +678,7 @@ extern "C" int PREFIX(_close)(FILEHANDLE fh) #if !MBED_CONF_PLATFORM_STDIO_MINIMAL_CONSOLE_ONLY extern "C" int close(int fildes) { - if (fildes < 0) - { + if (fildes < 0) { errno = EBADF; return -1; } From 3e0e9d018ab933adff3dee503a5f44a0e5302eed Mon Sep 17 00:00:00 2001 From: "Jost, Chris" <79271064+chrJost@users.noreply.github.com> Date: Wed, 5 Jul 2023 11:22:22 +0200 Subject: [PATCH 09/16] add nullpointer check in LWIP::socket_close --- connectivity/lwipstack/source/LWIPStack.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/connectivity/lwipstack/source/LWIPStack.cpp b/connectivity/lwipstack/source/LWIPStack.cpp index c67887e62da..210b6e1b750 100644 --- a/connectivity/lwipstack/source/LWIPStack.cpp +++ b/connectivity/lwipstack/source/LWIPStack.cpp @@ -287,8 +287,9 @@ nsapi_error_t LWIP::socket_close(nsapi_socket_t handle) /* Check if TCP FSM is in ESTABLISHED state. * Then give extra time for connection close handshaking until TIME_WAIT state. * The purpose is to prevent eth/wifi driver stop and FIN ACK corrupt. - * This may happend if network interface disconnect follows immediately after socket_close.*/ - if (NETCONNTYPE_GROUP(s->conn->type) == NETCONN_TCP && s->conn->pcb.tcp->state == ESTABLISHED) { + * This may happend if network interface disconnect follows immediately after socket_close. + * In case of a TCP RESET flag, the pcb structure is already deleted, therefore check for nullpointer.*/ + if (NETCONNTYPE_GROUP(s->conn->type) == NETCONN_TCP && (nullptr == s->conn->pcb.tcp || s->conn->pcb.tcp->state == ESTABLISHED)) { _event_flag.clear(TCP_CLOSED_FLAG); netconn_shutdown(s->conn, false, true); _event_flag.wait_any(TCP_CLOSED_FLAG, TCP_CLOSE_TIMEOUT); From c933a883d821357036961c50e802f548956d37fa Mon Sep 17 00:00:00 2001 From: Joseph Duchesne Date: Mon, 14 Aug 2023 11:07:23 -0400 Subject: [PATCH 10/16] Fix crash when using FDCAN3 RX IRQ on STM32G473 (and others) --- targets/TARGET_STM/can_api.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 293dedaa0f3..73bfa81f346 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -24,7 +24,13 @@ #include "PeripheralPins.h" #include "mbed_error.h" +// Some STM32G4 series (and others) have 3 FDCAN devices +// while others have 2 +#ifdef FDCAN3 +static uintptr_t can_irq_contexts[3] = {0}; +#else static uintptr_t can_irq_contexts[2] = {0}; +#endif static can_irq_handler irq_handler; /** Call all the init functions From 0010978d84f54df371f8bc1d4e035b1d0ab1eb43 Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Thu, 13 Jul 2023 16:21:38 +0800 Subject: [PATCH 11/16] connectivity: drivers: Update Nuvoton M467 EMAC DMA_IE ctl In IRQ Handler, to disable some interrupt type of DMA error. It could avoid unexpected repeated interrupt.The masked bit of DMA_IE could be recovered in next EMAC IRQ event. Signed-off-by: cyliang tw --- .../TARGET_M460/m460_eth.c | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c index 7a69c0943aa..591de2204f2 100644 --- a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c @@ -325,6 +325,7 @@ void EMAC0_IRQHandler(void) uint32_t interrupt,dma_status_reg, mac_status_reg; int status; uint32_t dma_addr; + uint32_t dma_ie = DmaIntEnable; // Check GMAC interrupt mac_status_reg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacInterruptStatus); @@ -401,6 +402,7 @@ void EMAC0_IRQHandler(void) if(interrupt & synopGMACDmaRxNormal) { //NU_RAW_Debug(("rx\n")); NU_RAW_Debug(("%s:: Rx Normal \r\n", __FUNCTION__)); + dma_ie &= ~DmaIntRxNormMask; // disable RX interrupt // to handle received data if (nu_eth_txrx_cb != NULL) { nu_eth_txrx_cb('R', nu_userData); @@ -409,16 +411,17 @@ void EMAC0_IRQHandler(void) if(interrupt & synopGMACDmaRxAbnormal) { mbed_error_printf("%s::Abnormal Rx Interrupt Seen \r\n",__FUNCTION__); - gmacdev->synopGMACNetStats.rx_over_errors++; - if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown - synopGMAC_resume_dma_rx(gmacdev);//To handle GBPS with 12 descriptors + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + gmacdev->synopGMACNetStats.rx_over_errors++; + dma_ie &= ~DmaIntRxAbnMask; + synopGMAC_resume_dma_rx(gmacdev); //To handle GBPS with 12 descriptors } } if(interrupt & synopGMACDmaRxStopped) { mbed_error_printf("%s::Receiver stopped seeing Rx interrupts \r\n",__FUNCTION__); //Receiver gone in to stopped state if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown - gmacdev->synopGMACNetStats.rx_over_errors++; + gmacdev->synopGMACNetStats.rx_over_errors++; synopGMAC_enable_dma_rx(gmacdev); } } @@ -450,13 +453,13 @@ void EMAC0_IRQHandler(void) synopGMAC_take_desc_ownership_tx(gmacdev); synopGMAC_enable_dma_tx(gmacdev); - mbed_error_printf("%s::Transmission Resumed\n",__FUNCTION__); + mbed_error_printf("%s::Transmission Resumed\n", __FUNCTION__); } } /* Enable the interrupt before returning from ISR*/ // if( !(interrupt & synopGMACDmaRxNormal)) { /* RxNormal will enable INT in numaker_eth_trigger_rx */ - synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + synopGMAC_enable_interrupt(gmacdev, dma_ie); // } return; } @@ -515,7 +518,10 @@ int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf) // synopGMAC_disable_dma_rx(gmacdev); // it will encounter DMA interrupt status as "Receiver stopped seeing Rx interrupts" *len = synop_handle_received_data(NU_M460_INTF, buf); dump_desc(gmacdev->RxBusyDesc); - if( *len <= 0 ) return -1; /* No available RX frame */ + if( *len <= 0 ) { + synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); + return -1; /* No available RX frame */ + } // length of payload should be <= 1514 if (*len > (NU_ETH_MAX_FLEN - 4)) { From d7654b4d6210a6d9b08173cfd32863998e3132cf Mon Sep 17 00:00:00 2001 From: Maxim Markin Date: Mon, 14 Aug 2023 11:35:00 +0300 Subject: [PATCH 12/16] Add workaround for G474 hardfault --- .../STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c index d4038599ad9..7ac77172c21 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c @@ -473,6 +473,9 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Request Wait For Interrupt */ __WFI(); + __ISB(); // Workaround for STM32G4 errata + // see chapter 2.2.8 - Wrong instruction fetches from flash memory upon wakeup from Sleep or Stop mode when debug in low-power mode is enabled + // https://www.st.com/resource/en/errata_sheet/es0430-stm32g471xx473xx474xx483xx484xx-device-errata-stmicroelectronics.pdf } else { From 15110452deaedcd46a7b71c805f9d80aa6c5ceb9 Mon Sep 17 00:00:00 2001 From: Charles Date: Fri, 11 Aug 2023 14:34:06 +0200 Subject: [PATCH 13/16] update drivers STM32WL CUBE V1.3.0 --- .../STM32Cube_FW/CMSIS/stm32wl54xx.h | 331 +- .../STM32Cube_FW/CMSIS/stm32wl55xx.h | 331 +- .../STM32Cube_FW/CMSIS/stm32wl5mxx.h | 11558 ++++++++++++++++ .../STM32Cube_FW/CMSIS/stm32wle4xx.h | 323 +- .../STM32Cube_FW/CMSIS/stm32wle5xx.h | 323 +- .../STM32Cube_FW/CMSIS/stm32wlxx.h | 18 +- .../STM32Cube_FW/CMSIS/system_stm32wlxx.h | 3 +- .../Legacy/stm32_hal_legacy.h | 242 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal.c | 250 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal.h | 210 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c | 288 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h | 686 +- .../stm32wlxx_hal_adc_ex.c | 95 +- .../stm32wlxx_hal_adc_ex.h | 14 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c | 45 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.h | 31 +- .../stm32wlxx_hal_cortex.c | 23 +- .../stm32wlxx_hal_cortex.h | 20 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.c | 44 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.h | 68 +- .../stm32wlxx_hal_crc_ex.c | 103 +- .../stm32wlxx_hal_crc_ex.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c | 213 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.h | 45 +- .../stm32wlxx_hal_cryp_ex.c | 13 +- .../stm32wlxx_hal_cryp_ex.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c | 151 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.h | 65 +- .../stm32wlxx_hal_dac_ex.c | 81 +- .../stm32wlxx_hal_dac_ex.h | 18 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h | 15 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c | 44 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h | 13 +- .../stm32wlxx_hal_dma_ex.c | 26 +- .../stm32wlxx_hal_dma_ex.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c | 51 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.h | 29 +- .../stm32wlxx_hal_flash.c | 23 +- .../stm32wlxx_hal_flash.h | 12 +- .../stm32wlxx_hal_flash_ex.c | 23 +- .../stm32wlxx_hal_flash_ex.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c | 90 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h | 17 +- .../stm32wlxx_hal_gpio_ex.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c | 25 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c | 36 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h | 17 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c | 759 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h | 17 +- .../stm32wlxx_hal_i2c_ex.c | 30 +- .../stm32wlxx_hal_i2c_ex.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c | 25 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.c | 28 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c | 151 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h | 24 +- .../stm32wlxx_hal_irda_ex.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c | 27 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h | 13 +- .../stm32wlxx_hal_lptim.c | 198 +- .../stm32wlxx_hal_lptim.h | 150 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c | 109 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.h | 39 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c | 32 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.h | 12 +- .../stm32wlxx_hal_pwr_ex.c | 12 +- .../stm32wlxx_hal_pwr_ex.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c | 280 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h | 74 +- .../stm32wlxx_hal_rcc_ex.c | 58 +- .../stm32wlxx_hal_rcc_ex.h | 17 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c | 28 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h | 13 +- .../stm32wlxx_hal_rng_ex.c | 15 +- .../stm32wlxx_hal_rng_ex.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c | 102 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.h | 21 +- .../stm32wlxx_hal_rtc_ex.c | 26 +- .../stm32wlxx_hal_rtc_ex.h | 13 +- .../stm32wlxx_hal_smartcard.c | 297 +- .../stm32wlxx_hal_smartcard.h | 24 +- .../stm32wlxx_hal_smartcard_ex.c | 23 +- .../stm32wlxx_hal_smartcard_ex.h | 12 +- .../stm32wlxx_hal_smbus.c | 105 +- .../stm32wlxx_hal_smbus.h | 22 +- .../stm32wlxx_hal_smbus_ex.c | 148 +- .../stm32wlxx_hal_smbus_ex.h | 26 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c | 45 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.h | 15 +- .../stm32wlxx_hal_spi_ex.c | 13 +- .../stm32wlxx_hal_spi_ex.h | 12 +- .../stm32wlxx_hal_subghz.c | 152 +- .../stm32wlxx_hal_subghz.h | 43 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c | 1169 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h | 260 +- .../stm32wlxx_hal_tim_ex.c | 367 +- .../stm32wlxx_hal_tim_ex.h | 112 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c | 309 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h | 77 +- .../stm32wlxx_hal_uart_ex.c | 65 +- .../stm32wlxx_hal_uart_ex.h | 14 +- .../stm32wlxx_hal_usart.c | 147 +- .../stm32wlxx_hal_usart.h | 30 +- .../stm32wlxx_hal_usart_ex.c | 23 +- .../stm32wlxx_hal_usart_ex.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.c | 25 +- .../STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.h | 14 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c | 30 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h | 339 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h | 24 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.c | 17 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.h | 35 +- .../stm32wlxx_ll_cortex.h | 34 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.c | 16 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.h | 15 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.c | 83 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.h | 201 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.c | 17 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.h | 13 +- .../stm32wlxx_ll_dmamux.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.c | 61 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.h | 60 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.c | 14 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_hsem.h | 23 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_ipcc.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.c | 36 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.h | 197 +- .../stm32wlxx_ll_lpuart.c | 18 +- .../stm32wlxx_ll_lpuart.h | 367 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.c | 50 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.h | 21 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.c | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.h | 12 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c | 28 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.h | 76 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.h | 13 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c | 14 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h | 12 +- .../stm32wlxx_ll_system.h | 27 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.c | 108 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h | 408 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c | 18 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h | 226 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.c | 32 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.h | 24 +- .../STM32WLxx_HAL_Driver/stm32wlxx_ll_wwdg.h | 13 +- .../STM32Cube_FW/stm32wlxx_hal_conf.h | 4 +- .../STM32Cube_FW/system_stm32wlxx.c | 24 +- 157 files changed, 19335 insertions(+), 5501 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl5mxx.h diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h index d6229a0badb..ebf378815ba 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2020(-2021) STMicroelectronics. + * Copyright (c) 2020-2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -57,7 +57,7 @@ /****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< Cortex-M0+ System Tick Interrupt */ @@ -196,7 +196,7 @@ typedef enum #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ -#else /* CORE_CM4*/ +#else /* CORE_CM4 */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ @@ -205,7 +205,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU not present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -239,10 +239,10 @@ typedef struct __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ - __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ @@ -257,6 +257,11 @@ typedef struct __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ } ADC_Common_TypeDef; +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + /** * @brief AES hardware accelerator */ @@ -818,7 +823,7 @@ typedef struct uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */ + uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ @@ -1313,7 +1318,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1470,71 +1475,129 @@ typedef struct #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ -/******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ -#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ -#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ -#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ -#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ -#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ - -#define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ -#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ -#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ -#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ -#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ +/******************** Bit definition for ADC_AWD1TR register ****************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 /******************** Bit definition for ADC_CHSELR register ****************/ #define ADC_CHSELR_CHSEL_Pos (0U) @@ -1663,39 +1726,67 @@ typedef struct #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ -/******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ -#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ -#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ -#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ -#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ -#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ - -#define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ -#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ -#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ -#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ -#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ - +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ @@ -5901,12 +5992,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -5942,13 +6033,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -11432,11 +11523,23 @@ typedef struct /******************** LPUART Instance *****************************************/ #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) + +/******************************************************************************/ +/* For a painless codes migration between the STM32WLxx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32WL Family */ +/******************************************************************************/ +#if defined(CORE_CM0PLUS) +/* Aliases for __IRQn */ +#define SVC_IRQn SVCall_IRQn +#endif /* CORE_CM0PLUS */ /** * @} */ - /** +/** * @} */ @@ -11454,8 +11557,6 @@ typedef struct * @} */ - /** +/** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h index 523a0398f46..92173584728 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2020(-2021) STMicroelectronics. + * Copyright (c) 2020-2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -57,7 +57,7 @@ /****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< Cortex-M0+ System Tick Interrupt */ @@ -196,7 +196,7 @@ typedef enum #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ -#else /* CORE_CM4*/ +#else /* CORE_CM4 */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ @@ -205,7 +205,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU not present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -239,10 +239,10 @@ typedef struct __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ - __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ @@ -257,6 +257,11 @@ typedef struct __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ } ADC_Common_TypeDef; +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + /** * @brief AES hardware accelerator */ @@ -818,7 +823,7 @@ typedef struct uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */ + uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ @@ -1313,7 +1318,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1470,71 +1475,129 @@ typedef struct #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ -/******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ -#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ -#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ -#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ -#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ -#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ - -#define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ -#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ -#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ -#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ -#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ +/******************** Bit definition for ADC_AWD1TR register ****************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 /******************** Bit definition for ADC_CHSELR register ****************/ #define ADC_CHSELR_CHSEL_Pos (0U) @@ -1663,39 +1726,67 @@ typedef struct #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ -/******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ -#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ -#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ -#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ -#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ -#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ - -#define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ -#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ -#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ -#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ -#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ - +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ @@ -5901,12 +5992,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -5942,13 +6033,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -11428,11 +11519,23 @@ typedef struct /******************** LPUART Instance *****************************************/ #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) + +/******************************************************************************/ +/* For a painless codes migration between the STM32WLxx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32WL Family */ +/******************************************************************************/ +#if defined(CORE_CM0PLUS) +/* Aliases for __IRQn */ +#define SVC_IRQn SVCall_IRQn +#endif /* CORE_CM0PLUS */ /** * @} */ - /** +/** * @} */ @@ -11450,8 +11553,6 @@ typedef struct * @} */ - /** +/** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl5mxx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl5mxx.h new file mode 100644 index 00000000000..c61a73d20e0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl5mxx.h @@ -0,0 +1,11558 @@ +/** + ****************************************************************************** + * @file stm32wl5mxx.h + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32wl5mxx devices. + * + * This file contains:selected + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wl5mxx + * @{ + */ + +#ifndef __STM32WL5Mxx_H +#define __STM32WL5Mxx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#define DUAL_CORE + + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wl5mxx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#if defined(CORE_CM0PLUS) + /*!< Interrupt Number Definition for M0 */ + typedef enum + { + /****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M0+ System Tick Interrupt */ + + /************* STM32WLxx specific Interrupt Numbers on M0 core ************************************************/ + TZIC_ILA_IRQn = 0, /*!< Security Interrupt controller illegal access interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + RTC_LSECSS_IRQn = 2, /*!< RTC Wakeup + RTC Tamper and RTC TimeStamp + RTC Alarms (A & B) and*/ + /*!< RTC SSRU Interrupts and LSECSS Interrupts */ + RCC_FLASH_C1SEV_IRQn = 3, /*!< RCC Interrupt, FLASH interrupt and CPU1 SEV */ + EXTI1_0_IRQn = 4, /*!< EXTI Line 1:0 Interrupt */ + EXTI3_2_IRQn = 5, /*!< EXTI Line 3:2 Interrupt */ + EXTI15_4_IRQn = 6, /*!< EXTI Line 15:4 interrupt */ + ADC_COMP_DAC_IRQn = 7, /*!< ADC, COMP1, COMP2, DAC interrupts */ + DMA1_Channel1_2_3_IRQn = 8, /*!< DMA1 Channels 1,2,3 Interrupt */ + DMA1_Channel4_5_6_7_IRQn = 9, /*!< DMA1 Channels 4,5,6,7 Interrupt */ + DMA2_DMAMUX1_OVR_IRQn = 10, /*!< DMA2 Channels[1..7] and DMAMUX1 Overrun Interrupt */ + LPTIM1_IRQn = 11, /*!< LPTIM1 Global Interrupt */ + LPTIM2_IRQn = 12, /*!< LPTIM2 Global Interrupt */ + LPTIM3_IRQn = 13, /*!< LPTIM3 Global Interrupt */ + TIM1_IRQn = 14, /*!< TIM1 Global Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Global Interrupt */ + TIM16_IRQn = 16, /*!< TIM16 Global Interrupt */ + TIM17_IRQn = 17, /*!< TIM17 Global Interrupt */ + IPCC_C2_RX_C2_TX_IRQn = 18, /*!< IPCC RX Occupied and TX Free Interrupt */ + HSEM_IRQn = 19, /*!< HSEM Interrupt */ + RNG_IRQn = 20, /*!< RNG Interrupt */ + AES_PKA_IRQn = 21, /*!< AES and PKA Interrupt */ + I2C1_IRQn = 22, /*!< I2C1 Event and Error Interrupt */ + I2C2_IRQn = 23, /*!< I2C2 Event and Error Interrupt */ + I2C3_IRQn = 24, /*!< I2C3 Event and Error Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ + SUBGHZSPI_IRQn = 30, /*!< SUBGHZSPI Interrupt */ + SUBGHZ_Radio_IRQn = 31, /*!< SUBGHZ Radio Interrupt */ + } IRQn_Type; +#else /* CORE_CM4 */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WLxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_SSRU_IRQn = 2, /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC_IRQn = 18, /*!< ADC Interrupt */ + DAC_IRQn = 19, /*!< DAC Interrupt */ + C2SEV_PWR_C2H_IRQn = 20, /*!< CPU2 SEV Interrupt */ + COMP_IRQn = 21, /*!< COMP1 and COMP2 Interrupts */ + EXTI9_5_IRQn = 22, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 23, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 24, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 25, /*!< TIM1 Trigger and Communication Interrupts */ + TIM1_CC_IRQn = 26, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 27, /*!< TIM2 Global Interrupt */ + TIM16_IRQn = 28, /*!< TIM16 Global Interrupt */ + TIM17_IRQn = 29, /*!< TIM17 Global Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 32, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 33, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + SPI2_IRQn = 35, /*!< SPI2 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + USART2_IRQn = 37, /*!< USART2 Interrupt */ + LPUART1_IRQn = 38, /*!< LPUART1 Interrupt */ + LPTIM1_IRQn = 39, /*!< LPTIM1 Global Interrupt */ + LPTIM2_IRQn = 40, /*!< LPTIM2 Global Interrupt */ + EXTI15_10_IRQn = 41, /*!< EXTI Lines [15:10] Interrupt */ + RTC_Alarm_IRQn = 42, /*!< RTC Alarms (A and B) Interrupt */ + LPTIM3_IRQn = 43, /*!< LPTIM3 Global Interrupt */ + SUBGHZSPI_IRQn = 44, /*!< SUBGHZSPI Interrupt */ + IPCC_C1_RX_IRQn = 45, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 46, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 47, /*!< HSEM Interrupt */ + I2C3_EV_IRQn = 48, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 49, /*!< I2C3 Error Interrupt */ + SUBGHZ_Radio_IRQn = 50, /*!< SUBGHZ Radio Interrupt */ + AES_IRQn = 51, /*!< AES Interrupt */ + RNG_IRQn = 52, /*!< RNG Interrupt */ + PKA_IRQn = 53, /*!< PKA Interrupt */ + DMA2_Channel1_IRQn = 54, /*!< DMA2 Channel 1 Interrupt */ + DMA2_Channel2_IRQn = 55, /*!< DMA2 Channel 2 Interrupt */ + DMA2_Channel3_IRQn = 56, /*!< DMA2 Channel 3 Interrupt */ + DMA2_Channel4_IRQn = 57, /*!< DMA2 Channel 4 Interrupt */ + DMA2_Channel5_IRQn = 58, /*!< DMA2 Channel 5 Interrupt */ + DMA2_Channel6_IRQn = 59, /*!< DMA2 Channel 6 Interrupt */ + DMA2_Channel7_IRQn = 60, /*!< DMA2 Channel 7 Interrupt */ + DMAMUX1_OVR_IRQn = 61 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +#if defined(CORE_CM0PLUS) +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M0 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< M0 core uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< FPU not present */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +#else /* CORE_CM4 */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< FPU not present */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +#endif + +#include "system_stm32wlxx.h" +#include + +/** + * @} + */ + + + + + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x18 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; +#endif + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t ACR2; /*!< FLASH Access control register 2, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Global Security Controller + */ +typedef struct{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + uint32_t RESERVED2[3]; /*!< Reserved2, Address offset: 0x14-0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + uint32_t RESERVED3[67]; /*!< Reserved3, Address offset: 0x24-0x12C */ + __IO uint32_t MPCWM1_UPWMR; /*!< TZSC Unprivileged Water Mark 1 register, Address offset: 0x130 */ + __IO uint32_t MPCWM1_UPWWMR; /*!< TZSC Unprivileged Writable Water Mark 1 register, Address offset: 0x134 */ + __IO uint32_t MPCWM2_UPWMR; /*!< TZSC Unprivileged Water Mark 2 register, Address offset: 0x138 */ + uint32_t RESERVED4; /*!< Reserved4, Address offset: 0x13C */ + __IO uint32_t MPCWM3_UPWMR; /*!< TZSC Unprivileged Water Mark 2 register, Address offset: 0x140 */ +} GTZC_TZSC_TypeDef; + +typedef struct{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x0C */ + __IO uint32_t MISR1; /*!< TZIC interrupt status register 1, Address offset: 0x10 */ + uint32_t RESERVED2[3]; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t ICR1; /*!< TZIC interrupt clear register 1, Address offset: 0x20 */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM repetition register, Address offset: 0x28 */ +} LPTIM_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + uint32_t RESERVED0[8]; /*!< Reserved, Address offset: 0x38-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ + __IO uint32_t SECCFGR; /*!< PWR Security Configuration Register, Address offset: 0x8C */ + __IO uint32_t SUBGHZSPICR; /*!< PWR SUBGHZSPI Control Register, Address offset: 0x90 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x94 */ + __IO uint32_t RSSCMDR; /*!< PWR RSS Command Register, Address offset: 0x98 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ +uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clocks enable register, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + __IO uint32_t APB3SMENR; /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ +uint32_t RESERVED7[28]; /*!< Reserved, Address offset: 0x98-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ + __IO uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test control register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 20u +#define RTC_TAMP_NB 3u + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register part, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + uint32_t RESERVED1[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + uint32_t RESERVED2[62]; /*!< Reserved, Address offset: 0x110-0x204*/ + __IO uint32_t RFDCR; /*!< SYSCFG CPU2 radio debug control register, Address offset: 0x208 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED0[7];/*!< Reserved, Address offset: 0x10 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +/*!< Boundary memory map */ +#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 256 KB) base address */ +#define SYSTEM_FLASH_BASE 0x1FFF0000UL /*!< System FLASH(28Kb) base address */ +#define SRAM1_BASE 0x20000000UL /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2_BASE 0x20008000UL /*!< SRAM2(up to 32 KB) base address */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address */ + +#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U) +#define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ +#define SRAM2_SIZE 0x00008000UL /*!< SRAM2 default size : 32 kB */ + +/*!< Memory, OTP and Option bytes */ +#define RSSLIB_PFUNC_BASE (SYSTEM_FLASH_BASE + 0x00003A00UL) /*!< RSS area */ +#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ +#define UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x18010000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) +#define LPTIM3_BASE (APB1PERIPH_BASE + 0x00009800UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x0000B000UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC_COMMON_BASE (APB2PERIPH_BASE + 0x00002708UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB3PERIPH_BASE + 0x00000C00UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL) +#define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL) +#define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL) +#define GTZC_TZSC_BASE (AHB3PERIPH_BASE + 0x00004400UL) +#define GTZC_TZIC_BASE (AHB3PERIPH_BASE + 0x00004800UL) + +/*!< APB3 peripherals */ +#define SUBGHZSPI_BASE (APB3PERIPH_BASE + 0x00000000UL) + +#if defined(CORE_CM0PLUS) +#else +/*!< Peripherals available on CPU1 external PPB bus */ +#define DBGMCU_BASE (0xE0042000UL) +#endif + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define ADC ((ADC_TypeDef *) ADC_BASE) +#define ADC_COMMON ((ADC_Common_TypeDef *) ADC_COMMON_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +/* Peripherals available on AH3 bus */ +#define AES ((AES_TypeDef *) AES_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#if defined(CORE_CM0PLUS) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110U)) +#else +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#endif +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) +#define GTZC_TZSC ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE) +#define GTZC_TZIC ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE) + +/* Peripherals available on APB3 bus */ +#define SUBGHZSPI ((SPI_TypeDef *) SUBGHZSPI_BASE) + +#if defined(CORE_CM0PLUS) +#else +/* Peripherals available on CPU1 external PPB bus */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#endif + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register ****************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_PWRMODE_Pos (2U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ + +#define COMP_CSR_INPSEL_Pos (7U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ + +#define COMP_CSR_WINMODE_Pos (9U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ + +#define COMP_CSR_BLANKING_Pos (18U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_INMESEL_Pos (25U) +#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ +#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ +#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU1 */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ + +#define PWR_CR1_SUBGHZSPINSSSEL_Pos (3U) +#define PWR_CR1_SUBGHZSPINSSSEL_Msk (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos) /*!< 0x00000008 */ +#define PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk /*!< Sub-GHz radio SPI NSS source select */ + +#define PWR_CR1_FPDR_Pos (4U) +#define PWR_CR1_FPDR_Msk (0x1UL << PWR_CR1_FPDR_Pos) /*!< 0x00000010 */ +#define PWR_CR1_FPDR PWR_CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU1 */ + +#define PWR_CR1_FPDS_Pos (5U) +#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU1 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ + +#define PWR_CR1_VOS_Pos (9U) +#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ +#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling range selection */ +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ + +#define PWR_CR1_LPR_Pos (14U) +#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ +#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ + +/******************** Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDE_Pos (0U) +#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage detector enable */ + +#define PWR_CR2_PLS_Pos (1U) +#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ +#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< Power voltage detector level selection */ +#define PWR_CR2_PLS_0 (0x1UL << PWR_CR2_PLS_Pos) /*!< 0x00000002 */ +#define PWR_CR2_PLS_1 (0x2UL << PWR_CR2_PLS_Pos) /*!< 0x00000004 */ +#define PWR_CR2_PLS_2 (0x4UL << PWR_CR2_PLS_Pos) /*!< 0x00000008 */ + +#define PWR_CR2_PVME3_Pos (6U) +#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ +#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< Peripherical Voltage Monitor Vdda Enable */ + +/******************** Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_EWUP_Pos (0U) +#define PWR_CR3_EWUP_Msk (0x07UL << PWR_CR3_EWUP_Pos) /*!< 0x00000007 */ +#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */ +#define PWR_CR3_EWUP1_Pos (0U) +#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ +#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] */ +#define PWR_CR3_EWUP2_Pos (1U) +#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ +#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable external WKUP Pin 2 [line 1] */ +#define PWR_CR3_EWUP3_Pos (2U) +#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ +#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP Pin 3 [line 2] */ + +#define PWR_CR3_ULPEN_Pos (7U) +#define PWR_CR3_ULPEN_Msk (0x1UL << PWR_CR3_ULPEN_Pos) /*!< 0x00000080 */ +#define PWR_CR3_ULPEN PWR_CR3_ULPEN_Msk /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */ + +#define PWR_CR3_EWPVD_Pos (8U) +#define PWR_CR3_EWPVD_Msk (0x1UL << PWR_CR3_EWPVD_Pos) /*!< 0x00000100 */ +#define PWR_CR3_EWPVD PWR_CR3_EWPVD_Msk /*!< Enable wakeup PVD for CPU1 */ + +#define PWR_CR3_RRS_Pos (9U) +#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */ +#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention in STANDBY mode */ + +#define PWR_CR3_APC_Pos (10U) +#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ +#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU1 */ + +#define PWR_CR3_EWRFBUSY_Pos (11U) +#define PWR_CR3_EWRFBUSY_Msk (0x1UL << PWR_CR3_EWRFBUSY_Pos) /*!< 0x00008000 */ +#define PWR_CR3_EWRFBUSY PWR_CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU1 */ +#define PWR_CR3_EWRFIRQ_Pos (13U) +#define PWR_CR3_EWRFIRQ_Msk (0x1UL << PWR_CR3_EWRFIRQ_Pos) /*!< 0x00020000 */ +#define PWR_CR3_EWRFIRQ PWR_CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */ + +#define PWR_CR3_EC2H_Pos (14U) +#define PWR_CR3_EC2H_Msk (0x1UL << PWR_CR3_EC2H_Pos) /*!< 0x00040000 */ +#define PWR_CR3_EC2H PWR_CR3_EC2H_Msk /*!< CPU2 Hold interrupt for CPU1 */ + +#define PWR_CR3_EIWUL_Pos (15U) +#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00080000 */ +#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU1 */ + +/******************** Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_WP1_Pos (0U) +#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ +#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 [line 0] polarity */ +#define PWR_CR4_WP2_Pos (1U) +#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ +#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 [line 1] polarity */ +#define PWR_CR4_WP3_Pos (2U) +#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ +#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 [line 2] polarity */ + +#define PWR_CR4_VBE_Pos (8U) +#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT battery charging enable */ +#define PWR_CR4_VBRS_Pos (9U) +#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT battery charging resistor selection */ + +#define PWR_CR4_WRFBUSYP_Pos (11U) +#define PWR_CR4_WRFBUSYP_Msk (0x1UL << PWR_CR4_WRFBUSYP_Pos) /*!< 0x00008000 */ +#define PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk /*!< Wake-up radio busy polarity */ + +#define PWR_CR4_C2BOOT_Pos (15U) +#define PWR_CR4_C2BOOT_Msk (0x1UL << PWR_CR4_C2BOOT_Pos) /*!< 0x00008000 */ +#define PWR_CR4_C2BOOT PWR_CR4_C2BOOT_Msk /*!< Boot CPU2 after reset or wakeup from Stop or Standby modes */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_WUF_Pos (0U) +#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x00000007 */ +#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags of all pins */ +#define PWR_SR1_WUF1_Pos (0U) +#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Pin 1 [Flag 0] */ +#define PWR_SR1_WUF2_Pos (1U) +#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Pin 2 [Flag 1] */ +#define PWR_SR1_WUF3_Pos (2U) +#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wakeup Pin 3 [Flag 2] */ + +#define PWR_SR1_WPVDF_Pos (8U) +#define PWR_SR1_WPVDF_Msk (0x1UL << PWR_SR1_WPVDF_Pos) /*!< 0x00000100 */ +#define PWR_SR1_WPVDF PWR_SR1_WPVDF_Msk /*!< Wakeup PVD flag */ + +#define PWR_SR1_WRFBUSYF_Pos (11U) +#define PWR_SR1_WRFBUSYF_Msk (0x1UL << PWR_SR1_WRFBUSYF_Pos) /*!< 0x00000800 */ +#define PWR_SR1_WRFBUSYF PWR_SR1_WRFBUSYF_Msk /*!< Wakeup radio busy flag */ + +#define PWR_SR1_C2HF_Pos (14U) +#define PWR_SR1_C2HF_Msk (0x1UL << PWR_SR1_C2HF_Pos) /*!< 0x00004000 */ +#define PWR_SR1_C2HF PWR_SR1_C2HF_Msk /*!< CPU2 Hold interrupt flag */ + +#define PWR_SR1_WUFI_Pos (15U) +#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ +#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */ + +/******************** Bit definition for PWR_SR2 register ********************/ +#define PWR_SR2_C2BOOTS_Pos (0U) +#define PWR_SR2_C2BOOTS_Msk (0x1UL << PWR_SR2_C2BOOTS_Pos) /*!< 0x00000001 */ +#define PWR_SR2_C2BOOTS PWR_SR2_C2BOOTS_Msk /*!< CPU2 boot or wakeup request source information */ + +#define PWR_SR2_RFBUSYS_Pos (1U) +#define PWR_SR2_RFBUSYS_Msk (0x1UL << PWR_SR2_RFBUSYS_Pos) /*!< 0x00000002 */ +#define PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS_Msk /*!< Radio busy signal status */ + +#define PWR_SR2_RFBUSYMS_Pos (2U) +#define PWR_SR2_RFBUSYMS_Msk (0x1UL << PWR_SR2_RFBUSYMS_Pos) /*!< 0x00000004 */ +#define PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS_Msk /*!< Radio busy masked signal status */ + +#define PWR_SR2_SMPSRDY_Pos (3U) +#define PWR_SR2_SMPSRDY_Msk (0x1UL << PWR_SR2_SMPSRDY_Pos) /*!< 0x00000008 */ +#define PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY_Msk /*!< SMPS ready flag */ +#define PWR_SR2_LDORDY_Pos (4U) +#define PWR_SR2_LDORDY_Msk (0x1UL << PWR_SR2_LDORDY_Pos) /*!< 0x00000010 */ +#define PWR_SR2_LDORDY PWR_SR2_LDORDY_Msk /*!< LDO ready flag */ + +#define PWR_SR2_RFEOLF_Pos (5U) +#define PWR_SR2_RFEOLF_Msk (0x1UL << PWR_SR2_RFEOLF_Pos) /*!< 0x00000020 */ +#define PWR_SR2_RFEOLF PWR_SR2_RFEOLF_Msk /*!< Radio end of life flag */ + +#define PWR_SR2_REGMRS_Pos (6U) +#define PWR_SR2_REGMRS_Msk (0x1UL << PWR_SR2_REGMRS_Pos) /*!< 0x00000040 */ +#define PWR_SR2_REGMRS PWR_SR2_REGMRS_Msk /*!< Main regulator status */ + +#define PWR_SR2_FLASHRDY_Pos (7U) +#define PWR_SR2_FLASHRDY_Msk (0x1UL << PWR_SR2_FLASHRDY_Pos) /*!< 0x00000080 */ +#define PWR_SR2_FLASHRDY PWR_SR2_FLASHRDY_Msk /*!< Flash ready */ + +#define PWR_SR2_REGLPS_Pos (8U) +#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ +#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator ready */ +#define PWR_SR2_REGLPF_Pos (9U) +#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ +#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regulator being used */ + +#define PWR_SR2_VOSF_Pos (10U) +#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ +#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage scaling flag */ +#define PWR_SR2_PVDO_Pos (11U) +#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ +#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ + +#define PWR_SR2_PVMO3_Pos (14U) +#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ +#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */ + +/******************** Bit definition for PWR_SCR register ********************/ +#define PWR_SCR_CWUF_Pos (0U) +#define PWR_SCR_CWUF_Msk (0x7UL << PWR_SCR_CWUF_Pos) /*!< 0x00000007 */ +#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ +#define PWR_SCR_CWUF1_Pos (0U) +#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Pin 1 [Flag 0] */ +#define PWR_SCR_CWUF2_Pos (1U) +#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Pin 2 [Flag 1] */ +#define PWR_SCR_CWUF3_Pos (2U) +#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Pin 3 [Flag 2] */ + +#define PWR_SCR_CWPVDF_Pos (8U) +#define PWR_SCR_CWPVDF_Msk (0x1UL << PWR_SCR_CWPVDF_Pos) /*!< 0x00000100 */ +#define PWR_SCR_CWPVDF PWR_SCR_CWPVDF_Msk /*!< Clear wakeup PVD interrupt flag */ + +#define PWR_SCR_CWRFBUSYF_Pos (11U) +#define PWR_SCR_CWRFBUSYF_Msk (0x1UL << PWR_SCR_CWRFBUSYF_Pos) /*!< 0x00000800 */ +#define PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF_Msk /*!< Clear Radio busy interrupt flag */ + +#define PWR_SCR_CC2HF_Pos (14U) +#define PWR_SCR_CC2HF_Msk (0x1UL << PWR_SCR_CC2HF_Pos) /*!< 0x00004000 */ +#define PWR_SCR_CC2HF PWR_SCR_CC2HF_Msk /*!< Clear CPU2 Hold interrupt flag */ + +/******************** Bit definition for PWR_CR5 register ********************/ +#define PWR_CR5_RFEOLEN_Pos (14U) +#define PWR_CR5_RFEOLEN_Msk (0x1UL << PWR_CR5_RFEOLEN_Pos) /*!< 0x00004000 */ +#define PWR_CR5_RFEOLEN PWR_CR5_RFEOLEN_Msk /*!< Enable Radio End Of Life detector enabled */ + +#define PWR_CR5_SMPSEN_Pos (15U) +#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ +#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ + +/******************** Bit definition for PWR_PUCRA register *****************/ +#define PWR_PUCRA_PA0_Pos (0U) +#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up set */ +#define PWR_PUCRA_PA1_Pos (1U) +#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up set */ +#define PWR_PUCRA_PA2_Pos (2U) +#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up set */ +#define PWR_PUCRA_PA3_Pos (3U) +#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up set */ +#define PWR_PUCRA_PA4_Pos (4U) +#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up set */ +#define PWR_PUCRA_PA5_Pos (5U) +#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up set */ +#define PWR_PUCRA_PA6_Pos (6U) +#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up set */ +#define PWR_PUCRA_PA7_Pos (7U) +#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up set */ +#define PWR_PUCRA_PA8_Pos (8U) +#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ +#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up set */ +#define PWR_PUCRA_PA9_Pos (9U) +#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ +#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up set */ +#define PWR_PUCRA_PA10_Pos (10U) +#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ +#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-Up set */ +#define PWR_PUCRA_PA11_Pos (11U) +#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ +#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-Up set */ +#define PWR_PUCRA_PA12_Pos (12U) +#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-Up set */ +#define PWR_PUCRA_PA13_Pos (13U) +#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-Up set */ +#define PWR_PUCRA_PA14_Pos (14U) +#define PWR_PUCRA_PA14_Msk (0x1UL << PWR_PUCRA_PA14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk /*!< Pin PA14 Pull-Up set */ +#define PWR_PUCRA_PA15_Pos (15U) +#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRA register *****************/ +#define PWR_PDCRA_PA0_Pos (0U) +#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Down set */ +#define PWR_PDCRA_PA1_Pos (1U) +#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Down set */ +#define PWR_PDCRA_PA2_Pos (2U) +#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Down set */ +#define PWR_PDCRA_PA3_Pos (3U) +#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Down set */ +#define PWR_PDCRA_PA4_Pos (4U) +#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Down set */ +#define PWR_PDCRA_PA5_Pos (5U) +#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Down set */ +#define PWR_PDCRA_PA6_Pos (6U) +#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Down set */ +#define PWR_PDCRA_PA7_Pos (7U) +#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Down set */ +#define PWR_PDCRA_PA8_Pos (8U) +#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ +#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Down set */ +#define PWR_PDCRA_PA9_Pos (9U) +#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ +#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Down set */ +#define PWR_PDCRA_PA10_Pos (10U) +#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ +#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-Down set */ +#define PWR_PDCRA_PA11_Pos (11U) +#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ +#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-Down set */ +#define PWR_PDCRA_PA12_Pos (12U) +#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-Down set */ +#define PWR_PDCRA_PA13_Pos (13U) +#define PWR_PDCRA_PA13_Msk (0x1UL << PWR_PDCRA_PA13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk /*!< Pin PA13 Pull-Down set */ +#define PWR_PDCRA_PA14_Pos (14U) +#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-Down set */ +#define PWR_PDCRA_PA15_Pos (15U) +#define PWR_PDCRA_PA15_Msk (0x1UL << PWR_PDCRA_PA15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk /*!< Pin PA15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRB register *****************/ +#define PWR_PUCRB_PB0_Pos (0U) +#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up set */ +#define PWR_PUCRB_PB1_Pos (1U) +#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up set */ +#define PWR_PUCRB_PB2_Pos (2U) +#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up set */ +#define PWR_PUCRB_PB3_Pos (3U) +#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up set */ +#define PWR_PUCRB_PB4_Pos (4U) +#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up set */ +#define PWR_PUCRB_PB5_Pos (5U) +#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up set */ +#define PWR_PUCRB_PB6_Pos (6U) +#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up set */ +#define PWR_PUCRB_PB7_Pos (7U) +#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up set */ +#define PWR_PUCRB_PB8_Pos (8U) +#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ +#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up set */ +#define PWR_PUCRB_PB9_Pos (9U) +#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ +#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up set */ +#define PWR_PUCRB_PB10_Pos (10U) +#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */ +#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Pin PB10 Pull-Up set */ +#define PWR_PUCRB_PB11_Pos (11U) +#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */ +#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Pin PB11 Pull-Up set */ +#define PWR_PUCRB_PB12_Pos (12U) +#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Pin PB12 Pull-Up set */ +#define PWR_PUCRB_PB13_Pos (13U) +#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Pin PB13 Pull-Up set */ +#define PWR_PUCRB_PB14_Pos (14U) +#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Pin PB14 Pull-Up set */ +#define PWR_PUCRB_PB15_Pos (15U) +#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Pin PB15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRB register *****************/ +#define PWR_PDCRB_PB0_Pos (0U) +#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Down set */ +#define PWR_PDCRB_PB1_Pos (1U) +#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Down set */ +#define PWR_PDCRB_PB2_Pos (2U) +#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Down set */ +#define PWR_PDCRB_PB3_Pos (3U) +#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Down set */ +#define PWR_PDCRB_PB4_Pos (4U) +#define PWR_PDCRB_PB4_Msk (0x1UL << PWR_PDCRB_PB4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk /*!< Pin PB4 Pull-Down set */ +#define PWR_PDCRB_PB5_Pos (5U) +#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Down set */ +#define PWR_PDCRB_PB6_Pos (6U) +#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Down set */ +#define PWR_PDCRB_PB7_Pos (7U) +#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Down set */ +#define PWR_PDCRB_PB8_Pos (8U) +#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ +#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Down set */ +#define PWR_PDCRB_PB9_Pos (9U) +#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ +#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Down set */ +#define PWR_PDCRB_PB10_Pos (10U) +#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */ +#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Pin PB10 Pull-Down set */ +#define PWR_PDCRB_PB11_Pos (11U) +#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */ +#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Pin PB11 Pull-Down set */ +#define PWR_PDCRB_PB12_Pos (12U) +#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Pin PB12 Pull-Down set */ +#define PWR_PDCRB_PB13_Pos (13U) +#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Pin PB13 Pull-Down set */ +#define PWR_PDCRB_PB14_Pos (14U) +#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Pin PB14 Pull-Down set */ +#define PWR_PDCRB_PB15_Pos (15U) +#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Pin PB15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRC register *****************/ +#define PWR_PUCRC_PC0_Pos (0U) +#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Pin PC0 Pull-Up set */ +#define PWR_PUCRC_PC1_Pos (1U) +#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Pin PC1 Pull-Up set */ +#define PWR_PUCRC_PC2_Pos (2U) +#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Pin PC2 Pull-Up set */ +#define PWR_PUCRC_PC3_Pos (3U) +#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Pin PC3 Pull-Up set */ +#define PWR_PUCRC_PC4_Pos (4U) +#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Pin PC4 Pull-Up set */ +#define PWR_PUCRC_PC5_Pos (5U) +#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Pin PC5 Pull-Up set */ +#define PWR_PUCRC_PC6_Pos (6U) +#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Pin PC6 Pull-Up set */ +#define PWR_PUCRC_PC13_Pos (13U) +#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Pin PC13 Pull-Up set */ +#define PWR_PUCRC_PC14_Pos (14U) +#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-Up set */ +#define PWR_PUCRC_PC15_Pos (15U) +#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRC register *****************/ +#define PWR_PDCRC_PC0_Pos (0U) +#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Pin PC0 Pull-Down set */ +#define PWR_PDCRC_PC1_Pos (1U) +#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Pin PC1 Pull-Down set */ +#define PWR_PDCRC_PC2_Pos (2U) +#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Pin PC2 Pull-Down set */ +#define PWR_PDCRC_PC3_Pos (3U) +#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Pin PC3 Pull-Down set */ +#define PWR_PDCRC_PC4_Pos (4U) +#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Pin PC4 Pull-Down set */ +#define PWR_PDCRC_PC5_Pos (5U) +#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Pin PC5 Pull-Down set */ +#define PWR_PDCRC_PC6_Pos (6U) +#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Pin PC6 Pull-Down set */ +#define PWR_PDCRC_PC13_Pos (13U) +#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Pin PC13 Pull-Down set */ +#define PWR_PDCRC_PC14_Pos (14U) +#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-Down set */ +#define PWR_PDCRC_PC15_Pos (15U) +#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRH register *****************/ +#define PWR_PUCRH_PH3_Pos (3U) +#define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos) /*!< 0x00000004 */ +#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRH register *****************/ +#define PWR_PDCRH_PH3_Pos (3U) +#define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos) /*!< 0x00000004 */ +#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Down set */ + +/******************** Bit definition for PWR_C2CR1 register ********************/ +#define PWR_C2CR1_LPMS_Pos (0U) +#define PWR_C2CR1_LPMS_Msk (0x7UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_C2CR1_LPMS PWR_C2CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU2 */ +#define PWR_C2CR1_LPMS_0 (0x1UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_C2CR1_LPMS_1 (0x2UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_C2CR1_LPMS_2 (0x4UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000004 */ + +#define PWR_C2CR1_FPDR_Pos (4U) +#define PWR_C2CR1_FPDR_Msk (0x1UL << PWR_C2CR1_FPDR_Pos) /*!< 0x00000010 */ +#define PWR_C2CR1_FPDR PWR_C2CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU2 */ + +#define PWR_C2CR1_FPDS_Pos (5U) +#define PWR_C2CR1_FPDS_Msk (0x1UL << PWR_C2CR1_FPDS_Pos) /*!< 0x00000020 */ +#define PWR_C2CR1_FPDS PWR_C2CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU2 */ + +/******************** Bit definition for PWR_C2CR3 register ********************/ +#define PWR_C2CR3_EWUP_Pos (0U) +#define PWR_C2CR3_EWUP_Msk (0x07UL << PWR_C2CR3_EWUP_Pos) /*!< 0x00000007 */ +#define PWR_C2CR3_EWUP PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */ +#define PWR_C2CR3_EWUP1_Pos (0U) +#define PWR_C2CR3_EWUP1_Msk (0x1UL << PWR_C2CR3_EWUP1_Pos) /*!< 0x00000001 */ +#define PWR_C2CR3_EWUP1 PWR_C2CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] for CPU2 */ +#define PWR_C2CR3_EWUP2_Pos (1U) +#define PWR_C2CR3_EWUP2_Msk (0x1UL << PWR_C2CR3_EWUP2_Pos) /*!< 0x00000002 */ +#define PWR_C2CR3_EWUP2 PWR_C2CR3_EWUP2_Msk /*!< Enable external WKUP Pin 2 [line 1] for CPU2 */ +#define PWR_C2CR3_EWUP3_Pos (2U) +#define PWR_C2CR3_EWUP3_Msk (0x1UL << PWR_C2CR3_EWUP3_Pos) /*!< 0x00000004 */ +#define PWR_C2CR3_EWUP3 PWR_C2CR3_EWUP3_Msk /*!< Enable external WKUP Pin 3 [line 2] for CPU2 */ + +#define PWR_C2CR3_EWPVD_Pos (8U) +#define PWR_C2CR3_EWPVD_Msk (0x1UL << PWR_C2CR3_EWPVD_Pos) /*!< 0x00000100 */ +#define PWR_C2CR3_EWPVD PWR_C2CR3_EWPVD_Msk /*!< Enable wakeup PVD for CPU2 */ + +#define PWR_C2CR3_APC_Pos (10U) +#define PWR_C2CR3_APC_Msk (0x1UL << PWR_C2CR3_APC_Pos) /*!< 0x00000400 */ +#define PWR_C2CR3_APC PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU2 */ + +#define PWR_C2CR3_EWRFBUSY_Pos (11U) +#define PWR_C2CR3_EWRFBUSY_Msk (0x1UL << PWR_C2CR3_EWRFBUSY_Pos) /*!< 0x00000800 */ +#define PWR_C2CR3_EWRFBUSY PWR_C2CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU2 */ +#define PWR_C2CR3_EWRFIRQ_Pos (13U) +#define PWR_C2CR3_EWRFIRQ_Msk (0x1UL << PWR_C2CR3_EWRFIRQ_Pos) /*!< 0x00002000 */ +#define PWR_C2CR3_EWRFIRQ PWR_C2CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU2 */ + +#define PWR_C2CR3_EIWUL_Pos (15U) +#define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */ +#define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */ + +/******************** Bit definition for PWR_EXTSCR register ********************/ +#define PWR_EXTSCR_C1CSSF_Pos (0U) +#define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ +#define PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF_Msk /*!< Clear standby and stop flags for CPU1 */ +#define PWR_EXTSCR_C2CSSF_Pos (1U) +#define PWR_EXTSCR_C2CSSF_Msk (0x1UL << PWR_EXTSCR_C2CSSF_Pos) /*!< 0x00000002 */ +#define PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF_Msk /*!< Clear standby and stop flags for CPU2 */ + +#define PWR_EXTSCR_C1SBF_Pos (8U) +#define PWR_EXTSCR_C1SBF_Msk (0x1UL << PWR_EXTSCR_C1SBF_Pos) /*!< 0x00000100 */ +#define PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF_Msk /*!< System standby flag for CPU1 */ +#define PWR_EXTSCR_C1STOP2F_Pos (9U) +#define PWR_EXTSCR_C1STOP2F_Msk (0x1UL << PWR_EXTSCR_C1STOP2F_Pos) /*!< 0x00000200 */ +#define PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F_Msk /*!< System stop2 flag for CPU1 */ +#define PWR_EXTSCR_C1STOPF_Pos (10U) +#define PWR_EXTSCR_C1STOPF_Msk (0x1UL << PWR_EXTSCR_C1STOPF_Pos) /*!< 0x00000400 */ +#define PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF_Msk /*!< System stop0 or stop1 flag for CPU1 */ + +#define PWR_EXTSCR_C2SBF_Pos (11U) +#define PWR_EXTSCR_C2SBF_Msk (0x1UL << PWR_EXTSCR_C2SBF_Pos) /*!< 0x00000800 */ +#define PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF_Msk /*!< System standby flag for CPU2 */ +#define PWR_EXTSCR_C2STOP2F_Pos (12U) +#define PWR_EXTSCR_C2STOP2F_Msk (0x1UL << PWR_EXTSCR_C2STOP2F_Pos) /*!< 0x00001000 */ +#define PWR_EXTSCR_C2STOP2F PWR_EXTSCR_C2STOP2F_Msk /*!< System stop2 flag for CPU2 */ +#define PWR_EXTSCR_C2STOPF_Pos (13U) +#define PWR_EXTSCR_C2STOPF_Msk (0x1UL << PWR_EXTSCR_C2STOPF_Pos) /*!< 0x00002000 */ +#define PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF_Msk /*!< System stop0 or stop1 flag for CPU2 */ + +#define PWR_EXTSCR_C1DS_Pos (14U) +#define PWR_EXTSCR_C1DS_Msk (0x1UL << PWR_EXTSCR_C1DS_Pos) /*!< 0x00004000 */ +#define PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS_Msk /*!< CPU1 deepsleep mode flag */ +#define PWR_EXTSCR_C2DS_Pos (15U) +#define PWR_EXTSCR_C2DS_Msk (0x1UL << PWR_EXTSCR_C2DS_Pos) /*!< 0x00008000 */ +#define PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS_Msk /*!< CPU2 deepsleep mode flag */ + +/******************** Bit definition for PWR_SECCFGR register ********************/ +#define PWR_SECCFGR_C2EWILA_Pos (15U) +#define PWR_SECCFGR_C2EWILA_Msk (0x1UL << PWR_SECCFGR_C2EWILA_Pos) /*!< 0x00008000 */ +#define PWR_SECCFGR_C2EWILA PWR_SECCFGR_C2EWILA_Msk /*!< CPU2 illegal access interrupt enable */ + +/******************** Bit definition for PWR_SUBGHZSPICR register ********************/ +#define PWR_SUBGHZSPICR_NSS_Pos (15U) +#define PWR_SUBGHZSPICR_NSS_Msk (0x1UL << PWR_SUBGHZSPICR_NSS_Pos) /*!< 0x00008000 */ +#define PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk /*!< Sub-GHz radio SUBGHZSPI_NSS control */ + +/******************** Bit definition for PWR_RSSCMDR register ********************/ +#define PWR_RSSCMDR_RSSCMD_Pos (0U) +#define PWR_RSSCMDR_RSSCMD_Msk (0xFFUL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */ +#define PWR_RSSCMDR_RSSCMD PWR_RSSCMDR_RSSCMD_Msk /*!< RSS command */ +#define PWR_RSSCMDR_RSSCMD_0 (0x01UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000001 */ +#define PWR_RSSCMDR_RSSCMD_1 (0x02UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000002 */ +#define PWR_RSSCMDR_RSSCMD_2 (0x04UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000004 */ +#define PWR_RSSCMDR_RSSCMD_3 (0x08UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000008 */ +#define PWR_RSSCMDR_RSSCMD_4 (0x10UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000010 */ +#define PWR_RSSCMDR_RSSCMD_5 (0x20UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000020 */ +#define PWR_RSSCMDR_RSSCMD_6 (0x40UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000040 */ +#define PWR_RSSCMDR_RSSCMD_7 (0x80UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000080 */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register *****************/ +#define RCC_CR_MSION_Pos (0U) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ +#define RCC_CR_MSIRDY_Pos (1U) +#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ +#define RCC_CR_MSIPLLEN_Pos (2U) +#define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ +#define RCC_CR_MSIRGSEL_Pos (3U) +#define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */ +#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */ + +/*!< MSIRANGE configuration : 12 frequency ranges available */ +#define RCC_CR_MSIRANGE_Pos (4U) +#define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ +#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ +#define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ +#define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ +#define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ +#define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ +#define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ +#define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ +#define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ +#define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ +#define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ +#define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ +#define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ + +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSIASFS_Pos (11U) +#define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ +#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ +#define RCC_CR_HSIKERDY_Pos (12U) +#define RCC_CR_HSIKERDY_Msk (0x1UL << RCC_CR_HSIKERDY_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSIKERDY RCC_CR_HSIKERDY_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/ + +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< HSE sysclk prescaler */ +#define RCC_CR_HSEBYPPWR_Pos (21U) +#define RCC_CR_HSEBYPPWR_Msk (0x1UL << RCC_CR_HSEBYPPWR_Pos) /*!< 0x00200000 */ +#define RCC_CR_HSEBYPPWR RCC_CR_HSEBYPPWR_Msk /*!< Enable HSE32 VDDTCXO */ + +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ + +/******************** Bit definition for RCC_ICSCR register ***************/ +/*!< MSICAL configuration */ +#define RCC_ICSCR_MSICAL_Pos (0U) +#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ + +/*!< MSITRIM configuration */ +#define RCC_ICSCR_MSITRIM_Pos (8U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ + +/*!< HSICAL configuration */ +#define RCC_ICSCR_HSICAL_Pos (16U) +#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ + +/*!< HSITRIM configuration */ +#define RCC_ICSCR_HSITRIM_Pos (24U) +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +/*!< STOPWUCK configuration */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ + +/*!< HPREF configuration */ +#define RCC_CFGR_HPREF_Pos (16U) +#define RCC_CFGR_HPREF_Msk (0x1UL << RCC_CFGR_HPREF_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_HPREF RCC_CFGR_HPREF_Msk /*!< AHB prescaler flag */ + +/*!< PPRE1F configuration */ +#define RCC_CFGR_PPRE1F_Pos (17U) +#define RCC_CFGR_PPRE1F_Msk (0x1UL << RCC_CFGR_PPRE1F_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PPRE1F RCC_CFGR_PPRE1F_Msk /*!< CPU1 APB1 prescaler flag */ + +/*!< PPRE2F configuration */ +#define RCC_CFGR_PPRE2F_Pos (18U) +#define RCC_CFGR_PPRE2F_Msk (0x1UL << RCC_CFGR_PPRE2F_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PPRE2F RCC_CFGR_PPRE2F_Msk /*!< APB2 prescaler flag */ + +/*!< MCOSEL configuration */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ +#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ + +/*!< MCOPRE configuration */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLLSRC_Pos (0U) +#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */ +#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk +#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */ +#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */ + +#define RCC_PLLCFGR_PLLM_Pos (4U) +#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ +#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk +#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ +#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ + +#define RCC_PLLCFGR_PLLN_Pos (8U) +#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */ +#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk +#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */ +#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */ +#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */ +#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */ +#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */ +#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */ +#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */ + +#define RCC_PLLCFGR_PLLPEN_Pos (16U) +#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */ +#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk +#define RCC_PLLCFGR_PLLP_Pos (17U) +#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */ +#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk +#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */ +#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */ +#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */ +#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */ +#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */ + +#define RCC_PLLCFGR_PLLQEN_Pos (24U) +#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */ +#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk +#define RCC_PLLCFGR_PLLQ_Pos (25U) +#define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */ +#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk +#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */ +#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */ +#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */ + +#define RCC_PLLCFGR_PLLREN_Pos (28U) +#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */ +#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk +#define RCC_PLLCFGR_PLLR_Pos (29U) +#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */ +#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk +#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */ +#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */ +#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */ + + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_MSIRDYIE_Pos (2U) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLLRDYIE_Pos (5U) +#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_MSIRDYF_Pos (2U) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLLRDYF_Pos (5U) +#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk +#define RCC_CIFR_CSSF_Pos (8U) +#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_MSIRDYC_Pos (2U) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLLRDYC_Pos (5U) +#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk +#define RCC_CICR_CSSC_Pos (8U) +#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_DMA1RST_Pos (0U) +#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */ +#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk +#define RCC_AHB1RSTR_DMA2RST_Pos (1U) +#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */ +#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk +#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) +#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */ +#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register ***************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register ***************/ +#define RCC_AHB3RSTR_PKARST_Pos (16U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk +#define RCC_AHB3RSTR_AESRST_Pos (17U) +#define RCC_AHB3RSTR_AESRST_Msk (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */ +#define RCC_AHB3RSTR_AESRST RCC_AHB3RSTR_AESRST_Msk +#define RCC_AHB3RSTR_RNGRST_Pos (18U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk + +#define RCC_AHB3RSTR_HSEMRST_Pos (19U) +#define RCC_AHB3RSTR_HSEMRST_Msk (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */ +#define RCC_AHB3RSTR_HSEMRST RCC_AHB3RSTR_HSEMRST_Msk +#define RCC_AHB3RSTR_IPCCRST_Pos (20U) +#define RCC_AHB3RSTR_IPCCRST_Msk (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos)/*!< 0x00100000 */ +#define RCC_AHB3RSTR_IPCCRST RCC_AHB3RSTR_IPCCRST_Msk +#define RCC_AHB3RSTR_FLASHRST_Pos (25U) +#define RCC_AHB3RSTR_FLASHRST_Msk (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB3RSTR_FLASHRST RCC_AHB3RSTR_FLASHRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_DACRST_Pos (29U) +#define RCC_APB1RSTR1_DACRST_Msk (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */ +#define RCC_APB1RSTR1_DACRST RCC_APB1RSTR1_DACRST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_LPUART1RST_Pos (0U) +#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk +#define RCC_APB1RSTR2_LPTIM3RST_Pos (6U) +#define RCC_APB1RSTR2_LPTIM3RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */ +#define RCC_APB1RSTR2_LPTIM3RST RCC_APB1RSTR2_LPTIM3RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk + +/******************** Bit definition for RCC_APB3RSTR register **************/ +#define RCC_APB3RSTR_SUBGHZSPIRST_Pos (0U) +#define RCC_APB3RSTR_SUBGHZSPIRST_Msk (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTR_SUBGHZSPIRST RCC_APB3RSTR_SUBGHZSPIRST_Msk + +/******************** Bit definition for RCC_AHB1ENR register ****************/ +#define RCC_AHB1ENR_DMA1EN_Pos (0U) +#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk +#define RCC_AHB1ENR_DMA2EN_Pos (1U) +#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk +#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) +#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ +#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_PKAEN_Pos (16U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk +#define RCC_AHB3ENR_AESEN_Pos (17U) +#define RCC_AHB3ENR_AESEN_Msk (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB3ENR_AESEN RCC_AHB3ENR_AESEN_Msk +#define RCC_AHB3ENR_RNGEN_Pos (18U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HSEMEN_Pos (19U) +#define RCC_AHB3ENR_HSEMEN_Msk (0x1UL << RCC_AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB3ENR_HSEMEN RCC_AHB3ENR_HSEMEN_Msk +#define RCC_AHB3ENR_IPCCEN_Pos (20U) +#define RCC_AHB3ENR_IPCCEN_Msk (0x1UL << RCC_AHB3ENR_IPCCEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB3ENR_IPCCEN RCC_AHB3ENR_IPCCEN_Msk +#define RCC_AHB3ENR_FLASHEN_Pos (25U) +#define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_RTCAPBEN_Pos (10U) +#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ +#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_DACEN_Pos (29U) +#define RCC_APB1ENR1_DACEN_Msk (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */ +#define RCC_APB1ENR1_DACEN RCC_APB1ENR1_DACEN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_LPUART1EN_Pos (0U) +#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ +#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk +#define RCC_APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk +#define RCC_APB1ENR2_LPTIM3EN_Pos (6U) +#define RCC_APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */ +#define RCC_APB1ENR2_LPTIM3EN RCC_APB1ENR2_LPTIM3EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk + +/******************** Bit definition for RCC_APB3ENR register **************/ +#define RCC_APB3ENR_SUBGHZSPIEN_Pos (0U) +#define RCC_APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */ +#define RCC_APB3ENR_SUBGHZSPIEN RCC_APB3ENR_SUBGHZSPIEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register ****************/ +#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk +#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) +#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk +#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) +#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register ***************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk + +/******************** Bit definition for RCC_AHB3SMENR register ***************/ +#define RCC_AHB3SMENR_PKASMEN_Pos (16U) +#define RCC_AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB3SMENR_PKASMEN RCC_AHB3SMENR_PKASMEN_Msk +#define RCC_AHB3SMENR_AESSMEN_Pos (17U) +#define RCC_AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB3SMENR_AESSMEN RCC_AHB3SMENR_AESSMEN_Msk +#define RCC_AHB3SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */ +#define RCC_AHB3SMENR_RNGSMEN RCC_AHB3SMENR_RNGSMEN_Msk +#define RCC_AHB3SMENR_SRAM1SMEN_Pos (23U) +#define RCC_AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */ +#define RCC_AHB3SMENR_SRAM1SMEN RCC_AHB3SMENR_SRAM1SMEN_Msk +#define RCC_AHB3SMENR_SRAM2SMEN_Pos (24U) +#define RCC_AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */ +#define RCC_AHB3SMENR_SRAM2SMEN RCC_AHB3SMENR_SRAM2SMEN_Msk +#define RCC_AHB3SMENR_FLASHSMEN_Pos (25U) +#define RCC_AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */ +#define RCC_AHB3SMENR_FLASHSMEN RCC_AHB3SMENR_FLASHSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) +#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ +#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U) +#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk +#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U) +#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk +#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U) +#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk +#define RCC_APB1SMENR1_DACSMEN_Pos (29U) +#define RCC_APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */ +#define RCC_APB1SMENR1_DACSMEN RCC_APB1SMENR1_DACSMEN_Msk +#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ +#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) +#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk +#define RCC_APB1SMENR2_LPTIM3SMEN_Pos (6U) +#define RCC_APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */ +#define RCC_APB1SMENR2_LPTIM3SMEN RCC_APB1SMENR2_LPTIM3SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk + +/******************** Bit definition for RCC_APB3SMENR register **************/ +#define RCC_APB3SMENR_SUBGHZSPISMEN_Pos (0U) +#define RCC_APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */ +#define RCC_APB3SMENR_SUBGHZSPISMEN RCC_APB3SMENR_SUBGHZSPISMEN_Msk + +/******************** Bit definition for RCC_CCIPR register ******************/ +#define RCC_CCIPR_USART1SEL_Pos (0U) +#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk +#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk +#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ + +#define RCC_CCIPR_I2S2SEL_Pos (8U) +#define RCC_CCIPR_I2S2SEL_Msk (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR_I2S2SEL RCC_CCIPR_I2S2SEL_Msk +#define RCC_CCIPR_I2S2SEL_0 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR_I2S2SEL_1 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk +#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk +#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR_I2C2SEL_Pos (14U) +#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk +#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR_I2C3SEL_Pos (16U) +#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk +#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk +#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ + +#define RCC_CCIPR_LPTIM2SEL_Pos (20U) +#define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk +#define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ + +#define RCC_CCIPR_LPTIM3SEL_Pos (22U) +#define RCC_CCIPR_LPTIM3SEL_Msk (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR_LPTIM3SEL RCC_CCIPR_LPTIM3SEL_Msk +#define RCC_CCIPR_LPTIM3SEL_0 (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR_LPTIM3SEL_1 (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR_ADCSEL_Pos (28U) +#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk +#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ + +#define RCC_CCIPR_RNGSEL_Pos (30U) +#define RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk +#define RCC_CCIPR_RNGSEL_0 (0x1UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR_RNGSEL_1 (0x2UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk + +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSESYSEN_Pos (7U) +#define RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +#define RCC_BDCR_LSESYSRDY_Pos (11U) +#define RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk + +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk + +#define RCC_BDCR_LSCOEN_Pos (24U) +#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk +#define RCC_BDCR_LSCOSEL_Pos (25U) +#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk +#define RCC_CSR_LSIPRE_Pos (4U) +#define RCC_CSR_LSIPRE_Msk (0x1UL << RCC_CSR_LSIPRE_Pos) /*!< 0x00000010 */ +#define RCC_CSR_LSIPRE RCC_CSR_LSIPRE_Msk + +#define RCC_CSR_MSISRANGE_Pos (8U) +#define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */ +#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk +#define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */ +#define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */ +#define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */ +#define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */ + +#define RCC_CSR_RFRSTF_Pos (14U) +#define RCC_CSR_RFRSTF_Msk (0x1UL << RCC_CSR_RFRSTF_Pos) /*!< 0x0004000 */ +#define RCC_CSR_RFRSTF RCC_CSR_RFRSTF_Msk +#define RCC_CSR_RFRST_Pos (15U) +#define RCC_CSR_RFRST_Msk (0x1UL << RCC_CSR_RFRST_Pos) /*!< 0x0008000 */ +#define RCC_CSR_RFRST RCC_CSR_RFRST_Msk + +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_RFILARSTF_Pos (24U) +#define RCC_CSR_RFILARSTF_Msk (0x1UL << RCC_CSR_RFILARSTF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RFILARSTF RCC_CSR_RFILARSTF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_EXTCFGR register *******************/ +#define RCC_EXTCFGR_SHDHPRE_Pos (0U) +#define RCC_EXTCFGR_SHDHPRE_Msk (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */ +#define RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_Msk +#define RCC_EXTCFGR_SHDHPRE_0 (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */ +#define RCC_EXTCFGR_SHDHPRE_1 (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */ +#define RCC_EXTCFGR_SHDHPRE_2 (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */ +#define RCC_EXTCFGR_SHDHPRE_3 (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */ + +#define RCC_EXTCFGR_C2HPRE_Pos (4U) +#define RCC_EXTCFGR_C2HPRE_Msk (0xFUL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x000000F0 */ +#define RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_Msk +#define RCC_EXTCFGR_C2HPRE_0 (0x1UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000010 */ +#define RCC_EXTCFGR_C2HPRE_1 (0x2UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000020 */ +#define RCC_EXTCFGR_C2HPRE_2 (0x4UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000040 */ +#define RCC_EXTCFGR_C2HPRE_3 (0x8UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000080 */ + +#define RCC_EXTCFGR_SHDHPREF_Pos (16U) +#define RCC_EXTCFGR_SHDHPREF_Msk (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */ +#define RCC_EXTCFGR_SHDHPREF RCC_EXTCFGR_SHDHPREF_Msk +#define RCC_EXTCFGR_C2HPREF_Pos (17U) +#define RCC_EXTCFGR_C2HPREF_Msk (0x1UL << RCC_EXTCFGR_C2HPREF_Pos)/*!< 0x00020000 */ +#define RCC_EXTCFGR_C2HPREF RCC_EXTCFGR_C2HPREF_Msk + +/******************** Bit definition for RCC_C2AHB1ENR register ****************/ +#define RCC_C2AHB1ENR_DMA1EN_Pos (0U) +#define RCC_C2AHB1ENR_DMA1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB1ENR_DMA1EN RCC_C2AHB1ENR_DMA1EN_Msk +#define RCC_C2AHB1ENR_DMA2EN_Pos (1U) +#define RCC_C2AHB1ENR_DMA2EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA2EN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB1ENR_DMA2EN RCC_C2AHB1ENR_DMA2EN_Msk +#define RCC_C2AHB1ENR_DMAMUX1EN_Pos (2U) +#define RCC_C2AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB1ENR_DMAMUX1EN RCC_C2AHB1ENR_DMAMUX1EN_Msk +#define RCC_C2AHB1ENR_CRCEN_Pos (12U) +#define RCC_C2AHB1ENR_CRCEN_Msk (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos)/*!< 0x00001000 */ +#define RCC_C2AHB1ENR_CRCEN RCC_C2AHB1ENR_CRCEN_Msk + +/******************** Bit definition for RCC_C2AHB2ENR register ***************/ +#define RCC_C2AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_C2AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB2ENR_GPIOAEN RCC_C2AHB2ENR_GPIOAEN_Msk +#define RCC_C2AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_C2AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB2ENR_GPIOBEN RCC_C2AHB2ENR_GPIOBEN_Msk +#define RCC_C2AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_C2AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB2ENR_GPIOCEN RCC_C2AHB2ENR_GPIOCEN_Msk +#define RCC_C2AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_C2AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos)/*!< 0x00000080 */ +#define RCC_C2AHB2ENR_GPIOHEN RCC_C2AHB2ENR_GPIOHEN_Msk + +/******************** Bit definition for RCC_C2AHB3ENR register ***************/ +#define RCC_C2AHB3ENR_PKAEN_Pos (16U) +#define RCC_C2AHB3ENR_PKAEN_Msk (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ +#define RCC_C2AHB3ENR_PKAEN RCC_C2AHB3ENR_PKAEN_Msk +#define RCC_C2AHB3ENR_AESEN_Pos (17U) +#define RCC_C2AHB3ENR_AESEN_Msk (0x1UL << RCC_C2AHB3ENR_AESEN_Pos)/*!< 0x00020000 */ +#define RCC_C2AHB3ENR_AESEN RCC_C2AHB3ENR_AESEN_Msk +#define RCC_C2AHB3ENR_RNGEN_Pos (18U) +#define RCC_C2AHB3ENR_RNGEN_Msk (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos)/*!< 0x00040000 */ +#define RCC_C2AHB3ENR_RNGEN RCC_C2AHB3ENR_RNGEN_Msk +#define RCC_C2AHB3ENR_HSEMEN_Pos (19U) +#define RCC_C2AHB3ENR_HSEMEN_Msk (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos)/*!< 0x00080000 */ +#define RCC_C2AHB3ENR_HSEMEN RCC_C2AHB3ENR_HSEMEN_Msk +#define RCC_C2AHB3ENR_IPCCEN_Pos (20U) +#define RCC_C2AHB3ENR_IPCCEN_Msk (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos)/*!< 0x00100000 */ +#define RCC_C2AHB3ENR_IPCCEN RCC_C2AHB3ENR_IPCCEN_Msk +#define RCC_C2AHB3ENR_FLASHEN_Pos (25U) +#define RCC_C2AHB3ENR_FLASHEN_Msk (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos)/*!< 0x02000000 */ +#define RCC_C2AHB3ENR_FLASHEN RCC_C2AHB3ENR_FLASHEN_Msk + +/******************** Bit definition for RCC_C2APB1ENR1 register **************/ +#define RCC_C2APB1ENR1_TIM2EN_Pos (0U) +#define RCC_C2APB1ENR1_TIM2EN_Msk (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1ENR1_TIM2EN RCC_C2APB1ENR1_TIM2EN_Msk +#define RCC_C2APB1ENR1_RTCAPBEN_Pos (10U) +#define RCC_C2APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ +#define RCC_C2APB1ENR1_RTCAPBEN RCC_C2APB1ENR1_RTCAPBEN_Msk +#define RCC_C2APB1ENR1_SPI2EN_Pos (14U) +#define RCC_C2APB1ENR1_SPI2EN_Msk (0x1UL << RCC_C2APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB1ENR1_SPI2EN RCC_C2APB1ENR1_SPI2EN_Msk +#define RCC_C2APB1ENR1_USART2EN_Pos (17U) +#define RCC_C2APB1ENR1_USART2EN_Msk (0x1UL << RCC_C2APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB1ENR1_USART2EN RCC_C2APB1ENR1_USART2EN_Msk +#define RCC_C2APB1ENR1_I2C1EN_Pos (21U) +#define RCC_C2APB1ENR1_I2C1EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */ +#define RCC_C2APB1ENR1_I2C1EN RCC_C2APB1ENR1_I2C1EN_Msk +#define RCC_C2APB1ENR1_I2C2EN_Pos (22U) +#define RCC_C2APB1ENR1_I2C2EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */ +#define RCC_C2APB1ENR1_I2C2EN RCC_C2APB1ENR1_I2C2EN_Msk +#define RCC_C2APB1ENR1_I2C3EN_Pos (23U) +#define RCC_C2APB1ENR1_I2C3EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C3EN_Pos)/*!< 0x00800000 */ +#define RCC_C2APB1ENR1_I2C3EN RCC_C2APB1ENR1_I2C3EN_Msk +#define RCC_C2APB1ENR1_DACEN_Pos (29U) +#define RCC_C2APB1ENR1_DACEN_Msk (0x1UL << RCC_C2APB1ENR1_DACEN_Pos)/*!< 0x20000000 */ +#define RCC_C2APB1ENR1_DACEN RCC_C2APB1ENR1_DACEN_Msk +#define RCC_C2APB1ENR1_LPTIM1EN_Pos (31U) +#define RCC_C2APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ +#define RCC_C2APB1ENR1_LPTIM1EN RCC_C2APB1ENR1_LPTIM1EN_Msk + +/******************** Bit definition for RCC_C2APB1ENR2 register **************/ +#define RCC_C2APB1ENR2_LPUART1EN_Pos (0U) +#define RCC_C2APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_C2APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1ENR2_LPUART1EN RCC_C2APB1ENR2_LPUART1EN_Msk +#define RCC_C2APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_C2APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */ +#define RCC_C2APB1ENR2_LPTIM2EN RCC_C2APB1ENR2_LPTIM2EN_Msk +#define RCC_C2APB1ENR2_LPTIM3EN_Pos (6U) +#define RCC_C2APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */ +#define RCC_C2APB1ENR2_LPTIM3EN RCC_C2APB1ENR2_LPTIM3EN_Msk + +/******************** Bit definition for RCC_C2APB2ENR register **************/ +#define RCC_C2APB2ENR_ADCEN_Pos (9U) +#define RCC_C2APB2ENR_ADCEN_Msk (0x1UL << RCC_C2APB2ENR_ADCEN_Pos)/*!< 0x00000200 */ +#define RCC_C2APB2ENR_ADCEN RCC_C2APB2ENR_ADCEN_Msk +#define RCC_C2APB2ENR_TIM1EN_Pos (11U) +#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos)/*!< 0x00000800 */ +#define RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk +#define RCC_C2APB2ENR_SPI1EN_Pos (12U) +#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos)/*!< 0x00001000 */ +#define RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk +#define RCC_C2APB2ENR_USART1EN_Pos (14U) +#define RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk +#define RCC_C2APB2ENR_TIM16EN_Pos (17U) +#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk +#define RCC_C2APB2ENR_TIM17EN_Pos (18U) +#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */ +#define RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk +#define RCC_C2APB2ENR_SAI1EN_Pos (21U) +#define RCC_C2APB2ENR_SAI1EN_Msk (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */ +#define RCC_C2APB2ENR_SAI1EN RCC_C2APB2ENR_SAI1EN_Msk + +/******************** Bit definition for RCC_C2APB3ENR register **************/ +#define RCC_C2APB3ENR_SUBGHZSPIEN_Pos (0U) +#define RCC_C2APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_C2APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB3ENR_SUBGHZSPIEN RCC_C2APB3ENR_SUBGHZSPIEN_Msk + +/******************** Bit definition for RCC_C2AHB1SMENR register ****************/ +#define RCC_C2AHB1SMENR_DMA1SMEN_Pos (0U) +#define RCC_C2AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB1SMENR_DMA1SMEN RCC_C2AHB1SMENR_DMA1SMEN_Msk +#define RCC_C2AHB1SMENR_DMA2SMEN_Pos (1U) +#define RCC_C2AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB1SMENR_DMA2SMEN RCC_C2AHB1SMENR_DMA2SMEN_Msk +#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos (2U) +#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB1SMENR_DMAMUX1SMEN RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk +#define RCC_C2AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_C2AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ +#define RCC_C2AHB1SMENR_CRCSMEN RCC_C2AHB1SMENR_CRCSMEN_Msk + +/******************** Bit definition for RCC_C2AHB2SMENR register ***************/ +#define RCC_C2AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_C2AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB2SMENR_GPIOASMEN RCC_C2AHB2SMENR_GPIOASMEN_Msk +#define RCC_C2AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_C2AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB2SMENR_GPIOBSMEN RCC_C2AHB2SMENR_GPIOBSMEN_Msk +#define RCC_C2AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_C2AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB2SMENR_GPIOCSMEN RCC_C2AHB2SMENR_GPIOCSMEN_Msk +#define RCC_C2AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_C2AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */ +#define RCC_C2AHB2SMENR_GPIOHSMEN RCC_C2AHB2SMENR_GPIOHSMEN_Msk + +/******************** Bit definition for RCC_C2AHB3SMENR register ***************/ +#define RCC_C2AHB3SMENR_PKASMEN_Pos (16U) +#define RCC_C2AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ +#define RCC_C2AHB3SMENR_PKASMEN RCC_C2AHB3SMENR_PKASMEN_Msk +#define RCC_C2AHB3SMENR_AESSMEN_Pos (17U) +#define RCC_C2AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_AESSMEN_Pos)/*!< 0x00020000 */ +#define RCC_C2AHB3SMENR_AESSMEN RCC_C2AHB3SMENR_AESSMEN_Msk +#define RCC_C2AHB3SMENR_RNGSMEN_Pos (18U) +#define RCC_C2AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */ +#define RCC_C2AHB3SMENR_RNGSMEN RCC_C2AHB3SMENR_RNGSMEN_Msk +#define RCC_C2AHB3SMENR_SRAM1SMEN_Pos (23U) +#define RCC_C2AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */ +#define RCC_C2AHB3SMENR_SRAM1SMEN RCC_C2AHB3SMENR_SRAM1SMEN_Msk +#define RCC_C2AHB3SMENR_SRAM2SMEN_Pos (24U) +#define RCC_C2AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */ +#define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk +#define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U) +#define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */ +#define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk + +/******************** Bit definition for RCC_C2APB1SMENR1 register **************/ +#define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_C2APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1SMENR1_TIM2SMEN RCC_C2APB1SMENR1_TIM2SMEN_Msk +#define RCC_C2APB1SMENR1_RTCAPBSMEN_Pos (10U) +#define RCC_C2APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ +#define RCC_C2APB1SMENR1_RTCAPBSMEN RCC_C2APB1SMENR1_RTCAPBSMEN_Msk +#define RCC_C2APB1SMENR1_SPI2SMEN_Pos (14U) +#define RCC_C2APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB1SMENR1_SPI2SMEN RCC_C2APB1SMENR1_SPI2SMEN_Msk +#define RCC_C2APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_C2APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB1SMENR1_USART2SMEN RCC_C2APB1SMENR1_USART2SMEN_Msk +#define RCC_C2APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_C2APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ +#define RCC_C2APB1SMENR1_I2C1SMEN RCC_C2APB1SMENR1_I2C1SMEN_Msk +#define RCC_C2APB1SMENR1_I2C2SMEN_Pos (22U) +#define RCC_C2APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ +#define RCC_C2APB1SMENR1_I2C2SMEN RCC_C2APB1SMENR1_I2C2SMEN_Msk +#define RCC_C2APB1SMENR1_I2C3SMEN_Pos (23U) +#define RCC_C2APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */ +#define RCC_C2APB1SMENR1_I2C3SMEN RCC_C2APB1SMENR1_I2C3SMEN_Msk +#define RCC_C2APB1SMENR1_DACSMEN_Pos (29U) +#define RCC_C2APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */ +#define RCC_C2APB1SMENR1_DACSMEN RCC_C2APB1SMENR1_DACSMEN_Msk +#define RCC_C2APB1SMENR1_LPTIM1SMEN_Pos (31U) +#define RCC_C2APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ +#define RCC_C2APB1SMENR1_LPTIM1SMEN RCC_C2APB1SMENR1_LPTIM1SMEN_Msk + +/******************** Bit definition for RCC_C2APB1SMENR2 register **************/ +#define RCC_C2APB1SMENR2_LPUART1SMEN_Pos (0U) +#define RCC_C2APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1SMENR2_LPUART1SMEN RCC_C2APB1SMENR2_LPUART1SMEN_Msk +#define RCC_C2APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_C2APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */ +#define RCC_C2APB1SMENR2_LPTIM2SMEN RCC_C2APB1SMENR2_LPTIM2SMEN_Msk +#define RCC_C2APB1SMENR2_LPTIM3SMEN_Pos (6U) +#define RCC_C2APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */ +#define RCC_C2APB1SMENR2_LPTIM3SMEN RCC_C2APB1SMENR2_LPTIM3SMEN_Msk + +/******************** Bit definition for RCC_C2APB2SMENR register **************/ +#define RCC_C2APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_C2APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_C2APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */ +#define RCC_C2APB2SMENR_ADCSMEN RCC_C2APB2SMENR_ADCSMEN_Msk +#define RCC_C2APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ +#define RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk +#define RCC_C2APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ +#define RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk +#define RCC_C2APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk +#define RCC_C2APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk +#define RCC_C2APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ +#define RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk + +/******************** Bit definition for RCC_C2APB3SMENR register **************/ +#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos (0U) +#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB3SMENR_SUBGHZSPISMEN RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions + */ +#define RNG_VER_3_2 + +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *****************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -5174,13 +5265,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -9729,11 +9820,19 @@ typedef struct /******************** LPUART Instance *****************************************/ #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) + +/******************************************************************************/ +/* For a painless codes migration between the STM32WLxx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32WL Family */ +/******************************************************************************/ /** * @} */ - /** +/** * @} */ @@ -9751,8 +9850,6 @@ typedef struct * @} */ - /** +/** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h index cb49d85314c..760e7b3fa7f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2020(-2021) STMicroelectronics. + * Copyright (c) 2020-2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -139,7 +139,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU not present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -172,10 +172,10 @@ typedef struct __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ - __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ @@ -190,6 +190,11 @@ typedef struct __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ } ADC_Common_TypeDef; +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + /** * @brief AES hardware accelerator */ @@ -655,7 +660,7 @@ typedef struct uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */ + uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ @@ -1131,7 +1136,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1288,71 +1293,129 @@ typedef struct #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ -/******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ -#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ -#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ -#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ -#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ -#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ - -#define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ -#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ -#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ -#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ -#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ +/******************** Bit definition for ADC_AWD1TR register ****************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 /******************** Bit definition for ADC_CHSELR register ****************/ #define ADC_CHSELR_CHSEL_Pos (0U) @@ -1481,39 +1544,67 @@ typedef struct #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ -/******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ -#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ -#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ -#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ -#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ -#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ - -#define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ -#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ -#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ -#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ -#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ - +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ @@ -5133,12 +5224,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -5174,13 +5265,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -9725,11 +9816,19 @@ typedef struct /******************** LPUART Instance *****************************************/ #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) + +/******************************************************************************/ +/* For a painless codes migration between the STM32WLxx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32WL Family */ +/******************************************************************************/ /** * @} */ - /** +/** * @} */ @@ -9747,8 +9846,6 @@ typedef struct * @} */ - /** +/** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h index f53d4dd5ec0..5e2d09d4b89 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2020(-2021) STMicroelectronics. + * Copyright (c) 2020-2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -56,12 +56,13 @@ application */ -#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && !defined (STM32WLE5xx) && !defined (STM32WLE4xx) +#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && !defined (STM32WLE5xx) && !defined (STM32WLE4xx) && !defined(STM32WL5Mxx) /* #define STM32WL55xx */ /*!< STM32WL55xx Devices */ /* #define STM32WL54xx */ /*!< STM32WL54xx Devices */ /* #define STM32WLE5xx */ /*!< STM32WLE5xx Devices */ /* #define STM32WLE4xx */ /*!< STM32WLE4xx Devices */ -#endif + /* #define STM32WL5Mxx */ /*!< STM32WL5Mxx Devices */ +#endif /* STM32WL55xx ... */ /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. @@ -79,7 +80,7 @@ * @brief CMSIS Device version number */ #define __STM32WLxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32WLxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WLxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WLxx_CMSIS_DEVICE_VERSION ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\ @@ -103,9 +104,11 @@ #include "stm32wl54xx.h" #elif defined(STM32WLE4xx) #include "stm32wle4xx.h" +#elif defined(STM32WL5Mxx) + #include "stm32wl5mxx.h" #else #error "Please select first the target STM32WLxx device used in your application, for instance xxx (in stm32wlxx.h file)" -#endif +#endif /* STM32WL55xx ... */ /** * @} @@ -275,8 +278,3 @@ typedef enum /** * @} */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h index b29530621c5..25ce8e3fae2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2020(-2021) STMicroelectronics. + * Copyright (c) 2020-2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -103,4 +103,3 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h index 5057a2d47e3..241b54ec4b0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,14 +37,16 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF #endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ /** * @} */ @@ -105,6 +106,13 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + /** * @} */ @@ -206,6 +214,11 @@ extern "C" { #endif #endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + /** * @} */ @@ -214,6 +227,11 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ /** * @} */ @@ -221,7 +239,7 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4) +#if defined(STM32C0) #else #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ @@ -255,11 +273,18 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID @@ -402,6 +427,10 @@ extern "C" { #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -481,7 +510,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -506,6 +535,9 @@ extern "C" { #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ /** @@ -624,12 +656,12 @@ extern "C" { #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -645,6 +677,24 @@ extern "C" { #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ + /** * @} */ @@ -882,9 +932,19 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + #if defined(STM32U5) #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U #endif /* STM32U5 */ /** * @} @@ -953,7 +1013,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1037,8 +1097,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1049,15 +1109,22 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ /** * @} @@ -1224,6 +1291,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1440,6 +1511,19 @@ extern "C" { * @{ */ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + /** * @} */ @@ -1641,6 +1725,79 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + /** * @} */ @@ -2810,6 +2967,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3274,7 +3436,7 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3387,8 +3549,8 @@ extern "C" { #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE @@ -3399,7 +3561,26 @@ extern "C" { #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT -#endif +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + /** * @} */ @@ -3416,7 +3597,8 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3480,10 +3662,15 @@ extern "C" { #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3812,6 +3999,16 @@ extern "C" { * @} */ +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ @@ -3826,5 +4023,4 @@ extern "C" { #endif /* STM32_HAL_LEGACY */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c index 45d49c610c0..bb438f4d709 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c @@ -5,6 +5,17 @@ * @brief HAL module driver. * This is the common part of the HAL initialization * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +30,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -53,19 +53,30 @@ * @{ */ /** - * @brief STM32WLxx HAL Driver version number - */ + * @brief STM32WLxx HAL Driver version number + */ #define __STM32WLxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WLxx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32WLxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32WLxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WLxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WLxx_HAL_VERSION ((__STM32WLxx_HAL_VERSION_MAIN << 24U)\ - |(__STM32WLxx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32WLxx_HAL_VERSION_SUB2 << 8U )\ - |(__STM32WLxx_HAL_VERSION_RC)) + |(__STM32WLxx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32WLxx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32WLxx_HAL_VERSION_RC)) #define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ +#if defined(STM32WL5Mxx) +#define RADIO_SWITCH_CTRL_GPIO_PORT GPIOC +#define RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define RADIO_SWITCH_CTRL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define RADIO_SWITCH_CTRL3_PIN GPIO_PIN_3 +#define RADIO_SWITCH_CTRL1_PIN GPIO_PIN_4 +#define RADIO_SWITCH_CTRL2_PIN GPIO_PIN_5 + +#endif /* STM32WL5Mxx */ + /** * @} */ @@ -90,8 +101,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ */ /** @addtogroup HAL_Exported_Functions_Group1 - * @brief HAL Initialization and Configuration functions - * + * @brief HAL Initialization and Configuration functions + * @verbatim =============================================================================== ##### HAL Initialization and Configuration functions ##### @@ -304,8 +315,8 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) */ /** @addtogroup HAL_Exported_Functions_Group2 - * @brief HAL Control functions - * + * @brief HAL Control functions + * @verbatim =============================================================================== ##### HAL Control functions ##### @@ -329,7 +340,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ @@ -520,8 +531,8 @@ uint32_t HAL_GetUIDw2(void) */ /** @addtogroup HAL_Exported_Functions_Group3 - * @brief HAL Debug functions - * + * @brief HAL Debug functions + * @verbatim =============================================================================== ##### HAL Debug functions ##### @@ -601,8 +612,8 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) */ /** @defgroup HAL_Exported_Functions_Group4 HAL System Configuration functions - * @brief HAL System Configuration functions - * + * @brief HAL System Configuration functions + * @verbatim =============================================================================== ##### HAL system configuration functions ##### @@ -649,17 +660,17 @@ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - + LL_VREFBUF_SetVoltageScaling(VoltageScaling); - + /* Restrieve Calibration data and store them into trimming field */ if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0) { - TrimmingValue = ((uint32_t) *VREFBUF_SC0_CAL_ADDR) & 0x3FU; + TrimmingValue = ((uint32_t) * VREFBUF_SC0_CAL_ADDR) & 0x3FU; } else { - TrimmingValue = ((uint32_t) *VREFBUF_SC1_CAL_ADDR) & 0x3FU; + TrimmingValue = ((uint32_t) * VREFBUF_SC1_CAL_ADDR) & 0x3FU; } assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); @@ -687,7 +698,7 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) * @brief Tune the Internal Voltage Reference buffer (VREFBUF). * @note Each VrefBuf voltage scale is calibrated in production for each device, * data stored in flash memory. - * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and + * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and * applies this calibration data as trimming value at each scale change. * Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig * can be used in a second time to fine tune the trimming. @@ -816,17 +827,190 @@ void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt) * @} */ +#if defined(STM32WL5Mxx) +/** @defgroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions + * @brief HAL Radio Configuration functions + * +@verbatim + =============================================================================== + ##### HAL Radio configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable the Radio + (+) Configure the Radio to Rx, Tx Low Power or Tx High Power + +@endverbatim + * @{ + */ + +/* RADIO Control functions ****************************************************/ +/** + * @brief Init Radio Switch + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RADIO_Init(void) +{ + HAL_StatusTypeDef status; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable the Radio Switch Clock */ + RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE(); + + /* Configure the Radio Switch pin */ + gpio_init_structure.Pin = (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN); + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + HAL_GPIO_Init(RADIO_SWITCH_CTRL_GPIO_PORT, &gpio_init_structure); + + /* Lock RF Switch GPIOs configuration to avoid any user change */ + /* Only a MCU reset will unlock this configuration */ + status = HAL_GPIO_LockPin(RADIO_SWITCH_CTRL_GPIO_PORT, (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN)); + if (status == HAL_OK) + { + /* By default, the RF Switch is off */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET); + } + + return status; +} + +/** + * @brief DeInit Radio Switch + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RADIO_DeInit(void) +{ + /* Enable the Radio Switch Clock */ + RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE(); + + /* Turn off switch */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET); + + /* Disable the Radio Switch Clock */ + RADIO_SWITCH_CTRL_GPIO_CLK_DISABLE(); + + return HAL_OK; +} + +/** + * @brief Configure Radio Switch. + * @param Config: Specifies the Radio RF switch path to be set. + * This parameter can be one of following parameters: + * @arg RADIO_SWITCH_OFF + * @arg RADIO_SWITCH_RX + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (Config) + { + case RADIO_SWITCH_OFF: + { + /* Turn off switch */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET); + break; + } + case RADIO_SWITCH_RX: + { + /* Turns On in Rx Mode the RF Switch */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_SET); + + break; + } + case RADIO_SWITCH_RFO_LP: + { + /* Turns On in Tx Low Power the RF Switch */ + HAL_GPIO_WriteMultipleStatePin(RADIO_SWITCH_CTRL_GPIO_PORT, RADIO_SWITCH_CTRL2_PIN, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL3_PIN)); + break; + } + case RADIO_SWITCH_RFO_HP: + { + /* Turns On in Tx High Power the RF Switch */ + HAL_GPIO_WriteMultipleStatePin(RADIO_SWITCH_CTRL_GPIO_PORT, RADIO_SWITCH_CTRL1_PIN, + (RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN)); + break; + } + default: + { + status = HAL_ERROR; + break; + } + } + + return status; +} + +/** + * @brief Get If TCXO is to be present on board + * @note never remove called by MW, + * @retval + * RADIO_CONF_TCXO_NOT_SUPPORTED + * RADIO_CONF_TCXO_SUPPORTED + */ +uint8_t HAL_RADIO_IsTCXO(void) +{ + return RADIO_CONF_TCXO_SUPPORTED; +} + +/** + * @brief Get If DCDC is to be present on board + * @note never remove called by MW, + * @retval + * RADIO_CONF_DCDC_NOT_SUPPORTED + * RADIO_CONF_DCDC_SUPPORTED + */ +uint8_t HAL_RADIO_IsDCDC(void) +{ + return RADIO_CONF_DCDC_SUPPORTED; +} + +/** + * @brief Return RF Output Max Power Configuration + * @retval + * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode + * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode + */ +int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config) +{ + int32_t ret; + + if (Config == RADIO_RFO_LP_MAXPOWER) + { + ret = RADIO_CONF_RFO_LP_MAX_15_dBm; + } + else + { + ret = RADIO_CONF_RFO_HP_MAX_22_dBm; + } + + return ret; +} + /** * @} */ +#endif /* STM32WL5Mxx */ -#endif /* HAL_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_MODULE_ENABLED */ /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + * @} + */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.h index b992c5b0bbf..a823722b78d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -24,7 +23,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32wlxx_hal_conf.h" @@ -53,6 +52,7 @@ typedef enum HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef; + /** * @} */ @@ -71,10 +71,34 @@ typedef struct uint32_t InterruptMask2; /*!< The SYSCFG Interrupt Mask to be configured. This parameter can be a combination of @ref SYSCFG_IM_GRP2 */ } SYSCFG_InterruptTypeDef; + /** * @} */ -#endif +#endif /* DUAL_CORE */ + +#if defined(STM32WL5Mxx) +/** @defgroup HAL_RADIO_SWITCH_CONFIG RADIO Switch Config + * @{ + */ +typedef enum +{ + RADIO_SWITCH_OFF = 0, + RADIO_SWITCH_RX = 1, + RADIO_SWITCH_RFO_LP = 2, + RADIO_SWITCH_RFO_HP = 3, +} HAL_RADIO_SwitchConfig_TypeDef; + +typedef enum +{ + RADIO_RFO_LP_MAXPOWER = 0, + RADIO_RFO_HP_MAXPOWER, +} HAL_RADIO_RFOMaxPowerConfig_TypeDef; + +/** + * @} + */ +#endif /* STM32WL5Mxx */ /** * @} @@ -185,8 +209,8 @@ typedef struct #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ /** - * @} - */ + * @} + */ #if defined(DUAL_CORE) /** @defgroup SYSCFG_IM_GRP1 SYSCFG INTERRUPT MASK GROUP1 @@ -295,6 +319,29 @@ typedef struct */ #endif /* DUAL_CORE */ +#if defined(STM32WL5Mxx) +/** @defgroup RADIO_Exported_Constants RADIO Exported Constants + * @{ + */ +#define RADIO_CONF_TCXO_NOT_SUPPORTED 0U +#define RADIO_CONF_TCXO_SUPPORTED 1U + +#define RADIO_CONF_DCDC_NOT_SUPPORTED 0U +#define RADIO_CONF_DCDC_SUPPORTED 1U + +#define RADIO_CONF_RFO_HP_MAX_22_dBm ((int32_t) 22) +#define RADIO_CONF_RFO_HP_MAX_20_dBm ((int32_t) 20) +#define RADIO_CONF_RFO_HP_MAX_17_dBm ((int32_t) 17) +#define RADIO_CONF_RFO_HP_MAX_14_dBm ((int32_t) 14) +#define RADIO_CONF_RFO_LP_MAX_15_dBm ((int32_t) 15) +#define RADIO_CONF_RFO_LP_MAX_14_dBm ((int32_t) 14) +#define RADIO_CONF_RFO_LP_MAX_10_dBm ((int32_t) 10) + +/** + * @} + */ +#endif /* STM32WL5Mxx */ + /** * @} */ @@ -536,7 +583,8 @@ typedef struct * @arg @ref SYSCFG_FLAG_PKASRAM_BUSY PKA SRAM Erase Ongoing * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) & (__FLAG__))!= 0) ? 1 : 0) +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) &\ + (__FLAG__))!= 0) ? 1 : 0) /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. */ @@ -589,73 +637,73 @@ typedef struct #if defined(DUAL_CORE) #if defined(CORE_CM0PLUS) #define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \ - ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) + ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) #define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \ - ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) + ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) #else /* !CORE_CM0PLUS */ #define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \ - ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ - (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) + ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) #define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \ - ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \ - (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) + ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) #endif /* CORE_CM0PLUS */ #endif /* DUAL_CORE */ @@ -775,6 +823,24 @@ void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt); * @} */ +#if defined( STM32WL5Mxx) +/** @addtogroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions + * @{ + */ + +/* RADIO Control functions ****************************************************/ +HAL_StatusTypeDef HAL_RADIO_Init(void); +HAL_StatusTypeDef HAL_RADIO_DeInit(void); +HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config); +uint8_t HAL_RADIO_IsTCXO(void); +uint8_t HAL_RADIO_IsDCDC(void); +int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config); + +/** + * @} + */ +#endif /* STM32WL5Mxx */ + /** * @} */ @@ -789,8 +855,6 @@ void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* __STM32WLxx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c index b3eb314a56d..03068bd5c14 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c @@ -6,19 +6,22 @@ * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on regular group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management + * + Peripheral Control functions + * + Peripheral State functions * Other functions (extended functions) are available in file * "stm32wlxx_hal_adc_ex.c". * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### ADC peripheral features ##### @@ -275,18 +278,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -525,6 +516,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - Clock configuration */ /* - ADC resolution */ /* - Oversampling */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ /* - Trigger frequency mode */ /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ /* and disable phases are performed automatically by hardware */ @@ -539,10 +541,62 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - internal measurement paths (VrefInt, ...) */ /* (set into HAL_ADC_ConfigChannel() ) */ - /* Configuration of ADC resolution */ + tmpCFGR1 |= (hadc->Init.Resolution | + ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + + /* Update setting of discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + } + else + { + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + hadc->Init.ExternalTrigConvEdge); + } + + /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_RES, - hadc->Init.Resolution); + ADC_CFGR1_RES | + ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG, + tmpCFGR1); tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | hadc->Init.TriggerFrequencyMode @@ -579,81 +633,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) } } - /* Configuration of ADC: */ - /* - discontinuous mode */ - /* - LowPowerAutoWait mode */ - /* - LowPowerAutoPowerOff mode */ - /* - continuous conversion mode */ - /* - overrun */ - /* - external trigger to start conversion */ - /* - external trigger polarity */ - /* - data alignment */ - /* - resolution */ - /* - scan direction */ - /* - DMA continuous request */ - tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | - ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - hadc->Init.DataAlign | - ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | - ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - - /* Update setting of discontinuous mode only if continuous mode is disabled */ - if (hadc->Init.DiscontinuousConvMode == ENABLE) - { - if (hadc->Init.ContinuousConvMode == DISABLE) - { - /* Enable the selected ADC group regular discontinuous mode */ - tmpCFGR1 |= ADC_CFGR1_DISCEN; - } - else - { - /* ADC regular group discontinuous was intended to be enabled, */ - /* but ADC regular group modes continuous and sequencer discontinuous */ - /* cannot be enabled simultaneously. */ - - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | - hadc->Init.ExternalTrigConvEdge); - } - - /* Update ADC configuration register with previous settings */ - MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_DISCEN | - ADC_CFGR1_AUTOFF | - ADC_CFGR1_WAIT | - ADC_CFGR1_CONT | - ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTSEL | - ADC_CFGR1_EXTEN | - ADC_CFGR1_ALIGN | - ADC_CFGR1_SCANDIR | - ADC_CFGR1_DMACFG, - tmpCFGR1); - - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_LFTRIG | - ADC_CFGR2_OVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS | - ADC_CFGR2_TOVS, - tmpCFGR2); - /* Channel sampling time configuration */ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); @@ -677,53 +656,26 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) } else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) { - /* Count number of ranks available in HAL ADC handle variable */ - uint32_t ADCGroupRegularSequencerRanksCount; - - /* Parse all ranks from 1 to 8 */ - for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++) - { - /* Check each sequencer rank until value of end of sequence */ - if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) == - ADC_CHSELR_SQ1) - { - break; - } - } - - if (ADCGroupRegularSequencerRanksCount == 1UL) - { - /* Set ADC group regular sequencer: */ - /* Set sequencer scan length by clearing ranks above rank 1 */ - /* and do not modify rank 1 value. */ - SET_BIT(hadc->Instance->CHSELR, - ADC_CHSELR_SQ2_TO_SQ8); - } - else - { - /* Set ADC group regular sequencer: */ - /* - Set ADC group regular sequencer to value memorized */ - /* in HAL ADC handle */ - /* Note: This value maybe be initialized at a unknown value, */ - /* therefore after the first call of "HAL_ADC_Init()", */ - /* each rank corresponding to parameter "NbrOfConversion" */ - /* must be set using "HAL_ADC_ConfigChannel()". */ - /* - Set sequencer scan length by clearing ranks above maximum rank */ - /* and do not modify other ranks value. */ - MODIFY_REG(hadc->Instance->CHSELR, - ADC_CHSELR_SQ_ALL, - (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks) - ); - } + /* Set ADC group regular sequencer: */ + /* - Set ADC group regular sequencer to value memorized */ + /* in HAL ADC handle */ + /* Note: This value maybe be initialized at a unknown value, */ + /* therefore after the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + ADC_CHSELR_SQ_ALL, + (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) + | (hadc->ADCGroupRegularSequencerRanks) + ); } /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core peripheral clocking. */ - /* Check through register CFGR1 (excluding analog watchdog configuration: */ - /* set into separate dedicated function, and bits of ADC resolution set */ - /* out of temporary variable 'tmpCFGR1'). */ - if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES)) - == tmpCFGR1) + if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + == hadc->Init.SamplingTimeCommon1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -846,8 +798,10 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register SMPR */ hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; - /* Reset register TR1 */ - hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1); + /* Reset registers AWDxTR */ + hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); + hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); + hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); /* Reset register CHSELR */ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); @@ -1416,9 +1370,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event - * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) - * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) - * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all + * STM32 series) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all + * STM32 series) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all + * STM32 series) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. @@ -2306,7 +2263,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf wait_loop_index--; } } - else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VBAT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); @@ -2411,6 +2369,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_awd_high_threshold_shifted; uint32_t tmp_awd_low_threshold_shifted; + uint32_t backup_setting_adc_enable_state = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2450,6 +2409,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Analog watchdog configuration */ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { + /* Constraint of ADC on this STM32 series: ADC must be disable + to modify bitfields of register ADC_CFGR1 */ + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + backup_setting_adc_enable_state = 1UL; + tmp_hal_status = ADC_Disable(hadc); + } + /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels. */ @@ -2457,7 +2424,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG { case ADC_ANALOGWATCHDOG_SINGLE_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, - __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_ALL_REG: @@ -2469,6 +2437,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG break; } + if (backup_setting_adc_enable_state == 1UL) + { + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Enable(hadc); + } + } + /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -2507,7 +2483,9 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG break; case ADC_ANALOGWATCHDOG_ALL_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, + pAnalogWDGConfig->WatchdogNumber, + LL_ADC_AWD_ALL_CHANNELS_REG); break; default: /* ADC_ANALOGWATCHDOG_NONE */ @@ -2743,14 +2721,16 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) + if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) + != 0UL) { /* Delay for temperature sensor buffer stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) + * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2997,5 +2977,3 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h index 598e5fd2a80..1552cdb3239 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -63,27 +62,33 @@ typedef struct /** * @brief Structure definition of ADC instance and ADC group regular. * @note Parameters of this structure are shared within 2 scopes: - * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC + * groups regular and injected): ClockPrescaler, Resolution, DataAlign, * ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled - * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. + * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on + * group regular. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter - * (which fulfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous + clock derived from system clock or PLL (Refer to reference manual for list of + clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. - Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only - if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC - must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. - Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. + Note: In case of synchronous clock mode based on HCLK/1, the configuration must + be enabled only if the system clock has a 50% duty clock cycle (APB + prescaler configured inside RCC must be bypassed and PCLK clock must have + 50% duty cycle). Refer to reference manual for details. + Note: In case of usage of asynchronous clock, the selected clock must be + preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ uint32_t Resolution; /*!< Configure the ADC resolution. @@ -94,15 +99,16 @@ typedef struct This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. - On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are - available: + On this STM32 series, ADC group regular sequencer both modes "fully configurable" + or "not fully configurable" are available: - sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. - Sequence length: Set number of ranks in the scan sequence. - Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). - sequencer configured to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by channel HW number. + sequencer length and each rank affectation to a channel are fixed by channel + HW number. - Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. @@ -110,101 +116,156 @@ typedef struct - Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): + This parameter can be associated to parameter 'DiscontinuousConvMode' to have + main sequence subdivided in successive parts. Sequencer is automatically enabled + if several channels are set (sequencer cannot be disabled, as it can be the case + on other STM32 devices): If only 1 channel is set: Conversion is performed in single mode. If several channels are set: Conversions are performed in sequence mode. This parameter can be a value of @ref ADC_Scan_mode */ - uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. + uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and + interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of @ref ADC_EOCSelection. */ - FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for ADC group regular) has been retrieved by user software, + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the + previous conversion (for ADC group regular) has been retrieved by user software, using function HAL_ADC_GetValue(). - This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun - for low frequency applications. + This feature automatically adapts the frequency of ADC conversions triggers to + the speed of the system that reads the data. Moreover, this avoids risk of + overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). - Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: - use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */ - - FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). - This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, - after the first ADC conversion start trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), + HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC + flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended + benefit (except specific case of high load of CPU or DMA transfers which + can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, + when ADC conversion data is needed: + use HAL_ADC_PollForConversion() to ensure that conversion is completed and + HAL_ADC_GetValue() to retrieve conversion result and trig another + conversion start. */ + + FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a + conversion and automatically wakes-up when a new conversion is triggered + (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode + (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) + or continuous mode for ADC group regular, after the first ADC conversion + start trigger occurred (software start or external trigger). This parameter + can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group + sequencer. This parameter is dependent on ScanConvMode: - sequencer configured to fully configurable: Number of ranks in the scan sequence is configurable using this parameter. - Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. - Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks - (sequencer ranks above 'NbrOfConversion' are discarded). + Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to + parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. + Afterwards, when all needed sequencer ranks are set, parameter + 'NbrOfConversion' can be updated without modifying configuration of + sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). - sequencer configured to not fully configurable: - Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded. + Number of ranks in the scan sequence is defined by number of channels set in + the sequence. This parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. - Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - - FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence - (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. - Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ - - uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. - If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. + Note: This parameter must be modified when no conversion is on going on regular + group (ADC disabled, or ADC enabled without continuous mode or external + trigger that could launch a conversion). */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed + in Complete-sequence/Discontinuous-sequence (main sequence subdivided in + successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: On this STM32 series, ADC group regular number of discontinuous + ranks increment is fixed to one-by-one. */ + + uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion + start. + If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger + is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ - uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) - or in continuous mode (DMA transfer unlimited, whatever number of conversions). - This parameter can be set to ENABLE or DISABLE. - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA + transfer stops when number of conversions is reached) or in continuous + mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ENABLE or DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. + Otherwise an overrun will be triggered when DMA buffer maximum + pointer is reached. */ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear - end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function - HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). + Note: In case of overrun set to data preserved and usage with programming model + with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of + conversion flags, this induces the release of the preserved data. If + needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), + placed in user program code (called before end of conversion flags clear) Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data - overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ + - Usage with ADC conversion by polling for event or interruption: Error is + reported only if overrun is set to data preserved. If overrun is set to + data overwritten, user can willingly not read all the converted data, + this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun + setting (DMA is expected to process all data from data register). */ uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, + each channel can use one of these two settings. On some other STM32 devices + this parameter in channel wise and is located into ADC channel + initialization structure. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, + TS_vbat, TS_temp (values rough order: few tens of microseconds). */ uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, + each channel can use one of these two settings. On some other STM32 devices + this parameter in channel wise and is located into ADC channel + initialization structure. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, + TS_vbat, TS_temp (values rough order: few tens of microseconds). */ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ + Note: This parameter can be modified only if there is no conversion is + ongoing on ADC group regular. */ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ + Caution: this setting overwrites the previous oversampling configuration + if oversampling is already enabled. */ uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. @@ -225,16 +286,19 @@ typedef struct * ADC state can be either: * - For all parameters: ADC disabled or enabled without conversion on going on regular group. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) - * on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL - Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ + Note: Depending on devices and ADC instances, some channels may not be available + on device package pins. Refer to device datasheet for channels + availability. */ - uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank. + uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its + conversion rank. This parameter is dependent on ScanConvMode: - sequencer configured to fully configurable: Channels ordering into each rank of scan sequence: @@ -242,18 +306,26 @@ typedef struct - sequencer configured to not fully configurable: rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. + Despite the channel rank is fixed, this parameter allow an additional + possibility: to remove the selected rank (selected channel) from sequencer. This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON - Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings. - - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Note: On this STM32 family, two different sampling time settings are available + (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), + each channel can use one of these two settings. + + Note: In case of usage of internal measurement channels (VrefInt/Vbat/ + TempSensor), sampling time constraints must be respected (sampling time + can be adjusted in function of ADC clock frequency and sampling time + setting) Refer to device datasheet for timings values. */ } ADC_ChannelConfTypeDef; @@ -262,48 +334,62 @@ typedef struct * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: - * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular. + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion + on going on ADC groups regular. * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. */ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. - For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') - For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels + by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls + of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. - For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. - For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all + channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying + successively the AWD init structure. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. - For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). - For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' + is configured on single channel (only 1 channel can be + monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, + call successively the function HAL_ADC_AnalogWDGConfig() + for each channel to be added (or removed with value + 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. - Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. */ + /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. - Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored.*/ + /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): - ADC data register bitfield [15:4] (12 most significant bits). */ + ADC data register bitfield [15:4] (12 most significant bits).*/ } ADC_AnalogWDGConfTypeDef; /** @defgroup ADC_States ADC States @@ -321,7 +407,7 @@ typedef struct /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to internal process (ex : calibration) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ @@ -330,17 +416,25 @@ typedef struct #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur + (either by continuous mode, external trigger, low power + auto power-on (if feature available), multimode ADC master + control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag + raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/ -#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group + injected is ongoing or can occur (either by auto-injection + mode, external trigger, low power auto power-on (if feature + available), multimode ADC master control (if feature + available))*/ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data + available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow + occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ @@ -348,7 +442,9 @@ typedef struct #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave + state, controlled by another ADC master (when feature + available) */ /** @@ -364,17 +460,20 @@ typedef struct __ADC_HandleTypeDef typedef struct #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { - ADC_TypeDef *Instance; /*!< Register base address */ - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - __IO uint32_t ErrorCode; /*!< ADC Error code */ - - uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + HAL_LockTypeDef Lock; /*!< ADC locking object */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks + setting, used in mode "fully configurable" (refer to + parameter 'ScanConvMode') */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ - void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer + callback */ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ @@ -438,22 +537,38 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ -#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ - -#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ -#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ -#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ -#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ -#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ -#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ -#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ -#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ -#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ -#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ -#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ -#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock + without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler + configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock + with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock + with prescaler division by 4 */ + +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without + prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler + division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler + division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler + division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler + division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler + division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler + division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler + division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler + division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler + division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler + division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler + division by 256 */ /** * @} */ @@ -472,8 +587,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -494,14 +611,23 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* as default setting equivalent to scan enable. */ /* In case of migration from another STM32 device, the user will be */ /* warned of change of setting choices with assert check. */ -#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */ -#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */ - -#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ -#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ - -#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */ -#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */ +/* Sequencer set to fully configurable */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: + only the rank 1 is enabled (no scan sequence on several ranks) */ +#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: + sequencer length and each rank affectation to a channel are configurable. */ + +/* Sequencer set to not fully configurable */ +#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, + channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ + | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, + channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ +#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ /** * @} */ @@ -510,13 +636,27 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< Software start. */ +/** ADC group regular conversion trigger from external peripheral */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< TIM1 TRGO. Trigger edge set to + rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture + compare: input capture or output + capture). Trigger edge set to + rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< TIM2 TRGO. Trigger edge set to + rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< TIM2 channel 4 event (capture + compare: input capture or output + capture). Trigger edge set to + rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< TIM2 channel 3 event (capture + compare: input capture or output + capture). Trigger edge set to + rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< External interrupt line 11. Trigger + edge set to rising edge (default + setting). */ /** * @} */ @@ -524,10 +664,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger + detection disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular trigger + polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular trigger + polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular trigger + polarity set to both rising and + falling edges */ /** * @} */ @@ -544,8 +689,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ +/** + * @brief ADC group regular behavior in case of overrun + */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of + overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of + overrun: data overwritten */ /** * @} */ @@ -553,17 +703,24 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ -#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */ - -#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ -#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ -#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ -#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ -#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ -#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ -#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ -#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of ranks in + the sequence is defined by number of channels enabled, rank + of each channel is defined by channel number (channel 0 fixed + on rank 0, channel 1 fixed on rank1, ...). + Setting relevant if parameter "ScanConvMode" is set to + sequencer not fully configurable. */ +#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from sequencer. + Setting relevant if parameter "ScanConvMode" is set to + sequencer not fully configurable. */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ /** * @} */ @@ -571,8 +728,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels * @{ */ -#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ -#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ +#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of + channels: sampling time nb 1 */ +#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of + channels: sampling time nb 2 */ /** * @} */ @@ -580,14 +739,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ -#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ -#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ -#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ -#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ -#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ +#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ /** * @} */ @@ -595,28 +754,30 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number * @{ */ -#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ -#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ -#define ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_DACCH1) /*!< ADC internal channel connected to DAC channel 1. */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel Internal voltage reference*/ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: + Vbat voltage through a divider ladder of + factor 1/3 to have Vbat always below Vdda. */ +#define ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_DACCH1) /*!< Internal channel DAC channel 1. */ /** * @} */ @@ -634,9 +795,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a + regular group, single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to + regular group, all channels */ /** * @} */ @@ -644,14 +807,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +/** + * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed + * to result as the ADC oversampling conversion data (before potential shift) + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ /** * @} */ @@ -659,15 +826,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ -#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +/** + * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling + * conversion data) + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ /** * @} */ @@ -675,8 +846,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: + continuous mode (all conversions of + OVS ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: + discontinuous mode (each conversion of + OVS ratio needs a trigger) */ /** * @} */ @@ -684,8 +859,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode * @{ */ -#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ -#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ + +/** + * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion + * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion + * start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + */ +#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ +#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ /** * @} */ @@ -693,28 +875,33 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_Event_type ADC Event type * @{ */ +/** + * @note Analog watchdog 1 is available on all stm32 series + * Analog watchdog 2 and 3 are not available on all series + */ #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ -#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ -#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ /** * @} */ -#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility + with other STM32 devices having only one analog watchdog */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ #define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< overrun interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< Analog watchdog 3 interrupt source (additional analog watchdog) */ /** * @} */ @@ -1005,7 +1192,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) -#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */ +/* Internal definition to differentiate sequencer setting fixed or configurable */ +#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /** * @} @@ -1265,7 +1453,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (1) On STM32WL, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel + * (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ @@ -1565,11 +1754,14 @@ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). * On STM32WL, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see + parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. @@ -1712,5 +1904,3 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); #endif /* STM32WLxx_HAL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c index 267367d08a5..86332a73a12 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c @@ -5,23 +5,19 @@ * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: - * + Operation functions - * ++ Calibration - * +++ ADC automatic self-calibration - * +++ Calibration factors get or set + * + Peripheral Control functions * Other functions (generic functions) are available in file * "stm32wlxx_hal_adc.c". * ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim @@ -61,6 +57,7 @@ /* Calibration time max = 116 / fADC (refer to datasheet) */ /* = 178 176 CPU cycles */ #define ADC_CALIBRATION_TIMEOUT (178176UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ +#define ADC_DISABLE_TIMEOUT (2UL) /** * @} @@ -105,7 +102,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; - uint32_t backup_setting_adc_dma_transfer; /* Note: Variable not declared as volatile because register read is already declared as volatile */ + uint32_t backup_setting_cfgr1; + uint32_t calibration_index; + uint32_t calibration_factor_accumulated = 0; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -125,37 +125,74 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - /* Disable ADC DMA transfer request during calibration */ + /* Manage settings impacting calibration */ + /* - Disable ADC mode auto power-off */ + /* - Disable ADC DMA transfer request during calibration */ /* Note: Specificity of this STM32 series: Calibration factor is */ /* available in data register and also transferred by DMA. */ /* To not insert ADC calibration factor among ADC conversion data */ /* in array variable, DMA transfer must be disabled during */ /* calibration. */ - backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); - CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); - /* Start ADC calibration */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL); + /* ADC calibration procedure */ + /* Note: Perform an averaging of 8 calibrations for optimized accuracy */ + for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++) + { + /* Start ADC calibration */ + LL_ADC_StartCalibration(hadc->Instance); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } - /* Wait for calibration completion */ - while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance); + } + /* Compute average */ + calibration_factor_accumulated /= calibration_index; + /* Apply calibration factor */ + LL_ADC_Enable(hadc->Instance); + LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated); + LL_ADC_Disable(hadc->Instance); + + /* Wait for ADC effectively disabled before changing configuration */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while (LL_ADC_IsEnabled(hadc->Instance) != 0UL) { - wait_loop_index++; - if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - __HAL_UNLOCK(hadc); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } - /* Restore ADC DMA transfer request after calibration */ - SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); + /* Restore configuration after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, @@ -345,5 +382,3 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.h index f2c20425e83..26cc974f604 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -184,6 +183,3 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *had #endif #endif /* STM32WLxx_HAL_ADC_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c index ccde72415fd..c5b40c69c4b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c @@ -6,11 +6,20 @@ * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: * + Initialization and de-initialization functions - * + Start/Stop operation functions in polling mode - * + Start/Stop operation functions in interrupt mode (through EXTI interrupt) * + Peripheral control functions * + Peripheral state functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ================================================================================ ##### COMP Peripheral features ##### @@ -145,18 +154,6 @@ @endverbatim ****************************************************************************** - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -378,7 +375,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_C2_EXTI_EnableEvent_0_31(exti_line); #else LL_EXTI_EnableEvent_0_31(exti_line); -#endif +#endif /* CORE_CM0PLUS */ } else { @@ -386,7 +383,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_C2_EXTI_DisableEvent_0_31(exti_line); #else LL_EXTI_DisableEvent_0_31(exti_line); -#endif +#endif /* CORE_CM0PLUS */ } /* Configure EXTI interrupt mode */ @@ -396,7 +393,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_C2_EXTI_EnableIT_0_31(exti_line); #else LL_EXTI_EnableIT_0_31(exti_line); -#endif +#endif /* CORE_CM0PLUS */ } else { @@ -404,7 +401,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_C2_EXTI_DisableIT_0_31(exti_line); #else LL_EXTI_DisableIT_0_31(exti_line); -#endif +#endif /* CORE_CM0PLUS */ } } else @@ -414,14 +411,14 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_C2_EXTI_DisableEvent_0_31(exti_line); #else LL_EXTI_DisableEvent_0_31(exti_line); -#endif +#endif /* CORE_CM0PLUS */ /* Disable EXTI interrupt mode */ #if defined(CORE_CM0PLUS) LL_C2_EXTI_DisableIT_0_31(exti_line); #else LL_EXTI_DisableIT_0_31(exti_line); -#endif +#endif /* CORE_CM0PLUS */ } /* Set HAL COMP handle state */ @@ -917,7 +914,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -965,7 +962,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ if(hcomp == NULL) @@ -985,7 +982,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1012,5 +1009,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.h index 317e76d6ce3..b1215376050 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -100,7 +99,7 @@ typedef enum typedef struct __COMP_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ { COMP_TypeDef *Instance; /*!< Register base address */ COMP_InitTypeDef Init; /*!< COMP required parameters */ @@ -287,7 +286,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer } while(0) #else #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) -#endif +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). @@ -386,7 +385,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1) #else #define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Disable the COMP1 EXTI line in interrupt mode. @@ -396,7 +395,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1) #else #define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Generate a software interrupt on the COMP1 EXTI line. @@ -412,7 +411,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1) #else #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Disable the COMP1 EXTI line in event mode. @@ -422,7 +421,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1) #else #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Check whether the COMP1 EXTI line flag is set. @@ -692,7 +691,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -703,8 +702,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ @@ -726,5 +725,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); #endif #endif /* STM32WLxx_HAL_COMP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.c index a53b98cd122..05673da75a8 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.c @@ -8,6 +8,17 @@ * + Initialization and Configuration functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -87,17 +98,6 @@ | | | 0 bit for subpriority ========================================================================================================================== - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -564,4 +564,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h index 9797364e6b1..2a0ef1b38f9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -179,7 +178,7 @@ typedef struct #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) -#define MPU_TEX_LEVEL4 ((uint8_t)0x04) + /** * @} */ @@ -363,8 +362,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2) || \ - ((TYPE) == MPU_TEX_LEVEL4)) + ((TYPE) == MPU_TEX_LEVEL2)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \ @@ -460,7 +458,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif #endif /* __STM32WLxx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.c index 40a643c0320..27ccf339845 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -29,17 +40,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -62,8 +62,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup CRC_Private_Functions CRC Private Functions - * @{ - */ + * @{ + */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); /** @@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 */ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * + * @brief management functions. + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ /** @addtogroup CRC_Private_Functions - * @{ - */ + * @{ + */ /** * @brief Enter 8-bit input data to the CRC calculator. @@ -514,5 +514,3 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.h index 1f9dcc87ce8..7c785926198 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -60,19 +59,22 @@ typedef struct { uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. - If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. - If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, - e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. - No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of @@ -87,14 +89,18 @@ typedef struct uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. Can be either one of the following values @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion - @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 - @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ } CRC_InitTypeDef; /** @@ -112,12 +118,16 @@ typedef struct uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. Can be either - @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) - - Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error - must occur if InputBufferFormat is not one of the three values listed above */ + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ } CRC_HandleTypeDef; /** * @} @@ -199,15 +209,6 @@ typedef struct * @} */ -/** @defgroup CRC_Aliases CRC API aliases - * @{ - */ -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ -/** - * @} - */ - /** * @} */ @@ -267,7 +268,6 @@ typedef struct #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) @@ -340,5 +340,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); #endif #endif /* STM32WLxx_HAL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.c index d2d759c682c..cc543d7a25d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.c @@ -6,6 +6,17 @@ * This file provides firmware functions to manage the extended * functionalities of the CRC peripheral. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ================================================================================ ##### How to use this driver ##### @@ -16,17 +27,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) { + status = HAL_ERROR; } - - switch (PolyLength) + else { - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - status = HAL_ERROR; - } - break; - - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - status = HAL_ERROR; - break; + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } } if (status == HAL_OK) { @@ -221,5 +230,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.h index 019895b9681..56769eae26c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_crc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -149,5 +148,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ #endif #endif /* STM32WLxx_HAL_CRC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c index 3ba989878cf..42e2cffe4bc 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c @@ -11,6 +11,17 @@ * + CRYP IRQ handler management * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -283,17 +294,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -432,6 +432,8 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef + (+) For interleave mode, API HAL_CRYP_SaveContext and HAL_CRYP_RestoreContext to be used to save then Restore CRYP + configuration and parameters. CRYP_IVCONFIG_ONCE should be selected for KeyIVConfigSkip parameter. @endverbatim * @{ @@ -1082,6 +1084,111 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) } #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +/** + * @brief CRYP peripheral parameters storage when processing Interleaved mode . + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure where CRYP parameters will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Save CRYP handle parameters */ + pcont->DataType = (uint32_t)(hcryp->Init.DataType); + pcont->KeySize = (uint32_t)(hcryp->Init.KeySize); + pcont->pKey = hcryp->Init.pKey; + pcont->pInitVect = hcryp->Init.pInitVect; + pcont->Algorithm = (uint32_t)(hcryp->Init.Algorithm); + pcont->DataWidthUnit = (uint32_t)(hcryp->Init.DataWidthUnit); + pcont->KeyIVConfigSkip = (uint32_t)(hcryp->Init.KeyIVConfigSkip); + pcont->Phase = (uint32_t)(hcryp->Phase); + pcont->KeyIVConfig = (uint32_t)(hcryp->KeyIVConfig); + + /* Save CRYP CR register content */ + pcont->CR_Reg = READ_REG(hcryp->Instance->CR); + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Save Initialisation Vector registers */ + pcont->IVR0_Reg = READ_REG(hcryp->Instance->IVR0); + pcont->IVR1_Reg = READ_REG(hcryp->Instance->IVR1); + pcont->IVR2_Reg = READ_REG(hcryp->Instance->IVR2); + pcont->IVR3_Reg = READ_REG(hcryp->Instance->IVR3); + } + + /* To load Key for next piece of message */ + hcryp->KeyIVConfig = 0; + + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + +} + +/** + * @brief Restore CRYP parameters needed for Interleaved mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure that contains CRYP parameters stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Restore CRYP handle parameters */ + hcryp->Init.DataType = pcont->DataType; + hcryp->Init.KeySize = pcont->KeySize; + hcryp->Init.pKey = pcont->pKey; + hcryp->Init.pInitVect = pcont->pInitVect; + hcryp->Init.Algorithm = pcont->Algorithm; + hcryp->Init.DataWidthUnit = pcont->DataWidthUnit; + hcryp->Init.KeyIVConfigSkip = pcont->KeyIVConfigSkip; + hcryp->Phase = pcont->Phase; + hcryp->KeyIVConfig = pcont->KeyIVConfig; + + /* Restore CRYP CR register content */ + WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Restore Initialisation Vector registers */ + WRITE_REG(hcryp->Instance->IVR0, (uint32_t)(pcont->IVR0_Reg)); + WRITE_REG(hcryp->Instance->IVR1, (uint32_t)(pcont->IVR1_Reg)); + WRITE_REG(hcryp->Instance->IVR2, (uint32_t)(pcont->IVR2_Reg)); + WRITE_REG(hcryp->Instance->IVR3, (uint32_t)(pcont->IVR3_Reg)); + } + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} + /** * @} */ @@ -1209,7 +1316,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1309,7 +1416,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1408,7 +1515,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1518,7 +1625,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1628,7 +1735,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1754,7 +1861,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1994,7 +2101,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)|| (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { if (hcryp->KeyIVConfig == 1U) { @@ -2025,7 +2132,15 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); } } /* if (DoKeyIVConfig == 1U) */ - + else + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2141,7 +2256,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { if (hcryp->KeyIVConfig == 1U) { @@ -2219,7 +2334,62 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); } } /* if (DoKeyIVConfig == 1U) */ - + else /* if (dokeyivconfig == 0U) */ + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & error code*/ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & Key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } + } + else /*Algorithm CTR */ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + } + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -5590,4 +5760,3 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.h index 9bc4a1fe5a5..b1ee0369d64 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,7 +106,7 @@ typedef enum typedef struct __CRYP_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ { AES_TypeDef *Instance; /*!< AES Register base address */ @@ -197,6 +196,29 @@ typedef struct } CRYP_HandleTypeDef; +/** + * @brief CRYP Context Structure definition + */ + +typedef struct +{ + uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */ + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */ + uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */ + uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */ + uint32_t Phase; /*!< CRYP peripheral phase */ + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */ + uint32_t CR_Reg; /*!< CRYP CR register */ + uint32_t IVR0_Reg; /*!< CRYP IVR0 register */ + uint32_t IVR1_Reg; /*!< CRYP IVR1 register */ + uint32_t IVR2_Reg; /*!< CRYP IVR2 register */ + uint32_t IVR3_Reg; /*!< CRYP IVR3 register */ + +} CRYP_ContextTypeDef; + #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition * @brief HAL CRYP Callback ID enumeration definition @@ -352,6 +374,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point #define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ #define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ +#define CRYP_IVCONFIG_ONCE 0x00000004U /*!< Peripheral IV configuration do once for interleave mode */ /** * @} @@ -512,6 +535,9 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp); #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont); +HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont); + /** * @} */ @@ -577,7 +603,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((DATATYPE) == CRYP_DATATYPE_1B)) #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ - ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE) || \ + ((CONFIG) == CRYP_IVCONFIG_ONCE)) #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ (((((ALGO) == CRYP_AES_CTR)) && \ @@ -644,5 +671,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); #endif #endif /* STM32WLxx_HAL_CRYP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.c index 116b02a773d..292f7497787 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.c @@ -9,13 +9,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -385,5 +384,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.h index 451ddd74966..3e8e779d87c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -129,5 +128,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); #endif #endif /* STM32WLxx_HAL_CRYP_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c index f712cd18c22..8f489dc2278 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### @@ -53,13 +64,6 @@ (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. - *** DAC connect feature *** - =============================== - [..] - Each DAC channel can be connected internally. - To connect, use - sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; - *** GPIO configurations guidelines *** ===================== [..] @@ -142,7 +146,7 @@ DAC_OUTx = VREF+ * DOR / 4095 (+) with DOR is the Data Output Register [..] - VEF+ is the input voltage reference (refer to the device datasheet) + VREF+ is the input voltage reference (refer to the device datasheet) [..] e.g. To set DAC_OUT1 to 0.7V, use (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V @@ -209,7 +213,7 @@ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions HAL_DAC_RegisterCallback() to register a user callback, + Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -220,7 +224,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default + Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -231,12 +235,12 @@ (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DAC_Init - and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit + reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init + and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -244,8 +248,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit - or HAL_DAC_Init function. + using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit + or @ref HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -265,17 +269,6 @@ (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -355,8 +348,6 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; - - if (hdac->MspInitCallback == NULL) { hdac->MspInitCallback = HAL_DAC_MspInit; @@ -558,7 +549,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @param pData The destination peripheral Buffer address. + * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: @@ -567,7 +558,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; @@ -608,16 +599,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } } - /* Enable the DMA channel */ /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); @@ -652,8 +640,6 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { - HAL_StatusTypeDef status; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -666,25 +652,16 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Disable the DMA channel */ /* Disable the DMA channel */ - status = HAL_DMA_Abort(hdac->DMA_Handle1); + (void)HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); - /* Check if DMA Channel effectively disabled */ - if (status != HAL_OK) - { - /* Update DAC state machine to error */ - hdac->State = HAL_DAC_STATE_ERROR; - } - else - { - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - } + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -697,22 +674,25 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + uint32_t itsource = hdac->Instance->CR; + uint32_t itflag = hdac->Instance->SR; + + if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - /* Set DAC error code to chanel1 DMA underrun error */ + /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -741,7 +721,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -853,13 +833,17 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { + uint32_t result; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); + result = hdac->Instance->DOR1; + /* Returns the DAC channel data output register value */ - return hdac->Instance->DOR1; + return result; } /** @@ -872,8 +856,10 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; uint32_t tickstart; @@ -902,10 +888,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; + /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) - /* Sample on old configuration */ { - /* SampleTime */ /* Get timeout */ tickstart = HAL_GetTick(); @@ -915,22 +900,27 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } - HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; /* HoldTime */ - MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), + (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ - MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), + (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) @@ -976,7 +966,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -985,7 +975,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf __HAL_UNLOCK(hdac); /* Return function status */ - return HAL_OK; + return status; } /** @@ -1014,7 +1004,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1027,7 +1017,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval DAC Error Code */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } @@ -1051,6 +1041,8 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) /** * @brief Register a User DAC Callback * To be used instead of the weak (surcharged) predefined callback + * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1077,9 +1069,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1136,14 +1125,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback * DAC Callback is redirected to the weak (surcharged) predefined callback + * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1160,9 +1149,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1227,8 +1213,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -1314,9 +1298,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* DAC */ #endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.h index 5b336b93b97..908ef5e9cd7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -64,7 +63,7 @@ typedef enum typedef struct __DAC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ { DAC_TypeDef *Instance; /*!< Register base address */ @@ -79,13 +78,13 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -122,7 +121,7 @@ typedef struct uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ - uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . + uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode @@ -132,9 +131,7 @@ typedef struct uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ - } DAC_ChannelConfTypeDef; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -278,6 +275,20 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @} */ +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define DAC_DELAY_STARTUP_US (8UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Macros DAC Exported Macros @@ -352,7 +363,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @retval State of interruption (SET or RESET) */ -#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. * @param __HANDLE__ specifies the DAC handle. @@ -426,12 +438,10 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); - void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); - HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); @@ -454,9 +464,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA * @{ */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); - -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -465,8 +475,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} @@ -501,7 +511,4 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif -#endif /*STM32WLxx_HAL_DAC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +#endif /* STM32WLxx_HAL_DAC_H */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.c index e1c02f9d53f..f5c872a669a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.c @@ -2,25 +2,30 @@ ****************************************************************************** * @file stm32wlxx_hal_dac_ex.c * @author MCD Application Team - * @brief DAC HAL module driver. + * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - *** Dual mode IO operation *** - ============================== - (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : - Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in - Channel 1 and Channel 2. - *** Signal generation operation *** =================================== + [..] (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @@ -31,17 +36,6 @@ at least one time after reset). @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -64,6 +58,16 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/* Delay for DAC minimum trimming time. */ +/* Note: minimum time needed between two calibration steps */ +/* The delay below is specified under conditions: */ +/* - DAC channel output buffer enabled */ +/* Literal set to maximum value (refer to device datasheet, */ +/* electrical characteristics, parameter "tTRIM"). */ +/* Unit: us */ +#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -128,7 +132,8 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 hdac->State = HAL_DAC_STATE_BUSY; /* Enable the triangle wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -176,7 +181,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -201,7 +207,6 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t * @retval HAL status * @note Calibration runs about 7 ms. */ - HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -209,6 +214,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo __IO uint32_t tmp; uint32_t trimmingvalue; uint32_t delta; + __IO uint32_t wait_loop_index; /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration; @@ -263,9 +269,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while(wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { @@ -285,13 +297,19 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1U); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while(wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* OPAMP_CSR_OUTCAL is actually one value more */ + /* Trimming is actually one value more */ trimmingvalue++; /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); @@ -325,7 +343,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo * @param NewTrimmingValue DAC new trimming value * @retval HAL status */ - HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) { @@ -367,7 +384,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * @retval Trimming value : range: 0->31 * */ -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -395,5 +412,3 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.h index 4fdd710d035..ea7d5490776 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,6 +81,7 @@ extern "C" { * @} */ + /** * @} */ @@ -176,7 +176,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel); /** * @} @@ -200,6 +200,4 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); } #endif -#endif /*STM32WLxx_HAL_DAC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32WLxx_HAL_DAC_EX_H */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h index 010f9e02c98..0e803376d58 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -28,7 +27,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wlxx.h" -#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ #include /* Exported types ------------------------------------------------------------*/ @@ -208,5 +207,3 @@ typedef enum #endif #endif /* ___STM32WLxx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c index ee221a4795e..96b01d18274 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -73,17 +84,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -229,8 +229,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) } else { - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGen = NULL; + hdma->DMAmuxRequestGenStatus = NULL; hdma->DMAmuxRequestGenStatusMask = 0U; } @@ -312,8 +312,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGen = NULL; + hdma->DMAmuxRequestGenStatus = NULL; hdma->DMAmuxRequestGenStatusMask = 0U; /* Clean callbacks */ @@ -460,7 +460,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; } - if (hdma->DMAmuxRequestGen != 0U) + if (hdma->DMAmuxRequestGen != NULL) { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ @@ -526,7 +526,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if (hdma->DMAmuxRequestGen != 0U) + if (hdma->DMAmuxRequestGen != NULL) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ @@ -580,7 +580,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if (hdma->DMAmuxRequestGen != 0U) + if (hdma->DMAmuxRequestGen != NULL) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ @@ -688,7 +688,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level } /*Check for DMAMUX Request generator (if used) overrun status */ - if (hdma->DMAmuxRequestGen != 0U) + if (hdma->DMAmuxRequestGen != NULL) { /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) @@ -831,7 +831,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback Pointer to private callbacsk function which has pointer to + * @param pCallback Pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1211,7 +1211,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if (hdma->DMAmuxRequestGen != 0U) + if (hdma->DMAmuxRequestGen != NULL) { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; @@ -1316,5 +1316,3 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h index d281ed43736..fc8db4c424c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -682,5 +681,3 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, ui #endif #endif /* STM32WLxx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.c index 4371d4237ca..b6c33ef11b9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.c @@ -7,6 +7,17 @@ * functionalities of the DMA Extension peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -26,17 +37,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -158,7 +158,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, H /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ - if (hdma->DMAmuxRequestGen == 0U) + if (hdma->DMAmuxRequestGen == NULL) { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; @@ -316,5 +316,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.h index 8fcb59746ba..940de25ea10 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -264,5 +263,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #endif #endif /* STM32WLxx_HAL_DMA_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c index 74bfae77d61..b5f69c27bb8 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c @@ -7,7 +7,17 @@ * functionalities of the General Purpose Input/Output (EXTI) peripheral: * + Initialization and de-initialization functions * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * + ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### @@ -70,17 +80,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -108,8 +107,8 @@ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ -#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */ -#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ +#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ /** * @} */ @@ -124,8 +123,8 @@ */ /** @addtogroup EXTI_Exported_Functions_Group1 - * @brief Configuration functions - * + * @brief Configuration functions + * @verbatim =============================================================================== ##### Configuration functions ##### @@ -224,7 +223,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); #else regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ regval = *regaddr; /* Mask or set line */ @@ -245,7 +244,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); #else regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ regval = *regaddr; /* Mask or set line */ @@ -290,7 +289,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); - /* Store handle line number to configiguration structure */ + /* Store handle line number to configuration structure */ pExtiConfig->Line = hexti->Line; /* compute line register offset and line mask */ @@ -303,7 +302,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); #else regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ regval = *regaddr; /* Check if selected line is enable */ @@ -321,7 +320,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); #else regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ regval = *regaddr; /* Check if selected line is enable */ @@ -360,7 +359,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { regval = SYSCFG->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24u); + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } } @@ -400,7 +399,7 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); #else regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ regval = (*regaddr & ~maskline); *regaddr = regval; @@ -409,7 +408,7 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); #else regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ regval = (*regaddr & ~maskline); *regaddr = regval; @@ -496,8 +495,8 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin */ /** @addtogroup EXTI_Exported_Functions_Group2 - * @brief EXTI IO functions. - * + * @brief EXTI IO functions. + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -648,5 +647,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.h index e5b79290c06..20cbd8df50e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -127,7 +126,7 @@ typedef struct #else #define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) #define EXTI_LINE_37 (EXTI_RESERVED | EXTI_REG2 | 0x05u) -#endif +#endif /* DUAL_CORE */ #define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u) #if defined (DUAL_CORE) #define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u) @@ -137,7 +136,7 @@ typedef struct #define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) #define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) #define EXTI_LINE_41 (EXTI_RESERVED | EXTI_REG2 | 0x09u) -#endif +#endif /* DUAL_CORE */ #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) #define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) @@ -247,14 +246,14 @@ typedef struct * @{ */ #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ - (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) @@ -326,5 +325,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); #endif #endif /* STM32WLxx_HAL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.c index 9e6729889b4..0ff8413932f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.c @@ -9,6 +9,17 @@ * + Memory Control functions * + Peripheral Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FLASH peripheral features ##### @@ -75,17 +86,6 @@ (+) Monitor the Flash flags status @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -763,4 +763,3 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h index 0fbe16b854a..2f5023cf57a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1009,4 +1008,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #endif /* STM32WLxx_HAL_FLASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.c index 0813233a634..50333c2e1f7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.c @@ -7,6 +7,17 @@ * functionalities of the FLASH extended peripheral: * + Extended programming operations functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### Flash Extended features ##### @@ -74,17 +85,6 @@ (++) Returns if the FLASH registers are protected against non-privilege accesses @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -1371,4 +1371,3 @@ static uint32_t FLASH_OB_GetSecureMode(uint32_t Reg, uint32_t Bit, uint32_t Valu * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.h index ad9d96a9f66..166edb6ce94 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -130,4 +129,3 @@ void FLASH_PageErase(uint32_t Page); #endif /* STM32WLxx_HAL_FLASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c index a51154c5037..8a6035f0574 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c @@ -7,7 +7,17 @@ * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### @@ -73,6 +83,10 @@ (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not @@ -89,17 +103,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -230,6 +233,23 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2u] = temp; + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + /* Clear EXTI line configuration */ #ifdef CORE_CM0PLUS temp = EXTI->C2IMR1; @@ -262,23 +282,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) #else EXTI->EMR1 = temp; #endif /* CORE_CM0PLUS */ - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR1; - temp &= ~(iocurrent); - if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) - { - temp |= iocurrent; - } - EXTI->RTSR1 = temp; - - temp = EXTI->FTSR1; - temp &= ~(iocurrent); - if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) - { - temp |= iocurrent; - } - EXTI->FTSR1 = temp; } } @@ -400,11 +403,9 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) /** * @brief Set or clear the selected data port bit. - * * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family * @param GPIO_Pin specifies the port bit to be written. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). @@ -430,6 +431,33 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin } } +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + /** * @brief Toggle the specified GPIO pin. * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WLxx family @@ -539,5 +567,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h index 332a7c379a0..6a1f23ea850 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -241,6 +240,9 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ @@ -296,6 +298,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); @@ -322,5 +325,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif #endif /* STM32WLxx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio_ex.h index f6f2897848f..4e634ee2ba4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -180,5 +179,3 @@ extern "C" { #endif #endif /* STM32WLxx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c index fee8189027b..0172060db82 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c @@ -10,6 +10,17 @@ * + TZSC and TZSC-MPCWM Lock functions * + TZIC Initialization and Configuration functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GTZC main features ##### @@ -40,7 +51,6 @@ (++) Privileged watermark for internal memories (++) Secure and privileged access mode for securable peripherals - ============================================================================== ##### How to use this driver ##### ============================================================================== [..] @@ -65,17 +75,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -755,4 +754,4 @@ __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId) * @} */ #endif /* GTZC_TZSC */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h index d3aa3be60ad..39f8a98277b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -322,4 +321,4 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); #endif #endif /* STM32WLxx_HAL_GTZC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c index 1f3bc9323e8..aaa669c9aa2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c @@ -14,6 +14,17 @@ * + IRQ handler management * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -23,9 +34,9 @@ (++) the semaphore ID from 0 to 15 (++) the process ID from 0 to 255 (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter : - (++) the semaphore ID from 0 to 15. Note that the process ID value is implicitly assumed as zero + (++) the semaphore ID from 0_ID to 15. Note that the process ID value is implicitly assumed as zero (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter : - (++) the semaphore ID from 0 to 15 + (++) the semaphore ID from 0_ID to 15 (++) It returns 1 if the given semaphore is taken otherwise (Free) zero (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters : (++) the semaphore ID from 0 to 15 @@ -71,17 +82,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -101,6 +101,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #if defined(DUAL_CORE) +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + #ifndef HSEM_R_MASTERID #define HSEM_R_MASTERID HSEM_R_COREID #endif @@ -112,6 +116,10 @@ #ifndef HSEM_CR_MASTERID #define HSEM_CR_MASTERID HSEM_CR_COREID #endif + +/** + * @} + */ #endif /* DUAL_CORE */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -359,5 +367,3 @@ __weak void HAL_HSEM_FreeCallback(uint32_t SemMask) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h index 3455d0e7010..2e83042401f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -130,12 +129,12 @@ extern "C" { HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); /* HSEM semaphore fast take (lock) using 1-Step method ***********************/ HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); -/* HSEM Check semaphore state Taken or not **********************************/ -uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); /* HSEM Release **************************************************************/ void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); /* HSEM Release All************************************************************/ void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); +/* HSEM Check semaphore state Taken or not **********************************/ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); /** * @} @@ -206,5 +205,3 @@ void HAL_HSEM_IRQHandler(void); #endif #endif /* STM32WLxx_HAL_HSEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c index 1bf9eb747a1..8b698e21a6e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -147,7 +158,7 @@ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointerHAL_I2C_AbortCpltCallback() + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can @@ -156,13 +167,11 @@ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using - HAL_I2C_Slave_Seq_Transmit_IT() - or using HAL_I2C_Slave_Seq_Transmit_DMA() + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using - HAL_I2C_Slave_Seq_Receive_IT() - or usingHAL_I2C_Slave_Seq_Receive_DMA() + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can @@ -308,18 +317,6 @@ (@) You can refer to the I2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -404,6 +401,9 @@ */ /* Private macro -------------------------------------------------------------*/ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -438,10 +438,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -454,8 +458,8 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); @@ -707,6 +711,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) /** * @brief Register a User I2C Callback * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be registered @@ -737,8 +743,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -827,14 +831,14 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } /** * @brief Unregister an I2C Callback * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be unregistered @@ -857,9 +861,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) @@ -947,8 +948,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -971,8 +970,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -987,8 +984,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1003,9 +998,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1019,8 +1011,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1434,22 +1424,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1514,6 +1509,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; hi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1556,6 +1552,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } return HAL_ERROR; @@ -1568,6 +1565,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -2639,9 +2637,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2661,9 +2656,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2672,30 +2664,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2733,9 +2724,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2755,9 +2743,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2766,29 +2751,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2801,7 +2786,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); return HAL_OK; } @@ -2825,8 +2810,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2848,9 +2831,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2859,28 +2839,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } if (hi2c->hdmatx != NULL) { @@ -2915,12 +2903,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2928,11 +2912,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -2972,8 +2956,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2995,9 +2977,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -3006,25 +2985,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } if (hi2c->hdmarx != NULL) @@ -3060,11 +3049,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3072,11 +3058,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3319,6 +3305,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -3765,6 +3755,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3824,7 +3817,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3861,6 +3855,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4002,7 +3998,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4012,15 +4009,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -4042,6 +4039,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4101,7 +4101,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4138,6 +4139,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4279,7 +4282,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4289,15 +4293,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4870,6 +4874,143 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5151,6 +5292,145 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5192,7 +5472,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5204,7 +5484,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5815,7 +6095,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->hdmatx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) @@ -5825,7 +6105,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->hdmarx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); } } else @@ -6288,7 +6568,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6347,11 +6627,12 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles I2C Communication Timeout. + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -6392,8 +6673,8 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6430,8 +6711,8 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6465,8 +6746,8 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6484,13 +6765,22 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } else { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -6517,66 +6807,133 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /** - * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @brief This function handles errors detection during an I2C Communication. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) { - /* In case of Soft End condition, generate the STOP condition */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - /* Wait until STOP Flag is reset */ + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; - return HAL_ERROR; + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |=HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } } } } - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + error_code |= HAL_I2C_ERROR_AF; + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= error_code; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** @@ -6606,14 +6963,16 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, + MODIFY_REG(hi2c->Instance->CR2, \ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request)); + I2C_CR2_START | I2C_CR2_STOP)), tmp); } /** @@ -6674,6 +7033,12 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ @@ -6792,5 +7157,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h index ce949ac6a0d..5037fbf7ee4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -218,6 +217,10 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ @@ -834,5 +837,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* STM32WLxx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c index bb0332432e1..e61e3c95361 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c @@ -5,8 +5,21 @@ * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: - * + Extended features functions + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2C peripheral Extended features ##### @@ -32,18 +45,6 @@ (++) HAL_I2CEx_EnableFastModePlus() (++) HAL_I2CEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -343,7 +344,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - /** * @} */ @@ -356,5 +356,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h index fd5e4b0c0bb..17c729f5af8 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -166,5 +165,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32WLxx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c index 8890e8ab334..f8be035a357 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -168,18 +179,7 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ @@ -1854,4 +1854,3 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, #endif /* HAL_I2S_MODULE_ENABLED */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.h index 13847174233..8665b1725fd 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -551,4 +550,3 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #endif /* STM32WLxx_HAL_I2S_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.c index 5aa40c734d5..accd95ebbda 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.c @@ -9,6 +9,17 @@ * + Initialization and de-initialization functions * + Configuration, notification and interrupts handling * + Peripheral State and Error functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -37,18 +48,7 @@ or when a message has been retrieved from a chosen channel by calling the HAL_IPCC_NotifyCPU() API. -@endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + @endverbatim ****************************************************************************** */ @@ -773,9 +773,9 @@ void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance) /** * @} */ -#endif /* IPCC */ + /** * @} */ +#endif /* IPCC */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.h index b0f3b947758..2f739b5624c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_ipcc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -289,4 +288,3 @@ void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_ #endif /* STM32WLxx_HAL_IPCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c index 5f5951dfebb..c6db81dfec7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -40,7 +51,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), the normal or low power mode and the clock prescaler in the hirda handle Init structure. @@ -171,17 +183,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -462,6 +463,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) /** * @brief Register a User IRDA Callback * To be used instead of the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -490,8 +493,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -576,15 +577,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -604,51 +604,50 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) { case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -690,9 +689,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -771,13 +767,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -803,10 +802,10 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. */ #endif /* CORE_CM0PLUS */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -836,7 +835,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->gState = HAL_IRDA_STATE_BUSY_TX; - /* Init tickstart for timeout management*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->TxXferSize = Size; @@ -846,7 +845,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */ } else { @@ -947,7 +946,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - /* Init tickstart for timeout management*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->RxXferSize = Size; @@ -1024,7 +1023,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. */ #endif /* CORE_CM0PLUS */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1130,8 +1129,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + /* Enable the IRDA Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1163,7 +1170,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. */ #endif /* CORE_CM0PLUS */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1314,8 +1321,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1407,7 +1417,10 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_OREFLAG(hirda); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Enable the IRDA DMA Rx request */ @@ -1506,7 +1519,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -1704,7 +1718,8 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised @@ -2296,7 +2311,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ uint32_t temp1; @@ -2313,7 +2328,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } @@ -2401,21 +2416,21 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { case IRDA_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; default: ret = HAL_ERROR; @@ -2425,7 +2440,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { - hirda->Instance->BRR = tmpreg; + hirda->Instance->BRR = (uint16_t)tmpreg; } else { @@ -2448,7 +2463,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - /* Init tickstart for timeout management*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -2483,11 +2498,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) } /** - * @brief Handle IRDA Communication Timeout. + * @brief Handle IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param Flag Specifies the IRDA flag to check. - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -2503,7 +2519,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -2887,7 +2904,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) @@ -2904,7 +2921,7 @@ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); hirda->pTxBuffPtr += 2U; } @@ -3012,4 +3029,4 @@ static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h index 8fa70cd3b9b..a531b8c8fd2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -143,7 +142,7 @@ typedef struct IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ @@ -816,11 +815,11 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); @@ -854,8 +853,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); */ /* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} @@ -879,4 +878,3 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #endif /* STM32WLxx_HAL_IRDA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda_ex.h index 77587817dfe..af2e58480c9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -193,4 +192,3 @@ extern "C" { #endif /* STM32WLxx_HAL_IRDA_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c index d95f3681d14..49021f485f9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c @@ -8,6 +8,17 @@ * + Initialization and Start functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### IWDG Generic features ##### @@ -86,18 +97,6 @@ the reload register @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -125,7 +124,7 @@ the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. The timeout value is multiplied by 1000 to be converted in milliseconds. - LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT + LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ #define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) @@ -281,5 +280,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h index cf6667214f0..3fac9326aec 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -236,5 +235,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); #endif #endif /* STM32WLxx_HAL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c index 9b849c8ec09..ac67d9f5708 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c @@ -11,6 +11,17 @@ * + Reading operation functions. * + Peripheral State functions. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -145,17 +156,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -507,7 +507,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -572,7 +572,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -583,7 +583,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -594,7 +594,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF + * This parameter must be a value between 0x0001 and 0xFFFF * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status @@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -695,7 +695,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -731,7 +731,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Enable Update Event interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -742,7 +742,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -790,7 +790,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -818,7 +818,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -829,7 +829,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -913,7 +913,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -933,6 +933,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -966,7 +967,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Enable Update Event interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -977,7 +978,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM in Set once mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1025,7 +1026,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1053,7 +1054,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1142,7 +1143,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1189,7 +1190,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1200,7 +1201,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Encoder interface. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1250,7 +1251,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1281,7 +1282,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1360,7 +1361,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1397,7 +1398,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable "switch to up direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1410,7 +1411,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1458,7 +1459,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1489,7 +1490,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1502,7 +1503,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1567,7 +1568,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1584,12 +1585,13 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1604,7 +1606,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1615,7 +1617,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1628,8 +1630,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && - (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1655,7 +1657,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1683,7 +1685,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1694,7 +1696,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1710,8 +1712,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && - (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1760,7 +1762,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1777,12 +1779,13 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1802,7 +1805,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Update Event interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1833,7 +1836,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1846,7 +1849,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1859,7 +1862,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2221,9 +2224,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2302,9 +2302,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -2332,55 +2329,63 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; break; case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; break; case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; break; case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; break; case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; break; case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; break; case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; break; case HAL_LPTIM_UPDATE_EVENT_CB_ID : - hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Legacy weak Update event detection Callback */ + /* Legacy weak Update event detection Callback */ + hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; break; case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID : - hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Legacy weak Repetition counter register write complete Callback */ + /* Legacy weak Repetition counter register write complete Callback */ + hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; break; default : @@ -2394,11 +2399,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; default : @@ -2413,9 +2420,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2473,15 +2477,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) { /* Reset the LPTIM callback to the legacy weak callbacks */ - lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ - lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ - lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ - lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ - lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ - lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ - lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Update event detection Callback */ - lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Repetition counter register write complete Callback */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; + lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; + lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2524,10 +2528,13 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpOR; uint32_t tmpRCR; - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ @@ -2658,7 +2665,8 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CFGR = tmpCFGR; hlptim->Instance->OR = tmpOR; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** * @} @@ -2673,5 +2681,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.h index 0807f79569d..0bc2b78acc0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -99,37 +98,39 @@ typedef struct */ typedef struct { - LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ - LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - uint32_t OutputPolarity; /*!< Specifies the Output polarity. - This parameter can be a value of @ref LPTIM_Output_Polarity */ + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ - uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare - values is done immediately or after the end of current period. - This parameter can be a value of @ref LPTIM_Updating_Mode */ + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ - uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event - or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ - uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). - This parameter can be a value of @ref LPTIM_Input1_Source */ + uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). + This parameter can be a value of @ref LPTIM_Input1_Source */ - uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). - Note: This parameter is used only for encoder feature so is used only - for LPTIM1 instance. - This parameter can be a value of @ref LPTIM_Input2_Source */ + uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). + Note: This parameter is used only for encoder feature so is used only + for LPTIM1 instance. + This parameter can be a value of @ref LPTIM_Input2_Source */ - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - Note: When using repetition counter the UpdateMode field must be set to - LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable behavior may occur. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + uint32_t RepetitionCounter;/*!< Specifies the repetition counter value. + Each time the RCR downcounter reaches zero, an update event is + generated and counting restarts from the RCR value (N). + Note: When using repetition counter the UpdateMode field must be + set to LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable + behavior may occur. + This parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. */ } LPTIM_InitTypeDef; /** @@ -393,7 +394,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval None */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -573,40 +574,37 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #if defined(CORE_CM0PLUS) -#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= \ - LPTIM_EXTI_LINE_LPTIM1) -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= \ - ~(LPTIM_EXTI_LINE_LPTIM1)) - -#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= \ - LPTIM_EXTI_LINE_LPTIM2) -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= \ - ~(LPTIM_EXTI_LINE_LPTIM2)) - -#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= \ - LPTIM_EXTI_LINE_LPTIM3) -#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= \ - ~(LPTIM_EXTI_LINE_LPTIM3)) +#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->C2IMR1\ + |= LPTIM_EXTI_LINE_LPTIM1) +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->C2IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) + +#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->C2IMR1\ + |= LPTIM_EXTI_LINE_LPTIM2) +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->C2IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) + +#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->C2IMR1\ + |= LPTIM_EXTI_LINE_LPTIM3) +#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->C2IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM3)) #else -#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= \ - LPTIM_EXTI_LINE_LPTIM1) -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= \ - ~(LPTIM_EXTI_LINE_LPTIM1)) - -#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= \ - LPTIM_EXTI_LINE_LPTIM2) -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= \ - ~(LPTIM_EXTI_LINE_LPTIM2)) - -#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->IMR1 |= \ - LPTIM_EXTI_LINE_LPTIM3) -#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR1 &= \ - ~(LPTIM_EXTI_LINE_LPTIM3)) -#endif +#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1) +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) + +#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2) +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) + +#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM3) +#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM3)) +#endif /* CORE_CM0PLUS */ /** * @} @@ -693,9 +691,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -826,36 +824,38 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) #define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL) -#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ - || \ - (((__INSTANCE__) == LPTIM2) && \ + || \ + (((__INSTANCE__) == LPTIM2) && \ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \ - || \ - (((__INSTANCE__) == LPTIM3) && \ + || \ + (((__INSTANCE__) == LPTIM3) && \ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ - (((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) /** @@ -885,5 +885,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); #endif #endif /* STM32WLxx_HAL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c index edc23a197cc..063b084a93b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c @@ -9,6 +9,17 @@ * + Start an operation * + Retrieve the operation result * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -229,17 +240,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -252,7 +252,7 @@ #if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) /** @defgroup PKA PKA - * @brief PKA HAL module driver. + * @brief PKA HAL module driver. * @{ */ @@ -263,14 +263,14 @@ */ #define PKA_RAM_SIZE 894U #define PKA_RAM_ERASE_TIMEOUT 1000U -/** - * @} - */ /* Private macro -------------------------------------------------------------*/ #define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ TAB[INDEX] = 0UL; \ } while(0) +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -300,7 +300,8 @@ void PKA_ECCMulFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in); void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in); void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1); -void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3); +void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, + const uint8_t *pOp3); /** * @} */ @@ -312,8 +313,8 @@ void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *p */ /** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -324,9 +325,7 @@ void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *p (+) User must implement HAL_PKA_MspInit() function in which he configures all related peripherals resources (CLOCK, IT and NVIC ). - (+) Call the function HAL_PKA_Init() to configure the selected device with - the selected configuration: - (++) Security level + (+) Call the function HAL_PKA_Init() to configure the device. (+) Call the function HAL_PKA_DeInit() to restore the default configuration of the selected PKAx peripheral. @@ -518,7 +517,8 @@ __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, + pPKA_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -678,8 +678,8 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca */ /** @defgroup PKA_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -893,7 +893,8 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT * @param out Output information * @param outExt Additional Output information (facultative) */ -void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt) +void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, + PKA_ECDSASignOutExtParamTypeDef *outExt) { uint32_t size; @@ -931,7 +932,8 @@ HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTy } /** - * @brief Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt. + * @brief Verify the validity of a signature using elliptic curves + * over prime fields in non-blocking mode with Interrupt. * @param hpka PKA handle * @param in Input information * @retval HAL status @@ -1041,7 +1043,7 @@ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckI */ uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka) { - #define PKA_POINT_IS_ON_CURVE 0UL +#define PKA_POINT_IS_ON_CURVE 0UL /* Invert the value of the PKA RAM containing the result of the operation */ return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL; } @@ -1662,8 +1664,8 @@ __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka) */ /** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions - * @brief Peripheral State and Error functions - * + * @brief Peripheral State and Error functions + * @verbatim =============================================================================== ##### Peripheral State and Error functions ##### @@ -1690,7 +1692,7 @@ HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) * @brief Return the PKA error code. * @param hpka PKA handle * @retval PKA error code -*/ + */ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) { /* Return PKA handle error code */ @@ -2012,7 +2014,8 @@ HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t T tickstart = HAL_GetTick(); /* Set the mode and deactivate the interrupts */ - MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, mode << PKA_CR_MODE_Pos); + MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, + mode << PKA_CR_MODE_Pos); /* Start the computation */ hpka->Instance->CR |= PKA_CR_START; @@ -2070,7 +2073,8 @@ HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode) hpka->ErrorCode = HAL_PKA_ERROR_NONE; /* Set the mode and activate interrupts */ - MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE); + MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, + (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE); /* Start the computation */ hpka->Instance->CR |= PKA_CR_START; @@ -2134,8 +2138,9 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); /* Move the Montgomery parameter to PKA RAM */ - PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->expSize / 4UL); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->expSize / 4UL)); + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, + in->OpSize / 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL)); } @@ -2221,11 +2226,13 @@ void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in) __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ - PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, in->modulusSize); + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, + in->modulusSize); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL)); /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ - PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, in->modulusSize); + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, + in->modulusSize); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); /* Move the input parameters signature part r to PKA RAM */ @@ -2344,12 +2351,12 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); /* Move the input parameters Point P coordinate x to PKA RAM */ - PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); /* Move the input parameters Point P coordinate y to PKA RAM */ - PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); } @@ -2391,7 +2398,8 @@ void PKA_ECCMulFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); /* Move the Montgomery parameter to PKA RAM */ - PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, (in->modulusSize + 3UL) / 4UL); + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, + (in->modulusSize + 3UL) / 4UL); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL)); } /** @@ -2443,10 +2451,22 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) */ void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1) { + uint32_t bytetoskip = 0UL; + uint32_t newSize; + if (pOp1 != NULL) { + /* Count the number of zero bytes */ + while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL)) + { + bytetoskip++; + } + + /* Get new size after skipping zero bytes */ + newSize = size - bytetoskip; + /* Get the number of bit per operand */ - hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(size, *pOp1); + hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]); /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size); @@ -2462,7 +2482,8 @@ void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const * @param pOp2 Generic pointer to input data * @param pOp3 Generic pointer to input data */ -void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3) +void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, + const uint8_t *pOp3) { /* Get the number of bit per operand */ hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size); @@ -2502,5 +2523,3 @@ void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *p /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.h index 4b3a194e3ec..e3eec34dd9d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -29,19 +28,19 @@ extern "C" { #include "stm32wlxx_hal_def.h" /** @addtogroup STM32WLxx_HAL_Driver - * @{ - */ + * @{ + */ #if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) /** @addtogroup PKA - * @{ - */ + * @{ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PKA_Exported_Types PKA Exported Types - * @{ - */ + * @{ + */ /** @defgroup HAL_state_structure_definition HAL state structure definition * @brief HAL State structures definition @@ -364,7 +363,7 @@ typedef struct } while(0) #else #define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET) -#endif +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ /** @brief Enable the specified PKA interrupt. * @param __HANDLE__ specifies the PKA Handle @@ -397,7 +396,8 @@ typedef struct * @arg @ref PKA_IT_RAMERR RAM error interrupt enable * @retval The new state of __INTERRUPT__ (SET or RESET) */ -#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified PKA flag is set or not. * @param __HANDLE__ specifies the PKA Handle @@ -408,7 +408,8 @@ typedef struct * @arg @ref PKA_FLAG_RAMERR RAM error * @retval The new state of __FLAG__ (SET or RESET) */ -#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the PKA Handle @@ -459,7 +460,8 @@ void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka); #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, + pPKA_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ @@ -480,7 +482,8 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes); HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout); HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); -void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt); +void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, + PKA_ECDSASignOutExtParamTypeDef *outExt); HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout); HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); @@ -563,5 +566,3 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); #endif #endif /* STM32WLxx_HAL_PKA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c index 86b503d8a24..a77a2626a53 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -112,22 +111,26 @@ void HAL_PWR_DeInit(void) #endif /* Clear all flags */ +#if defined(DUAL_CORE) LL_PWR_WriteReg(SCR, LL_PWR_SCR_CWUF | LL_PWR_SCR_CWRFBUSYF | LL_PWR_SCR_CWPVDF -#if defined(DUAL_CORE) | LL_PWR_SCR_CC2HF -#endif ); - - LL_PWR_WriteReg(EXTSCR, -#ifdef CORE_CM0PLUS - LL_PWR_EXTSCR_C2CSSF #else - LL_PWR_EXTSCR_C1CSSF -#endif + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CWUF + | LL_PWR_SCR_CWRFBUSYF + | LL_PWR_SCR_CWPVDF ); +#endif /* DUAL_CORE */ + +#ifdef CORE_CM0PLUS + LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C2CSSF); +#else + LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C1CSSF); +#endif /* CORE_CM0PLUS */ } @@ -699,4 +702,3 @@ __weak void HAL_PWR_PVDCallback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.h index 179ed09eb35..a69df4ea738 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -582,4 +581,3 @@ void HAL_PWR_PVDCallback(void); #endif /* STM32WLxx_HAL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c index 34613a5d1f1..e42ce056f7e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c @@ -11,13 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1161,4 +1160,3 @@ __weak void HAL_PWREx_PVM3Callback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.h index 27b14329c42..331b20c863b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -651,4 +650,3 @@ void HAL_PWREx_PVM3Callback(void); #endif /* STM32WLxx_HAL_PWR_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c index 27b9281c036..08f8ffdb9e9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### RCC specific features ##### @@ -36,17 +47,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -89,9 +89,13 @@ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ -#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (IOPORT_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__)))) #define __COUNTOF(_A_) (sizeof(_A_) / sizeof(*(_A_))) /** @@ -359,7 +363,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) { - if ((LL_RCC_MSI_IsReady() != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) { return HAL_ERROR; } @@ -385,7 +389,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) else { /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + /* Selects the Multiple Speed oscillator (MSI) clock range. */ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); @@ -400,7 +404,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); - /* Configure the source of time base considering new system clocks settings*/ + /* Configure the source of time base considering new system clocks settings */ status = HAL_InitTick(uwTickPrio); if (status != HAL_OK) { @@ -428,9 +432,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + /* Selects the Multiple Speed oscillator (MSI) clock range. */ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); } @@ -464,7 +468,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) { - if ((LL_RCC_HSE_IsReady() != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) { return HAL_ERROR; } @@ -483,7 +487,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ @@ -497,7 +501,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ @@ -524,14 +528,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not be disabled */ - if ((LL_RCC_HSI_IsReady() != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) { return HAL_ERROR; } /* Otherwise, just the calibration is allowed */ else { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } } @@ -555,7 +559,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else @@ -598,7 +602,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) { /* If LSIRDY is set while LSION is not enabled, - LSIPRE can't be updated */ + LSIPRE can't be updated */ return HAL_ERROR; } @@ -627,7 +631,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ @@ -644,7 +648,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ @@ -695,7 +699,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* LSE oscillator enable */ @@ -714,7 +718,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); @@ -730,7 +734,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); @@ -747,7 +751,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); @@ -761,7 +765,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* LSE oscillator disable */ @@ -800,7 +804,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ @@ -826,7 +830,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ @@ -843,13 +847,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - /* Disable all PLL outputs to save power */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); - - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_RNGCLK | RCC_PLL_ADCCLK); - - - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ @@ -860,6 +858,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } + + /* Disable the PLL source and outputs to save power when PLL is off */ + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); } } else @@ -945,7 +946,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Check that the new number of wait states is taken into account to access the Flash @@ -1092,7 +1093,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* apply system clock switch */ LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* check system clock source switch status */ @@ -1111,7 +1112,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Check that the new number of wait states is taken into account to access the Flash @@ -1130,7 +1131,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); - /* Configure the source of time base considering new system clocks settings*/ + /* Configure the source of time base considering new system clocks settings */ return HAL_InitTick(uwTickPrio); } @@ -1162,7 +1163,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @brief Select the clock source to output on MCO1 pin(PA8). * @note PA8 should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8) + * @arg @ref RCC_MCO1_PA8 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO @@ -1186,23 +1187,31 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef gpio_initstruct; + uint32_t mco_gpio_index; + GPIO_TypeDef * mco_gpio_port; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - /* MCO1 Clock Enable */ - __MCO1_CLK_ENABLE(); - /* Configure the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; + + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); + + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index )); + + /* Configure the MCOx pin in alternate function mode */ + gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); /* Configure the microcontroller clock output (MCO) */ LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); @@ -1211,7 +1220,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /** * @brief Return the SYSCLK frequency. * - * @note The system computed by this function is not the real + * @note The system computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is MSI, function returns values based on MSI range @@ -1254,7 +1263,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) { /* MSI or PLL with MSI source used as system clock source */ - /*Retrieve MSI frequency range in HZ*/ + /* Retrieve MSI frequency range in Hz */ msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? LL_RCC_MSI_GetRange() : @@ -1382,6 +1391,10 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { + uint32_t regvalue; + uint32_t regICSRvalue; + uint32_t regPLLCFGRvalue; + /* Check the parameters */ if (RCC_OscInitStruct != NULL) { @@ -1389,116 +1402,45 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + /* Get register values */ + regvalue = RCC->CR; /* Control register */ + regICSRvalue = RCC->ICSCR; /* Get Internal Clock Sources Calibration register */ + regPLLCFGRvalue = RCC->PLLCFGR; /* Get PLL Configuration register */ /* Get the HSE configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSEBYPPWR) == RCC_CR_HSEBYPPWR) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_PWR; - } - else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - if ((RCC->CR & RCC_CR_HSEPRE) == RCC_CR_HSEPRE) - { - RCC_OscInitStruct->HSEDiv = RCC_HSE_DIV2; - } - else - { - RCC_OscInitStruct->HSEDiv = RCC_HSE_DIV1; - } + RCC_OscInitStruct->HSEState = (regvalue & RCC_HSE_BYPASS_PWR); + RCC_OscInitStruct->HSEDiv = (regvalue & RCC_CR_HSEPRE); /* Get the MSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION) - { - RCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - RCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } - RCC_OscInitStruct->MSICalibrationValue = LL_RCC_MSI_GetCalibTrimming(); - RCC_OscInitStruct->MSIClockRange = LL_RCC_MSI_GetRange(); + RCC_OscInitStruct->MSIState = (regvalue & RCC_CR_MSION); + RCC_OscInitStruct->MSICalibrationValue = ((regICSRvalue & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); + RCC_OscInitStruct->MSIClockRange = (regvalue & RCC_CR_MSIRANGE); /* Get the HSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } + RCC_OscInitStruct->HSIState = (regvalue & RCC_CR_HSION); + RCC_OscInitStruct->HSICalibrationValue = ((regICSRvalue & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); - RCC_OscInitStruct->HSICalibrationValue = LL_RCC_HSI_GetCalibTrimming(); + /* Get the PLL configuration -----------------------------------------------*/ + RCC_OscInitStruct->PLL.PLLState = ((regvalue & RCC_CR_PLLON) >> RCC_CR_PLLON_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLSource = (regPLLCFGRvalue & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (regPLLCFGRvalue & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = ((regPLLCFGRvalue & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (regPLLCFGRvalue & RCC_PLLCFGR_PLLP); + RCC_OscInitStruct->PLL.PLLQ = (regPLLCFGRvalue & RCC_PLLCFGR_PLLQ); + RCC_OscInitStruct->PLL.PLLR = (regPLLCFGRvalue & RCC_PLLCFGR_PLLR); - /* Get the LSE configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY; - } - } - else if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY; - } - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } + /* Get Backup Domain register */ + regvalue = RCC->BDCR; - /* Get the LSI configuration -----------------------------------------------*/ - if (((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } + /* Get the LSE configuration -----------------------------------------------*/ + RCC_OscInitStruct->LSEState = (regvalue & RCC_LSE_BYPASS); - if ((RCC->CSR & RCC_CSR_LSIPRE) == RCC_CSR_LSIPRE) - { - RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128; - } - else - { - RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1; - } + /* Get Control/Status register */ + regvalue = RCC->CSR; - /* Get the PLL configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = LL_RCC_PLL_GetMainSource(); - RCC_OscInitStruct->PLL.PLLM = LL_RCC_PLL_GetDivider(); - RCC_OscInitStruct->PLL.PLLN = LL_RCC_PLL_GetN(); - RCC_OscInitStruct->PLL.PLLP = LL_RCC_PLL_GetP(); - RCC_OscInitStruct->PLL.PLLQ = LL_RCC_PLL_GetQ(); - RCC_OscInitStruct->PLL.PLLR = LL_RCC_PLL_GetR(); + /* Get the LSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->LSIState = (regvalue & RCC_LSI_ON); + RCC_OscInitStruct->LSIDiv = (regvalue & RCC_CSR_LSIPRE); } } @@ -1512,6 +1454,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { + uint32_t regvalue; + /* Check the parameters */ if ((RCC_ClkInitStruct != NULL) && (pFLatency != NULL)) { @@ -1522,25 +1466,31 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->ClockType |= RCC_CLOCKTYPE_HCLK2; #endif /* DUAL_CORE */ + /* Get Clock Configuration Register */ + regvalue = RCC->CFGR; + /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource(); + RCC_ClkInitStruct->SYSCLKSource = (regvalue & RCC_CFGR_SWS); /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler(); + RCC_ClkInitStruct->AHBCLKDivider = (regvalue & RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler(); + RCC_ClkInitStruct->APB1CLKDivider = (regvalue & RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler(); + RCC_ClkInitStruct->APB2CLKDivider = (regvalue & RCC_CFGR_PPRE2); + + /* Get Extended Clock Recovery Register */ + regvalue = RCC->EXTCFGR; #if defined(DUAL_CORE) /* Get the AHBCLK2Divider configuration ------------------------------------*/ - RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler(); + RCC_ClkInitStruct->AHBCLK2Divider = (regvalue & RCC_EXTCFGR_C2HPRE); #endif /* DUAL_CORE */ /* Get the AHBCLK3Divider configuration ------------------------------------*/ - RCC_ClkInitStruct->AHBCLK3Divider = LL_RCC_GetAHB3Prescaler(); + RCC_ClkInitStruct->AHBCLK3Divider = ((regvalue & RCC_EXTCFGR_SHDHPRE) << 4); /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = __HAL_FLASH_GET_LATENCY(); @@ -1718,5 +1668,3 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h index eb82375a157..64d9836e185 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -52,7 +51,8 @@ extern "C" { #define RCC_FLAG_MASK 0x1FU /* Defines Oscillator Masks */ -#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ +#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ + RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ /** @defgroup RCC_Timeout_Value Timeout Values * @{ @@ -118,8 +118,7 @@ extern "C" { #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ ((__PLL__) == RCC_PLL_ON)) -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ - ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) @@ -190,7 +189,7 @@ extern "C" { ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) -#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1)) +#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1_PA8) #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ @@ -235,7 +234,7 @@ typedef struct This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ + This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ @@ -632,8 +631,29 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 0x00000000U /*!< MCO1 index */ -#define RCC_MCO RCC_MCO1 /*!< MCO to be compliant with other families with 1 MCO */ + +/* @cond */ + /* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) + +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +/* @endcond */ + +#define RCC_MCO1_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO1 RCC_MCO1_PA8 + +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO */ /** * @} */ @@ -641,16 +661,16 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ -#define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ -#define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selected as MCO1 source */ -#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selected as MCO1 source */ -#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selected as MCO1 source */ -#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selected as MCO1 source */ -#define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< Main PLLRCLK selected as MCO1 source */ -#define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< LSI selected as MCO1 source */ -#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selected as MCO1 source */ -#define RCC_MCO1SOURCE_PLLPCLK LL_RCC_MCO1SOURCE_PLLPCLK /*!< Main PLLPCLK selected as MCO1 source */ -#define RCC_MCO1SOURCE_PLLQCLK LL_RCC_MCO1SOURCE_PLLQCLK /*!< Main PLLQCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< Main PLLRCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< LSI selected as MCO1 source */ +#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLLPCLK LL_RCC_MCO1SOURCE_PLLPCLK /*!< Main PLLPCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLLQCLK LL_RCC_MCO1SOURCE_PLLQCLK /*!< Main PLLQCLK selected as MCO1 source */ /** * @} */ @@ -658,7 +678,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler * @{ */ -#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ +#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ #define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ #define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ #define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ @@ -2206,7 +2226,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -2397,7 +2417,3 @@ uint32_t HAL_RCC_GetResetSource(void); #endif #endif /* STM32WLxx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c index 4a719257277..c1aa0f3cbcb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1018,36 +1017,11 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { - GPIO_InitTypeDef GPIO_InitStruct; - FlagStatus backupchanged = RESET; - /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); - /* LSCO Pin Clock Enable */ - __LSCO1_CLK_ENABLE(); - - /* Configure the LSCO pin in analog mode */ - GPIO_InitStruct.Pin = LSCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_LSCO; - HAL_GPIO_Init(LSCO1_GPIO_PORT, &GPIO_InitStruct); - - /* Update LSCOSEL clock source in Backup Domain control register */ - if (LL_PWR_IsEnabledBkUpAccess() == 0U) - { - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - + /* Update LSCO selection according to parameter and enable LSCO */ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - - if (backupchanged == SET) - { - HAL_PWR_DisableBkUpAccess(); - } } /** @@ -1056,23 +1030,8 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) */ void HAL_RCCEx_DisableLSCO(void) { - FlagStatus backupchanged = RESET; - - if (LL_PWR_IsEnabledBkUpAccess() == 0U) - { - /* Enable access to the backup domain */ - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - + /* Clear LSCOEN in BDCR register */ LL_RCC_LSCO_Disable(); - - /* Restore previous configuration */ - if (backupchanged == SET) - { - /* Disable access to the backup domain */ - HAL_PWR_DisableBkUpAccess(); - } } /** @@ -1221,6 +1180,3 @@ static uint32_t RCC_PLL_GetFreqDomain_Q(void) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h index d14a81ed26a..b02b7882320 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -347,7 +346,7 @@ typedef struct /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ -#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ /** * @} */ @@ -355,7 +354,7 @@ typedef struct /** @defgroup RCCEx_EXTI_LINE_HSECSS RCC HSE CSS external interrupt line * @{ */ -#define RCC_EXTI_LINE_HSECSS EXTI_IMR2_IM43 /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */ +#define RCC_EXTI_LINE_HSECSS EXTI_IMR2_IM43 /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */ /** * @} */ @@ -700,5 +699,3 @@ void HAL_RCCEx_DisableMSIPLLMode(void); #endif #endif /* STM32WLxx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c index 60dd1b7f367..5b6de5025fb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -79,17 +90,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -115,7 +115,7 @@ */ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ -#define RNG_HTCFG 0x0000AA74U /*!< Recommended value for NIST compliance */ +#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliance */ /** * @} */ @@ -463,7 +463,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1048,5 +1048,3 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h index cc62fd8f979..c8078227ec2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -387,5 +386,3 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif /* STM32WLxx_HAL_RNG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c index 34591bc868b..f615937a499 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c @@ -11,13 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -45,7 +44,7 @@ */ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ -#define RNG_HTCFG 0x0000AA74U /*!< Recommended value for NIST compliance */ +#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliance */ /** * @} */ @@ -347,5 +346,3 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h index c1792c73df2..4e96a957737 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -246,5 +245,3 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif /* STM32WLxx_HAL_RNG_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c index 67c97889b9d..3e84756f9e0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c @@ -15,6 +15,17 @@ * + RTC Tamper and TimeStamp Pins Selection * + Interrupts and flags management * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### RTC Operating Condition ##### @@ -98,9 +109,9 @@ The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. - Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + Function HAL_RTC_RegisterCallback() allows to register following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. (+) TimeStampEventCallback : RTC TimeStamp Event callback. @@ -118,9 +129,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. @@ -138,13 +149,13 @@ (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. - By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions : - examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback(). + examples AlarmAEventCallback(), TimeStampEventCallback(). Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. @@ -152,8 +163,8 @@ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() - or @ref HAL_RTC_Init() function. + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -161,17 +172,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -303,36 +303,46 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check if the calendar has been not initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); - - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* Calendar is already initialized */ + /* Set flag to OK */ + status = HAL_OK; + } if (status == HAL_OK) { @@ -1941,5 +1951,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.h index cd5a87d0c46..2c3db28a036 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -711,6 +710,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : \ (RTC->SCR = (RTC_CLEAR_ALRBF))) +/** + * @brief Check whether if the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U) + #if defined(CORE_CM0PLUS) #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) #define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) @@ -958,6 +964,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); #endif #endif /* STM32WLxx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c index f4c85267b14..042839f7b78 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c @@ -11,6 +11,17 @@ * + Extended Control functions * + Extended RTC features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -93,18 +104,7 @@ (+) Before calling these functions you have to call HAL_RTC_Init() in order to perform TAMP base address offset calculation. - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + @endverbatim ****************************************************************************** */ @@ -2172,5 +2172,3 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h index 6906e9f1366..ff66df3471d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1370,5 +1369,3 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg #endif #endif /* STM32WLxx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c index 67f585ec2e3..af5aaa51ee1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -35,7 +46,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -166,17 +178,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -198,23 +199,24 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ @@ -466,6 +468,9 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Register a User SMARTCARD Callback * To be used instead of the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -483,7 +488,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -494,8 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmartcard); if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -581,15 +585,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -610,51 +614,50 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmartcard); - if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) { switch (CallbackID) { case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ break; case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -696,9 +699,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -725,62 +725,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (##) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() [..] (#) Non-Blocking mode transfers could be aborted using Abort API's : - (++) HAL_SMARTCARD_Abort() - (++) HAL_SMARTCARD_AbortTransmit() - (++) HAL_SMARTCARD_AbortReceive() - (++) HAL_SMARTCARD_Abort_IT() - (++) HAL_SMARTCARD_AbortTransmit_IT() - (++) HAL_SMARTCARD_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (++) HAL_SMARTCARD_AbortCpltCallback() - (++) HAL_SMARTCARD_AbortTransmitCpltCallback() - (++) HAL_SMARTCARD_AbortReceiveCpltCallback() + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -799,11 +804,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - uint8_t *ptmpdata = pData; + const uint8_t *ptmpdata = pData; /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -828,7 +833,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -855,8 +860,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, - Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -864,14 +869,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable the Peripheral first to update mode */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* In case of TX only mode, if NACK is enabled, receiver block has been enabled for Transmit phase. Disable this receiver block. */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); @@ -973,7 +978,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin * @param Size amount of data to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -1001,7 +1006,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -1131,7 +1136,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, * @param Size amount of data to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -1158,7 +1163,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -1311,7 +1316,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); @@ -1373,8 +1379,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1465,7 +1471,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1505,8 +1512,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1533,14 +1540,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t abortcplt = 1U; - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ /* DMA Tx Handle is valid */ if (hsmartcard->hdmatx != NULL) { @@ -1634,8 +1643,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1767,7 +1776,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1806,8 +1816,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1832,8 +1842,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2261,7 +2271,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ uint32_t temp1; @@ -2278,7 +2288,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) { return hsmartcard->ErrorCode; } @@ -2304,14 +2314,18 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) { /* Init the SMARTCARD Callback settings */ - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak + RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak + TxFifoEmptyCallback */ } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2352,7 +2366,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength)); + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2400,21 +2415,26 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; default: ret = HAL_ERROR; @@ -2424,7 +2444,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { - hsmartcard->Instance->BRR = tmpreg; + hsmartcard->Instance->BRR = (uint16_t)tmpreg; } else { @@ -2555,11 +2575,12 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar } /** - * @brief Handle SMARTCARD Communication Timeout. + * @brief Handle SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration. * @retval HAL status @@ -2575,7 +2596,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -2769,8 +2791,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2818,8 +2840,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2880,8 +2902,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2987,14 +3009,14 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the Peripheral first to update mode */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* In case of TX only mode, if NACK is enabled, receiver block has been enabled for Transmit phase. Disable this receiver block. */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); @@ -3158,4 +3180,3 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h index 4d20df41e41..4a1abab101b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -198,7 +197,7 @@ typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ @@ -1094,13 +1093,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); /* Transfer Abort functions */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); @@ -1127,8 +1126,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) * @{ */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); /** * @} @@ -1152,4 +1151,3 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmar #endif /* STM32WLxx_HAL_SMARTCARD_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c index 6a27ed4709a..7f5cb59a771 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================= ##### SMARTCARD peripheral extended features ##### @@ -27,17 +38,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -491,4 +491,3 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.h index 2a32cfe998f..adc9fad90b2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -335,4 +334,3 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs #endif /* STM32WLxx_HAL_SMARTCARD_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c index 63210321ce5..f6b2a79714a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c @@ -10,6 +10,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -131,7 +142,7 @@ [..] For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. [..] - By default, after theHAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET + By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are @@ -145,7 +156,7 @@ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() or HAL_SMBUS_Init() function. [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or @@ -156,18 +167,6 @@ (@) You can refer to the SMBUS HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -209,20 +208,28 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ +/* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +/* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); +/* Private function to handle start, restart or stop a transfer */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); /** * @} */ @@ -577,6 +584,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** * @brief Register a User SMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be registered @@ -606,9 +616,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -684,14 +691,15 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } /** * @brief Unregister an SMBUS Callback * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be unregistered @@ -712,9 +720,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -790,8 +795,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -815,8 +818,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); if (HAL_SMBUS_STATE_READY == hsmbus->State) { @@ -831,8 +832,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -847,9 +846,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -863,8 +859,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -1872,6 +1866,9 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2162,6 +2159,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); } @@ -2183,6 +2183,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2584,7 +2587,10 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Store current volatile hsmbus->State, misra rule */ + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2654,6 +2660,27 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu return HAL_OK; } +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + hsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) + { + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); + } +} + /** * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hsmbus SMBUS handle. @@ -2746,5 +2773,3 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h index 8db5112e2bf..8bb30142429 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -27,7 +26,6 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wlxx_hal_def.h" -#include "stm32wlxx_hal_smbus_ex.h" /** @addtogroup STM32WLxx_HAL_Driver * @{ @@ -513,6 +511,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag @@ -525,7 +524,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval None */ -#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified SMBUS peripheral. * @param __HANDLE__ specifies the SMBUS Handle. @@ -654,6 +655,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @} */ +/* Include SMBUS HAL Extended module */ +#include "stm32wlxx_hal_smbus_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions * @{ @@ -785,5 +789,3 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif /* STM32WLxx_HAL_SMBUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c index f249e07dfdc..94b744165d7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c @@ -7,6 +7,17 @@ * functionalities of SMBUS Extended peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### SMBUS peripheral Extended features ##### @@ -15,26 +26,18 @@ [..] Comparing to other previous devices, the SMBUS interface for STM32WLxx devices contains the following additional features + (+) Disable or enable wakeup from Stop mode(s) (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== + (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions : + (++) HAL_SMBUSEx_EnableWakeUp() + (++) HAL_SMBUSEx_DisableWakeUp() (#) Configure the enable or disable of fast mode plus driving capability using the functions : (++) HAL_SMBUSEx_EnableFastModePlus() (++) HAL_SMBUSEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -62,15 +65,109 @@ * @{ */ -/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### WakeUp Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Enable wakeup from stop mode */ + hsmbus->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Disable wakeup from stop mode */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: (+) Configure Fast Mode Plus @endverbatim @@ -82,14 +179,14 @@ * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref SMBUSEx_FastModePlus values * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. * @note For all I2C3 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. * @retval None */ void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) @@ -106,14 +203,14 @@ void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref SMBUSEx_FastModePlus values * @note For I2C1, fast mode plus driving capability can be disabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. * @note For all I2C2 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. * @note For all I2C3 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. * @retval None */ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) @@ -125,6 +222,9 @@ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); } +/** + * @} + */ /** * @} @@ -142,5 +242,3 @@ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h index 82327b188f5..606a930a251 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -37,7 +36,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants * @{ @@ -75,7 +73,17 @@ extern "C" { * @{ */ -/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions +/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); @@ -134,5 +142,3 @@ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32WLxx_HAL_SMBUS_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c index dd824024111..118bc5a2c6c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c @@ -9,7 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -184,18 +194,6 @@ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1009,7 +1007,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; @@ -1257,7 +1255,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD __IO uint32_t tmpreg = 0U; uint32_t spi_cr1; uint32_t spi_cr2; - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ @@ -3074,7 +3072,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ @@ -3191,7 +3189,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ @@ -3568,7 +3566,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Initialize the 8bit temporary pointer */ @@ -3688,7 +3686,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /* Read 16bit CRC to flush Data Register */ tmpreg = READ_REG(hspi->Instance->DR); /* To avoid GCC warning */ - UNUSED(tmpreg); + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3743,7 +3741,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Initialize the 8bit temporary pointer */ @@ -3960,7 +3958,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if(count == 0U) + if (count == 0U) { tmp_timeout = 0U; } @@ -3987,7 +3985,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4042,10 +4040,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if(count == 0U) + if (count == 0U) { tmp_timeout = 0U; - } + } count--; } } @@ -4436,4 +4434,3 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.h index ac094a520e1..1dda8b4f923 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -778,7 +777,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @@ -849,4 +849,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* STM32WLxx_HAL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.c index 1fff487edcf..c5bf1616beb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -111,5 +110,3 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.h index 136dcbd41a6..49d73588ed7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,4 +71,3 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); #endif /* STM32WLxx_HAL_SPI_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c index bc5a3f72a75..c66c8dbea83 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c @@ -8,6 +8,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -71,6 +82,7 @@ (+) RxTxTimeoutCallback : callback for Rx Tx Timeout. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. + (+) LrFhssHopCallback : callback for LoRa Frequency Hopping Spread Spectrum Hopping. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] @@ -92,6 +104,7 @@ (+) RxTxTimeoutCallback : callback for Rx Tx Timeout. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. + (+) LrFhssHopCallback : callback for LoRa Frequency Hopping Spread Spectrum Hopping. [..] For specific callback CADStatusCallback use dedicated register callbacks : @ref HAL_SUBGHZ_UnRegisterCadStatusCallback(). @@ -115,18 +128,6 @@ not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. #endif - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -209,12 +210,16 @@ HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz); * in the SUBGHZ_HandleTypeDef and initialize the associated handle. * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. + * @note In case of exiting from Standby mode, before calling this function, + * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY + * to avoid the reset of Radio peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) { HAL_StatusTypeDef status; __IO uint32_t count; + HAL_SUBGHZ_StateTypeDef subghz_state; /* Check the hsubghz handle allocation */ if (hsubghz == NULL) @@ -229,7 +234,9 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); - if (hsubghz->State == HAL_SUBGHZ_STATE_RESET) + subghz_state = hsubghz->State; + if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || + (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) { /* Allocate lock resource and initialize it */ hsubghz->Lock = HAL_UNLOCKED; @@ -245,6 +252,7 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) hsubghz->CRCErrorCallback = HAL_SUBGHZ_CRCErrorCallback; hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; hsubghz->RxTxTimeoutCallback = HAL_SUBGHZ_RxTxTimeoutCallback; + hsubghz->LrFhssHopCallback = HAL_SUBGHZ_LrFhssHopCallback; if (hsubghz->MspInitCallback == NULL) { @@ -257,43 +265,49 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SUBGHZ_MspInit(hsubghz); #endif /* USE_HAL_ SUBGHZ_REGISTER_CALLBACKS */ + +#if defined(CM0PLUS) + /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ + LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#else + /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#endif /* CM0PLUS */ } - hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + if (subghz_state == HAL_SUBGHZ_STATE_RESET) + { + /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; - /* De-asserts the reset signal of the Radio peripheral */ - LL_RCC_RF_DisableReset(); + /* De-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_DisableReset(); - /* Verify that Radio in reset status flag is set */ - count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; - do - { - if (count == 0U) + do { - status = HAL_ERROR; - hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; - break; - } - count--; - } while (LL_RCC_IsRFUnderReset() != 0UL); + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (LL_RCC_IsRFUnderReset() != 0UL); - /* Asserts the reset signal of the Radio peripheral */ - LL_PWR_UnselectSUBGHZSPI_NSS(); + /* Asserts the reset signal of the Radio peripheral */ + LL_PWR_UnselectSUBGHZSPI_NSS(); #if defined(CM0PLUS) - /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ - LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); - - /* Enable wakeup signal of the Radio peripheral */ - LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); + /* Enable wakeup signal of the Radio peripheral */ + LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); #else - /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ - LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); - - /* Enable wakeup signal of the Radio peripheral */ - LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); + /* Enable wakeup signal of the Radio peripheral */ + LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); #endif /* CM0PLUS */ + } /* Clear Pending Flag */ LL_PWR_ClearFlag_RFBUSY(); @@ -306,7 +320,8 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; } - hsubghz->State = HAL_SUBGHZ_STATE_READY; + + hsubghz->State = HAL_SUBGHZ_STATE_READY; return status; } @@ -497,6 +512,10 @@ HAL_StatusTypeDef HAL_SUBGHZ_RegisterCallback(SUBGHZ_HandleTypeDef *hsubghz, hsubghz->MspDeInitCallback = pCallback; break; + case HAL_SUBGHZ_LR_FHSS_HOP_CB_ID : + hsubghz->LrFhssHopCallback = pCallback; + break; + default : /* Update the error code */ hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; @@ -603,6 +622,10 @@ HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCallback(SUBGHZ_HandleTypeDef *hsubghz, hsubghz->MspDeInitCallback = HAL_SUBGHZ_MspDeInit; break; + case HAL_SUBGHZ_LR_FHSS_HOP_CB_ID : + hsubghz->LrFhssHopCallback = HAL_SUBGHZ_LrFhssHopCallback; + break; + default : /* Update the error code */ hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; @@ -704,7 +727,7 @@ HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCadStatusCallback(SUBGHZ_HandleTypeDef *h if (HAL_SUBGHZ_STATE_READY == hsubghz->State) { - hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; /* Legacy weak AddrCallback */ + hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; /* Legacy weak AddrCallback */ } else { @@ -908,7 +931,6 @@ HAL_StatusTypeDef HAL_SUBGHZ_WriteRegister(SUBGHZ_HandleTypeDef *hsubghz, return (HAL_SUBGHZ_WriteRegisters(hsubghz, Address, &Value, 1U)); } - /** * @brief Read data register at an Address in the peripheral * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains @@ -924,7 +946,6 @@ HAL_StatusTypeDef HAL_SUBGHZ_ReadRegister(SUBGHZ_HandleTypeDef *hsubghz, return (HAL_SUBGHZ_ReadRegisters(hsubghz, Address, pValue, 1U)); } - /** * @brief Send a command to configure the peripheral * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains @@ -942,7 +963,7 @@ HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, HAL_StatusTypeDef status; /* LORA Modulation not available on STM32WLx4xx devices */ - assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0])); + assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); if (hsubghz->State == HAL_SUBGHZ_STATE_READY) { @@ -1198,13 +1219,16 @@ HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, */ void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) { - uint8_t tmpisr[2] = {0}; + uint8_t tmpisr[2U] = {0U}; uint16_t itsource; /* Retrieve Interrupts from SUBGHZ Irq Register */ - (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2); - itsource = tmpisr[0]; - itsource = (itsource << 8) | tmpisr[1]; + (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U); + itsource = tmpisr[0U]; + itsource = (itsource << 8U) | tmpisr[1U]; + + /* Clear SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U); /* Packet transmission completed Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET) @@ -1312,8 +1336,15 @@ void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } - /* Clear SUBGHZ Irq Register */ - (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2); + /* LR_FHSS Hop interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->LrFhssHopCallback(hsubghz); +#else + HAL_SUBGHZ_LrFhssHopCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } } /** @@ -1464,6 +1495,21 @@ __weak void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) */ } +/** + * @brief LR FHSS Hop callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_LrFhssHopCallback should be implemented in the user file + */ +} /** * @} */ @@ -1571,7 +1617,7 @@ void SUBGHZSPI_DeInit(void) } /** - * @brief Transmit data trough SUBGHZSPI peripheral + * @brief Transmit data through SUBGHZSPI peripheral * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. * @param Data data to transmit @@ -1630,7 +1676,7 @@ HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, } /** - * @brief Receive data trough SUBGHZSPI peripheral + * @brief Receive data through SUBGHZSPI peripheral * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. * @param pData pointer on data to receive @@ -1763,5 +1809,3 @@ HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h index 1d5ff01cec7..895a44320e7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -62,6 +61,7 @@ typedef enum HAL_SUBGHZ_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ HAL_SUBGHZ_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_SUBGHZ_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SUBGHZ_STATE_RESET_RF_READY = 0x03U, /*!< Peripheral not Initialized but RF is */ } HAL_SUBGHZ_StateTypeDef; /** @@ -104,6 +104,7 @@ typedef struct void (* RxTxTimeoutCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Rx Tx Timeout callback */ void (* MspInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp Init callback */ void (* MspDeInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp DeInit callback */ + void (* LrFhssHopCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ LR FHSS Hop callback */ #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } SUBGHZ_HandleTypeDef; @@ -122,8 +123,8 @@ typedef enum HAL_SUBGHZ_CRC_ERROR_CB_ID = 0x06U, /*!< SUBGHZ CRC error callback ID */ HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID = 0x07U, /*!< SUBGHZ Rx Tx timeout callback ID */ HAL_SUBGHZ_MSPINIT_CB_ID = 0x08U, /*!< SUBGHZ Msp Init callback ID */ - HAL_SUBGHZ_MSPDEINIT_CB_ID = 0x09U /*!< SUBGHZ Msp DeInit callback ID */ - + HAL_SUBGHZ_MSPDEINIT_CB_ID = 0x09U, /*!< SUBGHZ Msp DeInit callback ID */ + HAL_SUBGHZ_LR_FHSS_HOP_CB_ID = 0x0AU, /*!< SUBGHZ LR FHSS Hop callback ID */ } HAL_SUBGHZ_CallbackIDTypeDef; /** @@ -244,7 +245,7 @@ typedef enum #define SUBGHZ_IT_CAD_DONE 0x0080U #define SUBGHZ_IT_CAD_ACTIVITY_DETECTED 0x0100U #define SUBGHZ_IT_RX_TX_TIMEOUT 0x0200U - +#define SUBGHZ_IT_LR_FHSS_HOP 0x4000U /** * @brief SUBGHZ Radio Read/Write Command definition */ @@ -267,13 +268,22 @@ typedef enum * @retval None */ #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) -#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) +#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) + +#define __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET_RF_READY; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) #else -#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET) +#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET) +#define __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET_RF_READY) #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ /** * @} @@ -298,6 +308,7 @@ typedef enum * @arg SUBGHZ_IT_CAD_DONE * @arg SUBGHZ_IT_CAD_ACTIVITY_DETECTED * @arg SUBGHZ_IT_RX_TX_TIMEOUT + * @arg SUBGHZ_IT_LR_FHSS_HOP * @retval SET or RESET. */ #define SUBGHZ_CHECK_IT_SOURCE(__SUBGHZ_IRQ__, __INTERRUPT__) \ @@ -379,6 +390,7 @@ void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz); void HAL_SUBGHZ_CRCErrorCallback(SUBGHZ_HandleTypeDef *hsubghz); void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz); /** * @} */ @@ -411,4 +423,3 @@ uint32_t HAL_SUBGHZ_GetError(SUBGHZ_HandleTypeDef *hsubghz); #endif /* STM32WLxx_HAL_SUBGHZ_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c index a2575c2fcee..50b146828e6 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c @@ -29,6 +29,17 @@ * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -170,17 +181,6 @@ all interrupt callbacks are set to the corresponding weak functions: @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -205,11 +205,11 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -225,7 +225,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -278,6 +278,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -525,7 +526,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -539,7 +540,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -561,7 +562,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -660,6 +662,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -881,6 +884,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -926,34 +930,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -969,6 +977,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1003,26 +1013,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1038,8 +1052,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1052,7 +1068,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1078,7 +1094,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1099,7 +1116,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1120,7 +1138,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1140,7 +1159,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1151,34 +1171,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1194,6 +1218,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1232,26 +1258,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1301,6 +1331,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1522,7 +1553,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1566,34 +1599,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1609,6 +1646,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1643,26 +1682,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1678,8 +1721,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1692,7 +1737,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1718,7 +1763,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1739,7 +1785,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1759,7 +1806,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1779,7 +1827,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1790,34 +1839,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1833,6 +1886,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1871,26 +1926,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1940,6 +1999,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2150,7 +2210,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2199,27 +2261,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + if (status == HAL_OK) { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2235,6 +2302,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -2269,21 +2338,25 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2301,7 +2374,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2318,7 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2336,20 +2411,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - switch (Channel) { case TIM_CHANNEL_1: @@ -2362,7 +2423,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2382,7 +2444,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2402,7 +2465,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2422,7 +2486,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2433,11 +2498,26 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + /* Return function status */ - return HAL_OK; + return status; } /** @@ -2453,6 +2533,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); @@ -2495,18 +2577,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** * @} @@ -2563,6 +2649,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2966,6 +3053,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { @@ -3475,7 +3563,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData1 == NULL) && (Length > 0U)) + if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3500,7 +3588,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData2 == NULL) && (Length > 0U)) + if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3529,7 +3617,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } @@ -3559,7 +3647,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3567,11 +3656,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } @@ -3584,7 +3674,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3592,15 +3683,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } - case TIM_CHANNEL_ALL: + default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; @@ -3610,7 +3702,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3624,27 +3717,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - default: + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + break; + } } /* Return function status */ @@ -3969,9 +4062,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); @@ -4043,12 +4138,13 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4064,8 +4160,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); @@ -4122,7 +4220,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } - else + else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -4138,10 +4236,14 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } + else + { + status = HAL_ERROR; + } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4160,9 +4262,11 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); @@ -4277,12 +4381,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4307,6 +4412,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { + HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ @@ -4337,6 +4443,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC1_SetConfig(htim->Instance, &temp1); break; } + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -4344,60 +4451,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC2_SetConfig(htim->Instance, &temp1); break; } + default: + status = HAL_ERROR; break; } - switch (InputChannel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: + switch (InputChannel) { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; - default: - break; + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } else { @@ -4429,9 +4543,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR1 - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @param BurstRequestSrc TIM DMA Request sources @@ -4450,10 +4564,16 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; } /** @@ -4480,9 +4600,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR1 - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @param BurstRequestSrc TIM DMA Request sources @@ -4502,9 +4622,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4531,6 +4653,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint { /* nothing to do */ } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: @@ -4544,7 +4667,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4562,7 +4685,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4580,7 +4703,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4598,7 +4721,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4616,7 +4739,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4634,7 +4757,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4652,7 +4775,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4660,16 +4783,20 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4680,6 +4807,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4722,17 +4851,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4759,9 +4892,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR1 - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @param BurstRequestSrc TIM DMA Request sources @@ -4782,8 +4915,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; } /** @@ -4810,9 +4948,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR1 - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @param BurstRequestSrc TIM DMA Request sources @@ -4835,6 +4973,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4874,7 +5014,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4892,7 +5032,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4910,7 +5050,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4928,7 +5068,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4946,7 +5086,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4964,7 +5104,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4982,7 +5122,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4990,17 +5130,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -5011,6 +5155,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -5053,17 +5199,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -5127,9 +5277,11 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -5190,104 +5342,108 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - switch (Channel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: + switch (Channel) { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_1: { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; } - else + case TIM_CHANNEL_2: { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; } - break; - } - case TIM_CHANNEL_5: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_3: { - /* Enable the OCREF clear feature for Channel 5 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; } - else + case TIM_CHANNEL_4: { - /* Disable the OCREF clear feature for Channel 5 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; } - break; - } - case TIM_CHANNEL_6: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_5: { - /* Enable the OCREF clear feature for Channel 6 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; } - else + case TIM_CHANNEL_6: { - /* Disable the OCREF clear feature for Channel 6 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; } - break; + default: + break; } - default: - break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5297,8 +5453,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ @@ -5419,22 +5576,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: + status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5481,7 +5639,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5522,7 +5680,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5564,7 +5722,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -5839,8 +5997,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -5960,7 +6116,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -6026,19 +6182,16 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6082,128 +6235,153 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; break; case HAL_TIM_BREAK2_CB_ID : - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -6212,76 +6390,87 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -6310,7 +6499,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6320,7 +6509,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6330,7 +6519,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6340,7 +6529,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6350,7 +6539,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6360,7 +6549,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6370,7 +6559,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6388,7 +6577,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6405,7 +6594,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -6748,7 +6937,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -6796,7 +6985,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -6871,7 +7060,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -6947,7 +7136,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7021,7 +7210,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7082,7 +7271,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7135,7 +7324,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7189,8 +7378,9 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; @@ -7287,16 +7477,18 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: + status = HAL_ERROR; break; } - return HAL_OK; + + return status; } /** @@ -7672,20 +7864,20 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -7701,4 +7893,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h index 6efaa4016fd..406da1389bb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -65,8 +64,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -218,7 +219,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -268,32 +270,32 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. - This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. - This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + } TIM_BreakDeadTimeConfigTypeDef; /** @@ -664,10 +666,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -741,6 +741,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ @@ -781,16 +790,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ @@ -924,19 +933,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event - (if none of the break inputs BRK and BRK2 is active) */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ -/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ @@ -1225,7 +1233,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -1392,7 +1401,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. * @param __HANDLE__ TIM handle. * @retval None mode. @@ -1419,8 +1429,8 @@ mode. * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1434,7 +1444,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. - * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. @@ -1496,7 +1507,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -1718,6 +1730,17 @@ mode. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + /** * @} */ @@ -1779,7 +1802,7 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ - ((__MODE__) == TIM_UIFREMAP_ENALE)) + ((__MODE__) == TIM_UIFREMAP_ENABLE)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ @@ -1839,20 +1862,23 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ + ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ @@ -1969,13 +1995,13 @@ mode. ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -2074,13 +2100,19 @@ mode. ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2095,11 +2127,15 @@ mode. ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) /** * @} @@ -2130,7 +2166,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -2152,7 +2188,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2174,7 +2211,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2259,31 +2297,35 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2320,17 +2362,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2344,9 +2386,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); @@ -2378,5 +2420,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif #endif /* STM32WLxx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c index 379e3674fa1..cf36eeff44c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c @@ -12,6 +12,17 @@ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) * + Time OCRef clear configuration * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### @@ -56,24 +67,16 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -156,7 +159,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -172,6 +175,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -359,7 +363,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -391,7 +396,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -442,7 +448,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -474,7 +481,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -518,7 +526,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -534,7 +542,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ @@ -581,7 +590,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -721,6 +731,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -760,34 +771,38 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -803,7 +818,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -831,30 +848,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -870,8 +891,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -884,7 +907,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -910,7 +933,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -930,7 +954,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -950,7 +975,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -961,31 +987,35 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1001,6 +1031,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1031,23 +1063,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1178,6 +1214,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1216,34 +1253,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1259,6 +1300,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ @@ -1288,30 +1330,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1327,8 +1373,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1341,7 +1389,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1367,7 +1415,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1387,7 +1436,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1407,7 +1457,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1418,31 +1469,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } default: + status = HAL_ERROR; break; } - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1458,6 +1513,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1488,23 +1545,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1927,7 +1988,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -2000,7 +2061,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2083,9 +2144,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; uint32_t bkin_enable_mask; uint32_t bkin_polarity_mask; @@ -2176,12 +2238,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, break; } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -2325,6 +2388,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpbdtr; /* Check the parameters */ @@ -2359,10 +2423,11 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B break; } default: + status = HAL_ERROR; break; } - return HAL_OK; + return status; } /** @@ -2378,6 +2443,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* Check the parameters */ @@ -2432,10 +2498,11 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br break; } default: + status = HAL_ERROR; break; } - return HAL_OK; + return status; } /** @@ -2540,7 +2607,7 @@ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -2555,7 +2622,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -2575,7 +2642,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ @@ -2751,5 +2818,3 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.h index 9fba98bd875..a1b4a0b14f6 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -71,8 +70,7 @@ typedef struct This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ -} -TIMEx_BreakInputConfigTypeDef; +} TIMEx_BreakInputConfigTypeDef; /** * @} @@ -87,35 +85,35 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */ -#define TIM_TIM1_ETR_ADC_AWD1 TIM1_OR1_ETR_ADC_RMP_0 /* !< TIM1_ETR is connected to ADC AWD1 */ -#define TIM_TIM1_ETR_ADC_AWD2 TIM1_OR1_ETR_ADC_RMP_1 /* !< TIM1_ETR is connected to ADC AWD2 */ -#define TIM_TIM1_ETR_ADC_AWD3 (TIM1_OR1_ETR_ADC_RMP_0 | TIM1_OR1_ETR_ADC_RMP_1) /* !< TIM1_ETR is connected to ADC AWD3 */ -#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ -#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ - -#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */ -#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */ - -#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */ -#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */ -#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ -#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ - -#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */ -#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */ -#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */ -#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */ - -#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */ -#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */ -#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */ -#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */ - -#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */ -#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */ -#define TIM_TIM17_TI1_HSE TIM17_OR1_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */ -#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is not connected to I/O */ +#define TIM_TIM1_ETR_ADC_AWD1 TIM1_OR1_ETR_ADC_RMP_0 /*!< TIM1_ETR is connected to ADC AWD1 */ +#define TIM_TIM1_ETR_ADC_AWD2 TIM1_OR1_ETR_ADC_RMP_1 /*!< TIM1_ETR is connected to ADC AWD2 */ +#define TIM_TIM1_ETR_ADC_AWD3 (TIM1_OR1_ETR_ADC_RMP_0 | TIM1_OR1_ETR_ADC_RMP_1) /*!< TIM1_ETR is connected to ADC AWD3 */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ + +#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 Input capture 1 is connected to I/0 */ +#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /*!< TIM1 Input capture 1is connected to COMP1 OUT */ + +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2 External trigger ETR is connected to I/O */ +#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR_RMP /*!< TIM2 External trigger ETR is connected to LSE */ +#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ + +#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to I/O */ +#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_TI4_RMP_1) /*!< TIM2_TI4 is connected to COMP1 and COMP2 OUT */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16_TI1 is connected to I/O */ +#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /*!< TIM16_TI1 is connected to LSI Clock */ +#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /*!< TIM16_TI1 is connected to LSE Clock */ +#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_TI1_RMP_1) /*!< TIM16_TI1 is connected to RTC */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17_TI1 is connected to I/O */ +#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /*!< TIM17_TI1 is connected to MSI */ +#define TIM_TIM17_TI1_HSE TIM17_OR1_TI1_RMP_1 /*!< TIM17_TI1 is connected to HSE/32 */ +#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_TI1_RMP_1) /*!< TIM17_TI1 is connected to MCO */ /** * @} */ @@ -123,8 +121,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ -#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ /** * @} */ @@ -132,9 +130,9 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ /** * @} */ @@ -142,8 +140,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ -#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ /** * @} */ @@ -151,8 +149,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ /** * @} */ @@ -214,7 +212,7 @@ TIMEx_BreakInputConfigTypeDef; * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -247,7 +245,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -266,7 +265,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -300,11 +300,11 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); @@ -332,8 +332,8 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ @@ -344,7 +344,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); @@ -368,5 +368,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); #endif /* STM32WLxx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c index d466234670d..ddb18e59acb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -145,17 +156,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -177,27 +177,22 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ /* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -227,6 +222,16 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); * @} */ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -651,6 +656,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -691,6 +697,9 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Register a User UART Callback * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -722,8 +731,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_READY) { switch (CallbackID) @@ -813,14 +820,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -843,8 +851,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -936,8 +942,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } @@ -1073,7 +1077,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() - (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: (+) HAL_UARTEx_RxEventCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. @@ -1118,10 +1123,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -1145,8 +1150,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1160,7 +1163,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1168,8 +1171,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) @@ -1216,8 +1217,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u * RXNE are mapped on the same bit-field. * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required * to ensure proper alignment for pData. * @param huart UART handle. @@ -1254,8 +1255,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1282,8 +1281,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* as long as data have to be received */ while (huart->RxXferCount > 0U) { @@ -1331,7 +1328,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1354,8 +1351,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1377,8 +1372,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } @@ -1394,8 +1387,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } @@ -1415,8 +1406,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData * of u16 available through pData. * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required * to ensure proper alignment for pData. * @param huart UART handle. @@ -1447,22 +1438,20 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; if (!(IS_LPUART_INSTANCE(huart->Instance))) { /* Check that USART RTOEN bit is set */ - if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } - return(UART_Start_Receive_IT(huart, pData, Size)); + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1486,7 +1475,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1509,8 +1498,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1538,8 +1525,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; @@ -1549,8 +1534,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1604,22 +1587,20 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; if (!(IS_LPUART_INSTANCE(huart->Instance))) { /* Check that USART RTOEN bit is set */ - if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } - return(UART_Start_Receive_DMA(huart, pData, Size)); + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1637,8 +1618,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - __HAL_LOCK(huart); - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { @@ -1656,8 +1635,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1668,8 +1645,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ @@ -1681,15 +1656,16 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1786,9 +1762,10 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ @@ -1811,9 +1788,10 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ @@ -1880,9 +1858,10 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ @@ -1944,9 +1923,10 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ @@ -2045,7 +2025,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ @@ -2069,9 +2049,10 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ @@ -2157,9 +2138,10 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ @@ -2253,9 +2235,10 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ @@ -2434,9 +2417,10 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ @@ -2498,9 +2482,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check current reception Mode : If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - &&((isrflags & USART_ISR_IDLE) != 0U) - &&((cr1its & USART_ISR_IDLE) != 0U)) + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); @@ -2512,8 +2496,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ( (nb_remaining_rx_data > 0U) - &&(nb_remaining_rx_data < huart->RxXferSize)) + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; @@ -2538,13 +2522,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; } @@ -2554,8 +2543,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ( (huart->RxXferCount > 0U) - &&(nb_rx_data > 0U) ) + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); @@ -2571,13 +2560,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxISR = NULL; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; } @@ -3055,7 +3049,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1; uint32_t temp2; @@ -3071,7 +3065,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3265,7 +3259,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); @@ -3306,10 +3300,10 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) if (pclk != 0U) { /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { - huart->Instance->BRR = usartdiv; + huart->Instance->BRR = (uint16_t)usartdiv; } else { @@ -3444,6 +3438,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -3451,10 +3446,11 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /** - * @brief Handle UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart UART handle. * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -3552,10 +3548,11 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -3570,10 +3567,15 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } return HAL_OK; } @@ -3617,18 +3619,18 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } } - __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3767,6 +3769,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3801,16 +3807,20 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize/2U); + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -4098,7 +4108,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -4113,7 +4123,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } else { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4170,7 +4180,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -4190,7 +4200,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4261,6 +4271,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4276,13 +4299,14 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4340,6 +4364,19 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4355,13 +4392,14 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4470,6 +4508,19 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4485,13 +4536,14 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4620,6 +4672,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4635,13 +4700,14 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4694,4 +4760,3 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h index f2006d507b4..912f6ffcce9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -48,21 +47,21 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + - LPUART: Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + - UART: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + + where uart_ker_ckpres is the UART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref UARTEx_Word_Length. */ @@ -195,7 +194,7 @@ typedef enum /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TORTO = 0x02U, @@ -203,6 +202,17 @@ typedef enum */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -214,7 +224,7 @@ typedef struct __UART_HandleTypeDef UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -237,6 +247,8 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -805,7 +817,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -816,6 +828,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + /** * @} */ @@ -1614,11 +1636,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); @@ -1672,8 +1694,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); */ /* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} @@ -1716,4 +1738,3 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa #endif /* STM32WLxx_HAL_UART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c index ef07235709a..4e972f1f88d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### UART peripheral extended features ##### @@ -27,17 +38,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -739,11 +739,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -767,8 +766,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -785,6 +782,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -877,10 +875,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_IT(huart, pData, Size); @@ -956,10 +953,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } #endif /* CORE_CM0PLUS */ - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -989,6 +985,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } } +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + /** * @} */ @@ -1065,4 +1091,3 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.h index 34e000980e7..c45cdef1032 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -178,6 +177,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + /** * @} @@ -379,4 +380,3 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ #endif /* STM32WLxx_HAL_UART_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c index aa7d901d5ce..0e591368224 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -123,17 +134,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -318,7 +318,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ husart->Instance->CR2 &= ~USART_CR2_LINEN; husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); @@ -753,10 +754,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) @@ -795,7 +796,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; } else { @@ -998,13 +999,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint16_t uhMask; uint16_t rxdatacount; uint32_t tickstart; @@ -1052,7 +1053,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { prxdata8bits = NULL; ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; prxdata16bits = (uint16_t *) pRxData; } else @@ -1163,7 +1164,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1321,7 +1322,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -1340,7 +1344,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) @@ -1386,7 +1397,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { @@ -1447,8 +1458,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the USART Parity Error interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the TX and RX FIFO Threshold interrupts */ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); @@ -1473,7 +1487,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the USART Transmit Data Register Empty Interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -1503,10 +1524,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1550,8 +1571,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->XferErrorCallback = USART_DMAError; /* Enable the USART transmit DMA channel */ - tmp = (uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } if (status == HAL_OK) @@ -1681,8 +1702,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1743,11 +1767,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef status; - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1802,13 +1826,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART receive DMA channel */ tmp = (uint32_t *)&pRxData; - status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size); /* Enable the USART transmit DMA channel */ if (status == HAL_OK) { - tmp = (uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } } else @@ -1821,8 +1845,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1939,7 +1966,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART DMA Rx request before the DMA Tx request */ @@ -2031,9 +2061,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { + /* Disable the USART DMA Tx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ @@ -2056,9 +2087,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ @@ -2160,7 +2192,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at USART level */ @@ -2184,9 +2216,10 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ @@ -2261,7 +2294,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -2357,9 +2391,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); /* Abort the USART DMA Tx channel */ @@ -2608,7 +2643,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2619,7 +2654,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } @@ -2966,10 +3001,11 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** - * @brief Handle USART Communication Timeout. + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param husart USART handle. * @param Flag Specifies the USART flag to check. - * @param Status the Flag status (SET or RESET). + * @param Status the actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout timeout duration. * @retval HAL status @@ -3194,7 +3230,7 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; if ((state == HAL_USART_STATE_BUSY_TX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3209,7 +3245,7 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) } else { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3275,7 +3311,7 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -3296,7 +3332,7 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3828,4 +3864,3 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.h index 2371293af73..1902c1128d8 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -121,7 +120,7 @@ typedef struct __USART_HandleTypeDef USART_InitTypeDef Init; /*!< USART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ uint16_t TxXferSize; /*!< USART Tx Transfer size */ @@ -904,17 +903,17 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); @@ -941,8 +940,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); */ /* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} @@ -966,4 +965,3 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #endif /* STM32WLxx_HAL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c index a10093d6d6d..c509f4bcb61 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c @@ -8,6 +8,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### USART peripheral extended features ##### @@ -26,17 +37,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -534,4 +534,3 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.h index aee4cb7bb10..64c04115e60 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -279,4 +278,3 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui #endif /* STM32WLxx_HAL_USART_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.c index ac3c467b200..6576d3eab0a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.c @@ -7,6 +7,17 @@ * functionalities of the Window Watchdog (WWDG) peripheral: * + Initialization and Configuration functions * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### WWDG Specific features ##### @@ -55,7 +66,7 @@ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Configure the WWDG prescaler, refresh window value, counter value and early interrupt status using HAL_WWDG_Init() function. This will automatically - enable WWDG and start its downcounter. Time reference can be taken from + enable WWDG and start its downcounter. Time reference can be taken from function exit. Care must be taken to provide a counter value greater than 0x40 to prevent generation of immediate reset. (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is @@ -112,17 +123,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ #if !defined(CORE_CM0PLUS) @@ -421,4 +421,3 @@ __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) */ #endif /* CORE_CM0PLUS */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.h index c39f702104d..a1701899f5c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -193,7 +192,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -308,4 +307,3 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); #endif /* STM32WLxx_HAL_WWDG_H */ #endif /* CORE_CM0PLUS */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c index ba94eb11697..1f7c69831ac 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -213,6 +212,9 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + (void)(ADCxy_COMMON); + /* Force reset of ADC clock (core clock) */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); @@ -408,14 +410,14 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register SMPR */ CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL); - /* Reset register TR1 */ - MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); + /* Reset register AWD1TR */ + MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1); - /* Reset register TR2 */ - MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); + /* Reset register AWD2TR */ + MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2); - /* Reset register TR3 */ - MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); + /* Reset register AWD3TR */ + MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3); /* Reset register CHSELR */ CLEAR_BIT(ADCx->CHSELR, @@ -756,5 +758,3 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h index 17de5aa020d..65788a6def3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -69,7 +68,9 @@ extern "C" { /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ /* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 families + having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ @@ -101,12 +102,17 @@ extern "C" { /* GPIO pins) and internal channels (connected to internal paths) */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to + ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, + if set to mode "fully configurable", can contain channels with a restricted channel number. + Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" + position in register */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK + >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ @@ -194,17 +200,22 @@ extern "C" { #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) -#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET + in ADC_AWD_CRX_REGOFFSET_MASK */ /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS)) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) -#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ -#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ -#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ -#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET + in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate + threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate + threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to + position to perform a shift of 4 ranks */ #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) @@ -238,19 +249,31 @@ extern "C" { /* ADC registers bits groups */ -#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ + | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with + HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, + address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), + Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value + with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WL, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WL, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32WL, + temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V + (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Address of parameter TS_CAL2: On STM32WL, + temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V + (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) value + with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /** * @} @@ -298,8 +321,8 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetCommonClock(). */ } LL_ADC_CommonInitTypeDef; @@ -325,27 +348,29 @@ typedef struct { uint32_t Clock; /*!< Set ADC instance clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE - @note On this STM32 series, this parameter has some clock ratio constraints: - ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle - (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). + @note On this STM32 series, this parameter has some clock ratio constraints: + ADC clock synchronous (from PCLK) with prescaler 1 must be enabled + only if PCLK has a 50% duty clock cycle (APB prescaler configured + inside the RCC must be bypassed and the system clock must by 50% duty + cycle). + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetClock(). For more details, refer to description of this function. */ uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetDataAlignment(). */ uint32_t LowPowerMode; /*!< Set ADC low power mode. This parameter can be a value of @ref ADC_LL_EC_LP_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetLowPowerMode(). */ } LL_ADC_InitTypeDef; @@ -370,43 +395,57 @@ typedef struct */ typedef struct { - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or + from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge - (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). - In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge(default setting for compatibility + with some ADC on other STM32 families having this setting set by HW + default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_REG_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. - @note This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + @note This parameter has an effect only if group regular sequencer is set + to mode "fully configurable". Refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerLength(). */ - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is enabled - (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + @note This parameter has an effect only if group regular sequencer is + enabled (depending on the sequencer mode: scan length of 2 ranks or + more, or several ADC channels enabled in group regular sequencer. + Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC + conversions are performed in single mode (one conversion per trigger) or in + continuous mode (after the first trigger, following conversions launched + successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + Note: It is not possible to enable both ADC group regular continuous mode + and discontinuous mode. + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetContinuousMode(). */ - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer + by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetDMATransfer(). */ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetOverrun(). */ } LL_ADC_REG_InitTypeDef; @@ -462,7 +501,12 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC + configured in independent mode. Without DMA transfer, + register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ /** * @} */ @@ -767,9 +811,9 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds * @{ */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ -#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 ) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ /** * @} */ @@ -826,7 +870,11 @@ typedef struct /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro * @{ */ -#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro + @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on + calibration parameters. This value is coded on 16 bits + (to fit on signed word or double word) and corresponds + to an inconsistent temperature value. */ /** * @} */ @@ -1091,7 +1139,8 @@ typedef struct * (1) On STM32WL, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel + connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ @@ -1314,8 +1363,9 @@ typedef struct * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ + & LL_ADC_AWD_THRESHOLD_LOW) /** * @brief Helper macro to select the ADC common instance @@ -1541,12 +1591,15 @@ typedef struct * @note ADC measurement data must correspond to a resolution of 12 bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). * On STM32WL, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value + (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32WL, refer to datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage + (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: @@ -1632,7 +1685,8 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis * @} */ -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several + * ADC instances * @{ */ @@ -1940,8 +1994,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) * dependencies to ADC resolutions. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 RES LL_ADC_SetResolution * @param ADCx ADC instance * @param Resolution This parameter can be one of the following values: @@ -1979,8 +2032,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * dependencies to ADC resolutions. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment * @param ADCx ADC instance * @param DataAlignment This parameter can be one of the following values: @@ -2049,8 +2101,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * ADC channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n * CFGR1 AUTOFF LL_ADC_SetLowPowerMode * @param ADCx ADC instance @@ -2271,8 +2322,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, * depends on timers availability on the selected device. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource * @param ADCx ADC instance @@ -2352,8 +2402,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) * @note Applicable only for trigger source set to external trigger. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge * @param ADCx ADC instance * @param ExternalTriggerEdge This parameter can be one of the following values: @@ -2406,8 +2455,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * for more details. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable * @param ADCx ADC instance * @param Configurability This parameter can be one of the following values: @@ -2577,13 +2625,18 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; uint32_t rank_index; + uint32_t rank_shifted; /* Parse register for end of sequence identifier */ - for (rank_index = 0UL; rank_index < (32U - 4U); rank_index += 4U) + /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank + (ADC_CHSELR_SQ2), value "4" to length of end of sequence + identifier (0xF) */ + for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U) { - if ((channels_ranks & (ADC_CHSELR_SQ2 << rank_index)) == (ADC_CHSELR_SQ2 << rank_index)) + rank_shifted = (uint32_t)(0xF0UL << rank_index); + if ((channels_ranks & rank_shifted) == rank_shifted) { - sequencer_length = (ADC_CHSELR_SQ2 << rank_index); + sequencer_length = rank_shifted; break; } } @@ -2608,8 +2661,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * for more details. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection * @param ADCx ADC instance * @param ScanDirection This parameter can be one of the following values: @@ -2648,8 +2700,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) * continuous mode and sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: @@ -2760,7 +2811,8 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->CHSELR, ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -3226,8 +3278,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) * continuous mode and sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode * @param ADCx ADC instance * @param Continuous This parameter can be one of the following values: @@ -3279,8 +3330,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * use function @ref LL_ADC_DMA_GetRegAddr(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer * @param ADCx ADC instance @@ -3339,8 +3389,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) * overrun should be set to data overwritten. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun * @param ADCx ADC instance * @param Overrun This parameter can be one of the following values: @@ -3526,8 +3575,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 /* Retrieve sampling time bit corresponding to the selected channel */ /* and shift it to position 0. */ uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) - >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & - 0x1FUL)); + >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + + ADC_SMPR_SMPSEL0_BITOFFSET_POS) + & 0x1FUL)); /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) @@ -3573,8 +3623,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * ADC resolution configured). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n @@ -3626,7 +3675,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t } else { - preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)); + preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)); } MODIFY_REG(*preg, @@ -3713,8 +3763,10 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -3813,12 +3865,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n - * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n - * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n - * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n - * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n - * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds + * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 @@ -3836,10 +3888,15 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) + ); MODIFY_REG(*preg, - ADC_TR1_HT1 | ADC_TR1_LT1, + ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); } @@ -3889,12 +3946,12 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * ADC state: * ADC can be disabled, enabled with or without conversion on going * on ADC group regular. - * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n - * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n - * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n - * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n - * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n - * TR3 LT3 LL_ADC_SetAnalogWDThresholds + * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 @@ -3914,9 +3971,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, - (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) - + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -3934,12 +3993,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n - * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n - * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n - * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n - * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n - * TR3 LT3 LL_ADC_GetAnalogWDThresholds + * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 @@ -3958,14 +4017,16 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, - (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) - + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); return (uint32_t)(READ_BIT(*preg, - (AWDThresholdsHighLow | ADC_TR1_LT1)) + (AWDThresholdsHighLow | ADC_AWD1TR_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) - & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); + & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1))); } /** @@ -4016,8 +4077,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) * needs a trigger) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. + * ADC must be disabled. * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont * @param ADCx ADC instance * @param OverSamplingDiscont This parameter can be one of the following values: @@ -4279,6 +4339,9 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) * DMA transfer setting restore after calibration. * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), * @ref LL_ADC_REG_SetDMATransfer() ). + * @note In case of usage of feature auto power-off: + * This mode must be disabled during calibration + * Refer to function @ref LL_ADC_SetLowPowerMode(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. @@ -5105,5 +5168,3 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); #endif #endif /* STM32WLxx_LL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h index 8723f1af7e6..0c519ee58ff 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h @@ -3,6 +3,17 @@ * @file stm32wlxx_ll_bus.h * @author MCD Application Team * @brief Header file of BUS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ##### RCC Limitations ##### ============================================================================== @@ -20,17 +31,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -2523,5 +2523,3 @@ __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) #endif #endif /* __STM32WLxx_LL_BUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.c index a22a254a484..fe0b9ba7eac 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -25,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -165,7 +164,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) * - SUCCESS: COMP registers are initialized * - ERROR: COMP registers are not initialized */ -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; @@ -254,5 +253,3 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.h index 0477f7c605b..bb679ab5b5a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_comp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -319,7 +318,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * @arg @ref LL_COMP_WINDOWMODE_DISABLE * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE)); } @@ -356,7 +355,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE)); } @@ -450,7 +449,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * * (*) Parameter not available on all devices. */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL)); } @@ -513,7 +512,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_IO3 * @arg @ref LL_COMP_INPUT_MINUS_IO4 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN)); } @@ -544,7 +543,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST)); } @@ -579,7 +578,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY)); } @@ -622,7 +621,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * (1) Parameter availability depending on timer availability * on the selected device. */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING)); } @@ -667,7 +666,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); } @@ -694,7 +693,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); } @@ -719,7 +718,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE) >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS); @@ -735,7 +734,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) */ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx); -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct); +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct); void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); /** @@ -766,5 +765,3 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); #endif #endif /* STM32WLxx_LL_COMP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h index 300b7bb0ba2..a69d4064120 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h @@ -3,6 +3,17 @@ * @file stm32wlxx_ll_cortex.h * @author MCD Application Team * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +30,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -169,7 +169,7 @@ extern "C" { #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ -#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ + /** * @} */ @@ -445,11 +445,11 @@ __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) } /** - * @brief Get Constant number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture * @retval Value should be equal to 0xF for Cortex-M4 devices */ -__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); } @@ -583,7 +583,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) * or @ref LL_MPU_REGION_SIZE_4GB * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO - * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE @@ -647,5 +647,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) #endif #endif /* __STM32WLxx_LL_CORTEX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.c index 4c95eda79d3..9e864dbddf4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -102,6 +101,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.h index aeedf4a3af8..ec93655032d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -236,7 +235,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t } /** - * @brief Configure the reversal of the bit order of the Output data + * @brief Return type of reversal of the bit order of the Output data * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode * @param CRCx CRC Instance * @retval Returned value can be one of the following values: @@ -460,5 +459,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); #endif #endif /* STM32WLxx_LL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.c index 9051d787a6a..c69d56bdd4e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -60,56 +59,56 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) -#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ +#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ + ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ - ) \ - ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \ ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ - || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ + || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ ) #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \ ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ - || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ + || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ ) /** @@ -174,7 +173,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; @@ -286,5 +285,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.h index 9236a12e7dc..943184aca6c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -53,19 +52,23 @@ extern "C" { /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ /* - channel register offset of sample-and-hold sample time register SHSRx */ -#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 1 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL -#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ + | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) @@ -73,18 +76,33 @@ extern "C" { #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) -#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ -#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */ -#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */ - -#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ -#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ -#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, + DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted + to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted + to position 0 */ + +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 28 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx + channel 1 or 2 versus DORx channel 1 + (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx + channel 1 or 2 versus SHSRx channel 1 + (shifted left of 6 bits) */ /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 + bits (voltage range determined by analog voltage + references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -103,7 +121,7 @@ extern "C" { * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address -*/ + */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) @@ -123,38 +141,50 @@ extern "C" { */ typedef struct { - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: + internal (SW start) or from external peripheral + (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetTriggerSource(). */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. - If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS - If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE - @note If waveform automatic generation mode is disabled, this parameter is discarded. - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() + If waveform automatic generation mode is set to noise, this parameter + can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, + this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, + this parameter is discarded. + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveNoiseLFSR(), + @ref LL_DAC_SetWaveTriangleAmplitude() depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputBuffer(). */ uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputConnection(). */ - uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. - This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE + uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC + channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputMode(). */ } LL_DAC_InitTypeDef; /** @@ -175,7 +205,6 @@ typedef struct #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ - /** * @} */ @@ -337,7 +366,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ @@ -404,7 +433,7 @@ typedef struct * number is returned. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @retval 1...2 + * @retval 1 */ #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((__CHANNEL__) & DAC_SWTR_CHX_MASK) @@ -455,7 +484,7 @@ typedef struct * @ref LL_DAC_ConvertData12RightAligned(). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). @@ -467,9 +496,9 @@ typedef struct #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ __DAC_VOLTAGE__,\ __DAC_RESOLUTION__) \ - ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ - ) +((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ +) /** * @} @@ -484,6 +513,7 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ + /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ @@ -518,7 +548,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -553,7 +583,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -608,7 +638,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -647,7 +677,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -709,7 +739,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -772,7 +802,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -864,7 +894,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -903,7 +933,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -958,7 +988,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -981,11 +1011,10 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_SHSR1_TSAMPLE1, - SampleTime); + MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); } /** @@ -997,9 +1026,10 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * @arg @ref LL_DAC_CHANNEL_1 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); } @@ -1030,7 +1060,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1063,7 +1093,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_CHANNEL_1 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1119,7 +1149,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1139,7 +1169,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * (uint32_t)&< array or variable >, - * LL_DAC_DMA_GetRegAddr(DAC, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, + * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n @@ -1153,12 +1184,12 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, - ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -1208,7 +1239,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1260,7 +1291,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @arg @ref LL_DAC_CHANNEL_1 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1305,11 +1336,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR12R1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); } /** @@ -1325,11 +1355,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR12L1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); } /** @@ -1345,11 +1374,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR8R1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); } /** @@ -1364,9 +1392,10 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } @@ -1378,13 +1407,14 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management * @{ */ + /** * @brief Get DAC calibration offset flag for DAC channel 1 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); } @@ -1395,19 +1425,18 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } - /** * @brief Get DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } @@ -1459,7 +1488,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } @@ -1474,7 +1503,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) */ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** @@ -1501,5 +1530,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif #endif /* STM32WLxx_LL_DAC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.c index 9283c3b5391..94035a9b31b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -25,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -147,7 +146,7 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); } -#endif +#endif /* DMA2 */ else { status = ERROR; @@ -343,5 +342,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.h index d19b9582359..92c6c9295a4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2487,5 +2486,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif #endif /* STM32WLxx_LL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dmamux.h index ae3f46fc42b..70eea14752d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dmamux.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_dmamux.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1689,5 +1688,3 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMU #endif #endif /* STM32WLxx_LL_DMAMUX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.c index 81bd57d23af..06b7271984b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -24,7 +23,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -48,14 +47,14 @@ #define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ - || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ - || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) /** * @} @@ -82,56 +81,56 @@ ErrorStatus LL_EXTI_DeInit(void) { /* Rising Trigger selection register set to default reset values */ LL_EXTI_WriteReg(RTSR1, 0x00000000U); - + /* Falling Trigger selection register set to default reset values */ LL_EXTI_WriteReg(FTSR1, 0x00000000U); - + /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER1, 0x00000000U); - + /* Pending register set to default reset values */ LL_EXTI_WriteReg(PR1, 0xFFFFFFFFU); /* Rising Trigger selection register 2 set to default reset values */ LL_EXTI_WriteReg(RTSR2, 0x00000000U); - + /* Falling Trigger selection register 2 set to default reset values */ LL_EXTI_WriteReg(FTSR2, 0x00000000U); - + /* Software interrupt event register 2 set to default reset values */ LL_EXTI_WriteReg(SWIER2, 0x00000000U); - + /* Pending register 2 set to default reset values */ LL_EXTI_WriteReg(PR2, 0xFFFFFFFFU); - + /* Interrupt mask register set to default reset values */ #if defined(DUAL_CORE) && defined (CORE_CM0PLUS) LL_EXTI_WriteReg(C2IMR1, 0x00000000U); #else LL_EXTI_WriteReg(IMR1, 0x00000000U); -#endif - +#endif /* DUAL_CORE && CORE_CM0PLUS */ + /* Event mask register set to default reset values */ #if defined(DUAL_CORE) && defined (CORE_CM0PLUS) LL_EXTI_WriteReg(C2EMR1, 0x00000000U); #else LL_EXTI_WriteReg(EMR1, 0x00000000U); -#endif - +#endif /* DUAL_CORE && CORE_CM0PLUS */ + /* Interrupt mask register 2 set to default reset values */ #if defined(DUAL_CORE) && defined (CORE_CM0PLUS) LL_EXTI_WriteReg(C2IMR2, 0x00000000U); #else LL_EXTI_WriteReg(IMR2, 0x00000000U); -#endif - +#endif /* DUAL_CORE && CORE_CM0PLUS */ + /* Event mask register 2 set to default reset values */ #if defined(DUAL_CORE) && defined (CORE_CM0PLUS) LL_EXTI_WriteReg(C2EMR2, 0x00000000U); #else LL_EXTI_WriteReg(EMR2, 0x00000000U); -#endif - +#endif /* DUAL_CORE && CORE_CM0PLUS */ + return SUCCESS; } @@ -203,7 +202,7 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) default: status = ERROR; break; -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) { @@ -278,7 +277,7 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) default: status = ERROR; break; -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) { @@ -324,7 +323,7 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) /* De-configure EXTI Lines in range from 32 to 63 */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); -#endif +#endif /* DUAL_CORE && CORE_CM0PLUS */ } return status; } @@ -362,5 +361,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.h index fb26f047343..b5c4323197a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -125,13 +124,13 @@ typedef struct #if defined(DUAL_CORE) #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ -#endif +#endif /* DUAL_CORE */ #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ #if defined(DUAL_CORE) #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ #define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ -#endif +#endif /* DUAL_CORE */ #define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ #define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ #define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ @@ -139,14 +138,14 @@ typedef struct #define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ #if defined(DUAL_CORE) #define LL_EXTI_LINE_ALL_32_63 (EXTI_IMR2_IM34 | EXTI_IMR2_IM36 | EXTI_IMR2_IM37 | \ - EXTI_IMR2_IM38 | EXTI_IMR2_IM39 | EXTI_IMR2_IM40 | \ - EXTI_IMR2_IM41 | EXTI_IMR2_IM42 | EXTI_IMR2_IM43 | \ - EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | EXTI_IMR2_IM46) /*!< All Extended line not reserved*/ + EXTI_IMR2_IM38 | EXTI_IMR2_IM39 | EXTI_IMR2_IM40 | \ + EXTI_IMR2_IM41 | EXTI_IMR2_IM42 | EXTI_IMR2_IM43 | \ + EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | EXTI_IMR2_IM46) /*!< All Extended line not reserved*/ #else #define LL_EXTI_LINE_ALL_32_63 (EXTI_IMR2_IM34 | EXTI_IMR2_IM38 | EXTI_IMR2_IM42 | \ - EXTI_IMR2_IM43 | EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | \ - EXTI_IMR2_IM46) /*!< All Extended line not reserved*/ -#endif + EXTI_IMR2_IM43 | EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | \ + EXTI_IMR2_IM46) /*!< All Extended line not reserved*/ +#endif /* DUAL_CORE */ #if defined(USE_FULL_LL_DRIVER) #define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ @@ -218,8 +217,8 @@ typedef struct /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ + * @{ + */ /** @defgroup EXTI_LL_EF_IT_Management IT_Management * @{ */ @@ -312,7 +311,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->C2IMR1, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 @@ -364,7 +363,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->C2IMR2, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 @@ -454,7 +453,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) { CLEAR_BIT(EXTI->C2IMR1, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 @@ -506,7 +505,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->C2IMR2, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 @@ -596,7 +595,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) { return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 @@ -648,7 +647,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @} @@ -722,7 +721,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->C2EMR1, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Enable ExtiLine Event request for Lines in range 32 to 63 @@ -752,7 +751,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->C2EMR2, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 @@ -818,7 +817,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) { CLEAR_BIT(EXTI->C2EMR1, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Disable ExtiLine Event request for Lines in range 32 to 63 @@ -848,7 +847,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->C2EMR2, ExtiLine); } -#endif +#endif /* DUAL_CORE */ /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 @@ -914,7 +913,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) { return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 @@ -944,7 +943,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @} @@ -1407,7 +1406,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_45 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) @@ -1551,6 +1550,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); #endif #endif /* __STM32WLxx_LL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.c index 7f0df24451c..efb04e80a15 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -258,6 +257,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.h index e65b5ab16e3..2d240924e5b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1034,5 +1033,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif #endif /* STM32WLxx_LL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_hsem.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_hsem.h index 12cef215508..45eaadd77f5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_hsem.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_hsem.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -55,12 +54,15 @@ extern "C" { */ #define LL_HSEM_COREID_NONE 0U #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1 +#if defined(DUAL_CORE) #define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2 +#endif /* DUAL_CORE */ #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT /** * @} */ + /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_HSEM_ReadReg function * @{ @@ -286,6 +288,8 @@ __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) /** * @brief Release all semaphore with the same core id. * @rmtoll CR KEY LL_HSEM_ResetAllLock + * @rmtoll CR SEC LL_HSEM_ResetAllLock + * @rmtoll CR PRIV LL_HSEM_ResetAllLock * @param HSEMx HSEM Instance. * @param key Key value. * @param core This parameter can be one of the following values: @@ -576,7 +580,8 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ + /** * @} */ @@ -855,7 +860,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32 { return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @} */ @@ -879,5 +884,3 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32 #endif #endif /* __STM32WLxx_LL_HSEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c index 43921ec348f..ab7ad7a95e0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -231,5 +230,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h index 92823afbe90..ffb04293ead 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2271,5 +2270,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); #endif #endif /* STM32WLxx_LL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_ipcc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_ipcc.h index f92f9d78d66..36b6b0e08c5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_ipcc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_ipcc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -720,4 +719,3 @@ __STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const #endif /* STM32WLxx_LL_IPCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h index dc43d8f0920..620c97a7eaa 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -337,5 +336,3 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) #endif #endif /* STM32WLxx_LL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.c index 050feda5c69..d575df62889 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -28,7 +27,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -59,11 +58,11 @@ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) -#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) || \ - ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) +#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) -#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) || \ - ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) +#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -148,7 +147,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ @@ -199,13 +198,16 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpOR; uint32_t tmpRCR; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /********** Save LPTIM Config *********/ /* Save LPTIM source clock */ @@ -281,8 +283,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } @@ -312,7 +313,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) LPTIMx->CFGR = tmpCFGR; LPTIMx->OR = tmpOR; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** @@ -334,5 +336,3 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.h index c6e2f34d6b8..d695f945bf3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -67,22 +66,26 @@ typedef struct uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ uint32_t Prescaler; /*!< Specifies the prescaler division ratio. This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. - This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/ + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ uint32_t Waveform; /*!< Specifies the waveform shape. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ uint32_t Polarity; /*!< Specifies waveform polarity. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ } LL_LPTIM_InitTypeDef; /** @@ -100,9 +103,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -116,15 +119,15 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ -#define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event Interrupt Enable */ -#define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ +#define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event */ +#define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK */ /** * @} */ @@ -329,6 +332,19 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ @@ -336,7 +352,7 @@ typedef struct ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} @@ -366,7 +382,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -419,7 +435,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } @@ -462,7 +478,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -477,7 +493,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) @@ -489,9 +505,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @brief Get actual auto reload value * @rmtoll ARR ARR LL_LPTIM_GetAutoReload * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -515,7 +531,7 @@ __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repe * @param LPTIMx Low-Power Timer instance * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP)); } @@ -542,7 +558,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); } @@ -557,7 +573,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -585,7 +601,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -634,7 +650,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -661,7 +677,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); } @@ -705,7 +721,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -785,7 +801,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -860,7 +876,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * (*) Value not defined in all devices. \n * */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -875,7 +891,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -889,7 +905,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -925,13 +941,14 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } /** - * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. * @note This function must be called when the LPTIM instance is disabled. * @note When both external clock signal edges are considered active ones, * the LPTIM must also be clocked by an internal clock source with a @@ -966,7 +983,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -981,7 +998,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -1019,7 +1036,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -1058,7 +1075,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -1071,13 +1088,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) * @{ */ + /** * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); } @@ -1088,18 +1106,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } @@ -1110,7 +1128,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1132,7 +1150,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1149,12 +1167,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } @@ -1171,12 +1190,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1193,12 +1213,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1215,12 +1236,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1237,12 +1259,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully completed; If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully + completed; If so, a new one can be initiated. * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL); } @@ -1264,7 +1287,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL); } @@ -1305,7 +1328,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } @@ -1338,7 +1361,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } @@ -1371,7 +1394,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -1404,14 +1427,14 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** * @brief Enable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1422,7 +1445,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Disable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1433,18 +1456,18 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. - * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** * @brief Enable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP + * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1455,7 +1478,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP + * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1466,18 +1489,18 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. - * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP + * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** * @brief Enable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1488,7 +1511,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1499,18 +1522,18 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. - * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } /** * @brief Enable repetition register update successfully completed interrupt (REPOKIE). - * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK + * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1521,7 +1544,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx) /** * @brief Disable repetition register update successfully completed interrupt (REPOKIE). - * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK + * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1532,18 +1555,18 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled. - * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK + * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)) ? 1UL : 0UL); } /** * @brief Enable update event interrupt (UEIE). - * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE + * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1554,7 +1577,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx) /** * @brief Disable update event interrupt (UEIE). - * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE + * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1565,11 +1588,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the update event interrupt (UEIE) is enabled. - * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE + * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE * @param LPTIMx Low-Power Timer instance *@ retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)) ? 1UL : 0UL); } @@ -1596,5 +1619,3 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx) #endif #endif /* STM32WLxx_LL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.c index f9e20406c18..6720c5db7ba 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -127,7 +126,7 @@ * - SUCCESS: LPUART registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) { ErrorStatus status = SUCCESS; @@ -165,7 +164,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content * - ERROR: Problem occurred during LPUART Registers initialization */ -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk; @@ -281,6 +280,3 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h index 013c67dd3e4..1e952b4c70f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -154,16 +153,15 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_WriteReg function * @{ */ -#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -172,27 +170,27 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_ReadReg function * @{ */ -#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ -#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ -#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ -#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ -#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ -#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ /** * @} */ @@ -201,19 +199,21 @@ typedef struct * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions * @{ */ -#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ -#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ -#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ -#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ -#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ /** * @} */ @@ -234,10 +234,10 @@ typedef struct /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ */ -#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ /** * @} */ @@ -245,9 +245,9 @@ typedef struct /** @defgroup LPUART_LL_EC_PARITY Parity Control * @{ */ -#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** * @} */ @@ -255,8 +255,8 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP Wakeup * @{ */ -#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ -#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ /** * @} */ @@ -264,9 +264,9 @@ typedef struct /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth * @{ */ -#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ /** * @} */ @@ -274,18 +274,27 @@ typedef struct /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ -#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ -#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ -#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ -#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ -#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ -#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ -#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ -#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ -#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ -#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ -#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -293,8 +302,8 @@ typedef struct /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ */ -#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ /** * @} */ @@ -302,8 +311,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap * @{ */ -#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} */ @@ -311,8 +320,8 @@ typedef struct /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ -#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} */ @@ -320,8 +329,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ -#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} */ @@ -329,8 +338,11 @@ typedef struct /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ -#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ /** * @} */ @@ -338,8 +350,10 @@ typedef struct /** @defgroup LPUART_LL_EC_BITORDER Bit Order * @{ */ -#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ /** * @} */ @@ -347,8 +361,8 @@ typedef struct /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ -#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} */ @@ -356,10 +370,12 @@ typedef struct /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control * @{ */ -#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ /** * @} */ @@ -367,9 +383,9 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ -#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ -#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ -#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** * @} */ @@ -377,8 +393,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ -#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} */ @@ -386,8 +402,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -506,7 +522,7 @@ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -539,7 +555,7 @@ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -574,7 +590,7 @@ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -609,7 +625,7 @@ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -673,7 +689,7 @@ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -751,7 +767,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint * @arg @ref LL_LPUART_DIRECTION_TX * @arg @ref LL_LPUART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -785,7 +801,7 @@ __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -812,7 +828,7 @@ __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t * @arg @ref LL_LPUART_WAKEUP_IDLELINE * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); } @@ -841,7 +857,7 @@ __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t Dat * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); } @@ -874,7 +890,7 @@ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -921,7 +937,7 @@ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t Pre * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -948,7 +964,7 @@ __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_ * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); } @@ -1006,7 +1022,7 @@ __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t Swap * @arg @ref LL_LPUART_TXRX_STANDARD * @arg @ref LL_LPUART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); } @@ -1033,7 +1049,7 @@ __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); } @@ -1060,7 +1076,7 @@ __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); } @@ -1090,7 +1106,7 @@ __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); } @@ -1121,7 +1137,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_BITORDER_LSBFIRST * @arg @ref LL_LPUART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1165,7 +1181,7 @@ __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_ * @param LPUARTx LPUART Instance * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1178,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) * @arg @ref LL_LPUART_ADDRESS_DETECT_4B * @arg @ref LL_LPUART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); } @@ -1255,7 +1271,7 @@ __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t Ha * @arg @ref LL_LPUART_HWCONTROL_CTS * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1288,7 +1304,7 @@ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1317,7 +1333,7 @@ __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT * @arg @ref LL_LPUART_WAKEUP_ON_RXNE */ -__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); } @@ -1382,7 +1398,8 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri * @arg @ref LL_LPUART_PRESCALER_DIV256 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) { uint32_t lpuartdiv; uint32_t brrresult; @@ -1438,7 +1455,7 @@ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -1469,7 +1486,7 @@ __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : c */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -1492,7 +1509,7 @@ __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -1525,7 +1542,7 @@ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -1552,7 +1569,7 @@ __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_DE_POLARITY_HIGH * @arg @ref LL_LPUART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); } @@ -1571,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -1582,7 +1599,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -1593,7 +1610,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -1604,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -1615,7 +1632,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } @@ -1629,7 +1646,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -1640,7 +1657,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUART * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } @@ -1654,7 +1671,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -1665,7 +1682,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -1676,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -1687,7 +1704,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -1698,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -1709,7 +1726,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -1720,7 +1737,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -1731,7 +1748,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } @@ -1742,7 +1759,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -1753,7 +1770,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -1764,7 +1781,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -1775,7 +1792,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -1786,7 +1803,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -1797,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -1857,17 +1874,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); } -/** - * @brief Clear TX FIFO Empty Flag - * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); -} - /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC @@ -2232,7 +2238,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } @@ -2246,7 +2252,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -2257,7 +2263,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } @@ -2271,7 +2277,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -2282,7 +2288,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -2293,7 +2299,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -2304,7 +2310,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -2315,7 +2321,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -2326,7 +2332,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -2337,7 +2343,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -2348,7 +2354,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } @@ -2359,7 +2365,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -2370,7 +2376,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -2411,7 +2417,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -2444,7 +2450,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -2477,7 +2483,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -2492,7 +2498,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -2524,7 +2530,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) { return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -2535,7 +2541,7 @@ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) { return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); } @@ -2615,8 +2621,8 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx); -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct); +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); /** * @} @@ -2643,4 +2649,3 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); #endif /* STM32WLxx_LL_LPUART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.c index 275ae427f10..c70f33cb9f8 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -46,23 +45,23 @@ * @{ */ #define IS_LL_PKA_MODE(__VALUE__) (((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP) ||\ - ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\ - ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP) ||\ - ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_ECC) ||\ - ((__VALUE__) == LL_PKA_MODE_ECC_KP_PRIMITIVE) ||\ - ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\ - ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\ - ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\ - ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\ - ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\ - ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\ - ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\ - ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\ - ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\ - ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\ - ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\ - ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\ - ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL)) + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP) ||\ + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_ECC) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_KP_PRIMITIVE) ||\ + ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\ + ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\ + ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\ + ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\ + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL)) /** * @} */ @@ -159,6 +158,3 @@ void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.h index 35e63a2bc78..77a56909b7e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pka.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -94,7 +93,7 @@ typedef struct */ /** @defgroup PKA_LL_EC_MODE Operation Mode - * @brief List of opearation mode. + * @brief List of operation mode. * @{ */ #define LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP ((uint32_t)0x00000000U) /*!< Compute Montgomery parameter and modular exponentiation */ @@ -173,9 +172,9 @@ typedef struct * @param PKAx PKA Instance. * @param Mode This parameter can be one of the following values: * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM * @arg @ref LL_PKA_MODE_MODULAR_EXP - * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC * @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION @@ -235,9 +234,9 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @param Mode This parameter can be one of the following values: * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM * @arg @ref LL_PKA_MODE_MODULAR_EXP - * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC * @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION @@ -265,9 +264,9 @@ __STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode) * @param PKAx PKA Instance. * @retval Returned value can be one of the following values: * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM * @arg @ref LL_PKA_MODE_MODULAR_EXP - * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC * @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION @@ -533,5 +532,3 @@ void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); #endif #endif /* STM32WLxx_LL_PKA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.c index 241c4363a62..8660982ee75 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -147,4 +146,3 @@ ErrorStatus LL_PWR_DeInit(void) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.h index e13f7fbe6c4..e287bd79885 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2285,4 +2284,3 @@ ErrorStatus LL_PWR_DeInit(void); #endif /* __STM32WLxx_LL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c index 91efbd2d188..fc52397c184 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -627,7 +626,10 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) default: if (LL_RCC_PLL_IsReady() == 1U) { - rng_frequency = RCC_PLL_GetFreqDomain_RNG(); + if (LL_RCC_PLL_IsEnabledDomain_RNG() == 1U) + { + rng_frequency = RCC_PLL_GetFreqDomain_RNG(); + } } break; } @@ -654,7 +656,10 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */ if (LL_RCC_PLL_IsReady() == 1U) { - i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); + if (LL_RCC_PLL_IsEnabledDomain_I2S() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); + } } break; @@ -703,7 +708,10 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ if (LL_RCC_PLL_IsReady() == 1U) { - adc_frequency = RCC_PLL_GetFreqDomain_ADC(); + if (LL_RCC_PLL_IsEnabledDomain_ADC() == 1U) + { + adc_frequency = RCC_PLL_GetFreqDomain_ADC(); + } } break; case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */ @@ -1090,5 +1098,3 @@ static uint32_t RCC_PLL_GetFreqDomain_I2S(void) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.h index 159f81e0088..1febd507697 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -346,8 +345,8 @@ typedef struct /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency * @{ */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ /** * @} */ @@ -428,10 +427,10 @@ typedef struct /** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC * @{ */ -#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/ -#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock*/ -#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/ -#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/ +#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */ /** * @} */ @@ -439,10 +438,10 @@ typedef struct /** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC * @{ */ -#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL selected as RNG Clock */ -#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as RNG clock*/ -#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as RNG clock*/ -#define LL_RCC_RNG_CLKSOURCE_MSI (RCC_CCIPR_RNGSEL_1 | RCC_CCIPR_RNGSEL_0) /*!< MSI selected as RNG clock*/ +#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL selected as RNG Clock */ +#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_MSI (RCC_CCIPR_RNGSEL_1 | RCC_CCIPR_RNGSEL_0) /*!< MSI selected as RNG clock */ /** * @} */ @@ -525,7 +524,7 @@ typedef struct /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source * @{ */ -#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */ @@ -618,7 +617,7 @@ typedef struct * @{ */ #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ -#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */ +#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */ /** * @} */ @@ -2721,6 +2720,15 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); } +/** + * @brief Check if PLL output mapped on ADC domain clock is enabled + * @rmtoll PLLCFGR RCC_PLLCFGR_PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL); +} /** * @brief Enable PLL output mapped on RNG domain clock @@ -2744,6 +2752,16 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); } +/** + * @brief Check if PLL output mapped on RNG domain clock is enabled + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_RNG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL output mapped on I2S domain clock * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_I2S @@ -2766,6 +2784,16 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); } +/** + * @brief Check if PLL output mapped on I2S domain clock is enabled + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_I2S + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL output mapped on SYSCLK domain * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS @@ -2789,6 +2817,16 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); } +/** + * @brief Check if PLL output mapped on SYS domain clock is enabled + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL); +} + /** * @brief Configure PLL clock source * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource @@ -3400,5 +3438,3 @@ uint32_t LL_RCC_GetRTCClockFreq(void); #endif #endif /* __STM32WLxx_LL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c index 6ef53964e21..fab9fe4bd7f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -147,5 +146,3 @@ void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.h index 7271a3b73f1..33e0cbe57b3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -674,5 +673,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); #endif #endif /* __STM32WLxx_LL_RNG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c index b80c475b601..6da72d53337 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -890,5 +889,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.h index 218c9b08a72..f03a4d1df1d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -4599,5 +4598,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); #endif #endif /* STM32WLxx_LL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c index 3478ef6633c..a3dd3526273 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -27,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ @@ -530,4 +529,3 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_ #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h index 3e04ef1a224..61560af5e6c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2281,4 +2280,3 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, #endif /* STM32WLxx_LL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_system.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_system.h index d9ae6aa35c1..0d5523be395 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_system.h @@ -3,6 +3,18 @@ * @file stm32wlxx_ll_system.h * @author MCD Application Team * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -17,17 +29,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -590,7 +591,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL))) >> ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL)); #else - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> ((POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) & 0x0000000FUL))); + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)); #endif } @@ -1923,5 +1924,3 @@ __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) #endif #endif /* STM32WLxx_LL_SYSTEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.c index fa648fcf5b1..de9c89fe70f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -190,16 +189,16 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -274,12 +273,13 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -327,7 +327,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Set the fields of the TIMx output channel configuration data * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) * @retval None */ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) @@ -353,12 +354,13 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -392,7 +394,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy /** * @brief Set the fields of the TIMx input channel configuration data * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) * @retval None */ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) @@ -412,12 +415,13 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -444,7 +448,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy /** * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) * @retval None */ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) @@ -464,12 +469,13 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct /** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -528,7 +534,8 @@ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *T /** * @brief Set the fields of the TIMx Hall sensor interface configuration data * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) * @retval None */ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) @@ -555,12 +562,13 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -635,7 +643,8 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType /** * @brief Set the fields of the Break and Dead Time configuration data structure * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval None */ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) @@ -667,12 +676,13 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -697,13 +707,10 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); - } + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(TIMx)) { @@ -744,7 +751,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -823,7 +830,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -902,7 +909,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -981,7 +988,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1051,7 +1058,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1112,7 +1119,7 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1172,7 +1179,7 @@ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1205,7 +1212,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1238,7 +1245,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1271,7 +1278,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1313,4 +1320,3 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h index 649049acfd4..f9cea59480f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -216,24 +215,29 @@ typedef struct uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts @@ -241,10 +245,13 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; /** @@ -255,43 +262,51 @@ typedef struct uint32_t OCMode; /*!< Specifies the output mode. This parameter can be a value of @ref TIM_LL_EC_OCMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ uint32_t OCState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ } LL_TIM_OC_InitTypeDef; /** @@ -304,22 +319,26 @@ typedef struct uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t ICActiveInput; /*!< Specifies the input. This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_IC_InitTypeDef; @@ -331,47 +350,56 @@ typedef struct uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC2Filter; /*!< Specifies the TI2 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_ENCODER_InitTypeDef; @@ -384,26 +412,31 @@ typedef struct uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; /** @@ -414,97 +447,121 @@ typedef struct uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_LL_EC_OSSR - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE - This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() @note Bidirectional break input is only supported by advanced timers instances. - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE - This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() @note Bidirectional break input is only supported by advanced timers instances. - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ } LL_TIM_BDTR_InitTypeDef; /** @@ -1142,8 +1199,8 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap * @{ */ -#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR1_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */ -#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ +#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR1_RMP_MASK /*!< No internal trigger on TIM2_ITR1 */ +#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP) /*!< TIM2_ITR1 is connected to USB SOF */ /** * @} */ @@ -1237,10 +1294,6 @@ typedef struct * @} */ -/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros - * @{ - */ - /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); @@ -1264,10 +1317,17 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1278,7 +1338,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1292,7 +1352,8 @@ typedef struct ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1304,7 +1365,8 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1375,7 +1437,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -1408,7 +1470,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -1442,7 +1504,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -1469,7 +1531,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -1513,7 +1575,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -1555,13 +1617,14 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } /** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1579,7 +1642,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi } /** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1590,7 +1654,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -1617,7 +1681,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -1630,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -1657,7 +1721,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -1686,7 +1750,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -1714,14 +1778,15 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap * @param TIMx Timer instance * @retval None @@ -1747,7 +1812,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @param Counter Counter value * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) { return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); } @@ -1826,7 +1891,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -2026,7 +2091,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } /** @@ -2061,11 +2126,11 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } /** @@ -2127,7 +2192,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -2196,7 +2261,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -2443,7 +2508,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -2564,7 +2630,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2580,7 +2646,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2596,7 +2662,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2612,7 +2678,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2625,7 +2691,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } @@ -2638,7 +2704,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR6)); } @@ -2710,7 +2776,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); } @@ -2757,7 +2824,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2808,7 +2875,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2883,7 +2950,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2940,7 +3007,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -2997,7 +3064,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -3013,7 +3080,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -3029,7 +3096,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -3045,7 +3112,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -3092,7 +3159,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -3272,7 +3339,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -3598,7 +3665,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -3641,7 +3708,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -3761,11 +3828,11 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 * @param DMABurstLength This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS @@ -3906,7 +3973,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -3928,7 +3995,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -3950,7 +4017,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -3972,7 +4039,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -3994,7 +4061,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -4016,7 +4083,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } @@ -4038,7 +4105,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } @@ -4060,7 +4127,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -4082,7 +4149,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -4104,7 +4171,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -4126,7 +4193,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } @@ -4143,12 +4210,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -4165,12 +4233,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -4187,12 +4256,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -4209,12 +4279,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -4236,7 +4307,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); } @@ -4276,7 +4347,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -4309,7 +4380,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -4342,7 +4413,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -4375,7 +4446,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -4408,7 +4479,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -4441,7 +4512,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -4474,7 +4545,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -4507,7 +4578,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -4516,7 +4587,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) * @} */ -/** @defgroup TIM_LL_EF_DMA_Management DMA-Management +/** @defgroup TIM_LL_EF_DMA_Management DMA Management * @{ */ /** @@ -4547,7 +4618,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -4580,7 +4651,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -4613,7 +4684,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -4646,7 +4717,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -4679,7 +4750,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -4712,7 +4783,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -4745,7 +4816,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -4867,17 +4938,17 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ @@ -4902,4 +4973,3 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT #endif #endif /* __STM32WLxx_LL_TIM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c index 4f1a4583a02..1f22de92a8e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -126,7 +125,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -170,7 +169,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -294,7 +293,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; @@ -370,5 +369,4 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h index 830b0ad9e55..07f4200bf06 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -649,7 +648,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -688,7 +687,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -727,7 +726,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -766,7 +765,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -837,7 +836,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -915,7 +914,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -949,7 +948,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -976,7 +975,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -1007,7 +1006,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -1040,7 +1039,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -1067,7 +1066,7 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } @@ -1099,7 +1098,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } @@ -1130,7 +1129,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } @@ -1161,7 +1160,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } @@ -1240,7 +1239,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -1279,7 +1278,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); } @@ -1310,7 +1309,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -1371,7 +1370,7 @@ __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapCo * @arg @ref LL_USART_TXRX_STANDARD * @arg @ref LL_USART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); } @@ -1398,7 +1397,7 @@ __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); } @@ -1425,7 +1424,7 @@ __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); } @@ -1454,7 +1453,7 @@ __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); } @@ -1485,7 +1484,7 @@ __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_BITORDER_LSBFIRST * @arg @ref LL_USART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1524,7 +1523,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); } @@ -1592,7 +1591,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); } @@ -1636,7 +1635,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1649,7 +1648,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) * @arg @ref LL_USART_ADDRESS_DETECT_4B * @arg @ref LL_USART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); } @@ -1738,7 +1737,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1771,7 +1770,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); } @@ -1804,7 +1803,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1837,7 +1836,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) * @arg @ref LL_USART_WAKEUP_ON_STARTBIT * @arg @ref LL_USART_WAKEUP_ON_RXNE */ -__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); } @@ -1925,7 +1924,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) { uint32_t usartdiv; @@ -1974,7 +1973,7 @@ __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); } @@ -1997,7 +1996,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } @@ -2044,7 +2043,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); } @@ -2075,7 +2074,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -2092,7 +2091,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2104,7 +2103,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2151,7 +2150,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); } @@ -2190,7 +2189,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); } @@ -2222,7 +2221,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, * @param USARTx USART Instance * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } @@ -2239,7 +2238,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR */ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2251,7 +2250,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2268,7 +2267,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); } /** @@ -2280,7 +2279,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } @@ -2327,7 +2326,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -2373,7 +2372,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); } @@ -2415,7 +2414,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); } @@ -2454,7 +2453,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } @@ -2493,7 +2492,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); } @@ -2528,7 +2527,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -2555,7 +2554,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -2594,7 +2593,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -2625,7 +2624,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_DE_POLARITY_HIGH * @arg @ref LL_USART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); } @@ -2921,7 +2920,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -2932,7 +2931,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -2943,7 +2942,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -2954,7 +2953,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -2965,7 +2964,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } @@ -2981,7 +2980,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -2992,7 +2991,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } @@ -3008,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -3021,7 +3020,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); } @@ -3034,7 +3033,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -3047,7 +3046,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -3058,7 +3057,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); } @@ -3071,7 +3070,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); } @@ -3084,7 +3083,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); } @@ -3097,7 +3096,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); } @@ -3110,7 +3109,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); } @@ -3121,7 +3120,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -3132,7 +3131,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -3143,7 +3142,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -3154,7 +3153,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -3167,7 +3166,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } @@ -3178,7 +3177,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -3189,7 +3188,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -3202,7 +3201,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -3215,7 +3214,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -3226,7 +3225,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } @@ -3239,7 +3238,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -3252,7 +3251,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -3884,7 +3883,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } @@ -3900,7 +3899,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -3911,7 +3910,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } @@ -3927,7 +3926,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -3938,7 +3937,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -3949,7 +3948,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -3960,7 +3959,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); } @@ -3973,7 +3972,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); } @@ -3986,7 +3985,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -3999,7 +3998,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -4012,7 +4011,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); } @@ -4023,7 +4022,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -4036,7 +4035,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -4049,7 +4048,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } @@ -4062,7 +4061,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -4075,7 +4074,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } @@ -4088,7 +4087,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -4129,7 +4128,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -4162,7 +4161,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -4195,7 +4194,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -4210,7 +4209,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -4242,7 +4241,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -4253,7 +4252,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); } @@ -4361,10 +4360,10 @@ __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} @@ -4391,4 +4390,3 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS #endif /* STM32WLxx_LL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.c index 7571e610719..af1a1a4896c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -377,6 +376,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllrfreq = 0; + uint32_t range_sel; uint32_t msi_range; #if defined(DUAL_CORE) uint32_t hclk2freq; @@ -386,8 +386,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS if (UTILS_PLL_IsBusy() == SUCCESS) { /* Get the current MSI range */ - if (LL_RCC_MSI_IsEnabledRangeSelect() == 0U) + if (LL_RCC_MSI_IsEnabledRangeSelect() == 1U) { + range_sel = LL_RCC_MSIRANGESEL_RUN; msi_range = LL_RCC_MSI_GetRange(); switch (msi_range) { @@ -413,6 +414,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS } else { + range_sel = LL_RCC_MSIRANGESEL_STANDBY; msi_range = LL_RCC_MSI_GetRangeAfterStandby(); switch (msi_range) { @@ -434,7 +436,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { /* Calculate the new PLL output frequency & verify all PLL stages are correct (VCO input ranges, VCO output ranges & SYSCLK max) when assert activated */ - pllrfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range), + pllrfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(range_sel, msi_range), UTILS_PLLInitStruct); #if defined(DUAL_CORE) @@ -581,8 +583,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS if (UTILS_PLL_IsBusy() == SUCCESS) { /* Calculate the new PLL output frequency */ - pllrfreq = UTILS_GetPLLOutputFrequency(HSE_VALUE, UTILS_PLLInitStruct); - + if (LL_RCC_HSE_IsEnabledDiv2() != 1UL) + { + pllrfreq = UTILS_GetPLLOutputFrequency(HSE_VALUE, UTILS_PLLInitStruct); + } + else + { + /* HSE Pre is set */ + pllrfreq = UTILS_GetPLLOutputFrequency(HSE_VALUE/2UL, UTILS_PLLInitStruct); + } + #if defined(DUAL_CORE) hclk2freq = __LL_RCC_CALC_HCLK2_FREQ(pllrfreq, UTILS_ClkInitStruct->CPU2CLKDivider); @@ -788,5 +798,3 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.h index 6ac3e99817e..61803a4d447 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_utils.h @@ -3,6 +3,17 @@ * @file stm32wlxx_ll_utils.h * @author MCD Application Team * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,17 +27,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -331,5 +331,3 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS #endif #endif /* __STM32WLxx_LL_UTILS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_wwdg.h index 3ff825dd67b..d981c1763a5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -327,5 +326,3 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) #endif #endif /* STM32WLxx_LL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h index d10d8aa0b0e..e99225fb287 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h @@ -6,8 +6,8 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c index 745619ea3e4..ddfd46af0ce 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c @@ -4,17 +4,6 @@ * @author MCD Application Team * @brief CMSIS Cortex Device Peripheral Access Layer System Source File * - ****************************************************************************** - * @attention - * - * Copyright (c) 2020(-2021) STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** * This file provides two functions and one global variable to be called from * user application: * - SystemInit(): This function is called at startup just after reset and @@ -68,6 +57,17 @@ * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** */ /** @addtogroup CMSIS @@ -122,7 +122,7 @@ /* Note: Following vector table addresses must be defined in line with linker configuration. */ -/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2 +/*!< Uncomment the following line if you need to relocate CPU1 CM0+ and/or CPU2 CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept at address 0x00 which correspond to automatic remap of boot address selected */ /* #define USER_VECT_TAB_ADDRESS */ From eb2a255f1a01f789a832a38ca54169534b11aa03 Mon Sep 17 00:00:00 2001 From: Charles Date: Tue, 22 Aug 2023 12:17:04 +0200 Subject: [PATCH 14/16] Changed static to weak --- targets/TARGET_STM/sleep.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index b266c74c70a..8d1184194bf 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -40,7 +40,7 @@ extern void restore_timer_ctx(void); extern void SetSysClock(void); /* Wait loop - assuming tick is 1 us */ -static void wait_loop(uint32_t timeout) +__WEAK void wait_loop(uint32_t timeout) { uint32_t t1, t2, elapsed = 0; t1 = us_ticker_read(); @@ -52,7 +52,7 @@ static void wait_loop(uint32_t timeout) } -static void ForcePeriphOutofDeepSleep(void) +__WEAK void ForcePeriphOutofDeepSleep(void) { uint32_t pFLatency = 0; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; @@ -84,7 +84,7 @@ static void ForcePeriphOutofDeepSleep(void) } -static void ForceOscOutofDeepSleep(void) +__WEAK void ForceOscOutofDeepSleep(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; From 7e7c397adb9a5f103e306e4041484ac623600ed6 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Thu, 7 Sep 2023 10:07:15 +0300 Subject: [PATCH 15/16] Fix: Do not disable SPI for manual drive mode during transaction setup It has been reported that disabling SPI module causes glitch for manual SS drive mode Signed-off-by: Sadik.Ozer --- .../Libraries/PeriphDrivers/Source/SPI/spi_reva.c | 2 +- .../Libraries/PeriphDrivers/Source/SPI/spi_reva.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index 82a54ee2447..05d6ad32a91 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req) states[spi_num].started = 0; states[spi_num].req_done = 0; // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). - if (states[spi_num].ssDeassert == 1) { + if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1)) { (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index 2726ede6110..9b201d5e32d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req) states[spi_num].started = 0; states[spi_num].req_done = 0; // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). - if (states[spi_num].ssDeassert == 1) { + if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1) ) { (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); } From 9beb0e83f95116e9bd76ae54e1935e7dd47225f4 Mon Sep 17 00:00:00 2001 From: Lukas Karel Date: Mon, 11 Sep 2023 13:44:29 +0200 Subject: [PATCH 16/16] make cellular event queue size configurable update unit tests --- connectivity/cellular/mbed_lib.json | 4 ++++ .../cellular/source/framework/device/CellularDevice.cpp | 2 +- .../tests/UNITTESTS/framework/device/athandler/CMakeLists.txt | 1 + .../UNITTESTS/framework/device/cellularcontext/CMakeLists.txt | 1 + .../UNITTESTS/framework/device/cellulardevice/CMakeLists.txt | 1 + .../framework/device/cellularstatemachine/CMakeLists.txt | 1 + 6 files changed, 9 insertions(+), 1 deletion(-) diff --git a/connectivity/cellular/mbed_lib.json b/connectivity/cellular/mbed_lib.json index c8a24fc2cd4..ed16d4a73a3 100644 --- a/connectivity/cellular/mbed_lib.json +++ b/connectivity/cellular/mbed_lib.json @@ -48,6 +48,10 @@ "at-handler-buffer-size" : { "help": "Size of the AT handler buffer", "value": 32 + }, + "event-queue-size": { + "help": "The amount of events the default EventQueue should store", + "value": 10 } } } diff --git a/connectivity/cellular/source/framework/device/CellularDevice.cpp b/connectivity/cellular/source/framework/device/CellularDevice.cpp index 50d900e14ab..79417d3d8b8 100644 --- a/connectivity/cellular/source/framework/device/CellularDevice.cpp +++ b/connectivity/cellular/source/framework/device/CellularDevice.cpp @@ -39,7 +39,7 @@ CellularDevice::CellularDevice() : #if MBED_CONF_CELLULAR_USE_SMS _sms_ref_count(0), #endif //MBED_CONF_CELLULAR_USE_SMS - _info_ref_count(0), _queue(10 * EVENTS_EVENT_SIZE), _state_machine(0), + _info_ref_count(0), _queue(MBED_CONF_CELLULAR_EVENT_QUEUE_SIZE * EVENTS_EVENT_SIZE), _state_machine(0), _status_cb(), _nw(0) #ifdef MBED_CONF_RTOS_PRESENT , _queue_thread(osPriorityNormal, 2048, NULL, "cellular_queue") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt index 2f8e40ce47d..85a5e17e062 100644 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt @@ -15,6 +15,7 @@ target_compile_definitions(${TEST_NAME} DEVICE_INTERRUPTIN=1 MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 + MBED_CONF_CELLULAR_EVENT_QUEUE_SIZE=10 MBED_CONF_RTOS_PRESENT=1 ) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt index af73d4776c7..afb57309c9c 100644 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt @@ -21,6 +21,7 @@ target_compile_definitions(${TEST_NAME} DEVICE_INTERRUPTIN=1 MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 + MBED_CONF_CELLULAR_EVENT_QUEUE_SIZE=10 ) target_sources(${TEST_NAME} diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt index 48843591c97..675f4abadf2 100644 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt @@ -19,6 +19,7 @@ target_compile_definitions(${TEST_NAME} DEVICE_INTERRUPTIN=1 MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 + MBED_CONF_CELLULAR_EVENT_QUEUE_SIZE=10 ) target_sources(${TEST_NAME} diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt index e5e66bdc927..4c2d0a574f0 100644 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt @@ -20,6 +20,7 @@ target_compile_definitions(${TEST_NAME} DEVICE_INTERRUPTIN=1 MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 + MBED_CONF_CELLULAR_EVENT_QUEUE_SIZE=10 ) target_sources(${TEST_NAME}