Verilator compile fails when compiling with the RV32E parameter set

[ColinDBates]

Observed Behavior

As the attached log file shows, fusesoc.log, Verilator compile of the Cheri Ibex fails if the RV32E parameter is set.

Expected Behavior

RV32E enables 16x GP registers, which matches the CHERIoT spec. Without the RV32E option there are 16x redundant GP registers implemented.

The attached patch, ibex_cheri_rv32e.patch.txt, fixes the compile issue for me and has been lightly tested. The patch also propagates the RV32E parameter through the top_tracing module.

Steps to reproduce the issue

I'm using the Sonata System project.

My Environment

EDA tool and version:
Verilator 5.023 devel rev v5.020-200-g88831ca21

Operating system:
Ubuntu 20.04

Version of the Ibex source code:
Sonata main with RV32E parameter set at the ibex_top level

[marnovandermaas]

Thanks for the patch, definitely useful to fix this lint issues.

[kliuMsft]

Please try a2f2976. Verilator compilation works for me on this commit.

[ColinDBates]

Hi Kunyan,

It looks like you might have some missing lint checks in Verilator. In particular, I'm seeing a lot of WIDTHEXPAND and WIDTHTRUNC errors in the cheri_trvk_stage module.

I've currently got the following Verilator command line (which has a lot less tough lint optioning as compared with the Sonata project)
verilator -f lowrisc_sonata_system_0.vc -DDISABLE_PRIM_CDC_RAND_DELAY --trace --trace-fst --trace-structs --trace-params --trace-max-array 1024 --notiming -CFLAGS "-Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator" -LDFLAGS "-pthread -lutil -lelf" -Wall -Wno-UNOPTFLAT -Wno-GENUNNAMED -Wno-STMTDLY -Wwarn-IMPERFECTSCH -Wno-ASSIGNDLY -Wno-UNUSEDSIGNAL +define+RVFI --unroll-count 72 -j 4

Cheers

[ColinDBates]

Or, maybe, you are not setting RV32E parameter in your compile?

[kliuMsft]

I did set RV32E, but my verilator setting probably is different from yours. I can't say I fully agree with verilator's lint rules.. however, the index width complaints probably should be fixed (even though they aren't real RTL issues since the cheriot_ibex design guarantee all regfile addresses <=16 when cheri_pmode=1). I can look into that.

[kliuMsft]

Please take at the latest commit 3f0ec86. Basically,

1. RV32E is now a top-level parameter at ibexc_top_tracing level.
2. In ibexc_top, NCAPS now fixed to 16.
3. I took a closer look at the verilator warnings. Currently, I have -Wno-WIDTH and -Wno-UNOPTFLAT in my setup. Basically I am not convinced that the verilator WIDTH warnings provides much value and OPTFLAT warnings keep declaring false combinatorial loops. So I would recommend keeping those 2 warnings turned off.