diff --git a/ChipWhisperer-Husky/src/conf_usb.h b/ChipWhisperer-Husky/src/conf_usb.h index e7cdc38..3a6c00e 100644 --- a/ChipWhisperer-Husky/src/conf_usb.h +++ b/ChipWhisperer-Husky/src/conf_usb.h @@ -68,7 +68,6 @@ struct {\ */ #define USB_DEVICE_VENDOR_ID 0x2B3E -#define USB_DEVICE_PRODUCT_ID 0xACE5 #define USB_DEVICE_MAJOR_VERSION 9 #define USB_DEVICE_MINOR_VERSION 0 @@ -84,13 +83,22 @@ struct {\ extern char usb_serial_number[33]; #define USB_DEVICE_MANUFACTURE_NAME "NewAE Technology Inc." -#define USB_DEVICE_PRODUCT_NAME "ChipWhisperer Husky" #define USB_DEVICE_GET_SERIAL_NAME_POINTER usb_serial_number #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 +#ifdef ChipWhisperer_Husky +#define USB_DEVICE_PRODUCT_NAME "ChipWhisperer Husky" #define FW_VER_MAJOR 1 #define FW_VER_MINOR 5 #define FW_VER_DEBUG 0 +#define USB_DEVICE_PRODUCT_ID 0xACE5 +#elif ChipWhisperer_Husky_Plus +#define USB_DEVICE_PRODUCT_NAME "ChipWhisperer Husky Plus" +#define FW_VER_MAJOR 1 +#define FW_VER_MINOR 0 +#define FW_VER_DEBUG 0 +#define USB_DEVICE_PRODUCT_ID 0xACE6 +#endif //! To authorize the High speed #if (UC3A3||UC3A4) diff --git a/ChipWhisperer-Husky/src/config/conf_clock.h b/ChipWhisperer-Husky/src/config/conf_clock.h new file mode 100644 index 0000000..39f660a --- /dev/null +++ b/ChipWhisperer-Husky/src/config/conf_clock.h @@ -0,0 +1,92 @@ +/** + * \file + * + * \brief SAM3U clock configuration. + * + * Copyright (c) 2011 - 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef CONF_CLOCK_H_INCLUDED +#define CONF_CLOCK_H_INCLUDED + +// ===== System Clock (MCK) Source Options +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS +#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK + +// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 + +// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) +// Use mul and div effective values here. +#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL0_MUL 16 +#define CONFIG_PLL0_DIV 1 + +// ===== UPLL (UTMI) Hardware fixed at 480 MHZ. + +// ===== USB Clock Source fixed at UPLL. + +// ===== Target frequency (System clock) +// - XTAL frequency: 12MHZ +// - System clock source: PLLA +// - System clock prescaler: 2 (divided by 2) +// - PLLA source: XTAL +// - PLLA output: XTAL * 16 / 1 +// - System clock is: 12 * 16 / 1 / 2 = 96MHZ +// ===== Target frequency (USB Clock) +// - USB clock source: UPLL +// - UPLL frequency: 480MHZ +// - USB clock: 480MHZ + + +#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/ChipWhisperer-Husky/src/config/conf_sleepmgr.h b/ChipWhisperer-Husky/src/config/conf_sleepmgr.h new file mode 100644 index 0000000..44f9762 --- /dev/null +++ b/ChipWhisperer-Husky/src/config/conf_sleepmgr.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Sleep manager configuration + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef CONF_SLEEPMGR_H +#define CONF_SLEEPMGR_H + +#define CONFIG_SLEEPMGR_ENABLE + +#endif /* CONF_SLEEPMGR_H */ diff --git a/ChipWhisperer-Husky/src/config/conf_uart_serial.h b/ChipWhisperer-Husky/src/config/conf_uart_serial.h new file mode 100644 index 0000000..e499429 --- /dev/null +++ b/ChipWhisperer-Husky/src/config/conf_uart_serial.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Serial USART service configuration. + * + * Copyright (C) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef CONF_USART_SERIAL_H +#define CONF_USART_SERIAL_H + +/** UART Interface */ +#define CONF_UART CONSOLE_UART +/** Baudrate setting */ +#define CONF_UART_BAUDRATE 115200 +/** Parity setting */ +#define CONF_UART_PARITY UART_MR_PAR_NO + +#endif/* CONF_USART_SERIAL_H_INCLUDED */ diff --git a/ChipWhisperer-Husky/src/config/conf_usb.h b/ChipWhisperer-Husky/src/config/conf_usb.h new file mode 100644 index 0000000..e7cdc38 --- /dev/null +++ b/ChipWhisperer-Husky/src/config/conf_usb.h @@ -0,0 +1,309 @@ +/** + * \file + * + * \brief USB configuration file + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _CONF_USB_H_ +#define _CONF_USB_H_ + +#include "compiler.h" + +//#warning You must refill the following definitions with a correct values + +#define NAEUSB_MPSSE_SUPPORT 1 + +#if NAEUSB_MPSSE_SUPPORT == 1 +#define UDI_MPSSE_EP_BULK_IN (0x01 | USB_EP_DIR_IN) +#define UDI_MPSSE_EP_BULK_OUT (0x02 | USB_EP_DIR_OUT) + +#define UDI_COMPOSITE_DESC_T \ + udi_vendor_desc_t udi_vendor; \ +union { \ +struct { \ + usb_iad_desc_t udi_iad;\ + udi_cdc_comm_desc_t udi_cdc_comm; \ + udi_cdc_data_desc_t udi_cdc_data; \ +};\ +struct {\ + udi_vendor_desc_t udi_vendor_mpsse; \ +};\ +}; +#endif + + +/** + * USB Device Configuration + * @{ + */ + +#define USB_DEVICE_VENDOR_ID 0x2B3E +#define USB_DEVICE_PRODUCT_ID 0xACE5 + +#define USB_DEVICE_MAJOR_VERSION 9 +#define USB_DEVICE_MINOR_VERSION 0 +#define USB_DEVICE_POWER 500 // Consumption on Vbus line (mA) +#define USB_DEVICE_ATTR \ +(USB_CONFIG_ATTR_BUS_POWERED) +// (USB_CONFIG_ATTR_SELF_POWERED) +// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) +// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) + +//! USB Device string definitions +#define USB_DEVICE_HS_SUPPORT 1 +extern char usb_serial_number[33]; + +#define USB_DEVICE_MANUFACTURE_NAME "NewAE Technology Inc." +#define USB_DEVICE_PRODUCT_NAME "ChipWhisperer Husky" +#define USB_DEVICE_GET_SERIAL_NAME_POINTER usb_serial_number +#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 + +#define FW_VER_MAJOR 1 +#define FW_VER_MINOR 5 +#define FW_VER_DEBUG 0 + +//! To authorize the High speed +#if (UC3A3||UC3A4) +//#define USB_DEVICE_HS_SUPPORT +#endif + +/** + * USB Device Callbacks definitions (Optional) + * @{ + */ +void main_sof_action(void); +void main_resume_action(void); +void main_suspend_action(void); +#define UDC_VBUS_EVENT(b_vbus_high) +#define UDC_SOF_EVENT() main_sof_action() +#define UDC_SUSPEND_EVENT() main_suspend_action() +#define UDC_RESUME_EVENT() main_resume_action() +//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature +// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() +// extern void user_callback_remotewakeup_enable(void); +// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() +// extern void user_callback_remotewakeup_disable(void); +//! When a extra string descriptor must be supported +//! other than manufacturer, product and serial string +// #define UDC_GET_EXTRA_STRING() +//@} + +//@} + +/** + * USB Device low level configuration + * When only one interface is used, these configurations are defined by the class module. + * For composite device, these configuration must be defined here + * @{ + */ +//! Control endpoint size +#define USB_DEVICE_EP_CTRL_SIZE 64 + +//! Number of interfaces for this device +#define USB_DEVICE_NB_INTERFACE 3 // 1 or more + +//! Total endpoint used by all interfaces +//! Note: +//! It is possible to define an IN and OUT endpoints with the same number on XMEGA product only +//! E.g. MSC class can be have IN endpoint 0x81 and OUT endpoint 0x01 +#define USB_DEVICE_MAX_EP 6 // 0 to max endpoint requested by interfaces +//@} + +//@} + + +/** + * USB Interface Configuration + * @{ + */ + +/** + * Configuration of CDC interface (if used) + * @{ + */ + +//! Number of communication port used (1 to 3) +#define UDI_CDC_PORT_NB 1 + +bool cdc_enable(uint8_t port); +void cdc_disable(uint8_t port); +//! Interface callback definition +#define UDI_CDC_ENABLE_EXT(port) cdc_enable(port) +#define UDI_CDC_DISABLE_EXT(port) cdc_disable(port) +//#define UDI_CDC_RX_NOTIFY(port) +//#define UDI_CDC_TX_EMPTY_NOTIFY(port) +#define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port) +extern void my_callback_rx_notify(uint8_t port); +#define UDI_CDC_TX_EMPTY_NOTIFY(port) +#include "usb_protocol_cdc.h" +extern void my_callback_config(uint8_t port, usb_cdc_line_coding_t * cfg); +#define UDI_CDC_SET_CODING_EXT(port,cfg) my_callback_config(port,cfg) +//#define UDI_CDC_SET_CODING_EXT(port,cfg) + +#define UDI_CDC_SET_DTR_EXT(port,set) +#define UDI_CDC_SET_RTS_EXT(port,set) +/* + * #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() + * extern bool my_callback_cdc_enable(void); + * #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() + * extern void my_callback_cdc_disable(void); + * #define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port) + * extern void my_callback_rx_notify(uint8_t port); + * #define UDI_CDC_TX_EMPTY_NOTIFY(port) my_callback_tx_empty_notify(port) + * extern void my_callback_tx_empty_notify(uint8_t port); + * #define UDI_CDC_SET_CODING_EXT(port,cfg) my_callback_config(port,cfg) + * extern void my_callback_config(uint8_t port, usb_cdc_line_coding_t * cfg); + * #define UDI_CDC_SET_DTR_EXT(port,set) my_callback_cdc_set_dtr(port,set) + * extern void my_callback_cdc_set_dtr(uint8_t port, bool b_enable); + * #define UDI_CDC_SET_RTS_EXT(port,set) my_callback_cdc_set_rts(port,set) + * extern void my_callback_cdc_set_rts(uint8_t port, bool b_enable); + */ + +//! Define it when the transfer CDC Device to Host is a low rate (<512000 bauds) +//! to reduce CDC buffers size +#define UDI_CDC_LOW_RATE + +//! Default configuration of communication port +#define UDI_CDC_DEFAULT_RATE 115200 +#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 +#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE +#define UDI_CDC_DEFAULT_DATABITS 8 + +/** + * USB CDC low level configuration + * In standalone these configurations are defined by the CDC module. + * For composite device, these configuration must be defined here + * @{ + */ +//! Endpoints' numbers used by single or first CDC port +#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint + +//! Interface numbers used by single or first CDC port +#define UDI_CDC_COMM_IFACE_NUMBER_0 1 +#define UDI_CDC_DATA_IFACE_NUMBER_0 2 + +/** + * Configuration of vendor interface + * @{ + */ +//! Interface callback definition +bool main_vendor_enable(void); +void main_vendor_disable(void); +bool main_setup_out_received(void); +bool main_setup_in_received(void); +#define UDI_VENDOR_ENABLE_EXT() main_vendor_enable() +#define UDI_VENDOR_DISABLE_EXT() main_vendor_disable() +#define UDI_VENDOR_SETUP_OUT_RECEIVED() main_setup_out_received() +#define UDI_VENDOR_SETUP_IN_RECEIVED() main_setup_in_received() + +//! endpoints size for full speed +//! Note: Disable the endpoints of a type, if size equal 0 +#define UDI_VENDOR_EPS_SIZE_INT_FS 0 /*64*/ +#define UDI_VENDOR_EPS_SIZE_BULK_FS 64 +#if SAMG55 +#define UDI_VENDOR_EPS_SIZE_ISO_FS 0 +#else +#define UDI_VENDOR_EPS_SIZE_ISO_FS 0 /*256*/ +#endif + +//! endpoints size for high speed +#define UDI_VENDOR_EPS_SIZE_INT_HS 0 /*64*/ +#define UDI_VENDOR_EPS_SIZE_BULK_HS 512 +#define UDI_VENDOR_EPS_SIZE_ISO_HS 0 /*64*/ + +//! Endpoint numbers definition +#define UDI_VENDOR_EP_BULK_IN (0x05 | USB_EP_DIR_IN) +#define UDI_VENDOR_EP_BULK_OUT (0x06 | USB_EP_DIR_OUT) + +/** + * \name UDD Configuration + */ +//@{ +//! Maximum 6 endpoints used by vendor interface +#define UDI_VENDOR_EP_NB_INT ((UDI_VENDOR_EPS_SIZE_INT_FS)?2:0) +#define UDI_VENDOR_EP_NB_BULK ((UDI_VENDOR_EPS_SIZE_BULK_FS)?2:0) +#define UDI_VENDOR_EP_NB_ISO ((UDI_VENDOR_EPS_SIZE_ISO_FS)?2:0) + +//! Interface number +#define UDI_VENDOR_IFACE_NUMBER 0 + +#ifndef UDI_COMPOSITE_DESC_T +#define UDI_COMPOSITE_DESC_T \ +udi_vendor_desc_t udi_vendor; \ +usb_iad_desc_t udi_iad;\ +udi_cdc_comm_desc_t udi_cdc_comm; \ +udi_cdc_data_desc_t udi_cdc_data; +#endif + + +//! USB Interfaces descriptor value for Full Speed +#define UDI_COMPOSITE_DESC_FS \ +.udi_vendor = UDI_VENDOR_DESC_FS, \ +.udi_iad = UDI_CDC_IAD_DESC_0, \ +.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ +.udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, + +#define UDI_COMPOSITE_DESC_HS \ +.udi_vendor = UDI_VENDOR_DESC_HS, \ +.udi_iad = UDI_CDC_IAD_DESC_0, \ +.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ +.udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, + +//! USB Interface APIs +#define UDI_COMPOSITE_API &udi_api_vendor, \ +&udi_api_cdc_comm, \ +&udi_api_cdc_data, +/** + * USB Device Driver Configuration + * @{ + */ +//@} + +//! The includes of classes and other headers must be done at the end of this file to avoid compile error +#include "udi_vendor.h" +#include "udi_cdc.h" +/* Example of include for interface +#include "udi_msc.h" +#include "udi_hid_kbd.h" +#include "udi_hid_mouse.h" +#include "udi_cdc.h" +#include "udi_phdc.h" +#include "udi_vendor.h" +*/ +/* Declaration of callbacks used by USB +#include "callback_def.h" +*/ + +#endif // _CONF_USB_H_ diff --git a/ChipWhisperer-Husky/src/main.c b/ChipWhisperer-Husky/src/main.c index 61e3bee..6776593 100644 --- a/ChipWhisperer-Husky/src/main.c +++ b/ChipWhisperer-Husky/src/main.c @@ -164,7 +164,6 @@ int main(void) while (true) { if (current_transfer_len == 0) { - cdc_send_to_pc(); MPSSE_main_sendrecv_byte(); } } diff --git a/ChipWhisperer-Husky/src/naeusb b/ChipWhisperer-Husky/src/naeusb index eb5209e..8ded0ec 160000 --- a/ChipWhisperer-Husky/src/naeusb +++ b/ChipWhisperer-Husky/src/naeusb @@ -1 +1 @@ -Subproject commit eb5209e03b73406a3d992ebffb5bf797b061a1cd +Subproject commit 8ded0ecc49f4e1a51fc310c161a13d2e31b435af diff --git a/ChipWhisperer-Husky/src/symbols.txt b/ChipWhisperer-Husky/src/symbols.txt new file mode 100644 index 0000000..8a5750d --- /dev/null +++ b/ChipWhisperer-Husky/src/symbols.txt @@ -0,0 +1,15969 @@ +# 1 "./config/conf_usb.h" +# 1 "C:\\Users\\alexl\\code\\chipwhisperer-husky\\ChipWhisperer-Husky\\src//" +# 1 "" +#define __STDC__ 1 +#define __STDC_VERSION__ 199901L +#define __STDC_UTF_16__ 1 +#define __STDC_UTF_32__ 1 +#define __STDC_HOSTED__ 1 +#define __GNUC__ 10 +#define __GNUC_MINOR__ 3 +#define __GNUC_PATCHLEVEL__ 1 +#define __VERSION__ "10.3.1 20210824 (release)" +#define __ATOMIC_RELAXED 0 +#define __ATOMIC_SEQ_CST 5 +#define __ATOMIC_ACQUIRE 2 +#define __ATOMIC_RELEASE 3 +#define __ATOMIC_ACQ_REL 4 +#define __ATOMIC_CONSUME 1 +#define __OPTIMIZE__ 1 +#define __FINITE_MATH_ONLY__ 0 +#define __SIZEOF_INT__ 4 +#define __SIZEOF_LONG__ 4 +#define __SIZEOF_LONG_LONG__ 8 +#define __SIZEOF_SHORT__ 2 +#define __SIZEOF_FLOAT__ 4 +#define __SIZEOF_DOUBLE__ 8 +#define __SIZEOF_LONG_DOUBLE__ 8 +#define __SIZEOF_SIZE_T__ 4 +#define __CHAR_BIT__ 8 +#define __BIGGEST_ALIGNMENT__ 8 +#define __ORDER_LITTLE_ENDIAN__ 1234 +#define __ORDER_BIG_ENDIAN__ 4321 +#define __ORDER_PDP_ENDIAN__ 3412 +#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ +#define __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__ +#define __SIZEOF_POINTER__ 4 +#define __SIZE_TYPE__ unsigned int +#define __PTRDIFF_TYPE__ int +#define __WCHAR_TYPE__ unsigned int +#define __WINT_TYPE__ unsigned int +#define __INTMAX_TYPE__ long long int +#define __UINTMAX_TYPE__ long long unsigned int +#define __CHAR16_TYPE__ short unsigned int +#define __CHAR32_TYPE__ long unsigned int +#define __SIG_ATOMIC_TYPE__ int +#define __INT8_TYPE__ signed char +#define __INT16_TYPE__ short int +#define __INT32_TYPE__ long int +#define __INT64_TYPE__ long long int +#define __UINT8_TYPE__ unsigned char +#define __UINT16_TYPE__ short unsigned int +#define __UINT32_TYPE__ long unsigned int +#define __UINT64_TYPE__ long long unsigned int +#define __INT_LEAST8_TYPE__ signed char +#define __INT_LEAST16_TYPE__ short int +#define __INT_LEAST32_TYPE__ long int +#define __INT_LEAST64_TYPE__ long long int +#define __UINT_LEAST8_TYPE__ unsigned char +#define __UINT_LEAST16_TYPE__ short unsigned int +#define __UINT_LEAST32_TYPE__ long unsigned int +#define __UINT_LEAST64_TYPE__ long long unsigned int +#define __INT_FAST8_TYPE__ int +#define __INT_FAST16_TYPE__ int +#define __INT_FAST32_TYPE__ int +#define __INT_FAST64_TYPE__ long long int +#define __UINT_FAST8_TYPE__ unsigned int +#define __UINT_FAST16_TYPE__ unsigned int +#define __UINT_FAST32_TYPE__ unsigned int +#define __UINT_FAST64_TYPE__ long long unsigned int +#define __INTPTR_TYPE__ int +#define __UINTPTR_TYPE__ unsigned int +#define __GXX_ABI_VERSION 1014 +#define __SCHAR_MAX__ 0x7f +#define __SHRT_MAX__ 0x7fff +#define __INT_MAX__ 0x7fffffff +#define __LONG_MAX__ 0x7fffffffL +#define __LONG_LONG_MAX__ 0x7fffffffffffffffLL +#define __WCHAR_MAX__ 0xffffffffU +#define __WCHAR_MIN__ 0U +#define __WINT_MAX__ 0xffffffffU +#define __WINT_MIN__ 0U +#define __PTRDIFF_MAX__ 0x7fffffff +#define __SIZE_MAX__ 0xffffffffU +#define __SCHAR_WIDTH__ 8 +#define __SHRT_WIDTH__ 16 +#define __INT_WIDTH__ 32 +#define __LONG_WIDTH__ 32 +#define __LONG_LONG_WIDTH__ 64 +#define __WCHAR_WIDTH__ 32 +#define __WINT_WIDTH__ 32 +#define __PTRDIFF_WIDTH__ 32 +#define __SIZE_WIDTH__ 32 +#define __INTMAX_MAX__ 0x7fffffffffffffffLL +#define __INTMAX_C(c) c ## LL +#define __UINTMAX_MAX__ 0xffffffffffffffffULL +#define __UINTMAX_C(c) c ## ULL +#define __INTMAX_WIDTH__ 64 +#define __SIG_ATOMIC_MAX__ 0x7fffffff +#define __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1) +#define __SIG_ATOMIC_WIDTH__ 32 +#define __INT8_MAX__ 0x7f +#define __INT16_MAX__ 0x7fff +#define __INT32_MAX__ 0x7fffffffL +#define __INT64_MAX__ 0x7fffffffffffffffLL +#define __UINT8_MAX__ 0xff +#define __UINT16_MAX__ 0xffff +#define __UINT32_MAX__ 0xffffffffUL +#define __UINT64_MAX__ 0xffffffffffffffffULL +#define __INT_LEAST8_MAX__ 0x7f +#define __INT8_C(c) c +#define __INT_LEAST8_WIDTH__ 8 +#define __INT_LEAST16_MAX__ 0x7fff +#define __INT16_C(c) c +#define __INT_LEAST16_WIDTH__ 16 +#define __INT_LEAST32_MAX__ 0x7fffffffL +#define __INT32_C(c) c ## L +#define __INT_LEAST32_WIDTH__ 32 +#define __INT_LEAST64_MAX__ 0x7fffffffffffffffLL +#define __INT64_C(c) c ## LL +#define __INT_LEAST64_WIDTH__ 64 +#define __UINT_LEAST8_MAX__ 0xff +#define __UINT8_C(c) c +#define __UINT_LEAST16_MAX__ 0xffff +#define __UINT16_C(c) c +#define __UINT_LEAST32_MAX__ 0xffffffffUL +#define __UINT32_C(c) c ## UL +#define __UINT_LEAST64_MAX__ 0xffffffffffffffffULL +#define __UINT64_C(c) c ## ULL +#define __INT_FAST8_MAX__ 0x7fffffff +#define __INT_FAST8_WIDTH__ 32 +#define __INT_FAST16_MAX__ 0x7fffffff +#define __INT_FAST16_WIDTH__ 32 +#define __INT_FAST32_MAX__ 0x7fffffff +#define __INT_FAST32_WIDTH__ 32 +#define __INT_FAST64_MAX__ 0x7fffffffffffffffLL +#define __INT_FAST64_WIDTH__ 64 +#define __UINT_FAST8_MAX__ 0xffffffffU +#define __UINT_FAST16_MAX__ 0xffffffffU +#define __UINT_FAST32_MAX__ 0xffffffffU +#define __UINT_FAST64_MAX__ 0xffffffffffffffffULL +#define __INTPTR_MAX__ 0x7fffffff +#define __INTPTR_WIDTH__ 32 +#define __UINTPTR_MAX__ 0xffffffffU +#define __GCC_IEC_559 0 +#define __GCC_IEC_559_COMPLEX 0 +#define __FLT_EVAL_METHOD__ 0 +#define __FLT_EVAL_METHOD_TS_18661_3__ 0 +#define __DEC_EVAL_METHOD__ 2 +#define __FLT_RADIX__ 2 +#define __FLT_MANT_DIG__ 24 +#define __FLT_DIG__ 6 +#define __FLT_MIN_EXP__ (-125) +#define __FLT_MIN_10_EXP__ (-37) +#define __FLT_MAX_EXP__ 128 +#define __FLT_MAX_10_EXP__ 38 +#define __FLT_DECIMAL_DIG__ 9 +#define __FLT_MAX__ 3.4028234663852886e+38F +#define __FLT_NORM_MAX__ 3.4028234663852886e+38F +#define __FLT_MIN__ 1.1754943508222875e-38F +#define __FLT_EPSILON__ 1.1920928955078125e-7F +#define __FLT_DENORM_MIN__ 1.4012984643248171e-45F +#define __FLT_HAS_DENORM__ 1 +#define __FLT_HAS_INFINITY__ 1 +#define __FLT_HAS_QUIET_NAN__ 1 +#define __DBL_MANT_DIG__ 53 +#define __DBL_DIG__ 15 +#define __DBL_MIN_EXP__ (-1021) +#define __DBL_MIN_10_EXP__ (-307) +#define __DBL_MAX_EXP__ 1024 +#define __DBL_MAX_10_EXP__ 308 +#define __DBL_DECIMAL_DIG__ 17 +#define __DBL_MAX__ ((double)1.7976931348623157e+308L) +#define __DBL_NORM_MAX__ ((double)1.7976931348623157e+308L) +#define __DBL_MIN__ ((double)2.2250738585072014e-308L) +#define __DBL_EPSILON__ ((double)2.2204460492503131e-16L) +#define __DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L) +#define __DBL_HAS_DENORM__ 1 +#define __DBL_HAS_INFINITY__ 1 +#define __DBL_HAS_QUIET_NAN__ 1 +#define __LDBL_MANT_DIG__ 53 +#define __LDBL_DIG__ 15 +#define __LDBL_MIN_EXP__ (-1021) +#define __LDBL_MIN_10_EXP__ (-307) +#define __LDBL_MAX_EXP__ 1024 +#define __LDBL_MAX_10_EXP__ 308 +#define __DECIMAL_DIG__ 17 +#define __LDBL_DECIMAL_DIG__ 17 +#define __LDBL_MAX__ 1.7976931348623157e+308L +#define __LDBL_NORM_MAX__ 1.7976931348623157e+308L +#define __LDBL_MIN__ 2.2250738585072014e-308L +#define __LDBL_EPSILON__ 2.2204460492503131e-16L +#define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L +#define __LDBL_HAS_DENORM__ 1 +#define __LDBL_HAS_INFINITY__ 1 +#define __LDBL_HAS_QUIET_NAN__ 1 +#define __FLT32_MANT_DIG__ 24 +#define __FLT32_DIG__ 6 +#define __FLT32_MIN_EXP__ (-125) +#define __FLT32_MIN_10_EXP__ (-37) +#define __FLT32_MAX_EXP__ 128 +#define __FLT32_MAX_10_EXP__ 38 +#define __FLT32_DECIMAL_DIG__ 9 +#define __FLT32_MAX__ 3.4028234663852886e+38F32 +#define __FLT32_NORM_MAX__ 3.4028234663852886e+38F32 +#define __FLT32_MIN__ 1.1754943508222875e-38F32 +#define __FLT32_EPSILON__ 1.1920928955078125e-7F32 +#define __FLT32_DENORM_MIN__ 1.4012984643248171e-45F32 +#define __FLT32_HAS_DENORM__ 1 +#define __FLT32_HAS_INFINITY__ 1 +#define __FLT32_HAS_QUIET_NAN__ 1 +#define __FLT64_MANT_DIG__ 53 +#define __FLT64_DIG__ 15 +#define __FLT64_MIN_EXP__ (-1021) +#define __FLT64_MIN_10_EXP__ (-307) +#define __FLT64_MAX_EXP__ 1024 +#define __FLT64_MAX_10_EXP__ 308 +#define __FLT64_DECIMAL_DIG__ 17 +#define __FLT64_MAX__ 1.7976931348623157e+308F64 +#define __FLT64_NORM_MAX__ 1.7976931348623157e+308F64 +#define __FLT64_MIN__ 2.2250738585072014e-308F64 +#define __FLT64_EPSILON__ 2.2204460492503131e-16F64 +#define __FLT64_DENORM_MIN__ 4.9406564584124654e-324F64 +#define __FLT64_HAS_DENORM__ 1 +#define __FLT64_HAS_INFINITY__ 1 +#define __FLT64_HAS_QUIET_NAN__ 1 +#define __FLT32X_MANT_DIG__ 53 +#define __FLT32X_DIG__ 15 +#define __FLT32X_MIN_EXP__ (-1021) +#define __FLT32X_MIN_10_EXP__ (-307) +#define __FLT32X_MAX_EXP__ 1024 +#define __FLT32X_MAX_10_EXP__ 308 +#define __FLT32X_DECIMAL_DIG__ 17 +#define __FLT32X_MAX__ 1.7976931348623157e+308F32x +#define __FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x +#define __FLT32X_MIN__ 2.2250738585072014e-308F32x +#define __FLT32X_EPSILON__ 2.2204460492503131e-16F32x +#define __FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32x +#define __FLT32X_HAS_DENORM__ 1 +#define __FLT32X_HAS_INFINITY__ 1 +#define __FLT32X_HAS_QUIET_NAN__ 1 +#define __SFRACT_FBIT__ 7 +#define __SFRACT_IBIT__ 0 +#define __SFRACT_MIN__ (-0.5HR-0.5HR) +#define __SFRACT_MAX__ 0X7FP-7HR +#define __SFRACT_EPSILON__ 0x1P-7HR +#define __USFRACT_FBIT__ 8 +#define __USFRACT_IBIT__ 0 +#define __USFRACT_MIN__ 0.0UHR +#define __USFRACT_MAX__ 0XFFP-8UHR +#define __USFRACT_EPSILON__ 0x1P-8UHR +#define __FRACT_FBIT__ 15 +#define __FRACT_IBIT__ 0 +#define __FRACT_MIN__ (-0.5R-0.5R) +#define __FRACT_MAX__ 0X7FFFP-15R +#define __FRACT_EPSILON__ 0x1P-15R +#define __UFRACT_FBIT__ 16 +#define __UFRACT_IBIT__ 0 +#define __UFRACT_MIN__ 0.0UR +#define __UFRACT_MAX__ 0XFFFFP-16UR +#define __UFRACT_EPSILON__ 0x1P-16UR +#define __LFRACT_FBIT__ 31 +#define __LFRACT_IBIT__ 0 +#define __LFRACT_MIN__ (-0.5LR-0.5LR) +#define __LFRACT_MAX__ 0X7FFFFFFFP-31LR +#define __LFRACT_EPSILON__ 0x1P-31LR +#define __ULFRACT_FBIT__ 32 +#define __ULFRACT_IBIT__ 0 +#define __ULFRACT_MIN__ 0.0ULR +#define __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR +#define __ULFRACT_EPSILON__ 0x1P-32ULR +#define __LLFRACT_FBIT__ 63 +#define __LLFRACT_IBIT__ 0 +#define __LLFRACT_MIN__ (-0.5LLR-0.5LLR) +#define __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR +#define __LLFRACT_EPSILON__ 0x1P-63LLR +#define __ULLFRACT_FBIT__ 64 +#define __ULLFRACT_IBIT__ 0 +#define __ULLFRACT_MIN__ 0.0ULLR +#define __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR +#define __ULLFRACT_EPSILON__ 0x1P-64ULLR +#define __SACCUM_FBIT__ 7 +#define __SACCUM_IBIT__ 8 +#define __SACCUM_MIN__ (-0X1P7HK-0X1P7HK) +#define __SACCUM_MAX__ 0X7FFFP-7HK +#define __SACCUM_EPSILON__ 0x1P-7HK +#define __USACCUM_FBIT__ 8 +#define __USACCUM_IBIT__ 8 +#define __USACCUM_MIN__ 0.0UHK +#define __USACCUM_MAX__ 0XFFFFP-8UHK +#define __USACCUM_EPSILON__ 0x1P-8UHK +#define __ACCUM_FBIT__ 15 +#define __ACCUM_IBIT__ 16 +#define __ACCUM_MIN__ (-0X1P15K-0X1P15K) +#define __ACCUM_MAX__ 0X7FFFFFFFP-15K +#define __ACCUM_EPSILON__ 0x1P-15K +#define __UACCUM_FBIT__ 16 +#define __UACCUM_IBIT__ 16 +#define __UACCUM_MIN__ 0.0UK +#define __UACCUM_MAX__ 0XFFFFFFFFP-16UK +#define __UACCUM_EPSILON__ 0x1P-16UK +#define __LACCUM_FBIT__ 31 +#define __LACCUM_IBIT__ 32 +#define __LACCUM_MIN__ (-0X1P31LK-0X1P31LK) +#define __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK +#define __LACCUM_EPSILON__ 0x1P-31LK +#define __ULACCUM_FBIT__ 32 +#define __ULACCUM_IBIT__ 32 +#define __ULACCUM_MIN__ 0.0ULK +#define __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK +#define __ULACCUM_EPSILON__ 0x1P-32ULK +#define __LLACCUM_FBIT__ 31 +#define __LLACCUM_IBIT__ 32 +#define __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK) +#define __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK +#define __LLACCUM_EPSILON__ 0x1P-31LLK +#define __ULLACCUM_FBIT__ 32 +#define __ULLACCUM_IBIT__ 32 +#define __ULLACCUM_MIN__ 0.0ULLK +#define __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK +#define __ULLACCUM_EPSILON__ 0x1P-32ULLK +#define __QQ_FBIT__ 7 +#define __QQ_IBIT__ 0 +#define __HQ_FBIT__ 15 +#define __HQ_IBIT__ 0 +#define __SQ_FBIT__ 31 +#define __SQ_IBIT__ 0 +#define __DQ_FBIT__ 63 +#define __DQ_IBIT__ 0 +#define __TQ_FBIT__ 127 +#define __TQ_IBIT__ 0 +#define __UQQ_FBIT__ 8 +#define __UQQ_IBIT__ 0 +#define __UHQ_FBIT__ 16 +#define __UHQ_IBIT__ 0 +#define __USQ_FBIT__ 32 +#define __USQ_IBIT__ 0 +#define __UDQ_FBIT__ 64 +#define __UDQ_IBIT__ 0 +#define __UTQ_FBIT__ 128 +#define __UTQ_IBIT__ 0 +#define __HA_FBIT__ 7 +#define __HA_IBIT__ 8 +#define __SA_FBIT__ 15 +#define __SA_IBIT__ 16 +#define __DA_FBIT__ 31 +#define __DA_IBIT__ 32 +#define __TA_FBIT__ 63 +#define __TA_IBIT__ 64 +#define __UHA_FBIT__ 8 +#define __UHA_IBIT__ 8 +#define __USA_FBIT__ 16 +#define __USA_IBIT__ 16 +#define __UDA_FBIT__ 32 +#define __UDA_IBIT__ 32 +#define __UTA_FBIT__ 64 +#define __UTA_IBIT__ 64 +#define __REGISTER_PREFIX__ +#define __USER_LABEL_PREFIX__ +#define __GNUC_STDC_INLINE__ 1 +#define __CHAR_UNSIGNED__ 1 +#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +#define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +#define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +#define __GCC_ATOMIC_INT_LOCK_FREE 2 +#define __GCC_ATOMIC_LONG_LOCK_FREE 2 +#define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +#define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +#define __HAVE_SPECULATION_SAFE_VALUE 1 +#define __GCC_HAVE_DWARF2_CFI_ASM 1 +#define __PRAGMA_REDEFINE_EXTNAME 1 +#define __SIZEOF_WCHAR_T__ 4 +#define __SIZEOF_WINT_T__ 4 +#define __SIZEOF_PTRDIFF_T__ 4 +#undef __ARM_FEATURE_DSP +# 1 "" +#define __ARM_FEATURE_QBIT 1 +#define __ARM_FEATURE_SAT 1 +#undef __ARM_FEATURE_CRYPTO +# 1 "" +#define __ARM_FEATURE_UNALIGNED 1 +#undef __ARM_FEATURE_QRDMX +# 1 "" +#undef __ARM_FEATURE_CRC32 +# 1 "" +#undef __ARM_FEATURE_DOTPROD +# 1 "" +#undef __ARM_FEATURE_COMPLEX +# 1 "" +#define __ARM_32BIT_STATE 1 +#undef __ARM_FEATURE_MVE +# 1 "" +#undef __ARM_FEATURE_CMSE +# 1 "" +#undef __ARM_FEATURE_LDREX +# 1 "" +#define __ARM_FEATURE_LDREX 7 +#define __ARM_FEATURE_CLZ 1 +#undef __ARM_FEATURE_NUMERIC_MAXMIN +# 1 "" +#undef __ARM_FEATURE_SIMD32 +# 1 "" +#define __ARM_SIZEOF_MINIMAL_ENUM 1 +#define __ARM_SIZEOF_WCHAR_T 4 +#undef __ARM_ARCH_PROFILE +# 1 "" +#define __ARM_ARCH_PROFILE 77 +#define __arm__ 1 +#undef __ARM_ARCH +# 1 "" +#define __ARM_ARCH 7 +#define __APCS_32__ 1 +#define __GCC_ASM_FLAG_OUTPUTS__ 1 +#define __thumb__ 1 +#define __thumb2__ 1 +#define __THUMBEL__ 1 +#undef __ARM_ARCH_ISA_THUMB +# 1 "" +#define __ARM_ARCH_ISA_THUMB 2 +#define __ARMEL__ 1 +#define __SOFTFP__ 1 +#define __VFP_FP__ 1 +#undef __ARM_FP +# 1 "" +#undef __ARM_FP16_FORMAT_IEEE +# 1 "" +#undef __ARM_FP16_FORMAT_ALTERNATIVE +# 1 "" +#undef __ARM_FP16_ARGS +# 1 "" +#undef __ARM_FEATURE_FP16_SCALAR_ARITHMETIC +# 1 "" +#undef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +# 1 "" +#undef __ARM_FEATURE_FP16_FML +# 1 "" +#undef __ARM_FEATURE_FMA +# 1 "" +#undef __ARM_NEON__ +# 1 "" +#undef __ARM_NEON +# 1 "" +#undef __ARM_NEON_FP +# 1 "" +#define __THUMB_INTERWORK__ 1 +#define __ARM_ARCH_7M__ 1 +#define __ARM_PCS 1 +#define __ARM_EABI__ 1 +#undef __FDPIC__ +# 1 "" +#define __ARM_ARCH_EXT_IDIV__ 1 +#define __ARM_FEATURE_IDIV 1 +#define __ARM_ASM_SYNTAX_UNIFIED__ 1 +#undef __ARM_FEATURE_COPROC +# 1 "" +#define __ARM_FEATURE_COPROC 15 +#undef __ARM_FEATURE_CDE +# 1 "" +#undef __ARM_FEATURE_CDE_COPROC +# 1 "" +#undef __ARM_FEATURE_MATMUL_INT8 +# 1 "" +#undef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC +# 1 "" +#undef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC +# 1 "" +#undef __ARM_BF16_FORMAT_ALTERNATIVE +# 1 "" +#define __GXX_TYPEINFO_EQUALITY_INLINE 0 +#define __ELF__ 1 +# 1 "" +#define __USES_INITFINI__ 1 +#define DEBUG 1 +#define ARM_MATH_CM3 true +#define printf iprintf +#define UDD_ENABLE 1 +#define scanf iscanf +#define PLATFORMCW1190 1 +#define ChipWhisperer_Husky_Plus 1 +#define __SAM3U2C__ 1 +#define __PLAT_HUSKY__ 1 +# 1 "./config/conf_usb.h" +# 38 "./config/conf_usb.h" +#define _CONF_USB_H_ + +# 1 "naeusb/sam3u_hal/inc/compiler.h" 1 +# 45 "naeusb/sam3u_hal/inc/compiler.h" +#define UTILS_COMPILER_H +# 55 "naeusb/sam3u_hal/inc/compiler.h" +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 1 3 4 +# 39 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#define _STDDEF_H +#define _STDDEF_H_ + +#define _ANSI_STDDEF_H +# 131 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#define _PTRDIFF_T +#define _T_PTRDIFF_ +#define _T_PTRDIFF +#define __PTRDIFF_T +#define _PTRDIFF_T_ +#define _BSD_PTRDIFF_T_ +#define ___int_ptrdiff_t_h +#define _GCC_PTRDIFF_T +#define _PTRDIFF_T_DECLARED + + + + +# 143 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +typedef int ptrdiff_t; +# 155 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_ptrdiff_t +# 181 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#define __size_t__ +#define __SIZE_T__ +#define _SIZE_T +#define _SYS_SIZE_T_H +#define _T_SIZE_ +#define _T_SIZE +#define __SIZE_T +#define _SIZE_T_ +#define _BSD_SIZE_T_ +#define _SIZE_T_DEFINED_ +#define _SIZE_T_DEFINED +#define _BSD_SIZE_T_DEFINED_ +#define _SIZE_T_DECLARED +#define ___int_size_t_h +#define _GCC_SIZE_T +#define _SIZET_ + + + + + + +#define __size_t + + + + + +typedef unsigned int size_t; +# 231 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_size_t +# 260 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#define __wchar_t__ +#define __WCHAR_T__ +#define _WCHAR_T +#define _T_WCHAR_ +#define _T_WCHAR +#define __WCHAR_T +#define _WCHAR_T_ +#define _BSD_WCHAR_T_ +#define _WCHAR_T_DEFINED_ +#define _WCHAR_T_DEFINED +#define _WCHAR_T_H +#define ___int_wchar_t_h +#define __INT_WCHAR_T_H +#define _GCC_WCHAR_T +#define _WCHAR_T_DECLARED +# 287 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef _BSD_WCHAR_T_ +# 321 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +typedef unsigned int wchar_t; +# 340 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_wchar_t +# 390 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef NULL + + + + +#define NULL ((void *)0) + + + + + +#undef __need_NULL + + + + +#define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) +# 56 "naeusb/sam3u_hal/inc/compiler.h" 2 + + + + + +# 1 "naeusb/sam3u_hal/inc/parts.h" 1 +# 45 "naeusb/sam3u_hal/inc/parts.h" +#define ATMEL_PARTS_H +# 62 "naeusb/sam3u_hal/inc/parts.h" +#define AVR8_PART_IS_DEFINED(part) (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) + + + +#define AVR32_PART_IS_DEFINED(part) (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) + + + +#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) +# 82 "naeusb/sam3u_hal/inc/parts.h" +#define UC3A0 ( AVR32_PART_IS_DEFINED(UC3A0128) || AVR32_PART_IS_DEFINED(UC3A0256) || AVR32_PART_IS_DEFINED(UC3A0512) ) + + + + + +#define UC3A1 ( AVR32_PART_IS_DEFINED(UC3A1128) || AVR32_PART_IS_DEFINED(UC3A1256) || AVR32_PART_IS_DEFINED(UC3A1512) ) + + + + + +#define UC3A3 ( AVR32_PART_IS_DEFINED(UC3A364) || AVR32_PART_IS_DEFINED(UC3A364S) || AVR32_PART_IS_DEFINED(UC3A3128) || AVR32_PART_IS_DEFINED(UC3A3128S) || AVR32_PART_IS_DEFINED(UC3A3256) || AVR32_PART_IS_DEFINED(UC3A3256S) ) +# 103 "naeusb/sam3u_hal/inc/parts.h" +#define UC3A4 ( AVR32_PART_IS_DEFINED(UC3A464) || AVR32_PART_IS_DEFINED(UC3A464S) || AVR32_PART_IS_DEFINED(UC3A4128) || AVR32_PART_IS_DEFINED(UC3A4128S) || AVR32_PART_IS_DEFINED(UC3A4256) || AVR32_PART_IS_DEFINED(UC3A4256S) ) +# 117 "naeusb/sam3u_hal/inc/parts.h" +#define UC3B0 ( AVR32_PART_IS_DEFINED(UC3B064) || AVR32_PART_IS_DEFINED(UC3B0128) || AVR32_PART_IS_DEFINED(UC3B0256) || AVR32_PART_IS_DEFINED(UC3B0512) ) + + + + + + +#define UC3B1 ( AVR32_PART_IS_DEFINED(UC3B164) || AVR32_PART_IS_DEFINED(UC3B1128) || AVR32_PART_IS_DEFINED(UC3B1256) || AVR32_PART_IS_DEFINED(UC3B1512) ) +# 136 "naeusb/sam3u_hal/inc/parts.h" +#define UC3C0 ( AVR32_PART_IS_DEFINED(UC3C064C) || AVR32_PART_IS_DEFINED(UC3C0128C) || AVR32_PART_IS_DEFINED(UC3C0256C) || AVR32_PART_IS_DEFINED(UC3C0512C) ) + + + + + + +#define UC3C1 ( AVR32_PART_IS_DEFINED(UC3C164C) || AVR32_PART_IS_DEFINED(UC3C1128C) || AVR32_PART_IS_DEFINED(UC3C1256C) || AVR32_PART_IS_DEFINED(UC3C1512C) ) + + + + + + +#define UC3C2 ( AVR32_PART_IS_DEFINED(UC3C264C) || AVR32_PART_IS_DEFINED(UC3C2128C) || AVR32_PART_IS_DEFINED(UC3C2256C) || AVR32_PART_IS_DEFINED(UC3C2512C) ) +# 162 "naeusb/sam3u_hal/inc/parts.h" +#define UC3D3 ( AVR32_PART_IS_DEFINED(UC64D3) || AVR32_PART_IS_DEFINED(UC128D3) ) + + + + +#define UC3D4 ( AVR32_PART_IS_DEFINED(UC64D4) || AVR32_PART_IS_DEFINED(UC128D4) ) +# 177 "naeusb/sam3u_hal/inc/parts.h" +#define UC3L0 ( AVR32_PART_IS_DEFINED(UC3L016) || AVR32_PART_IS_DEFINED(UC3L032) || AVR32_PART_IS_DEFINED(UC3L064) ) + + + + + +#define UC3L0128 ( AVR32_PART_IS_DEFINED(UC3L0128) ) + + + +#define UC3L0256 ( AVR32_PART_IS_DEFINED(UC3L0256) ) + + + +#define UC3L3 ( AVR32_PART_IS_DEFINED(UC64L3U) || AVR32_PART_IS_DEFINED(UC128L3U) || AVR32_PART_IS_DEFINED(UC256L3U) ) + + + + + +#define UC3L4 ( AVR32_PART_IS_DEFINED(UC64L4U) || AVR32_PART_IS_DEFINED(UC128L4U) || AVR32_PART_IS_DEFINED(UC256L4U) ) + + + + + +#define UC3L3_L4 (UC3L3 || UC3L4) + + + + + + + +#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) + + +#define UC3B (UC3B0 || UC3B1) + + +#define UC3C (UC3C0 || UC3C1 || UC3C2) + + +#define UC3D (UC3D3 || UC3D4) + + +#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) + + + +#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) +# 240 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_A1 ( AVR8_PART_IS_DEFINED(ATxmega64A1) || AVR8_PART_IS_DEFINED(ATxmega128A1) ) + + + + +#define XMEGA_A3 ( AVR8_PART_IS_DEFINED(ATxmega64A3) || AVR8_PART_IS_DEFINED(ATxmega128A3) || AVR8_PART_IS_DEFINED(ATxmega192A3) || AVR8_PART_IS_DEFINED(ATxmega256A3) ) + + + + + + +#define XMEGA_A3B ( AVR8_PART_IS_DEFINED(ATxmega256A3B) ) + + + +#define XMEGA_A4 ( AVR8_PART_IS_DEFINED(ATxmega16A4) || AVR8_PART_IS_DEFINED(ATxmega32A4) ) +# 266 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_A1U ( AVR8_PART_IS_DEFINED(ATxmega64A1U) || AVR8_PART_IS_DEFINED(ATxmega128A1U) ) + + + + +#define XMEGA_A3U ( AVR8_PART_IS_DEFINED(ATxmega64A3U) || AVR8_PART_IS_DEFINED(ATxmega128A3U) || AVR8_PART_IS_DEFINED(ATxmega192A3U) || AVR8_PART_IS_DEFINED(ATxmega256A3U) ) + + + + + + +#define XMEGA_A3BU ( AVR8_PART_IS_DEFINED(ATxmega256A3BU) ) + + + +#define XMEGA_A4U ( AVR8_PART_IS_DEFINED(ATxmega16A4U) || AVR8_PART_IS_DEFINED(ATxmega32A4U) || AVR8_PART_IS_DEFINED(ATxmega64A4U) || AVR8_PART_IS_DEFINED(ATxmega128A4U) ) +# 294 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_B1 ( AVR8_PART_IS_DEFINED(ATxmega64B1) || AVR8_PART_IS_DEFINED(ATxmega128B1) ) + + + + +#define XMEGA_B3 ( AVR8_PART_IS_DEFINED(ATxmega64B3) || AVR8_PART_IS_DEFINED(ATxmega128B3) ) +# 309 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_C3 ( AVR8_PART_IS_DEFINED(ATxmega384C3) || AVR8_PART_IS_DEFINED(ATxmega256C3) || AVR8_PART_IS_DEFINED(ATxmega192C3) || AVR8_PART_IS_DEFINED(ATxmega128C3) || AVR8_PART_IS_DEFINED(ATxmega64C3) || AVR8_PART_IS_DEFINED(ATxmega32C3) ) +# 318 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_C4 ( AVR8_PART_IS_DEFINED(ATxmega32C4) || AVR8_PART_IS_DEFINED(ATxmega16C4) ) +# 328 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_D3 ( AVR8_PART_IS_DEFINED(ATxmega32D3) || AVR8_PART_IS_DEFINED(ATxmega64D3) || AVR8_PART_IS_DEFINED(ATxmega128D3) || AVR8_PART_IS_DEFINED(ATxmega192D3) || AVR8_PART_IS_DEFINED(ATxmega256D3) || AVR8_PART_IS_DEFINED(ATxmega384D3) ) +# 337 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_D4 ( AVR8_PART_IS_DEFINED(ATxmega16D4) || AVR8_PART_IS_DEFINED(ATxmega32D4) || AVR8_PART_IS_DEFINED(ATxmega64D4) || AVR8_PART_IS_DEFINED(ATxmega128D4) ) +# 349 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_E5 ( AVR8_PART_IS_DEFINED(ATxmega8E5) || AVR8_PART_IS_DEFINED(ATxmega16E5) || AVR8_PART_IS_DEFINED(ATxmega32E5) ) +# 362 "naeusb/sam3u_hal/inc/parts.h" +#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) + + +#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) + + +#define XMEGA_B (XMEGA_B1 || XMEGA_B3) + + +#define XMEGA_C (XMEGA_C3 || XMEGA_C4) + + +#define XMEGA_D (XMEGA_D3 || XMEGA_D4) + + +#define XMEGA_E (XMEGA_E5) + + + + +#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) +# 400 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX0 ( AVR8_PART_IS_DEFINED(ATmega640) || AVR8_PART_IS_DEFINED(ATmega1280) || AVR8_PART_IS_DEFINED(ATmega2560) ) + + + + + +#define MEGA_XX1 ( AVR8_PART_IS_DEFINED(ATmega1281) || AVR8_PART_IS_DEFINED(ATmega2561) ) +# 417 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) + + +#define MEGA_XX4 ( AVR8_PART_IS_DEFINED(ATmega164A) || AVR8_PART_IS_DEFINED(ATmega164PA) || AVR8_PART_IS_DEFINED(ATmega324A) || AVR8_PART_IS_DEFINED(ATmega324PA) || AVR8_PART_IS_DEFINED(ATmega644) || AVR8_PART_IS_DEFINED(ATmega644A) || AVR8_PART_IS_DEFINED(ATmega644PA) || AVR8_PART_IS_DEFINED(ATmega1284P) || AVR8_PART_IS_DEFINED(ATmega128RFA1) ) +# 433 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX4_A ( AVR8_PART_IS_DEFINED(ATmega164A) || AVR8_PART_IS_DEFINED(ATmega164PA) || AVR8_PART_IS_DEFINED(ATmega324A) || AVR8_PART_IS_DEFINED(ATmega324PA) || AVR8_PART_IS_DEFINED(ATmega644A) || AVR8_PART_IS_DEFINED(ATmega644PA) || AVR8_PART_IS_DEFINED(ATmega1284P) ) +# 444 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX8 ( AVR8_PART_IS_DEFINED(ATmega48) || AVR8_PART_IS_DEFINED(ATmega48A) || AVR8_PART_IS_DEFINED(ATmega48PA) || AVR8_PART_IS_DEFINED(ATmega88) || AVR8_PART_IS_DEFINED(ATmega88A) || AVR8_PART_IS_DEFINED(ATmega88PA) || AVR8_PART_IS_DEFINED(ATmega168) || AVR8_PART_IS_DEFINED(ATmega168A) || AVR8_PART_IS_DEFINED(ATmega168PA) || AVR8_PART_IS_DEFINED(ATmega328) || AVR8_PART_IS_DEFINED(ATmega328P) ) +# 459 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX8_A ( AVR8_PART_IS_DEFINED(ATmega48A) || AVR8_PART_IS_DEFINED(ATmega48PA) || AVR8_PART_IS_DEFINED(ATmega88A) || AVR8_PART_IS_DEFINED(ATmega88PA) || AVR8_PART_IS_DEFINED(ATmega168A) || AVR8_PART_IS_DEFINED(ATmega168PA) || AVR8_PART_IS_DEFINED(ATmega328P) ) +# 470 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX ( AVR8_PART_IS_DEFINED(ATmega16) || AVR8_PART_IS_DEFINED(ATmega16A) || AVR8_PART_IS_DEFINED(ATmega32) || AVR8_PART_IS_DEFINED(ATmega32A) || AVR8_PART_IS_DEFINED(ATmega64) || AVR8_PART_IS_DEFINED(ATmega64A) || AVR8_PART_IS_DEFINED(ATmega128) || AVR8_PART_IS_DEFINED(ATmega128A) ) +# 482 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX_A ( AVR8_PART_IS_DEFINED(ATmega16A) || AVR8_PART_IS_DEFINED(ATmega32A) || AVR8_PART_IS_DEFINED(ATmega64A) || AVR8_PART_IS_DEFINED(ATmega128A) ) + + + + + + +#define MEGA_RFA1 ( AVR8_PART_IS_DEFINED(ATmega128RFA1) ) + + + + +#define MEGA_RFR2 ( AVR8_PART_IS_DEFINED(ATmega64RFR2) || AVR8_PART_IS_DEFINED(ATmega128RFR2) || AVR8_PART_IS_DEFINED(ATmega256RFR2) || AVR8_PART_IS_DEFINED(ATmega644RFR2) || AVR8_PART_IS_DEFINED(ATmega1284RFR2) || AVR8_PART_IS_DEFINED(ATmega2564RFR2) ) +# 505 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) + + + + + +#define MEGA_XX_UN0 ( AVR8_PART_IS_DEFINED(ATmega16) || AVR8_PART_IS_DEFINED(ATmega16A) || AVR8_PART_IS_DEFINED(ATmega32) || AVR8_PART_IS_DEFINED(ATmega32A) ) +# 521 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX_UN1 ( AVR8_PART_IS_DEFINED(ATmega64) || AVR8_PART_IS_DEFINED(ATmega64A) || AVR8_PART_IS_DEFINED(ATmega128) || AVR8_PART_IS_DEFINED(ATmega128A) ) +# 531 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_XX_UN2 ( AVR8_PART_IS_DEFINED(ATmega169P) || AVR8_PART_IS_DEFINED(ATmega169PA) || AVR8_PART_IS_DEFINED(ATmega329P) || AVR8_PART_IS_DEFINED(ATmega329PA) ) +# 542 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_UNCATEGORIZED ( AVR8_PART_IS_DEFINED(AT90CAN128) || AVR8_PART_IS_DEFINED(AT90CAN32) || AVR8_PART_IS_DEFINED(AT90CAN64) || AVR8_PART_IS_DEFINED(AT90PWM1) || AVR8_PART_IS_DEFINED(AT90PWM216) || AVR8_PART_IS_DEFINED(AT90PWM2B) || AVR8_PART_IS_DEFINED(AT90PWM316) || AVR8_PART_IS_DEFINED(AT90PWM3B) || AVR8_PART_IS_DEFINED(AT90PWM81) || AVR8_PART_IS_DEFINED(AT90USB1286) || AVR8_PART_IS_DEFINED(AT90USB1287) || AVR8_PART_IS_DEFINED(AT90USB162) || AVR8_PART_IS_DEFINED(AT90USB646) || AVR8_PART_IS_DEFINED(AT90USB647) || AVR8_PART_IS_DEFINED(AT90USB82) || AVR8_PART_IS_DEFINED(ATmega1284) || AVR8_PART_IS_DEFINED(ATmega162) || AVR8_PART_IS_DEFINED(ATmega164P) || AVR8_PART_IS_DEFINED(ATmega165A) || AVR8_PART_IS_DEFINED(ATmega165P) || AVR8_PART_IS_DEFINED(ATmega165PA) || AVR8_PART_IS_DEFINED(ATmega168P) || AVR8_PART_IS_DEFINED(ATmega169A) || AVR8_PART_IS_DEFINED(ATmega16M1) || AVR8_PART_IS_DEFINED(ATmega16U2) || AVR8_PART_IS_DEFINED(ATmega16U4) || AVR8_PART_IS_DEFINED(ATmega256RFA2) || AVR8_PART_IS_DEFINED(ATmega324P) || AVR8_PART_IS_DEFINED(ATmega325) || AVR8_PART_IS_DEFINED(ATmega3250) || AVR8_PART_IS_DEFINED(ATmega3250A) || AVR8_PART_IS_DEFINED(ATmega3250P) || AVR8_PART_IS_DEFINED(ATmega3250PA) || AVR8_PART_IS_DEFINED(ATmega325A) || AVR8_PART_IS_DEFINED(ATmega325P) || AVR8_PART_IS_DEFINED(ATmega325PA) || AVR8_PART_IS_DEFINED(ATmega329) || AVR8_PART_IS_DEFINED(ATmega3290) || AVR8_PART_IS_DEFINED(ATmega3290A) || AVR8_PART_IS_DEFINED(ATmega3290P) || AVR8_PART_IS_DEFINED(ATmega3290PA) || AVR8_PART_IS_DEFINED(ATmega329A) || AVR8_PART_IS_DEFINED(ATmega32M1) || AVR8_PART_IS_DEFINED(ATmega32U2) || AVR8_PART_IS_DEFINED(ATmega32U4) || AVR8_PART_IS_DEFINED(ATmega48P) || AVR8_PART_IS_DEFINED(ATmega644P) || AVR8_PART_IS_DEFINED(ATmega645) || AVR8_PART_IS_DEFINED(ATmega6450) || AVR8_PART_IS_DEFINED(ATmega6450A) || AVR8_PART_IS_DEFINED(ATmega6450P) || AVR8_PART_IS_DEFINED(ATmega645A) || AVR8_PART_IS_DEFINED(ATmega645P) || AVR8_PART_IS_DEFINED(ATmega649) || AVR8_PART_IS_DEFINED(ATmega6490) || AVR8_PART_IS_DEFINED(ATmega6490A) || AVR8_PART_IS_DEFINED(ATmega6490P) || AVR8_PART_IS_DEFINED(ATmega649A) || AVR8_PART_IS_DEFINED(ATmega649P) || AVR8_PART_IS_DEFINED(ATmega64M1) || AVR8_PART_IS_DEFINED(ATmega64RFA2) || AVR8_PART_IS_DEFINED(ATmega8) || AVR8_PART_IS_DEFINED(ATmega8515) || AVR8_PART_IS_DEFINED(ATmega8535) || AVR8_PART_IS_DEFINED(ATmega88P) || AVR8_PART_IS_DEFINED(ATmega8A) || AVR8_PART_IS_DEFINED(ATmega8U2) ) +# 613 "naeusb/sam3u_hal/inc/parts.h" +#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || MEGA_UNCATEGORIZED) + + + + + +#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || MEGA_UNSPECIFIED) +# 639 "naeusb/sam3u_hal/inc/parts.h" +#define TINY_UNCATEGORIZED ( AVR8_PART_IS_DEFINED(ATtiny10) || AVR8_PART_IS_DEFINED(ATtiny13) || AVR8_PART_IS_DEFINED(ATtiny13A) || AVR8_PART_IS_DEFINED(ATtiny1634) || AVR8_PART_IS_DEFINED(ATtiny167) || AVR8_PART_IS_DEFINED(ATtiny20) || AVR8_PART_IS_DEFINED(ATtiny2313) || AVR8_PART_IS_DEFINED(ATtiny2313A) || AVR8_PART_IS_DEFINED(ATtiny24) || AVR8_PART_IS_DEFINED(ATtiny24A) || AVR8_PART_IS_DEFINED(ATtiny25) || AVR8_PART_IS_DEFINED(ATtiny26) || AVR8_PART_IS_DEFINED(ATtiny261) || AVR8_PART_IS_DEFINED(ATtiny261A) || AVR8_PART_IS_DEFINED(ATtiny4) || AVR8_PART_IS_DEFINED(ATtiny40) || AVR8_PART_IS_DEFINED(ATtiny4313) || AVR8_PART_IS_DEFINED(ATtiny43U) || AVR8_PART_IS_DEFINED(ATtiny44) || AVR8_PART_IS_DEFINED(ATtiny44A) || AVR8_PART_IS_DEFINED(ATtiny45) || AVR8_PART_IS_DEFINED(ATtiny461) || AVR8_PART_IS_DEFINED(ATtiny461A) || AVR8_PART_IS_DEFINED(ATtiny48) || AVR8_PART_IS_DEFINED(ATtiny5) || AVR8_PART_IS_DEFINED(ATtiny828) || AVR8_PART_IS_DEFINED(ATtiny84) || AVR8_PART_IS_DEFINED(ATtiny84A) || AVR8_PART_IS_DEFINED(ATtiny85) || AVR8_PART_IS_DEFINED(ATtiny861) || AVR8_PART_IS_DEFINED(ATtiny861A) || AVR8_PART_IS_DEFINED(ATtiny87) || AVR8_PART_IS_DEFINED(ATtiny88) || AVR8_PART_IS_DEFINED(ATtiny9) ) +# 679 "naeusb/sam3u_hal/inc/parts.h" +#define TINY (TINY_UNCATEGORIZED) +# 692 "naeusb/sam3u_hal/inc/parts.h" +#define SAM3S1 ( SAM_PART_IS_DEFINED(SAM3S1A) || SAM_PART_IS_DEFINED(SAM3S1B) || SAM_PART_IS_DEFINED(SAM3S1C) ) + + + + + +#define SAM3S2 ( SAM_PART_IS_DEFINED(SAM3S2A) || SAM_PART_IS_DEFINED(SAM3S2B) || SAM_PART_IS_DEFINED(SAM3S2C) ) + + + + + +#define SAM3S4 ( SAM_PART_IS_DEFINED(SAM3S4A) || SAM_PART_IS_DEFINED(SAM3S4B) || SAM_PART_IS_DEFINED(SAM3S4C) ) + + + + + +#define SAM3S8 ( SAM_PART_IS_DEFINED(SAM3S8B) || SAM_PART_IS_DEFINED(SAM3S8C) ) + + + + +#define SAM3SD8 ( SAM_PART_IS_DEFINED(SAM3SD8B) || SAM_PART_IS_DEFINED(SAM3SD8C) ) +# 725 "naeusb/sam3u_hal/inc/parts.h" +#define SAM3U1 ( SAM_PART_IS_DEFINED(SAM3U1C) || SAM_PART_IS_DEFINED(SAM3U1E) ) + + + + +#define SAM3U2 ( SAM_PART_IS_DEFINED(SAM3U2C) || SAM_PART_IS_DEFINED(SAM3U2E) ) + + + + +#define SAM3U4 ( SAM_PART_IS_DEFINED(SAM3U4C) || SAM_PART_IS_DEFINED(SAM3U4E) ) +# 745 "naeusb/sam3u_hal/inc/parts.h" +#define SAM3N00 ( SAM_PART_IS_DEFINED(SAM3N00A) || SAM_PART_IS_DEFINED(SAM3N00B) ) + + + + +#define SAM3N0 ( SAM_PART_IS_DEFINED(SAM3N0A) || SAM_PART_IS_DEFINED(SAM3N0B) || SAM_PART_IS_DEFINED(SAM3N0C) ) + + + + + +#define SAM3N1 ( SAM_PART_IS_DEFINED(SAM3N1A) || SAM_PART_IS_DEFINED(SAM3N1B) || SAM_PART_IS_DEFINED(SAM3N1C) ) + + + + + +#define SAM3N2 ( SAM_PART_IS_DEFINED(SAM3N2A) || SAM_PART_IS_DEFINED(SAM3N2B) || SAM_PART_IS_DEFINED(SAM3N2C) ) + + + + + +#define SAM3N4 ( SAM_PART_IS_DEFINED(SAM3N4A) || SAM_PART_IS_DEFINED(SAM3N4B) || SAM_PART_IS_DEFINED(SAM3N4C) ) +# 779 "naeusb/sam3u_hal/inc/parts.h" +#define SAM3X4 ( SAM_PART_IS_DEFINED(SAM3X4C) || SAM_PART_IS_DEFINED(SAM3X4E) ) + + + + +#define SAM3X8 ( SAM_PART_IS_DEFINED(SAM3X8C) || SAM_PART_IS_DEFINED(SAM3X8E) || SAM_PART_IS_DEFINED(SAM3X8H) ) +# 795 "naeusb/sam3u_hal/inc/parts.h" +#define SAM3A4 ( SAM_PART_IS_DEFINED(SAM3A4C) ) + + + +#define SAM3A8 ( SAM_PART_IS_DEFINED(SAM3A8C) ) +# 808 "naeusb/sam3u_hal/inc/parts.h" +#define SAM4S2 ( SAM_PART_IS_DEFINED(SAM4S2A) || SAM_PART_IS_DEFINED(SAM4S2B) || SAM_PART_IS_DEFINED(SAM4S2C) ) + + + + + +#define SAM4S4 ( SAM_PART_IS_DEFINED(SAM4S4A) || SAM_PART_IS_DEFINED(SAM4S4B) || SAM_PART_IS_DEFINED(SAM4S4C) ) + + + + + +#define SAM4S8 ( SAM_PART_IS_DEFINED(SAM4S8B) || SAM_PART_IS_DEFINED(SAM4S8C) ) + + + + +#define SAM4S16 ( SAM_PART_IS_DEFINED(SAM4S16B) || SAM_PART_IS_DEFINED(SAM4S16C) ) + + + + +#define SAM4SA16 ( SAM_PART_IS_DEFINED(SAM4SA16B) || SAM_PART_IS_DEFINED(SAM4SA16C) ) + + + + +#define SAM4SD16 ( SAM_PART_IS_DEFINED(SAM4SD16B) || SAM_PART_IS_DEFINED(SAM4SD16C) ) + + + + +#define SAM4SD32 ( SAM_PART_IS_DEFINED(SAM4SD32B) || SAM_PART_IS_DEFINED(SAM4SD32C) ) +# 850 "naeusb/sam3u_hal/inc/parts.h" +#define SAM4LS ( SAM_PART_IS_DEFINED(SAM4LS2A) || SAM_PART_IS_DEFINED(SAM4LS2B) || SAM_PART_IS_DEFINED(SAM4LS2C) || SAM_PART_IS_DEFINED(SAM4LS4A) || SAM_PART_IS_DEFINED(SAM4LS4B) || SAM_PART_IS_DEFINED(SAM4LS4C) || SAM_PART_IS_DEFINED(SAM4LS8A) || SAM_PART_IS_DEFINED(SAM4LS8B) || SAM_PART_IS_DEFINED(SAM4LS8C) ) +# 862 "naeusb/sam3u_hal/inc/parts.h" +#define SAM4LC ( SAM_PART_IS_DEFINED(SAM4LC2A) || SAM_PART_IS_DEFINED(SAM4LC2B) || SAM_PART_IS_DEFINED(SAM4LC2C) || SAM_PART_IS_DEFINED(SAM4LC4A) || SAM_PART_IS_DEFINED(SAM4LC4B) || SAM_PART_IS_DEFINED(SAM4LC4C) || SAM_PART_IS_DEFINED(SAM4LC8A) || SAM_PART_IS_DEFINED(SAM4LC8B) || SAM_PART_IS_DEFINED(SAM4LC8C) ) +# 879 "naeusb/sam3u_hal/inc/parts.h" +#define SAMD20J ( SAM_PART_IS_DEFINED(SAMD20J14) || SAM_PART_IS_DEFINED(SAMD20J15) || SAM_PART_IS_DEFINED(SAMD20J16) || SAM_PART_IS_DEFINED(SAMD20J17) || SAM_PART_IS_DEFINED(SAMD20J18) ) + + + + + + + +#define SAMD20G ( SAM_PART_IS_DEFINED(SAMD20G14) || SAM_PART_IS_DEFINED(SAMD20G15) || SAM_PART_IS_DEFINED(SAMD20G16) || SAM_PART_IS_DEFINED(SAMD20G17) || SAM_PART_IS_DEFINED(SAMD20G17U) || SAM_PART_IS_DEFINED(SAMD20G18) || SAM_PART_IS_DEFINED(SAMD20G18U) ) +# 897 "naeusb/sam3u_hal/inc/parts.h" +#define SAMD20E ( SAM_PART_IS_DEFINED(SAMD20E14) || SAM_PART_IS_DEFINED(SAMD20E15) || SAM_PART_IS_DEFINED(SAMD20E16) || SAM_PART_IS_DEFINED(SAMD20E17) || SAM_PART_IS_DEFINED(SAMD20E18) || SAM_PART_IS_DEFINED(SAMD20E1F) ) +# 911 "naeusb/sam3u_hal/inc/parts.h" +#define SAMD21J ( SAM_PART_IS_DEFINED(SAMD21J15A) || SAM_PART_IS_DEFINED(SAMD21J16A) || SAM_PART_IS_DEFINED(SAMD21J17A) || SAM_PART_IS_DEFINED(SAMD21J18A) ) + + + + + + +#define SAMD21G ( SAM_PART_IS_DEFINED(SAMD21G15A) || SAM_PART_IS_DEFINED(SAMD21G16A) || SAM_PART_IS_DEFINED(SAMD21G17A) || SAM_PART_IS_DEFINED(SAMD21G18A) ) + + + + + + +#define SAMD21E ( SAM_PART_IS_DEFINED(SAMD21E15A) || SAM_PART_IS_DEFINED(SAMD21E16A) || SAM_PART_IS_DEFINED(SAMD21E17A) || SAM_PART_IS_DEFINED(SAMD21E18A) ) +# 937 "naeusb/sam3u_hal/inc/parts.h" +#define SAMR21G ( SAM_PART_IS_DEFINED(SAMR21G16A) || SAM_PART_IS_DEFINED(SAMR21G17A) || SAM_PART_IS_DEFINED(SAMR21G18A) ) + + + + + +#define SAMR21E ( SAM_PART_IS_DEFINED(SAMR21E16A) || SAM_PART_IS_DEFINED(SAMR21E17A) || SAM_PART_IS_DEFINED(SAMR21E18A) ) +# 954 "naeusb/sam3u_hal/inc/parts.h" +#define SAMD10C ( SAM_PART_IS_DEFINED(SAMD10C12A) || SAM_PART_IS_DEFINED(SAMD10C13A) || SAM_PART_IS_DEFINED(SAMD10C14A) ) + + + + + +#define SAMD10DS ( SAM_PART_IS_DEFINED(SAMD10D12AS) || SAM_PART_IS_DEFINED(SAMD10D13AS) || SAM_PART_IS_DEFINED(SAMD10D14AS) ) + + + + + +#define SAMD10DM ( SAM_PART_IS_DEFINED(SAMD10D12AM) || SAM_PART_IS_DEFINED(SAMD10D13AM) || SAM_PART_IS_DEFINED(SAMD10D14AM) ) +# 977 "naeusb/sam3u_hal/inc/parts.h" +#define SAMD11C ( SAM_PART_IS_DEFINED(SAMD11C14A) ) + + + +#define SAMD11DS ( SAM_PART_IS_DEFINED(SAMD11D14AS) ) + + + +#define SAMD11DM ( SAM_PART_IS_DEFINED(SAMD11D14AM) ) +# 994 "naeusb/sam3u_hal/inc/parts.h" +#define SAM4E8 ( SAM_PART_IS_DEFINED(SAM4E8C) || SAM_PART_IS_DEFINED(SAM4E8E) ) + + + + +#define SAM4E16 ( SAM_PART_IS_DEFINED(SAM4E16C) || SAM_PART_IS_DEFINED(SAM4E16E) ) +# 1009 "naeusb/sam3u_hal/inc/parts.h" +#define SAM4N8 ( SAM_PART_IS_DEFINED(SAM4N8A) || SAM_PART_IS_DEFINED(SAM4N8B) || SAM_PART_IS_DEFINED(SAM4N8C) ) + + + + + +#define SAM4N16 ( SAM_PART_IS_DEFINED(SAM4N16B) || SAM_PART_IS_DEFINED(SAM4N16C) ) +# 1025 "naeusb/sam3u_hal/inc/parts.h" +#define SAM4C8_0 ( SAM_PART_IS_DEFINED(SAM4C8C_0) ) + + + +#define SAM4C8_1 ( SAM_PART_IS_DEFINED(SAM4C8C_1) ) + + + +#define SAM4C8 (SAM4C8_0 || SAM4C8_1) + +#define SAM4C16_0 ( SAM_PART_IS_DEFINED(SAM4C16C_0) ) + + + +#define SAM4C16_1 ( SAM_PART_IS_DEFINED(SAM4C16C_1) ) + + + +#define SAM4C16 (SAM4C16_0 || SAM4C16_1) + +#define SAM4C32_0 ( SAM_PART_IS_DEFINED(SAM4C32C_0) || SAM_PART_IS_DEFINED(SAM4C32E_0) ) + + + + +#define SAM4C32_1 ( SAM_PART_IS_DEFINED(SAM4C32C_1) || SAM_PART_IS_DEFINED(SAM4C32E_1) ) + + + + + +#define SAM4C32 (SAM4C32_0 || SAM4C32_1) + + + + + + + +#define SAM4CMP8_0 ( SAM_PART_IS_DEFINED(SAM4CMP8C_0) ) + + + +#define SAM4CMP8_1 ( SAM_PART_IS_DEFINED(SAM4CMP8C_1) ) + + + +#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1) + +#define SAM4CMP16_0 ( SAM_PART_IS_DEFINED(SAM4CMP16C_0) ) + + + +#define SAM4CMP16_1 ( SAM_PART_IS_DEFINED(SAM4CMP16C_1) ) + + + +#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1) + +#define SAM4CMP32_0 ( SAM_PART_IS_DEFINED(SAM4CMP32C_0) ) + + + +#define SAM4CMP32_1 ( SAM_PART_IS_DEFINED(SAM4CMP32C_1) ) + + + +#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1) + +#define SAM4CMS8_0 ( SAM_PART_IS_DEFINED(SAM4CMS8C_0) ) + + + +#define SAM4CMS8_1 ( SAM_PART_IS_DEFINED(SAM4CMS8C_1) ) + + + +#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1) + +#define SAM4CMS16_0 ( SAM_PART_IS_DEFINED(SAM4CMS16C_0) ) + + + +#define SAM4CMS16_1 ( SAM_PART_IS_DEFINED(SAM4CMS16C_1) ) + + + +#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1) + +#define SAM4CMS32_0 ( SAM_PART_IS_DEFINED(SAM4CMS32C_0) ) + + + +#define SAM4CMS32_1 ( SAM_PART_IS_DEFINED(SAM4CMS32C_1) ) + + + +#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1) + + + + + + + +#define SAM4CP16_0 ( SAM_PART_IS_DEFINED(SAM4CP16B_0) ) + + + +#define SAM4CP16_1 ( SAM_PART_IS_DEFINED(SAM4CP16B_1) ) + + + +#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1) + + + + + + +#define SAMG51 ( SAM_PART_IS_DEFINED(SAMG51G18) ) + + + +#define SAMG53 ( SAM_PART_IS_DEFINED(SAMG53G19) || SAM_PART_IS_DEFINED(SAMG53N19) ) + + + + +#define SAMG54 ( SAM_PART_IS_DEFINED(SAMG54G19) || SAM_PART_IS_DEFINED(SAMG54J19) || SAM_PART_IS_DEFINED(SAMG54N19) ) + + + + + +#define SAMG55 ( SAM_PART_IS_DEFINED(SAMG55G18) || SAM_PART_IS_DEFINED(SAMG55G19) || SAM_PART_IS_DEFINED(SAMG55J18) || SAM_PART_IS_DEFINED(SAMG55J19) || SAM_PART_IS_DEFINED(SAMG55N19) ) +# 1173 "naeusb/sam3u_hal/inc/parts.h" +#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) + + +#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) + + +#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4) + + +#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) + + +#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) + + +#define SAM4L (SAM4LS || SAM4LC) + + +#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) + + +#define SAMD21 (SAMD21J || SAMD21G || SAMD21E) + + +#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM) + + +#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM) + + +#define SAMD (SAMD20 || SAMD21 || SAMD10 || SAMD11) + + +#define SAMR21 (SAMR21G || SAMR21E) + + +#define SAM4E (SAM4E8 || SAM4E16) + + +#define SAM4N (SAM4N8 || SAM4N16) + + +#define SAM4C_0 (SAM4C8_0 || SAM4C16_0 || SAM4C32_0) +#define SAM4C_1 (SAM4C8_1 || SAM4C16_1 || SAM4C32_1) +#define SAM4C (SAM4C8 || SAM4C16 || SAM4C32) + + +#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0) + +#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1) + +#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32) + + + +#define SAM4CP_0 (SAM4CP16_0) +#define SAM4CP_1 (SAM4CP16_1) +#define SAM4CP (SAM4CP16) + + +#define SAMG (SAMG51 || SAMG53 || SAMG54) + + +#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11) + + + + +#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG) +# 62 "naeusb/sam3u_hal/inc/compiler.h" 2 +# 1 "naeusb/sam3u_hal/inc/preprocessor.h" 1 +# 45 "naeusb/sam3u_hal/inc/preprocessor.h" +#define _PREPROCESSOR_H_ + +# 1 "naeusb/sam3u_hal/inc/tpaste.h" 1 +# 45 "naeusb/sam3u_hal/inc/tpaste.h" +#define _TPASTE_H_ +# 66 "naeusb/sam3u_hal/inc/tpaste.h" +#define TPASTE2(a,b) a ##b +#define TPASTE3(a,b,c) a ##b ##c +#define TPASTE4(a,b,c,d) a ##b ##c ##d +#define TPASTE5(a,b,c,d,e) a ##b ##c ##d ##e +#define TPASTE6(a,b,c,d,e,f) a ##b ##c ##d ##e ##f +#define TPASTE7(a,b,c,d,e,f,g) a ##b ##c ##d ##e ##f ##g +#define TPASTE8(a,b,c,d,e,f,g,h) a ##b ##c ##d ##e ##f ##g ##h +#define TPASTE9(a,b,c,d,e,f,g,h,i) a ##b ##c ##d ##e ##f ##g ##h ##i +#define TPASTE10(a,b,c,d,e,f,g,h,i,j) a ##b ##c ##d ##e ##f ##g ##h ##i ##j +# 87 "naeusb/sam3u_hal/inc/tpaste.h" +#define ATPASTE2(a,b) TPASTE2( a, b) +#define ATPASTE3(a,b,c) TPASTE3( a, b, c) +#define ATPASTE4(a,b,c,d) TPASTE4( a, b, c, d) +#define ATPASTE5(a,b,c,d,e) TPASTE5( a, b, c, d, e) +#define ATPASTE6(a,b,c,d,e,f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7(a,b,c,d,e,f,g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8(a,b,c,d,e,f,g,h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9(a,b,c,d,e,f,g,h,i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a,b,c,d,e,f,g,h,i,j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +# 48 "naeusb/sam3u_hal/inc/preprocessor.h" 2 +# 1 "naeusb/sam3u_hal/inc/stringz.h" 1 +# 45 "naeusb/sam3u_hal/inc/stringz.h" +#define _STRINGZ_H_ +# 65 "naeusb/sam3u_hal/inc/stringz.h" +#define STRINGZ(x) #x +# 76 "naeusb/sam3u_hal/inc/stringz.h" +#define ASTRINGZ(x) STRINGZ(x) +# 49 "naeusb/sam3u_hal/inc/preprocessor.h" 2 +# 1 "naeusb/sam3u_hal/inc/mrepeat.h" 1 +# 45 "naeusb/sam3u_hal/inc/mrepeat.h" +#define _MREPEAT_H_ +# 55 "naeusb/sam3u_hal/inc/mrepeat.h" +# 1 "naeusb/sam3u_hal/inc/preprocessor.h" 1 +# 56 "naeusb/sam3u_hal/inc/mrepeat.h" 2 + + + +#define MREPEAT_LIMIT 256 +# 72 "naeusb/sam3u_hal/inc/mrepeat.h" +#define MREPEAT(count,macro,data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0(macro,data) +#define MREPEAT1(macro,data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2(macro,data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3(macro,data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4(macro,data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5(macro,data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6(macro,data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7(macro,data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8(macro,data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9(macro,data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10(macro,data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11(macro,data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12(macro,data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13(macro,data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14(macro,data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15(macro,data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16(macro,data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17(macro,data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18(macro,data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19(macro,data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20(macro,data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21(macro,data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22(macro,data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23(macro,data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24(macro,data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25(macro,data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26(macro,data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27(macro,data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28(macro,data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29(macro,data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30(macro,data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31(macro,data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32(macro,data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33(macro,data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34(macro,data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35(macro,data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36(macro,data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37(macro,data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38(macro,data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39(macro,data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40(macro,data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41(macro,data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42(macro,data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43(macro,data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44(macro,data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45(macro,data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46(macro,data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47(macro,data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48(macro,data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49(macro,data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50(macro,data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51(macro,data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52(macro,data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53(macro,data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54(macro,data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55(macro,data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56(macro,data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57(macro,data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58(macro,data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59(macro,data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60(macro,data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61(macro,data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62(macro,data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63(macro,data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64(macro,data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65(macro,data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66(macro,data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67(macro,data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68(macro,data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69(macro,data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70(macro,data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71(macro,data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72(macro,data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73(macro,data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74(macro,data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75(macro,data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76(macro,data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77(macro,data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78(macro,data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79(macro,data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80(macro,data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81(macro,data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82(macro,data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83(macro,data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84(macro,data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85(macro,data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86(macro,data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87(macro,data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88(macro,data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89(macro,data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90(macro,data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91(macro,data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92(macro,data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93(macro,data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94(macro,data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95(macro,data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96(macro,data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97(macro,data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98(macro,data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99(macro,data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro,data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro,data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro,data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro,data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro,data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro,data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro,data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro,data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro,data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro,data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro,data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro,data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro,data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro,data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro,data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro,data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro,data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro,data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro,data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro,data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro,data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro,data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro,data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro,data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro,data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro,data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro,data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro,data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro,data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro,data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro,data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro,data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro,data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro,data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro,data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro,data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro,data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro,data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro,data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro,data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro,data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro,data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro,data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro,data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro,data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro,data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro,data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro,data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro,data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro,data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro,data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro,data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro,data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro,data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro,data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro,data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro,data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro,data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro,data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro,data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro,data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro,data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro,data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro,data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro,data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro,data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro,data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro,data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro,data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro,data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro,data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro,data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro,data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro,data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro,data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro,data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro,data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro,data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro,data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro,data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro,data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro,data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro,data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro,data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro,data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro,data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro,data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro,data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro,data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro,data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro,data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro,data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro,data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro,data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro,data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro,data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro,data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro,data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro,data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro,data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro,data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro,data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro,data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro,data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro,data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro,data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro,data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro,data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro,data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro,data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro,data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro,data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro,data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro,data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro,data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro,data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro,data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro,data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro,data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro,data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro,data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro,data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro,data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro,data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro,data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro,data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro,data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro,data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro,data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro,data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro,data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro,data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro,data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro,data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro,data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro,data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro,data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro,data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro,data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro,data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro,data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro,data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro,data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro,data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro,data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro,data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro,data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro,data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro,data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro,data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro,data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro,data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro,data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro,data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro,data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro,data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro,data) MREPEAT255(macro, data) macro(255, data) +# 50 "naeusb/sam3u_hal/inc/preprocessor.h" 2 +# 63 "naeusb/sam3u_hal/inc/compiler.h" 2 + +# 1 "naeusb/sam3u_hal/inc/io.h" 1 +# 47 "naeusb/sam3u_hal/inc/io.h" +#define _SAM_IO_ +# 62 "naeusb/sam3u_hal/inc/io.h" +# 1 "naeusb/sam3u_hal/inc/sam3u.h" 1 +# 43 "naeusb/sam3u_hal/inc/sam3u.h" +#define _SAM3U_ + + + + + + +# 1 "naeusb/sam3u_hal/inc/sam3u2c.h" 1 +# 43 "naeusb/sam3u_hal/inc/sam3u2c.h" +#define _SAM3U2C_ +# 59 "naeusb/sam3u_hal/inc/sam3u2c.h" +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdint.h" 1 3 4 +# 9 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdint.h" 3 4 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 1 3 4 +# 10 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define _STDINT_H + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 1 3 4 + + + + + +#define _MACHINE__DEFAULT_TYPES_H + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 1 3 4 +# 22 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#define _SYS_FEATURES_H + + + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_newlib_version.h" 1 3 4 + + + +#define _NEWLIB_VERSION_H__ 1 + +#define _NEWLIB_VERSION "4.1.0" +#define __NEWLIB__ 4 +#define __NEWLIB_MINOR__ 1 +#define __NEWLIB_PATCHLEVEL__ 0 +# 29 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 2 3 4 + + + + +#define __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) + + + + + + +#define __GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi) +# 131 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#undef _DEFAULT_SOURCE +#define _DEFAULT_SOURCE 1 + + + +#undef _POSIX_SOURCE +#define _POSIX_SOURCE 1 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L +# 158 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#undef _ATFILE_SOURCE +#define _ATFILE_SOURCE 1 +# 247 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#define __ATFILE_VISIBLE 1 + + + + + +#define __BSD_VISIBLE 1 + + + + + + + +#define __GNU_VISIBLE 0 + + + + + + + +#define __ISO_C_VISIBLE 1999 + + + + + + + +#define __LARGEFILE_VISIBLE 0 + + + +#define __MISC_VISIBLE 1 + + + + + +#define __POSIX_VISIBLE 200809 +# 303 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#define __SVID_VISIBLE 1 +# 319 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#define __XSI_VISIBLE 0 +# 330 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\features.h" 3 4 +#define __SSP_FORTIFY_LEVEL 0 +# 9 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 2 3 4 + + + + + + +#define __EXP(x) __ ##x ##__ +# 26 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +#define __have_longlong64 1 + + + + + + +#define __have_long32 1 + + + + + + + +typedef signed char __int8_t; + +typedef unsigned char __uint8_t; + + + +#define ___int8_t_defined 1 + + + + + + + +typedef short int __int16_t; + +typedef short unsigned int __uint16_t; + + + +#define ___int16_t_defined 1 +# 77 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +typedef long int __int32_t; + +typedef long unsigned int __uint32_t; + + + +#define ___int32_t_defined 1 +# 103 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +typedef long long int __int64_t; + +typedef long long unsigned int __uint64_t; + + + +#define ___int64_t_defined 1 +# 134 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +typedef signed char __int_least8_t; + +typedef unsigned char __uint_least8_t; + + + +#define ___int_least8_t_defined 1 +# 160 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +typedef short int __int_least16_t; + +typedef short unsigned int __uint_least16_t; + + + +#define ___int_least16_t_defined 1 +# 182 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +typedef long int __int_least32_t; + +typedef long unsigned int __uint_least32_t; + + + +#define ___int_least32_t_defined 1 +# 200 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +typedef long long int __int_least64_t; + +typedef long long unsigned int __uint_least64_t; + + + +#define ___int_least64_t_defined 1 + + + + + + + +typedef long long int __intmax_t; + + + + + + + +typedef long long unsigned int __uintmax_t; + + + + + + + +typedef int __intptr_t; + +typedef unsigned int __uintptr_t; +# 244 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_default_types.h" 3 4 +#undef __EXP +# 13 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 2 3 4 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 1 3 4 +# 10 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define _SYS__INTSUP_H + + + + + +#define __STDINT_EXP(x) __ ##x ##__ +# 35 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 + + + + + + + + +#undef signed +#undef unsigned +#undef char +#undef short +#undef int +#undef __int20 +#undef __int20__ +#undef long +#define signed +0 +#define unsigned +0 +#define char +0 +#define short +1 +#define __int20 +2 +#define __int20__ +2 +#define int +2 +#define long +4 +# 67 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define _INTPTR_EQ_INT + + + + + + +#define _INT32_EQ_LONG + + + + + + + +#define __INT8 "hh" +# 93 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __INT16 "h" +# 104 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __INT32 "l" +# 113 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __INT64 "ll" + + + + + + +#define __FAST8 +# 129 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __FAST16 + + + + + + +#define __FAST32 +# 147 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __FAST64 "ll" + + + +#define __LEAST8 "hh" +# 162 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __LEAST16 "h" +# 173 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __LEAST32 "l" +# 182 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#define __LEAST64 "ll" + +#undef signed +#undef unsigned +#undef char +#undef short +#undef int +#undef long + + + + + +# 194 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#undef __int20 + +# 195 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_intsup.h" 3 4 +#undef __int20__ + + +# 14 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 2 3 4 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_stdint.h" 1 3 4 +# 10 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_stdint.h" 3 4 +#define _SYS__STDINT_H +# 20 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_stdint.h" 3 4 +typedef __int8_t int8_t ; +#define _INT8_T_DECLARED + + +typedef __uint8_t uint8_t ; +#define _UINT8_T_DECLARED + +#define __int8_t_defined 1 + + + + +typedef __int16_t int16_t ; +#define _INT16_T_DECLARED + + +typedef __uint16_t uint16_t ; +#define _UINT16_T_DECLARED + +#define __int16_t_defined 1 + + + + +typedef __int32_t int32_t ; +#define _INT32_T_DECLARED + + +typedef __uint32_t uint32_t ; +#define _UINT32_T_DECLARED + +#define __int32_t_defined 1 + + + + +typedef __int64_t int64_t ; +#define _INT64_T_DECLARED + + +typedef __uint64_t uint64_t ; +#define _UINT64_T_DECLARED + +#define __int64_t_defined 1 + + + +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED + + + +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED + + + +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED + + + +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +# 15 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 2 3 4 + + + + + + +typedef __int_least8_t int_least8_t; +typedef __uint_least8_t uint_least8_t; +#define __int_least8_t_defined 1 + + + +typedef __int_least16_t int_least16_t; +typedef __uint_least16_t uint_least16_t; +#define __int_least16_t_defined 1 + + + +typedef __int_least32_t int_least32_t; +typedef __uint_least32_t uint_least32_t; +#define __int_least32_t_defined 1 + + + +typedef __int_least64_t int_least64_t; +typedef __uint_least64_t uint_least64_t; +#define __int_least64_t_defined 1 +# 51 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 + typedef int int_fast8_t; + typedef unsigned int uint_fast8_t; +#define __int_fast8_t_defined 1 + + + + + + + + typedef int int_fast16_t; + typedef unsigned int uint_fast16_t; +#define __int_fast16_t_defined 1 + + + + + + + + typedef int int_fast32_t; + typedef unsigned int uint_fast32_t; +#define __int_fast32_t_defined 1 + + + + + + + + typedef long long int int_fast64_t; + typedef long long unsigned int uint_fast64_t; +#define __int_fast64_t_defined 1 +# 128 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INTPTR_MIN (-__INTPTR_MAX__ - 1) +#define INTPTR_MAX (__INTPTR_MAX__) +#define UINTPTR_MAX (__UINTPTR_MAX__) +# 152 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT8_MIN (-__INT8_MAX__ - 1) +#define INT8_MAX (__INT8_MAX__) +#define UINT8_MAX (__UINT8_MAX__) + + + + + + + +#define INT_LEAST8_MIN (-__INT_LEAST8_MAX__ - 1) +#define INT_LEAST8_MAX (__INT_LEAST8_MAX__) +#define UINT_LEAST8_MAX (__UINT_LEAST8_MAX__) +# 174 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT16_MIN (-__INT16_MAX__ - 1) +#define INT16_MAX (__INT16_MAX__) +#define UINT16_MAX (__UINT16_MAX__) + + + + + + + +#define INT_LEAST16_MIN (-__INT_LEAST16_MAX__ - 1) +#define INT_LEAST16_MAX (__INT_LEAST16_MAX__) +#define UINT_LEAST16_MAX (__UINT_LEAST16_MAX__) +# 196 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT32_MIN (-__INT32_MAX__ - 1) +#define INT32_MAX (__INT32_MAX__) +#define UINT32_MAX (__UINT32_MAX__) +# 212 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT_LEAST32_MIN (-__INT_LEAST32_MAX__ - 1) +#define INT_LEAST32_MAX (__INT_LEAST32_MAX__) +#define UINT_LEAST32_MAX (__UINT_LEAST32_MAX__) +# 230 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT64_MIN (-__INT64_MAX__ - 1) +#define INT64_MAX (__INT64_MAX__) +#define UINT64_MAX (__UINT64_MAX__) +# 246 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT_LEAST64_MIN (-__INT_LEAST64_MAX__ - 1) +#define INT_LEAST64_MAX (__INT_LEAST64_MAX__) +#define UINT_LEAST64_MAX (__UINT_LEAST64_MAX__) +# 262 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT_FAST8_MIN (-__INT_FAST8_MAX__ - 1) +#define INT_FAST8_MAX (__INT_FAST8_MAX__) +#define UINT_FAST8_MAX (__UINT_FAST8_MAX__) +# 278 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT_FAST16_MIN (-__INT_FAST16_MAX__ - 1) +#define INT_FAST16_MAX (__INT_FAST16_MAX__) +#define UINT_FAST16_MAX (__UINT_FAST16_MAX__) +# 294 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT_FAST32_MIN (-__INT_FAST32_MAX__ - 1) +#define INT_FAST32_MAX (__INT_FAST32_MAX__) +#define UINT_FAST32_MAX (__UINT_FAST32_MAX__) +# 310 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT_FAST64_MIN (-__INT_FAST64_MAX__ - 1) +#define INT_FAST64_MAX (__INT_FAST64_MAX__) +#define UINT_FAST64_MAX (__UINT_FAST64_MAX__) +# 326 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INTMAX_MAX (__INTMAX_MAX__) +#define INTMAX_MIN (-INTMAX_MAX - 1) + + + + + + + +#define UINTMAX_MAX (__UINTMAX_MAX__) + + + + + + + +#define SIZE_MAX (__SIZE_MAX__) + + + + + +#define SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1) +#define SIG_ATOMIC_MAX (__STDINT_EXP(INT_MAX)) + + + +#define PTRDIFF_MAX (__PTRDIFF_MAX__) + + + +#define PTRDIFF_MIN (-PTRDIFF_MAX - 1) + + + + +#define WCHAR_MIN (__WCHAR_MIN__) +# 374 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define WCHAR_MAX (__WCHAR_MAX__) +# 384 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define WINT_MAX (__WINT_MAX__) + + + + +#define WINT_MIN (__WINT_MIN__) + + + + + + +#define INT8_C(x) __INT8_C(x) +#define UINT8_C(x) __UINT8_C(x) +# 408 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT16_C(x) __INT16_C(x) +#define UINT16_C(x) __UINT16_C(x) +# 420 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT32_C(x) __INT32_C(x) +#define UINT32_C(x) __UINT32_C(x) +# 433 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INT64_C(x) __INT64_C(x) +#define UINT64_C(x) __UINT64_C(x) +# 449 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdint.h" 3 4 +#define INTMAX_C(x) __INTMAX_C(x) +#define UINTMAX_C(x) __UINTMAX_C(x) +# 10 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdint.h" 2 3 4 + + + +#define _GCC_WRAP_STDINT_H +# 60 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 + + +# 61 "naeusb/sam3u_hal/inc/sam3u2c.h" +typedef volatile const uint32_t RoReg; + + + +typedef volatile uint32_t WoReg; +typedef volatile uint32_t RwReg; +# 76 "naeusb/sam3u_hal/inc/sam3u2c.h" +typedef enum IRQn +{ + + NonMaskableInt_IRQn = -14, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + + SUPC_IRQn = 0, + RSTC_IRQn = 1, + RTC_IRQn = 2, + RTT_IRQn = 3, + WDT_IRQn = 4, + PMC_IRQn = 5, + EFC0_IRQn = 6, + EFC1_IRQn = 7, + UART_IRQn = 8, + SMC_IRQn = 9, + PIOA_IRQn = 10, + PIOB_IRQn = 11, + USART0_IRQn = 13, + USART1_IRQn = 14, + USART2_IRQn = 15, + HSMCI_IRQn = 17, + TWI0_IRQn = 18, + TWI1_IRQn = 19, + SPI_IRQn = 20, + SSC_IRQn = 21, + TC0_IRQn = 22, + TC1_IRQn = 23, + TC2_IRQn = 24, + PWM_IRQn = 25, + ADC12B_IRQn = 26, + ADC_IRQn = 27, + DMAC_IRQn = 28, + UDPHS_IRQn = 29 +} IRQn_Type; + +typedef struct _DeviceVectors +{ + + void* pvStack; + + + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + + void* pfnSUPC_Handler; + void* pfnRSTC_Handler; + void* pfnRTC_Handler; + void* pfnRTT_Handler; + void* pfnWDT_Handler; + void* pfnPMC_Handler; + void* pfnEFC0_Handler; + void* pfnEFC1_Handler; + void* pfnUART_Handler; + void* pfnSMC_Handler; + void* pfnPIOA_Handler; + void* pfnPIOB_Handler; + void* pvReserved12; + void* pfnUSART0_Handler; + void* pfnUSART1_Handler; + void* pfnUSART2_Handler; + void* pvReserved16; + void* pfnHSMCI_Handler; + void* pfnTWI0_Handler; + void* pfnTWI1_Handler; + void* pfnSPI_Handler; + void* pfnSSC_Handler; + void* pfnTC0_Handler; + void* pfnTC1_Handler; + void* pfnTC2_Handler; + void* pfnPWM_Handler; + void* pfnADC12B_Handler; + void* pfnADC_Handler; + void* pfnDMAC_Handler; + void* pfnUDPHS_Handler; +} DeviceVectors; + + +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + + +void ADC_Handler ( void ); +void ADC12B_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SMC_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UDPHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + + + + + +#define __CM3_REV 0x0200 +#define __MPU_PRESENT 1 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + + + + + +# 1 "naeusb/sam3u_hal/inc/core_cm3.h" 1 +# 32 "naeusb/sam3u_hal/inc/core_cm3.h" +#define __CORE_CM3_H_GENERIC +# 56 "naeusb/sam3u_hal/inc/core_cm3.h" +#define __CM3_CMSIS_VERSION_MAIN (0x03) +#define __CM3_CMSIS_VERSION_SUB (0x00) +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB ) + + +#define __CORTEX_M (0x03) +# 79 "naeusb/sam3u_hal/inc/core_cm3.h" +#define __ASM __asm +#define __INLINE inline +#define __STATIC_INLINE static inline +# 92 "naeusb/sam3u_hal/inc/core_cm3.h" +#define __FPU_USED 0 +# 119 "naeusb/sam3u_hal/inc/core_cm3.h" +# 1 "naeusb/sam3u_hal/inc/core_cmInstr.h" 1 +# 25 "naeusb/sam3u_hal/inc/core_cmInstr.h" +#define __CORE_CMINSTR_H +# 286 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline void __NOP(void) +{ + __asm volatile ("nop"); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __WFI(void) +{ + __asm volatile ("wfi"); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __WFE(void) +{ + __asm volatile ("wfe"); +} + + + + + + +__attribute__( ( always_inline ) ) static inline void __SEV(void) +{ + __asm volatile ("sev"); +} +# 330 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline void __ISB(void) +{ + __asm volatile ("isb"); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __DSB(void) +{ + __asm volatile ("dsb"); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __DMB(void) +{ + __asm volatile ("dmb"); +} +# 365 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __asm volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} +# 381 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __asm volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} +# 397 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __asm volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} +# 414 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __asm volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} +# 431 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __asm volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} +# 447 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __asm volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} +# 463 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __asm volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} +# 479 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __asm volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} +# 497 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __asm volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} +# 515 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __asm volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} +# 533 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __asm volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __CLREX(void) +{ + __asm volatile ("clrex"); +} +# 561 "naeusb/sam3u_hal/inc/core_cmInstr.h" +#define __SSAT(ARG1,ARG2) ({ uint32_t __RES, __ARG1 = (ARG1); __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); __RES; }) +# 577 "naeusb/sam3u_hal/inc/core_cmInstr.h" +#define __USAT(ARG1,ARG2) ({ uint32_t __RES, __ARG1 = (ARG1); __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); __RES; }) +# 592 "naeusb/sam3u_hal/inc/core_cmInstr.h" +__attribute__( ( always_inline ) ) static inline uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} +# 120 "naeusb/sam3u_hal/inc/core_cm3.h" 2 +# 1 "naeusb/sam3u_hal/inc/core_cmFunc.h" 1 +# 25 "naeusb/sam3u_hal/inc/core_cmFunc.h" +#define __CORE_CMFUNC_H +# 315 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __enable_irq(void) +{ + __asm volatile ("cpsie i"); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __disable_irq(void) +{ + __asm volatile ("cpsid i"); +} +# 338 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} +# 353 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __set_CONTROL(uint32_t control) +{ + __asm volatile ("MSR control, %0" : : "r" (control) ); +} +# 365 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_IPSR(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} +# 380 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_APSR(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} +# 395 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_xPSR(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} +# 410 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_PSP(void) +{ + register uint32_t result; + + __asm volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} +# 425 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __set_PSP(uint32_t topOfProcStack) +{ + __asm volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} +# 437 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_MSP(void) +{ + register uint32_t result; + + __asm volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} +# 452 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __set_MSP(uint32_t topOfMainStack) +{ + __asm volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} +# 464 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} +# 479 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __set_PRIMASK(uint32_t priMask) +{ + __asm volatile ("MSR primask, %0" : : "r" (priMask) ); +} +# 492 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __enable_fault_irq(void) +{ + __asm volatile ("cpsie f"); +} + + + + + + + +__attribute__( ( always_inline ) ) static inline void __disable_fault_irq(void) +{ + __asm volatile ("cpsid f"); +} +# 515 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} +# 530 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __set_BASEPRI(uint32_t value) +{ + __asm volatile ("MSR basepri, %0" : : "r" (value) ); +} +# 542 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __asm volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} +# 557 "naeusb/sam3u_hal/inc/core_cmFunc.h" +__attribute__( ( always_inline ) ) static inline void __set_FAULTMASK(uint32_t faultMask) +{ + __asm volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} +# 121 "naeusb/sam3u_hal/inc/core_cm3.h" 2 + + + + + + +#define __CORE_CM3_H_DEPENDANT +# 163 "naeusb/sam3u_hal/inc/core_cm3.h" +#define __I volatile const + +#define __O volatile +#define __IO volatile +# 194 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef union +{ + struct + { + + uint32_t _reserved0:27; + + + + + + uint32_t Q:1; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} APSR_Type; + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + + uint32_t _reserved0:15; + + + + + + uint32_t T:1; + uint32_t IT:2; + uint32_t Q:1; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} xPSR_Type; + + + + +typedef union +{ + struct + { + uint32_t nPRIV:1; + uint32_t SPSEL:1; + uint32_t FPCA:1; + uint32_t _reserved0:29; + } b; + uint32_t w; +} CONTROL_Type; +# 279 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile uint32_t ISER[8]; + uint32_t RESERVED0[24]; + volatile uint32_t ICER[8]; + uint32_t RSERVED1[24]; + volatile uint32_t ISPR[8]; + uint32_t RESERVED2[24]; + volatile uint32_t ICPR[8]; + uint32_t RESERVED3[24]; + volatile uint32_t IABR[8]; + uint32_t RESERVED4[56]; + volatile uint8_t IP[240]; + uint32_t RESERVED5[644]; + volatile uint32_t STIR; +} NVIC_Type; + + +#define NVIC_STIR_INTID_Pos 0 +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) +# 311 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile const uint32_t CPUID; + volatile uint32_t ICSR; + volatile uint32_t VTOR; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + volatile uint8_t SHP[12]; + volatile uint32_t SHCSR; + volatile uint32_t CFSR; + volatile uint32_t HFSR; + volatile uint32_t DFSR; + volatile uint32_t MMFAR; + volatile uint32_t BFAR; + volatile uint32_t AFSR; + volatile const uint32_t PFR[2]; + volatile const uint32_t DFR; + volatile const uint32_t ADR; + volatile const uint32_t MMFR[4]; + volatile const uint32_t ISAR[5]; + uint32_t RESERVED0[5]; + volatile uint32_t CPACR; +} SCB_Type; + + +#define SCB_CPUID_IMPLEMENTER_Pos 24 +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) + +#define SCB_CPUID_VARIANT_Pos 20 +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) + +#define SCB_CPUID_ARCHITECTURE_Pos 16 +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) + +#define SCB_CPUID_PARTNO_Pos 4 +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) + +#define SCB_CPUID_REVISION_Pos 0 +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) + + +#define SCB_ICSR_NMIPENDSET_Pos 31 +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) + +#define SCB_ICSR_PENDSVSET_Pos 28 +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) + +#define SCB_ICSR_PENDSVCLR_Pos 27 +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) + +#define SCB_ICSR_PENDSTSET_Pos 26 +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) + +#define SCB_ICSR_PENDSTCLR_Pos 25 +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) + +#define SCB_ICSR_ISRPREEMPT_Pos 23 +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) + +#define SCB_ICSR_ISRPENDING_Pos 22 +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) + +#define SCB_ICSR_VECTPENDING_Pos 12 +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) + +#define SCB_ICSR_RETTOBASE_Pos 11 +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) + +#define SCB_ICSR_VECTACTIVE_Pos 0 +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) + + + +#define SCB_VTOR_TBLBASE_Pos 29 +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) + +#define SCB_VTOR_TBLOFF_Pos 7 +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) + + + + + + +#define SCB_AIRCR_VECTKEY_Pos 16 +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) + +#define SCB_AIRCR_ENDIANESS_Pos 15 +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) + +#define SCB_AIRCR_PRIGROUP_Pos 8 +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) + +#define SCB_AIRCR_VECTRESET_Pos 0 +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) + + +#define SCB_SCR_SEVONPEND_Pos 4 +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) + +#define SCB_SCR_SLEEPDEEP_Pos 2 +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) + +#define SCB_SCR_SLEEPONEXIT_Pos 1 +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) + + +#define SCB_CCR_STKALIGN_Pos 9 +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) + +#define SCB_CCR_BFHFNMIGN_Pos 8 +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) + +#define SCB_CCR_DIV_0_TRP_Pos 4 +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) + +#define SCB_CCR_UNALIGN_TRP_Pos 3 +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) + +#define SCB_CCR_USERSETMPEND_Pos 1 +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) + +#define SCB_CCR_NONBASETHRDENA_Pos 0 +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) + + +#define SCB_SHCSR_USGFAULTENA_Pos 18 +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) + +#define SCB_SHCSR_SYSTICKACT_Pos 11 +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) + +#define SCB_SHCSR_PENDSVACT_Pos 10 +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) + +#define SCB_SHCSR_MONITORACT_Pos 8 +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) + +#define SCB_SHCSR_SVCALLACT_Pos 7 +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) + +#define SCB_SHCSR_USGFAULTACT_Pos 3 +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) + + +#define SCB_CFSR_USGFAULTSR_Pos 16 +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) + +#define SCB_CFSR_BUSFAULTSR_Pos 8 +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) + +#define SCB_CFSR_MEMFAULTSR_Pos 0 +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) + + +#define SCB_HFSR_DEBUGEVT_Pos 31 +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) + +#define SCB_HFSR_FORCED_Pos 30 +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) + +#define SCB_HFSR_VECTTBL_Pos 1 +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) + + +#define SCB_DFSR_EXTERNAL_Pos 4 +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) + +#define SCB_DFSR_VCATCH_Pos 3 +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) + +#define SCB_DFSR_DWTTRAP_Pos 2 +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) + +#define SCB_DFSR_BKPT_Pos 1 +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) + +#define SCB_DFSR_HALTED_Pos 0 +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) +# 536 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + uint32_t RESERVED0[1]; + volatile const uint32_t ICTR; + + volatile uint32_t ACTLR; + + + +} SCnSCB_Type; + + +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) + + + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) +# 573 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile uint32_t CTRL; + volatile uint32_t LOAD; + volatile uint32_t VAL; + volatile const uint32_t CALIB; +} SysTick_Type; + + +#define SysTick_CTRL_COUNTFLAG_Pos 16 +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) + +#define SysTick_CTRL_CLKSOURCE_Pos 2 +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) + +#define SysTick_CTRL_TICKINT_Pos 1 +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) + +#define SysTick_CTRL_ENABLE_Pos 0 +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) + + +#define SysTick_LOAD_RELOAD_Pos 0 +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) + + +#define SysTick_VAL_CURRENT_Pos 0 +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) + + +#define SysTick_CALIB_NOREF_Pos 31 +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) + +#define SysTick_CALIB_SKEW_Pos 30 +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) + +#define SysTick_CALIB_TENMS_Pos 0 +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) +# 623 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile union + { + volatile uint8_t u8; + volatile uint16_t u16; + volatile uint32_t u32; + } PORT [32]; + uint32_t RESERVED0[864]; + volatile uint32_t TER; + uint32_t RESERVED1[15]; + volatile uint32_t TPR; + uint32_t RESERVED2[15]; + volatile uint32_t TCR; +} ITM_Type; + + +#define ITM_TPR_PRIVMASK_Pos 0 +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) + + +#define ITM_TCR_BUSY_Pos 23 +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) + +#define ITM_TCR_TraceBusID_Pos 16 +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) + +#define ITM_TCR_GTSFREQ_Pos 10 +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) + +#define ITM_TCR_TSPrescale_Pos 8 +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) + +#define ITM_TCR_SWOENA_Pos 4 +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) + +#define ITM_TCR_TXENA_Pos 3 +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) + +#define ITM_TCR_SYNCENA_Pos 2 +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) + +#define ITM_TCR_TSENA_Pos 1 +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) + +#define ITM_TCR_ITMENA_Pos 0 +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) +# 682 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile uint32_t CTRL; + volatile uint32_t CYCCNT; + volatile uint32_t CPICNT; + volatile uint32_t EXCCNT; + volatile uint32_t SLEEPCNT; + volatile uint32_t LSUCNT; + volatile uint32_t FOLDCNT; + volatile const uint32_t PCSR; + volatile uint32_t COMP0; + volatile uint32_t MASK0; + volatile uint32_t FUNCTION0; + uint32_t RESERVED0[1]; + volatile uint32_t COMP1; + volatile uint32_t MASK1; + volatile uint32_t FUNCTION1; + uint32_t RESERVED1[1]; + volatile uint32_t COMP2; + volatile uint32_t MASK2; + volatile uint32_t FUNCTION2; + uint32_t RESERVED2[1]; + volatile uint32_t COMP3; + volatile uint32_t MASK3; + volatile uint32_t FUNCTION3; +} DWT_Type; + + +#define DWT_CTRL_NUMCOMP_Pos 28 +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) + +#define DWT_CTRL_NOTRCPKT_Pos 27 +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) + +#define DWT_CTRL_NOEXTTRIG_Pos 26 +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) + +#define DWT_CTRL_NOCYCCNT_Pos 25 +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) + +#define DWT_CTRL_NOPRFCNT_Pos 24 +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) + +#define DWT_CTRL_CYCEVTENA_Pos 22 +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) + +#define DWT_CTRL_FOLDEVTENA_Pos 21 +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) + +#define DWT_CTRL_LSUEVTENA_Pos 20 +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) + +#define DWT_CTRL_EXCEVTENA_Pos 18 +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) + +#define DWT_CTRL_CPIEVTENA_Pos 17 +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) + +#define DWT_CTRL_EXCTRCENA_Pos 16 +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) + +#define DWT_CTRL_PCSAMPLENA_Pos 12 +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) + +#define DWT_CTRL_SYNCTAP_Pos 10 +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) + +#define DWT_CTRL_CYCTAP_Pos 9 +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) + +#define DWT_CTRL_POSTINIT_Pos 5 +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) + +#define DWT_CTRL_POSTPRESET_Pos 1 +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) + +#define DWT_CTRL_CYCCNTENA_Pos 0 +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) + + +#define DWT_CPICNT_CPICNT_Pos 0 +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) + + +#define DWT_EXCCNT_EXCCNT_Pos 0 +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) + + +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) + + +#define DWT_LSUCNT_LSUCNT_Pos 0 +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) + + +#define DWT_FOLDCNT_FOLDCNT_Pos 0 +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) + + +#define DWT_MASK_MASK_Pos 0 +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) + + +#define DWT_FUNCTION_MATCHED_Pos 24 +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) + +#define DWT_FUNCTION_LNK1ENA_Pos 9 +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) + +#define DWT_FUNCTION_CYCMATCH_Pos 7 +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) + +#define DWT_FUNCTION_EMITRANGE_Pos 5 +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) + +#define DWT_FUNCTION_FUNCTION_Pos 0 +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) +# 827 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile uint32_t SSPSR; + volatile uint32_t CSPSR; + uint32_t RESERVED0[2]; + volatile uint32_t ACPR; + uint32_t RESERVED1[55]; + volatile uint32_t SPPR; + uint32_t RESERVED2[131]; + volatile const uint32_t FFSR; + volatile uint32_t FFCR; + volatile const uint32_t FSCR; + uint32_t RESERVED3[759]; + volatile const uint32_t TRIGGER; + volatile const uint32_t FIFO0; + volatile const uint32_t ITATBCTR2; + uint32_t RESERVED4[1]; + volatile const uint32_t ITATBCTR0; + volatile const uint32_t FIFO1; + volatile uint32_t ITCTRL; + uint32_t RESERVED5[39]; + volatile uint32_t CLAIMSET; + volatile uint32_t CLAIMCLR; + uint32_t RESERVED7[8]; + volatile const uint32_t DEVID; + volatile const uint32_t DEVTYPE; +} TPI_Type; + + +#define TPI_ACPR_PRESCALER_Pos 0 +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) + + +#define TPI_SPPR_TXMODE_Pos 0 +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) + + +#define TPI_FFSR_FtNonStop_Pos 3 +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) + +#define TPI_FFSR_TCPresent_Pos 2 +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) + +#define TPI_FFSR_FtStopped_Pos 1 +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) + +#define TPI_FFSR_FlInProg_Pos 0 +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) + + +#define TPI_FFCR_TrigIn_Pos 8 +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) + +#define TPI_FFCR_EnFCont_Pos 1 +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) + + +#define TPI_TRIGGER_TRIGGER_Pos 0 +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) + + +#define TPI_FIFO0_ITM_ATVALID_Pos 29 +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) + +#define TPI_FIFO0_ITM_bytecount_Pos 27 +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) + +#define TPI_FIFO0_ETM_bytecount_Pos 24 +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) + +#define TPI_FIFO0_ETM2_Pos 16 +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) + +#define TPI_FIFO0_ETM1_Pos 8 +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) + +#define TPI_FIFO0_ETM0_Pos 0 +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) + + +#define TPI_ITATBCTR2_ATREADY_Pos 0 +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) + + +#define TPI_FIFO1_ITM_ATVALID_Pos 29 +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) + +#define TPI_FIFO1_ITM_bytecount_Pos 27 +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) + +#define TPI_FIFO1_ETM_bytecount_Pos 24 +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) + +#define TPI_FIFO1_ITM2_Pos 16 +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) + +#define TPI_FIFO1_ITM1_Pos 8 +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) + +#define TPI_FIFO1_ITM0_Pos 0 +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) + + +#define TPI_ITATBCTR0_ATREADY_Pos 0 +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) + + +#define TPI_ITCTRL_Mode_Pos 0 +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) + + +#define TPI_DEVID_NRZVALID_Pos 11 +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) + +#define TPI_DEVID_MANCVALID_Pos 10 +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) + +#define TPI_DEVID_PTINVALID_Pos 9 +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) + +#define TPI_DEVID_MinBufSz_Pos 6 +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) + +#define TPI_DEVID_AsynClkIn_Pos 5 +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) + +#define TPI_DEVID_NrTraceInput_Pos 0 +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) + + +#define TPI_DEVTYPE_SubType_Pos 0 +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) + +#define TPI_DEVTYPE_MajorType_Pos 4 +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) +# 981 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile const uint32_t TYPE; + volatile uint32_t CTRL; + volatile uint32_t RNR; + volatile uint32_t RBAR; + volatile uint32_t RASR; + volatile uint32_t RBAR_A1; + volatile uint32_t RASR_A1; + volatile uint32_t RBAR_A2; + volatile uint32_t RASR_A2; + volatile uint32_t RBAR_A3; + volatile uint32_t RASR_A3; +} MPU_Type; + + +#define MPU_TYPE_IREGION_Pos 16 +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) + +#define MPU_TYPE_DREGION_Pos 8 +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) + +#define MPU_TYPE_SEPARATE_Pos 0 +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) + + +#define MPU_CTRL_PRIVDEFENA_Pos 2 +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) + +#define MPU_CTRL_HFNMIENA_Pos 1 +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) + +#define MPU_CTRL_ENABLE_Pos 0 +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) + + +#define MPU_RNR_REGION_Pos 0 +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) + + +#define MPU_RBAR_ADDR_Pos 5 +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) + +#define MPU_RBAR_VALID_Pos 4 +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) + +#define MPU_RBAR_REGION_Pos 0 +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) + + +#define MPU_RASR_ATTRS_Pos 16 +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) + +#define MPU_RASR_SRD_Pos 8 +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) + +#define MPU_RASR_SIZE_Pos 1 +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) + +#define MPU_RASR_ENABLE_Pos 0 +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) +# 1055 "naeusb/sam3u_hal/inc/core_cm3.h" +typedef struct +{ + volatile uint32_t DHCSR; + volatile uint32_t DCRSR; + volatile uint32_t DCRDR; + volatile uint32_t DEMCR; +} CoreDebug_Type; + + +#define CoreDebug_DHCSR_DBGKEY_Pos 16 +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) + +#define CoreDebug_DHCSR_S_HALT_Pos 17 +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) + +#define CoreDebug_DHCSR_C_STEP_Pos 2 +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) + +#define CoreDebug_DHCSR_C_HALT_Pos 1 +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) + + +#define CoreDebug_DCRSR_REGWnR_Pos 16 +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) + +#define CoreDebug_DCRSR_REGSEL_Pos 0 +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) + + +#define CoreDebug_DEMCR_TRCENA_Pos 24 +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) + +#define CoreDebug_DEMCR_MON_EN_Pos 16 +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) +# 1157 "naeusb/sam3u_hal/inc/core_cm3.h" +#define SCS_BASE (0xE000E000UL) +#define ITM_BASE (0xE0000000UL) +#define DWT_BASE (0xE0001000UL) +#define TPI_BASE (0xE0040000UL) +#define CoreDebug_BASE (0xE000EDF0UL) +#define SysTick_BASE (SCS_BASE + 0x0010UL) +#define NVIC_BASE (SCS_BASE + 0x0100UL) +#define SCB_BASE (SCS_BASE + 0x0D00UL) + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) +#define SCB ((SCB_Type *) SCB_BASE ) +#define SysTick ((SysTick_Type *) SysTick_BASE ) +#define NVIC ((NVIC_Type *) NVIC_BASE ) +#define ITM ((ITM_Type *) ITM_BASE ) +#define DWT ((DWT_Type *) DWT_BASE ) +#define TPI ((TPI_Type *) TPI_BASE ) +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) + + +#define MPU_BASE (SCS_BASE + 0x0D90UL) +#define MPU ((MPU_Type *) MPU_BASE ) +# 1214 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); + + reg_value = ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR; + reg_value &= ~((0xFFFFUL << 16) | (7UL << 8)); + reg_value = (reg_value | + ((uint32_t)0x5FA << 16) | + (PriorityGroupTmp << 8)); + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = reg_value; +} +# 1234 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8)) >> 8); +} +# 1246 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} +# 1258 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} +# 1274 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} +# 1286 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} +# 1298 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} +# 1313 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} +# 1328 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - 4)) & 0xff); } + else { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[(uint32_t)(IRQn)] = ((priority << (8 - 4)) & 0xff); } +} +# 1348 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - 4))); } + else { + return((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[(uint32_t)(IRQn)] >> (8 - 4))); } +} +# 1370 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} +# 1398 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + + + + +static inline void NVIC_SystemReset(void) +{ + __DSB(); + + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FA << 16) | + (((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8)) | + (1UL << 2)); + __DSB(); + while(1); +} +# 1455 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > (0xFFFFFFUL << 0)) return (1); + + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (ticks & (0xFFFFFFUL << 0)) - 1; + NVIC_SetPriority (SysTick_IRQn, (1<<4) - 1); + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0; + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2) | + (1UL << 1) | + (1UL << 0); + return (0); +} +# 1481 "naeusb/sam3u_hal/inc/core_cm3.h" +extern volatile int32_t ITM_RxBuffer; +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 +# 1495 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline uint32_t ITM_SendChar (uint32_t ch) +{ + if ((((ITM_Type *) (0xE0000000UL) )->TCR & (1UL << 0)) && + (((ITM_Type *) (0xE0000000UL) )->TER & (1UL << 0) ) ) + { + while (((ITM_Type *) (0xE0000000UL) )->PORT[0].u32 == 0); + ((ITM_Type *) (0xE0000000UL) )->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} +# 1514 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; + + if (ITM_RxBuffer != 0x5AA55AA5) { + ch = ITM_RxBuffer; + ITM_RxBuffer = 0x5AA55AA5; + } + + return (ch); +} +# 1533 "naeusb/sam3u_hal/inc/core_cm3.h" +static inline int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == 0x5AA55AA5) { + return (0); + } else { + return (1); + } +} +# 230 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 + +# 1 "naeusb/sam3u_hal/inc/system_sam3u.h" 1 +# 46 "naeusb/sam3u_hal/inc/system_sam3u.h" +#define SYSTEM_SAM3U_H_INCLUDED +# 57 "naeusb/sam3u_hal/inc/system_sam3u.h" +# 1 "naeusb/sam3u_hal/inc/compiler.h" 1 +# 58 "naeusb/sam3u_hal/inc/system_sam3u.h" 2 + +extern uint32_t SystemCoreClock; + + + + + +void SystemInit(void); + + + + + +void SystemCoreClockUpdate(void); + + + + +void system_init_flash(uint32_t ul_clk); +# 232 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 242 "naeusb/sam3u_hal/inc/sam3u2c.h" +# 1 "naeusb/sam3u_hal/inc/component/component_adc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_adc.h" +#define _SAM3U_ADC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_adc.h" +typedef struct { + WoReg ADC_CR; + RwReg ADC_MR; + RoReg Reserved1[2]; + WoReg ADC_CHER; + WoReg ADC_CHDR; + RoReg ADC_CHSR; + RoReg ADC_SR; + RoReg ADC_LCDR; + WoReg ADC_IER; + WoReg ADC_IDR; + RoReg ADC_IMR; + RoReg ADC_CDR[8]; + RoReg Reserved2[44]; + RwReg ADC_RPR; + RwReg ADC_RCR; + RoReg Reserved3[2]; + RwReg ADC_RNPR; + RwReg ADC_RNCR; + RoReg Reserved4[2]; + WoReg ADC_PTCR; + RoReg ADC_PTSR; +} Adc; + + +#define ADC_CR_SWRST (0x1u << 0) +#define ADC_CR_START (0x1u << 1) + +#define ADC_MR_TRGEN (0x1u << 0) +#define ADC_MR_TRGEN_DIS (0x0u << 0) +#define ADC_MR_TRGEN_EN (0x1u << 0) +#define ADC_MR_TRGSEL_Pos 1 +#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) +#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos))) +#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) +#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) +#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) +#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) +#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) +#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) +#define ADC_MR_LOWRES (0x1u << 4) +#define ADC_MR_LOWRES_BITS_10 (0x0u << 4) +#define ADC_MR_LOWRES_BITS_8 (0x1u << 4) +#define ADC_MR_SLEEP (0x1u << 5) +#define ADC_MR_SLEEP_NORMAL (0x0u << 5) +#define ADC_MR_SLEEP_SLEEP (0x1u << 5) +#define ADC_MR_PRESCAL_Pos 8 +#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) +#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) +#define ADC_MR_STARTUP_Pos 16 +#define ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) +#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos))) +#define ADC_MR_SHTIM_Pos 24 +#define ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) +#define ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos))) + +#define ADC_CHER_CH0 (0x1u << 0) +#define ADC_CHER_CH1 (0x1u << 1) +#define ADC_CHER_CH2 (0x1u << 2) +#define ADC_CHER_CH3 (0x1u << 3) +#define ADC_CHER_CH4 (0x1u << 4) +#define ADC_CHER_CH5 (0x1u << 5) +#define ADC_CHER_CH6 (0x1u << 6) +#define ADC_CHER_CH7 (0x1u << 7) + +#define ADC_CHDR_CH0 (0x1u << 0) +#define ADC_CHDR_CH1 (0x1u << 1) +#define ADC_CHDR_CH2 (0x1u << 2) +#define ADC_CHDR_CH3 (0x1u << 3) +#define ADC_CHDR_CH4 (0x1u << 4) +#define ADC_CHDR_CH5 (0x1u << 5) +#define ADC_CHDR_CH6 (0x1u << 6) +#define ADC_CHDR_CH7 (0x1u << 7) + +#define ADC_CHSR_CH0 (0x1u << 0) +#define ADC_CHSR_CH1 (0x1u << 1) +#define ADC_CHSR_CH2 (0x1u << 2) +#define ADC_CHSR_CH3 (0x1u << 3) +#define ADC_CHSR_CH4 (0x1u << 4) +#define ADC_CHSR_CH5 (0x1u << 5) +#define ADC_CHSR_CH6 (0x1u << 6) +#define ADC_CHSR_CH7 (0x1u << 7) + +#define ADC_SR_EOC0 (0x1u << 0) +#define ADC_SR_EOC1 (0x1u << 1) +#define ADC_SR_EOC2 (0x1u << 2) +#define ADC_SR_EOC3 (0x1u << 3) +#define ADC_SR_EOC4 (0x1u << 4) +#define ADC_SR_EOC5 (0x1u << 5) +#define ADC_SR_EOC6 (0x1u << 6) +#define ADC_SR_EOC7 (0x1u << 7) +#define ADC_SR_OVRE0 (0x1u << 8) +#define ADC_SR_OVRE1 (0x1u << 9) +#define ADC_SR_OVRE2 (0x1u << 10) +#define ADC_SR_OVRE3 (0x1u << 11) +#define ADC_SR_OVRE4 (0x1u << 12) +#define ADC_SR_OVRE5 (0x1u << 13) +#define ADC_SR_OVRE6 (0x1u << 14) +#define ADC_SR_OVRE7 (0x1u << 15) +#define ADC_SR_DRDY (0x1u << 16) +#define ADC_SR_GOVRE (0x1u << 17) +#define ADC_SR_ENDRX (0x1u << 18) +#define ADC_SR_RXBUFF (0x1u << 19) + +#define ADC_LCDR_LDATA_Pos 0 +#define ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) + +#define ADC_IER_EOC0 (0x1u << 0) +#define ADC_IER_EOC1 (0x1u << 1) +#define ADC_IER_EOC2 (0x1u << 2) +#define ADC_IER_EOC3 (0x1u << 3) +#define ADC_IER_EOC4 (0x1u << 4) +#define ADC_IER_EOC5 (0x1u << 5) +#define ADC_IER_EOC6 (0x1u << 6) +#define ADC_IER_EOC7 (0x1u << 7) +#define ADC_IER_OVRE0 (0x1u << 8) +#define ADC_IER_OVRE1 (0x1u << 9) +#define ADC_IER_OVRE2 (0x1u << 10) +#define ADC_IER_OVRE3 (0x1u << 11) +#define ADC_IER_OVRE4 (0x1u << 12) +#define ADC_IER_OVRE5 (0x1u << 13) +#define ADC_IER_OVRE6 (0x1u << 14) +#define ADC_IER_OVRE7 (0x1u << 15) +#define ADC_IER_DRDY (0x1u << 16) +#define ADC_IER_GOVRE (0x1u << 17) +#define ADC_IER_ENDRX (0x1u << 18) +#define ADC_IER_RXBUFF (0x1u << 19) + +#define ADC_IDR_EOC0 (0x1u << 0) +#define ADC_IDR_EOC1 (0x1u << 1) +#define ADC_IDR_EOC2 (0x1u << 2) +#define ADC_IDR_EOC3 (0x1u << 3) +#define ADC_IDR_EOC4 (0x1u << 4) +#define ADC_IDR_EOC5 (0x1u << 5) +#define ADC_IDR_EOC6 (0x1u << 6) +#define ADC_IDR_EOC7 (0x1u << 7) +#define ADC_IDR_OVRE0 (0x1u << 8) +#define ADC_IDR_OVRE1 (0x1u << 9) +#define ADC_IDR_OVRE2 (0x1u << 10) +#define ADC_IDR_OVRE3 (0x1u << 11) +#define ADC_IDR_OVRE4 (0x1u << 12) +#define ADC_IDR_OVRE5 (0x1u << 13) +#define ADC_IDR_OVRE6 (0x1u << 14) +#define ADC_IDR_OVRE7 (0x1u << 15) +#define ADC_IDR_DRDY (0x1u << 16) +#define ADC_IDR_GOVRE (0x1u << 17) +#define ADC_IDR_ENDRX (0x1u << 18) +#define ADC_IDR_RXBUFF (0x1u << 19) + +#define ADC_IMR_EOC0 (0x1u << 0) +#define ADC_IMR_EOC1 (0x1u << 1) +#define ADC_IMR_EOC2 (0x1u << 2) +#define ADC_IMR_EOC3 (0x1u << 3) +#define ADC_IMR_EOC4 (0x1u << 4) +#define ADC_IMR_EOC5 (0x1u << 5) +#define ADC_IMR_EOC6 (0x1u << 6) +#define ADC_IMR_EOC7 (0x1u << 7) +#define ADC_IMR_OVRE0 (0x1u << 8) +#define ADC_IMR_OVRE1 (0x1u << 9) +#define ADC_IMR_OVRE2 (0x1u << 10) +#define ADC_IMR_OVRE3 (0x1u << 11) +#define ADC_IMR_OVRE4 (0x1u << 12) +#define ADC_IMR_OVRE5 (0x1u << 13) +#define ADC_IMR_OVRE6 (0x1u << 14) +#define ADC_IMR_OVRE7 (0x1u << 15) +#define ADC_IMR_DRDY (0x1u << 16) +#define ADC_IMR_GOVRE (0x1u << 17) +#define ADC_IMR_ENDRX (0x1u << 18) +#define ADC_IMR_RXBUFF (0x1u << 19) + +#define ADC_CDR_DATA_Pos 0 +#define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) + +#define ADC_RPR_RXPTR_Pos 0 +#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) +#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) + +#define ADC_RCR_RXCTR_Pos 0 +#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) +#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) + +#define ADC_RNPR_RXNPTR_Pos 0 +#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) +#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) + +#define ADC_RNCR_RXNCTR_Pos 0 +#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) +#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) + +#define ADC_PTCR_RXTEN (0x1u << 0) +#define ADC_PTCR_RXTDIS (0x1u << 1) +#define ADC_PTCR_TXTEN (0x1u << 8) +#define ADC_PTCR_TXTDIS (0x1u << 9) + +#define ADC_PTSR_RXTEN (0x1u << 0) +#define ADC_PTSR_TXTEN (0x1u << 8) +# 243 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_adc12b.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_adc12b.h" +#define _SAM3U_ADC12B_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_adc12b.h" +typedef struct { + WoReg ADC12B_CR; + RwReg ADC12B_MR; + RoReg Reserved1[2]; + WoReg ADC12B_CHER; + WoReg ADC12B_CHDR; + RoReg ADC12B_CHSR; + RoReg ADC12B_SR; + RoReg ADC12B_LCDR; + WoReg ADC12B_IER; + WoReg ADC12B_IDR; + RoReg ADC12B_IMR; + RoReg ADC12B_CDR[8]; + RoReg Reserved2[5]; + RwReg ADC12B_ACR; + RwReg ADC12B_EMR; + RoReg Reserved3[37]; + RwReg ADC12B_RPR; + RwReg ADC12B_RCR; + RoReg Reserved4[2]; + RwReg ADC12B_RNPR; + RwReg ADC12B_RNCR; + RoReg Reserved5[2]; + WoReg ADC12B_PTCR; + RoReg ADC12B_PTSR; +} Adc12b; + + +#define ADC12B_CR_SWRST (0x1u << 0) +#define ADC12B_CR_START (0x1u << 1) + +#define ADC12B_MR_TRGEN (0x1u << 0) +#define ADC12B_MR_TRGEN_DIS (0x0u << 0) +#define ADC12B_MR_TRGEN_EN (0x1u << 0) +#define ADC12B_MR_TRGSEL_Pos 1 +#define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) +#define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos))) +#define ADC12B_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) +#define ADC12B_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) +#define ADC12B_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) +#define ADC12B_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) +#define ADC12B_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) +#define ADC12B_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) +#define ADC12B_MR_LOWRES (0x1u << 4) +#define ADC12B_MR_LOWRES_BITS_12 (0x0u << 4) +#define ADC12B_MR_LOWRES_BITS_10 (0x1u << 4) +#define ADC12B_MR_SLEEP (0x1u << 5) +#define ADC12B_MR_SLEEP_NORMAL (0x0u << 5) +#define ADC12B_MR_SLEEP_SLEEP (0x1u << 5) +#define ADC12B_MR_PRESCAL_Pos 8 +#define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) +#define ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos))) +#define ADC12B_MR_STARTUP_Pos 16 +#define ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos) +#define ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos))) +#define ADC12B_MR_SHTIM_Pos 24 +#define ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos) +#define ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos))) + +#define ADC12B_CHER_CH0 (0x1u << 0) +#define ADC12B_CHER_CH1 (0x1u << 1) +#define ADC12B_CHER_CH2 (0x1u << 2) +#define ADC12B_CHER_CH3 (0x1u << 3) +#define ADC12B_CHER_CH4 (0x1u << 4) +#define ADC12B_CHER_CH5 (0x1u << 5) +#define ADC12B_CHER_CH6 (0x1u << 6) +#define ADC12B_CHER_CH7 (0x1u << 7) + +#define ADC12B_CHDR_CH0 (0x1u << 0) +#define ADC12B_CHDR_CH1 (0x1u << 1) +#define ADC12B_CHDR_CH2 (0x1u << 2) +#define ADC12B_CHDR_CH3 (0x1u << 3) +#define ADC12B_CHDR_CH4 (0x1u << 4) +#define ADC12B_CHDR_CH5 (0x1u << 5) +#define ADC12B_CHDR_CH6 (0x1u << 6) +#define ADC12B_CHDR_CH7 (0x1u << 7) + +#define ADC12B_CHSR_CH0 (0x1u << 0) +#define ADC12B_CHSR_CH1 (0x1u << 1) +#define ADC12B_CHSR_CH2 (0x1u << 2) +#define ADC12B_CHSR_CH3 (0x1u << 3) +#define ADC12B_CHSR_CH4 (0x1u << 4) +#define ADC12B_CHSR_CH5 (0x1u << 5) +#define ADC12B_CHSR_CH6 (0x1u << 6) +#define ADC12B_CHSR_CH7 (0x1u << 7) + +#define ADC12B_SR_EOC0 (0x1u << 0) +#define ADC12B_SR_EOC1 (0x1u << 1) +#define ADC12B_SR_EOC2 (0x1u << 2) +#define ADC12B_SR_EOC3 (0x1u << 3) +#define ADC12B_SR_EOC4 (0x1u << 4) +#define ADC12B_SR_EOC5 (0x1u << 5) +#define ADC12B_SR_EOC6 (0x1u << 6) +#define ADC12B_SR_EOC7 (0x1u << 7) +#define ADC12B_SR_OVRE0 (0x1u << 8) +#define ADC12B_SR_OVRE1 (0x1u << 9) +#define ADC12B_SR_OVRE2 (0x1u << 10) +#define ADC12B_SR_OVRE3 (0x1u << 11) +#define ADC12B_SR_OVRE4 (0x1u << 12) +#define ADC12B_SR_OVRE5 (0x1u << 13) +#define ADC12B_SR_OVRE6 (0x1u << 14) +#define ADC12B_SR_OVRE7 (0x1u << 15) +#define ADC12B_SR_DRDY (0x1u << 16) +#define ADC12B_SR_GOVRE (0x1u << 17) +#define ADC12B_SR_ENDRX (0x1u << 18) +#define ADC12B_SR_RXBUFF (0x1u << 19) + +#define ADC12B_LCDR_LDATA_Pos 0 +#define ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos) + +#define ADC12B_IER_EOC0 (0x1u << 0) +#define ADC12B_IER_EOC1 (0x1u << 1) +#define ADC12B_IER_EOC2 (0x1u << 2) +#define ADC12B_IER_EOC3 (0x1u << 3) +#define ADC12B_IER_EOC4 (0x1u << 4) +#define ADC12B_IER_EOC5 (0x1u << 5) +#define ADC12B_IER_EOC6 (0x1u << 6) +#define ADC12B_IER_EOC7 (0x1u << 7) +#define ADC12B_IER_OVRE0 (0x1u << 8) +#define ADC12B_IER_OVRE1 (0x1u << 9) +#define ADC12B_IER_OVRE2 (0x1u << 10) +#define ADC12B_IER_OVRE3 (0x1u << 11) +#define ADC12B_IER_OVRE4 (0x1u << 12) +#define ADC12B_IER_OVRE5 (0x1u << 13) +#define ADC12B_IER_OVRE6 (0x1u << 14) +#define ADC12B_IER_OVRE7 (0x1u << 15) +#define ADC12B_IER_DRDY (0x1u << 16) +#define ADC12B_IER_GOVRE (0x1u << 17) +#define ADC12B_IER_ENDRX (0x1u << 18) +#define ADC12B_IER_RXBUFF (0x1u << 19) + +#define ADC12B_IDR_EOC0 (0x1u << 0) +#define ADC12B_IDR_EOC1 (0x1u << 1) +#define ADC12B_IDR_EOC2 (0x1u << 2) +#define ADC12B_IDR_EOC3 (0x1u << 3) +#define ADC12B_IDR_EOC4 (0x1u << 4) +#define ADC12B_IDR_EOC5 (0x1u << 5) +#define ADC12B_IDR_EOC6 (0x1u << 6) +#define ADC12B_IDR_EOC7 (0x1u << 7) +#define ADC12B_IDR_OVRE0 (0x1u << 8) +#define ADC12B_IDR_OVRE1 (0x1u << 9) +#define ADC12B_IDR_OVRE2 (0x1u << 10) +#define ADC12B_IDR_OVRE3 (0x1u << 11) +#define ADC12B_IDR_OVRE4 (0x1u << 12) +#define ADC12B_IDR_OVRE5 (0x1u << 13) +#define ADC12B_IDR_OVRE6 (0x1u << 14) +#define ADC12B_IDR_OVRE7 (0x1u << 15) +#define ADC12B_IDR_DRDY (0x1u << 16) +#define ADC12B_IDR_GOVRE (0x1u << 17) +#define ADC12B_IDR_ENDRX (0x1u << 18) +#define ADC12B_IDR_RXBUFF (0x1u << 19) + +#define ADC12B_IMR_EOC0 (0x1u << 0) +#define ADC12B_IMR_EOC1 (0x1u << 1) +#define ADC12B_IMR_EOC2 (0x1u << 2) +#define ADC12B_IMR_EOC3 (0x1u << 3) +#define ADC12B_IMR_EOC4 (0x1u << 4) +#define ADC12B_IMR_EOC5 (0x1u << 5) +#define ADC12B_IMR_EOC6 (0x1u << 6) +#define ADC12B_IMR_EOC7 (0x1u << 7) +#define ADC12B_IMR_OVRE0 (0x1u << 8) +#define ADC12B_IMR_OVRE1 (0x1u << 9) +#define ADC12B_IMR_OVRE2 (0x1u << 10) +#define ADC12B_IMR_OVRE3 (0x1u << 11) +#define ADC12B_IMR_OVRE4 (0x1u << 12) +#define ADC12B_IMR_OVRE5 (0x1u << 13) +#define ADC12B_IMR_OVRE6 (0x1u << 14) +#define ADC12B_IMR_OVRE7 (0x1u << 15) +#define ADC12B_IMR_DRDY (0x1u << 16) +#define ADC12B_IMR_GOVRE (0x1u << 17) +#define ADC12B_IMR_ENDRX (0x1u << 18) +#define ADC12B_IMR_RXBUFF (0x1u << 19) + +#define ADC12B_CDR_DATA_Pos 0 +#define ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos) + +#define ADC12B_ACR_GAIN_Pos 0 +#define ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos) +#define ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos))) +#define ADC12B_ACR_IBCTL_Pos 8 +#define ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos) +#define ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos))) +#define ADC12B_ACR_DIFF (0x1u << 16) +#define ADC12B_ACR_OFFSET (0x1u << 17) + +#define ADC12B_EMR_OFFMODES (0x1u << 0) +#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16 +#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos) +#define ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos))) + +#define ADC12B_RPR_RXPTR_Pos 0 +#define ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos) +#define ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos))) + +#define ADC12B_RCR_RXCTR_Pos 0 +#define ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos) +#define ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos))) + +#define ADC12B_RNPR_RXNPTR_Pos 0 +#define ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos) +#define ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos))) + +#define ADC12B_RNCR_RXNCTR_Pos 0 +#define ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos) +#define ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos))) + +#define ADC12B_PTCR_RXTEN (0x1u << 0) +#define ADC12B_PTCR_RXTDIS (0x1u << 1) +#define ADC12B_PTCR_TXTEN (0x1u << 8) +#define ADC12B_PTCR_TXTDIS (0x1u << 9) + +#define ADC12B_PTSR_RXTEN (0x1u << 0) +#define ADC12B_PTSR_TXTEN (0x1u << 8) +# 244 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_chipid.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_chipid.h" +#define _SAM3U_CHIPID_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_chipid.h" +typedef struct { + RoReg CHIPID_CIDR; + RoReg CHIPID_EXID; +} Chipid; + + +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) +#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) +#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) +#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) +#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) +#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) +#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) +#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) +#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) +#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) +#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) +#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) +#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) +#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) +#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) +#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) +#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) +#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) +#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) +#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) +#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) +#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) +#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) +#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) +#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) +#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) +#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) +#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) +#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) +#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) +#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) +#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) +#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) +#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) +#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) +#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) +#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) +#define CHIPID_CIDR_EXT (0x1u << 31) + +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) +# 245 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_dmac.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_dmac.h" +#define _SAM3U_DMAC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_dmac.h" +typedef struct { + RwReg DMAC_SADDR; + RwReg DMAC_DADDR; + RwReg DMAC_DSCR; + RwReg DMAC_CTRLA; + RwReg DMAC_CTRLB; + RwReg DMAC_CFG; + RoReg Reserved1[4]; +} DmacCh_num; + +#define DMACCH_NUM_NUMBER 4 +typedef struct { + RwReg DMAC_GCFG; + RwReg DMAC_EN; + RwReg DMAC_SREQ; + RwReg DMAC_CREQ; + RwReg DMAC_LAST; + RoReg Reserved1[1]; + WoReg DMAC_EBCIER; + WoReg DMAC_EBCIDR; + RoReg DMAC_EBCIMR; + RoReg DMAC_EBCISR; + WoReg DMAC_CHER; + WoReg DMAC_CHDR; + RoReg DMAC_CHSR; + RoReg Reserved2[2]; + DmacCh_num DMAC_CH_NUM[4]; + RoReg Reserved3[66]; + RwReg DMAC_WPMR; + RoReg DMAC_WPSR; +} Dmac; + + +#define DMAC_GCFG_ARB_CFG (0x1u << 4) +#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) +#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) + +#define DMAC_EN_ENABLE (0x1u << 0) + +#define DMAC_SREQ_SSREQ0 (0x1u << 0) +#define DMAC_SREQ_DSREQ0 (0x1u << 1) +#define DMAC_SREQ_SSREQ1 (0x1u << 2) +#define DMAC_SREQ_DSREQ1 (0x1u << 3) +#define DMAC_SREQ_SSREQ2 (0x1u << 4) +#define DMAC_SREQ_DSREQ2 (0x1u << 5) +#define DMAC_SREQ_SSREQ3 (0x1u << 6) +#define DMAC_SREQ_DSREQ3 (0x1u << 7) + +#define DMAC_CREQ_SCREQ0 (0x1u << 0) +#define DMAC_CREQ_DCREQ0 (0x1u << 1) +#define DMAC_CREQ_SCREQ1 (0x1u << 2) +#define DMAC_CREQ_DCREQ1 (0x1u << 3) +#define DMAC_CREQ_SCREQ2 (0x1u << 4) +#define DMAC_CREQ_DCREQ2 (0x1u << 5) +#define DMAC_CREQ_SCREQ3 (0x1u << 6) +#define DMAC_CREQ_DCREQ3 (0x1u << 7) + +#define DMAC_LAST_SLAST0 (0x1u << 0) +#define DMAC_LAST_DLAST0 (0x1u << 1) +#define DMAC_LAST_SLAST1 (0x1u << 2) +#define DMAC_LAST_DLAST1 (0x1u << 3) +#define DMAC_LAST_SLAST2 (0x1u << 4) +#define DMAC_LAST_DLAST2 (0x1u << 5) +#define DMAC_LAST_SLAST3 (0x1u << 6) +#define DMAC_LAST_DLAST3 (0x1u << 7) + +#define DMAC_EBCIER_BTC0 (0x1u << 0) +#define DMAC_EBCIER_BTC1 (0x1u << 1) +#define DMAC_EBCIER_BTC2 (0x1u << 2) +#define DMAC_EBCIER_BTC3 (0x1u << 3) +#define DMAC_EBCIER_CBTC0 (0x1u << 8) +#define DMAC_EBCIER_CBTC1 (0x1u << 9) +#define DMAC_EBCIER_CBTC2 (0x1u << 10) +#define DMAC_EBCIER_CBTC3 (0x1u << 11) +#define DMAC_EBCIER_ERR0 (0x1u << 16) +#define DMAC_EBCIER_ERR1 (0x1u << 17) +#define DMAC_EBCIER_ERR2 (0x1u << 18) +#define DMAC_EBCIER_ERR3 (0x1u << 19) + +#define DMAC_EBCIDR_BTC0 (0x1u << 0) +#define DMAC_EBCIDR_BTC1 (0x1u << 1) +#define DMAC_EBCIDR_BTC2 (0x1u << 2) +#define DMAC_EBCIDR_BTC3 (0x1u << 3) +#define DMAC_EBCIDR_CBTC0 (0x1u << 8) +#define DMAC_EBCIDR_CBTC1 (0x1u << 9) +#define DMAC_EBCIDR_CBTC2 (0x1u << 10) +#define DMAC_EBCIDR_CBTC3 (0x1u << 11) +#define DMAC_EBCIDR_ERR0 (0x1u << 16) +#define DMAC_EBCIDR_ERR1 (0x1u << 17) +#define DMAC_EBCIDR_ERR2 (0x1u << 18) +#define DMAC_EBCIDR_ERR3 (0x1u << 19) + +#define DMAC_EBCIMR_BTC0 (0x1u << 0) +#define DMAC_EBCIMR_BTC1 (0x1u << 1) +#define DMAC_EBCIMR_BTC2 (0x1u << 2) +#define DMAC_EBCIMR_BTC3 (0x1u << 3) +#define DMAC_EBCIMR_CBTC0 (0x1u << 8) +#define DMAC_EBCIMR_CBTC1 (0x1u << 9) +#define DMAC_EBCIMR_CBTC2 (0x1u << 10) +#define DMAC_EBCIMR_CBTC3 (0x1u << 11) +#define DMAC_EBCIMR_ERR0 (0x1u << 16) +#define DMAC_EBCIMR_ERR1 (0x1u << 17) +#define DMAC_EBCIMR_ERR2 (0x1u << 18) +#define DMAC_EBCIMR_ERR3 (0x1u << 19) + +#define DMAC_EBCISR_BTC0 (0x1u << 0) +#define DMAC_EBCISR_BTC1 (0x1u << 1) +#define DMAC_EBCISR_BTC2 (0x1u << 2) +#define DMAC_EBCISR_BTC3 (0x1u << 3) +#define DMAC_EBCISR_CBTC0 (0x1u << 8) +#define DMAC_EBCISR_CBTC1 (0x1u << 9) +#define DMAC_EBCISR_CBTC2 (0x1u << 10) +#define DMAC_EBCISR_CBTC3 (0x1u << 11) +#define DMAC_EBCISR_ERR0 (0x1u << 16) +#define DMAC_EBCISR_ERR1 (0x1u << 17) +#define DMAC_EBCISR_ERR2 (0x1u << 18) +#define DMAC_EBCISR_ERR3 (0x1u << 19) + +#define DMAC_CHER_ENA0 (0x1u << 0) +#define DMAC_CHER_ENA1 (0x1u << 1) +#define DMAC_CHER_ENA2 (0x1u << 2) +#define DMAC_CHER_ENA3 (0x1u << 3) +#define DMAC_CHER_SUSP0 (0x1u << 8) +#define DMAC_CHER_SUSP1 (0x1u << 9) +#define DMAC_CHER_SUSP2 (0x1u << 10) +#define DMAC_CHER_SUSP3 (0x1u << 11) +#define DMAC_CHER_KEEP0 (0x1u << 24) +#define DMAC_CHER_KEEP1 (0x1u << 25) +#define DMAC_CHER_KEEP2 (0x1u << 26) +#define DMAC_CHER_KEEP3 (0x1u << 27) + +#define DMAC_CHDR_DIS0 (0x1u << 0) +#define DMAC_CHDR_DIS1 (0x1u << 1) +#define DMAC_CHDR_DIS2 (0x1u << 2) +#define DMAC_CHDR_DIS3 (0x1u << 3) +#define DMAC_CHDR_RES0 (0x1u << 8) +#define DMAC_CHDR_RES1 (0x1u << 9) +#define DMAC_CHDR_RES2 (0x1u << 10) +#define DMAC_CHDR_RES3 (0x1u << 11) + +#define DMAC_CHSR_ENA0 (0x1u << 0) +#define DMAC_CHSR_ENA1 (0x1u << 1) +#define DMAC_CHSR_ENA2 (0x1u << 2) +#define DMAC_CHSR_ENA3 (0x1u << 3) +#define DMAC_CHSR_SUSP0 (0x1u << 8) +#define DMAC_CHSR_SUSP1 (0x1u << 9) +#define DMAC_CHSR_SUSP2 (0x1u << 10) +#define DMAC_CHSR_SUSP3 (0x1u << 11) +#define DMAC_CHSR_EMPT0 (0x1u << 16) +#define DMAC_CHSR_EMPT1 (0x1u << 17) +#define DMAC_CHSR_EMPT2 (0x1u << 18) +#define DMAC_CHSR_EMPT3 (0x1u << 19) +#define DMAC_CHSR_STAL0 (0x1u << 24) +#define DMAC_CHSR_STAL1 (0x1u << 25) +#define DMAC_CHSR_STAL2 (0x1u << 26) +#define DMAC_CHSR_STAL3 (0x1u << 27) + +#define DMAC_SADDR_SADDR_Pos 0 +#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) +#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos))) + +#define DMAC_DADDR_DADDR_Pos 0 +#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) +#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos))) + +#define DMAC_DSCR_DSCR_Pos 2 +#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) +#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos))) + +#define DMAC_CTRLA_BTSIZE_Pos 0 +#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) +#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos))) +#define DMAC_CTRLA_SCSIZE_Pos 16 +#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) +#define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) +#define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) +#define DMAC_CTRLA_DCSIZE_Pos 20 +#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) +#define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) +#define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) +#define DMAC_CTRLA_SRC_WIDTH_Pos 24 +#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) +#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) +#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) +#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) +#define DMAC_CTRLA_DST_WIDTH_Pos 28 +#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) +#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) +#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) +#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) +#define DMAC_CTRLA_DONE (0x1u << 31) + +#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) +#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) +#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) +#define DMAC_CTRLB_DST_DSCR (0x1u << 20) +#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) +#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) +#define DMAC_CTRLB_FC_Pos 21 +#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) +#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) +#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) +#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) +#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) +#define DMAC_CTRLB_SRC_INCR_Pos 24 +#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) +#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) +#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) +#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) +#define DMAC_CTRLB_DST_INCR_Pos 28 +#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) +#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) +#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) +#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) +#define DMAC_CTRLB_IEN (0x1u << 30) + +#define DMAC_CFG_SRC_PER_Pos 0 +#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) +#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos))) +#define DMAC_CFG_DST_PER_Pos 4 +#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) +#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos))) +#define DMAC_CFG_SRC_H2SEL (0x1u << 9) +#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) +#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) +#define DMAC_CFG_DST_H2SEL (0x1u << 13) +#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) +#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) +#define DMAC_CFG_SOD (0x1u << 16) +#define DMAC_CFG_SOD_DISABLE (0x0u << 16) +#define DMAC_CFG_SOD_ENABLE (0x1u << 16) +#define DMAC_CFG_LOCK_IF (0x1u << 20) +#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) +#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) +#define DMAC_CFG_LOCK_B (0x1u << 21) +#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) +#define DMAC_CFG_LOCK_IF_L (0x1u << 22) +#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) +#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) +#define DMAC_CFG_AHB_PROT_Pos 24 +#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) +#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos))) +#define DMAC_CFG_FIFOCFG_Pos 28 +#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) +#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) +#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) +#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) + +#define DMAC_WPMR_WPEN (0x1u << 0) +#define DMAC_WPMR_WPKEY_Pos 8 +#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) +#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos))) + +#define DMAC_WPSR_WPVS (0x1u << 0) +#define DMAC_WPSR_WPVSRC_Pos 8 +#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) +# 246 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_efc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_efc.h" +#define _SAM3U_EFC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_efc.h" +typedef struct { + RwReg EEFC_FMR; + WoReg EEFC_FCR; + RoReg EEFC_FSR; + RoReg EEFC_FRR; +} Efc; + + +#define EEFC_FMR_FRDY (0x1u << 0) +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) +#define EEFC_FMR_FAM (0x1u << 24) + +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) + +#define EEFC_FSR_FRDY (0x1u << 0) +#define EEFC_FSR_FCMDE (0x1u << 1) +#define EEFC_FSR_FLOCKE (0x1u << 2) + +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) +# 247 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_gpbr.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_gpbr.h" +#define _SAM3U_GPBR_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_gpbr.h" +typedef struct { + RwReg SYS_GPBR[4]; +} Gpbr; + + +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) +# 248 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_hsmci.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_hsmci.h" +#define _SAM3U_HSMCI_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_hsmci.h" +typedef struct { + WoReg HSMCI_CR; + RwReg HSMCI_MR; + RwReg HSMCI_DTOR; + RwReg HSMCI_SDCR; + RwReg HSMCI_ARGR; + WoReg HSMCI_CMDR; + RwReg HSMCI_BLKR; + RwReg HSMCI_CSTOR; + RoReg HSMCI_RSPR[4]; + RoReg HSMCI_RDR; + WoReg HSMCI_TDR; + RoReg Reserved1[2]; + RoReg HSMCI_SR; + WoReg HSMCI_IER; + WoReg HSMCI_IDR; + RoReg HSMCI_IMR; + RwReg HSMCI_DMA; + RwReg HSMCI_CFG; + RoReg Reserved2[35]; + RwReg HSMCI_WPMR; + RoReg HSMCI_WPSR; + RoReg Reserved3[69]; + RwReg HSMCI_FIFO[256]; +} Hsmci; + + +#define HSMCI_CR_MCIEN (0x1u << 0) +#define HSMCI_CR_MCIDIS (0x1u << 1) +#define HSMCI_CR_PWSEN (0x1u << 2) +#define HSMCI_CR_PWSDIS (0x1u << 3) +#define HSMCI_CR_SWRST (0x1u << 7) + +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) +#define HSMCI_MR_WRPROOF (0x1u << 12) +#define HSMCI_MR_FBYTE (0x1u << 13) +#define HSMCI_MR_PADV (0x1u << 14) + +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) + +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) +#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) +#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) +#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) + +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) + +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) +#define HSMCI_CMDR_OPDCMD (0x1u << 11) +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) +#define HSMCI_CMDR_MAXLAT (0x1u << 12) +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) +#define HSMCI_CMDR_TRDIR (0x1u << 18) +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) +#define HSMCI_CMDR_ATACS (0x1u << 26) +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) + +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) +#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) +#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) +#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) + +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) + +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) + +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) + +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) + +#define HSMCI_SR_CMDRDY (0x1u << 0) +#define HSMCI_SR_RXRDY (0x1u << 1) +#define HSMCI_SR_TXRDY (0x1u << 2) +#define HSMCI_SR_BLKE (0x1u << 3) +#define HSMCI_SR_DTIP (0x1u << 4) +#define HSMCI_SR_NOTBUSY (0x1u << 5) +#define HSMCI_SR_MCI_SDIOIRQA (0x1u << 8) +#define HSMCI_SR_SDIOWAIT (0x1u << 12) +#define HSMCI_SR_CSRCV (0x1u << 13) +#define HSMCI_SR_RINDE (0x1u << 16) +#define HSMCI_SR_RDIRE (0x1u << 17) +#define HSMCI_SR_RCRCE (0x1u << 18) +#define HSMCI_SR_RENDE (0x1u << 19) +#define HSMCI_SR_RTOE (0x1u << 20) +#define HSMCI_SR_DCRCE (0x1u << 21) +#define HSMCI_SR_DTOE (0x1u << 22) +#define HSMCI_SR_CSTOE (0x1u << 23) +#define HSMCI_SR_BLKOVRE (0x1u << 24) +#define HSMCI_SR_DMADONE (0x1u << 25) +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) +#define HSMCI_SR_XFRDONE (0x1u << 27) +#define HSMCI_SR_ACKRCV (0x1u << 28) +#define HSMCI_SR_ACKRCVE (0x1u << 29) +#define HSMCI_SR_OVRE (0x1u << 30) +#define HSMCI_SR_UNRE (0x1u << 31) + +#define HSMCI_IER_CMDRDY (0x1u << 0) +#define HSMCI_IER_RXRDY (0x1u << 1) +#define HSMCI_IER_TXRDY (0x1u << 2) +#define HSMCI_IER_BLKE (0x1u << 3) +#define HSMCI_IER_DTIP (0x1u << 4) +#define HSMCI_IER_NOTBUSY (0x1u << 5) +#define HSMCI_IER_MCI_SDIOIRQA (0x1u << 8) +#define HSMCI_IER_SDIOWAIT (0x1u << 12) +#define HSMCI_IER_CSRCV (0x1u << 13) +#define HSMCI_IER_RINDE (0x1u << 16) +#define HSMCI_IER_RDIRE (0x1u << 17) +#define HSMCI_IER_RCRCE (0x1u << 18) +#define HSMCI_IER_RENDE (0x1u << 19) +#define HSMCI_IER_RTOE (0x1u << 20) +#define HSMCI_IER_DCRCE (0x1u << 21) +#define HSMCI_IER_DTOE (0x1u << 22) +#define HSMCI_IER_CSTOE (0x1u << 23) +#define HSMCI_IER_BLKOVRE (0x1u << 24) +#define HSMCI_IER_DMADONE (0x1u << 25) +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) +#define HSMCI_IER_XFRDONE (0x1u << 27) +#define HSMCI_IER_ACKRCV (0x1u << 28) +#define HSMCI_IER_ACKRCVE (0x1u << 29) +#define HSMCI_IER_OVRE (0x1u << 30) +#define HSMCI_IER_UNRE (0x1u << 31) + +#define HSMCI_IDR_CMDRDY (0x1u << 0) +#define HSMCI_IDR_RXRDY (0x1u << 1) +#define HSMCI_IDR_TXRDY (0x1u << 2) +#define HSMCI_IDR_BLKE (0x1u << 3) +#define HSMCI_IDR_DTIP (0x1u << 4) +#define HSMCI_IDR_NOTBUSY (0x1u << 5) +#define HSMCI_IDR_MCI_SDIOIRQA (0x1u << 8) +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) +#define HSMCI_IDR_CSRCV (0x1u << 13) +#define HSMCI_IDR_RINDE (0x1u << 16) +#define HSMCI_IDR_RDIRE (0x1u << 17) +#define HSMCI_IDR_RCRCE (0x1u << 18) +#define HSMCI_IDR_RENDE (0x1u << 19) +#define HSMCI_IDR_RTOE (0x1u << 20) +#define HSMCI_IDR_DCRCE (0x1u << 21) +#define HSMCI_IDR_DTOE (0x1u << 22) +#define HSMCI_IDR_CSTOE (0x1u << 23) +#define HSMCI_IDR_BLKOVRE (0x1u << 24) +#define HSMCI_IDR_DMADONE (0x1u << 25) +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) +#define HSMCI_IDR_XFRDONE (0x1u << 27) +#define HSMCI_IDR_ACKRCV (0x1u << 28) +#define HSMCI_IDR_ACKRCVE (0x1u << 29) +#define HSMCI_IDR_OVRE (0x1u << 30) +#define HSMCI_IDR_UNRE (0x1u << 31) + +#define HSMCI_IMR_CMDRDY (0x1u << 0) +#define HSMCI_IMR_RXRDY (0x1u << 1) +#define HSMCI_IMR_TXRDY (0x1u << 2) +#define HSMCI_IMR_BLKE (0x1u << 3) +#define HSMCI_IMR_DTIP (0x1u << 4) +#define HSMCI_IMR_NOTBUSY (0x1u << 5) +#define HSMCI_IMR_MCI_SDIOIRQA (0x1u << 8) +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) +#define HSMCI_IMR_CSRCV (0x1u << 13) +#define HSMCI_IMR_RINDE (0x1u << 16) +#define HSMCI_IMR_RDIRE (0x1u << 17) +#define HSMCI_IMR_RCRCE (0x1u << 18) +#define HSMCI_IMR_RENDE (0x1u << 19) +#define HSMCI_IMR_RTOE (0x1u << 20) +#define HSMCI_IMR_DCRCE (0x1u << 21) +#define HSMCI_IMR_DTOE (0x1u << 22) +#define HSMCI_IMR_CSTOE (0x1u << 23) +#define HSMCI_IMR_BLKOVRE (0x1u << 24) +#define HSMCI_IMR_DMADONE (0x1u << 25) +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) +#define HSMCI_IMR_XFRDONE (0x1u << 27) +#define HSMCI_IMR_ACKRCV (0x1u << 28) +#define HSMCI_IMR_ACKRCVE (0x1u << 29) +#define HSMCI_IMR_OVRE (0x1u << 30) +#define HSMCI_IMR_UNRE (0x1u << 31) + +#define HSMCI_DMA_OFFSET_Pos 0 +#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) +#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos))) +#define HSMCI_DMA_CHKSIZE (0x1u << 4) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) +#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) +#define HSMCI_DMA_DMAEN (0x1u << 8) +#define HSMCI_DMA_ROPT (0x1u << 12) + +#define HSMCI_CFG_FIFOMODE (0x1u << 0) +#define HSMCI_CFG_FERRCTRL (0x1u << 4) +#define HSMCI_CFG_HSMODE (0x1u << 8) +#define HSMCI_CFG_LSYNC (0x1u << 12) + +#define HSMCI_WPMR_WP_EN (0x1u << 0) +#define HSMCI_WPMR_WP_KEY_Pos 8 +#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) +#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) + +#define HSMCI_WPSR_WP_VS_Pos 0 +#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) +#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) +#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) +#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) +#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) +#define HSMCI_WPSR_WP_VSRC_Pos 8 +#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) + +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) +# 249 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_matrix.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_matrix.h" +#define _SAM3U_MATRIX_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_matrix.h" +typedef struct { + RwReg MATRIX_MCFG[5]; + RoReg Reserved1[11]; + RwReg MATRIX_SCFG[10]; + RoReg Reserved2[6]; + RwReg MATRIX_PRAS0; + RoReg Reserved3[1]; + RwReg MATRIX_PRAS1; + RoReg Reserved4[1]; + RwReg MATRIX_PRAS2; + RoReg Reserved5[1]; + RwReg MATRIX_PRAS3; + RoReg Reserved6[1]; + RwReg MATRIX_PRAS4; + RoReg Reserved7[1]; + RwReg MATRIX_PRAS5; + RoReg Reserved8[1]; + RwReg MATRIX_PRAS6; + RoReg Reserved9[1]; + RwReg MATRIX_PRAS7; + RoReg Reserved10[1]; + RwReg MATRIX_PRAS8; + RoReg Reserved11[1]; + RwReg MATRIX_PRAS9; + RoReg Reserved12[1]; + RoReg Reserved13[12]; + RwReg MATRIX_MRCR; + RoReg Reserved14[56]; + RwReg MATRIX_WPMR; + RoReg MATRIX_WPSR; +} Matrix; + + +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) + +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +#define MATRIX_SCFG_ARBT_Pos 24 +#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) +#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) + +#define MATRIX_PRAS0_M0PR_Pos 0 +#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) +#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) +#define MATRIX_PRAS0_M1PR_Pos 4 +#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) +#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) +#define MATRIX_PRAS0_M2PR_Pos 8 +#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) +#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) +#define MATRIX_PRAS0_M3PR_Pos 12 +#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) +#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) +#define MATRIX_PRAS0_M4PR_Pos 16 +#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) +#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) + +#define MATRIX_PRAS1_M0PR_Pos 0 +#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) +#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) +#define MATRIX_PRAS1_M1PR_Pos 4 +#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) +#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) +#define MATRIX_PRAS1_M2PR_Pos 8 +#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) +#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) +#define MATRIX_PRAS1_M3PR_Pos 12 +#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) +#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) +#define MATRIX_PRAS1_M4PR_Pos 16 +#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) +#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) + +#define MATRIX_PRAS2_M0PR_Pos 0 +#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) +#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) +#define MATRIX_PRAS2_M1PR_Pos 4 +#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) +#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) +#define MATRIX_PRAS2_M2PR_Pos 8 +#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) +#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) +#define MATRIX_PRAS2_M3PR_Pos 12 +#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) +#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) +#define MATRIX_PRAS2_M4PR_Pos 16 +#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) +#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) + +#define MATRIX_PRAS3_M0PR_Pos 0 +#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) +#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) +#define MATRIX_PRAS3_M1PR_Pos 4 +#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) +#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) +#define MATRIX_PRAS3_M2PR_Pos 8 +#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) +#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) +#define MATRIX_PRAS3_M3PR_Pos 12 +#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) +#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) +#define MATRIX_PRAS3_M4PR_Pos 16 +#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) +#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) + +#define MATRIX_PRAS4_M0PR_Pos 0 +#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) +#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) +#define MATRIX_PRAS4_M1PR_Pos 4 +#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) +#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) +#define MATRIX_PRAS4_M2PR_Pos 8 +#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) +#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) +#define MATRIX_PRAS4_M3PR_Pos 12 +#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) +#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) +#define MATRIX_PRAS4_M4PR_Pos 16 +#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) +#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) + +#define MATRIX_PRAS5_M0PR_Pos 0 +#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) +#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos))) +#define MATRIX_PRAS5_M1PR_Pos 4 +#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) +#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos))) +#define MATRIX_PRAS5_M2PR_Pos 8 +#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) +#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos))) +#define MATRIX_PRAS5_M3PR_Pos 12 +#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) +#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos))) +#define MATRIX_PRAS5_M4PR_Pos 16 +#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) +#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos))) + +#define MATRIX_PRAS6_M0PR_Pos 0 +#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) +#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos))) +#define MATRIX_PRAS6_M1PR_Pos 4 +#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) +#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos))) +#define MATRIX_PRAS6_M2PR_Pos 8 +#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) +#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos))) +#define MATRIX_PRAS6_M3PR_Pos 12 +#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) +#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos))) +#define MATRIX_PRAS6_M4PR_Pos 16 +#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) +#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos))) + +#define MATRIX_PRAS7_M0PR_Pos 0 +#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) +#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos))) +#define MATRIX_PRAS7_M1PR_Pos 4 +#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) +#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos))) +#define MATRIX_PRAS7_M2PR_Pos 8 +#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) +#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos))) +#define MATRIX_PRAS7_M3PR_Pos 12 +#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) +#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos))) +#define MATRIX_PRAS7_M4PR_Pos 16 +#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) +#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos))) + +#define MATRIX_PRAS8_M0PR_Pos 0 +#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) +#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos))) +#define MATRIX_PRAS8_M1PR_Pos 4 +#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) +#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos))) +#define MATRIX_PRAS8_M2PR_Pos 8 +#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) +#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos))) +#define MATRIX_PRAS8_M3PR_Pos 12 +#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) +#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos))) +#define MATRIX_PRAS8_M4PR_Pos 16 +#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) +#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos))) + +#define MATRIX_PRAS9_M0PR_Pos 0 +#define MATRIX_PRAS9_M0PR_Msk (0x3u << MATRIX_PRAS9_M0PR_Pos) +#define MATRIX_PRAS9_M0PR(value) ((MATRIX_PRAS9_M0PR_Msk & ((value) << MATRIX_PRAS9_M0PR_Pos))) +#define MATRIX_PRAS9_M1PR_Pos 4 +#define MATRIX_PRAS9_M1PR_Msk (0x3u << MATRIX_PRAS9_M1PR_Pos) +#define MATRIX_PRAS9_M1PR(value) ((MATRIX_PRAS9_M1PR_Msk & ((value) << MATRIX_PRAS9_M1PR_Pos))) +#define MATRIX_PRAS9_M2PR_Pos 8 +#define MATRIX_PRAS9_M2PR_Msk (0x3u << MATRIX_PRAS9_M2PR_Pos) +#define MATRIX_PRAS9_M2PR(value) ((MATRIX_PRAS9_M2PR_Msk & ((value) << MATRIX_PRAS9_M2PR_Pos))) +#define MATRIX_PRAS9_M3PR_Pos 12 +#define MATRIX_PRAS9_M3PR_Msk (0x3u << MATRIX_PRAS9_M3PR_Pos) +#define MATRIX_PRAS9_M3PR(value) ((MATRIX_PRAS9_M3PR_Msk & ((value) << MATRIX_PRAS9_M3PR_Pos))) +#define MATRIX_PRAS9_M4PR_Pos 16 +#define MATRIX_PRAS9_M4PR_Msk (0x3u << MATRIX_PRAS9_M4PR_Pos) +#define MATRIX_PRAS9_M4PR(value) ((MATRIX_PRAS9_M4PR_Msk & ((value) << MATRIX_PRAS9_M4PR_Pos))) + +#define MATRIX_MRCR_RCB0 (0x1u << 0) +#define MATRIX_MRCR_RCB1 (0x1u << 1) +#define MATRIX_MRCR_RCB2 (0x1u << 2) +#define MATRIX_MRCR_RCB3 (0x1u << 3) +#define MATRIX_MRCR_RCB4 (0x1u << 4) + +#define MATRIX_WPMR_WPEN (0x1u << 0) +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) + +#define MATRIX_WPSR_WPVS (0x1u << 0) +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) +# 250 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_pdc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_pdc.h" +#define _SAM3U_PDC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_pdc.h" +typedef struct { + RwReg PERIPH_RPR; + RwReg PERIPH_RCR; + RwReg PERIPH_TPR; + RwReg PERIPH_TCR; + RwReg PERIPH_RNPR; + RwReg PERIPH_RNCR; + RwReg PERIPH_TNPR; + RwReg PERIPH_TNCR; + WoReg PERIPH_PTCR; + RoReg PERIPH_PTSR; +} Pdc; + + +#define PERIPH_RPR_RXPTR_Pos 0 +#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) +#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) + +#define PERIPH_RCR_RXCTR_Pos 0 +#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) +#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) + +#define PERIPH_TPR_TXPTR_Pos 0 +#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) +#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) + +#define PERIPH_TCR_TXCTR_Pos 0 +#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) +#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) + +#define PERIPH_RNPR_RXNPTR_Pos 0 +#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) +#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) + +#define PERIPH_RNCR_RXNCTR_Pos 0 +#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) +#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) + +#define PERIPH_TNPR_TXNPTR_Pos 0 +#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) +#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) + +#define PERIPH_TNCR_TXNCTR_Pos 0 +#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) +#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) + +#define PERIPH_PTCR_RXTEN (0x1u << 0) +#define PERIPH_PTCR_RXTDIS (0x1u << 1) +#define PERIPH_PTCR_TXTEN (0x1u << 8) +#define PERIPH_PTCR_TXTDIS (0x1u << 9) + +#define PERIPH_PTSR_RXTEN (0x1u << 0) +#define PERIPH_PTSR_TXTEN (0x1u << 8) +# 251 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_pio.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_pio.h" +#define _SAM3U_PIO_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_pio.h" +typedef struct { + WoReg PIO_PER; + WoReg PIO_PDR; + RoReg PIO_PSR; + RoReg Reserved1[1]; + WoReg PIO_OER; + WoReg PIO_ODR; + RoReg PIO_OSR; + RoReg Reserved2[1]; + WoReg PIO_IFER; + WoReg PIO_IFDR; + RoReg PIO_IFSR; + RoReg Reserved3[1]; + WoReg PIO_SODR; + WoReg PIO_CODR; + RwReg PIO_ODSR; + RoReg PIO_PDSR; + WoReg PIO_IER; + WoReg PIO_IDR; + RoReg PIO_IMR; + RoReg PIO_ISR; + WoReg PIO_MDER; + WoReg PIO_MDDR; + RoReg PIO_MDSR; + RoReg Reserved4[1]; + WoReg PIO_PUDR; + WoReg PIO_PUER; + RoReg PIO_PUSR; + RoReg Reserved5[1]; + RwReg PIO_ABSR; + RoReg Reserved6[3]; + WoReg PIO_SCIFSR; + WoReg PIO_DIFSR; + RoReg PIO_IFDGSR; + RwReg PIO_SCDR; + RoReg Reserved7[4]; + WoReg PIO_OWER; + WoReg PIO_OWDR; + RoReg PIO_OWSR; + RoReg Reserved8[1]; + WoReg PIO_AIMER; + WoReg PIO_AIMDR; + RoReg PIO_AIMMR; + RoReg Reserved9[1]; + WoReg PIO_ESR; + WoReg PIO_LSR; + RoReg PIO_ELSR; + RoReg Reserved10[1]; + WoReg PIO_FELLSR; + WoReg PIO_REHLSR; + RoReg PIO_FRLHSR; + RoReg Reserved11[1]; + RoReg PIO_LOCKSR; + RwReg PIO_WPMR; + RoReg PIO_WPSR; +} Pio; + + +#define PIO_PER_P0 (0x1u << 0) +#define PIO_PER_P1 (0x1u << 1) +#define PIO_PER_P2 (0x1u << 2) +#define PIO_PER_P3 (0x1u << 3) +#define PIO_PER_P4 (0x1u << 4) +#define PIO_PER_P5 (0x1u << 5) +#define PIO_PER_P6 (0x1u << 6) +#define PIO_PER_P7 (0x1u << 7) +#define PIO_PER_P8 (0x1u << 8) +#define PIO_PER_P9 (0x1u << 9) +#define PIO_PER_P10 (0x1u << 10) +#define PIO_PER_P11 (0x1u << 11) +#define PIO_PER_P12 (0x1u << 12) +#define PIO_PER_P13 (0x1u << 13) +#define PIO_PER_P14 (0x1u << 14) +#define PIO_PER_P15 (0x1u << 15) +#define PIO_PER_P16 (0x1u << 16) +#define PIO_PER_P17 (0x1u << 17) +#define PIO_PER_P18 (0x1u << 18) +#define PIO_PER_P19 (0x1u << 19) +#define PIO_PER_P20 (0x1u << 20) +#define PIO_PER_P21 (0x1u << 21) +#define PIO_PER_P22 (0x1u << 22) +#define PIO_PER_P23 (0x1u << 23) +#define PIO_PER_P24 (0x1u << 24) +#define PIO_PER_P25 (0x1u << 25) +#define PIO_PER_P26 (0x1u << 26) +#define PIO_PER_P27 (0x1u << 27) +#define PIO_PER_P28 (0x1u << 28) +#define PIO_PER_P29 (0x1u << 29) +#define PIO_PER_P30 (0x1u << 30) +#define PIO_PER_P31 (0x1u << 31) + +#define PIO_PDR_P0 (0x1u << 0) +#define PIO_PDR_P1 (0x1u << 1) +#define PIO_PDR_P2 (0x1u << 2) +#define PIO_PDR_P3 (0x1u << 3) +#define PIO_PDR_P4 (0x1u << 4) +#define PIO_PDR_P5 (0x1u << 5) +#define PIO_PDR_P6 (0x1u << 6) +#define PIO_PDR_P7 (0x1u << 7) +#define PIO_PDR_P8 (0x1u << 8) +#define PIO_PDR_P9 (0x1u << 9) +#define PIO_PDR_P10 (0x1u << 10) +#define PIO_PDR_P11 (0x1u << 11) +#define PIO_PDR_P12 (0x1u << 12) +#define PIO_PDR_P13 (0x1u << 13) +#define PIO_PDR_P14 (0x1u << 14) +#define PIO_PDR_P15 (0x1u << 15) +#define PIO_PDR_P16 (0x1u << 16) +#define PIO_PDR_P17 (0x1u << 17) +#define PIO_PDR_P18 (0x1u << 18) +#define PIO_PDR_P19 (0x1u << 19) +#define PIO_PDR_P20 (0x1u << 20) +#define PIO_PDR_P21 (0x1u << 21) +#define PIO_PDR_P22 (0x1u << 22) +#define PIO_PDR_P23 (0x1u << 23) +#define PIO_PDR_P24 (0x1u << 24) +#define PIO_PDR_P25 (0x1u << 25) +#define PIO_PDR_P26 (0x1u << 26) +#define PIO_PDR_P27 (0x1u << 27) +#define PIO_PDR_P28 (0x1u << 28) +#define PIO_PDR_P29 (0x1u << 29) +#define PIO_PDR_P30 (0x1u << 30) +#define PIO_PDR_P31 (0x1u << 31) + +#define PIO_PSR_P0 (0x1u << 0) +#define PIO_PSR_P1 (0x1u << 1) +#define PIO_PSR_P2 (0x1u << 2) +#define PIO_PSR_P3 (0x1u << 3) +#define PIO_PSR_P4 (0x1u << 4) +#define PIO_PSR_P5 (0x1u << 5) +#define PIO_PSR_P6 (0x1u << 6) +#define PIO_PSR_P7 (0x1u << 7) +#define PIO_PSR_P8 (0x1u << 8) +#define PIO_PSR_P9 (0x1u << 9) +#define PIO_PSR_P10 (0x1u << 10) +#define PIO_PSR_P11 (0x1u << 11) +#define PIO_PSR_P12 (0x1u << 12) +#define PIO_PSR_P13 (0x1u << 13) +#define PIO_PSR_P14 (0x1u << 14) +#define PIO_PSR_P15 (0x1u << 15) +#define PIO_PSR_P16 (0x1u << 16) +#define PIO_PSR_P17 (0x1u << 17) +#define PIO_PSR_P18 (0x1u << 18) +#define PIO_PSR_P19 (0x1u << 19) +#define PIO_PSR_P20 (0x1u << 20) +#define PIO_PSR_P21 (0x1u << 21) +#define PIO_PSR_P22 (0x1u << 22) +#define PIO_PSR_P23 (0x1u << 23) +#define PIO_PSR_P24 (0x1u << 24) +#define PIO_PSR_P25 (0x1u << 25) +#define PIO_PSR_P26 (0x1u << 26) +#define PIO_PSR_P27 (0x1u << 27) +#define PIO_PSR_P28 (0x1u << 28) +#define PIO_PSR_P29 (0x1u << 29) +#define PIO_PSR_P30 (0x1u << 30) +#define PIO_PSR_P31 (0x1u << 31) + +#define PIO_OER_P0 (0x1u << 0) +#define PIO_OER_P1 (0x1u << 1) +#define PIO_OER_P2 (0x1u << 2) +#define PIO_OER_P3 (0x1u << 3) +#define PIO_OER_P4 (0x1u << 4) +#define PIO_OER_P5 (0x1u << 5) +#define PIO_OER_P6 (0x1u << 6) +#define PIO_OER_P7 (0x1u << 7) +#define PIO_OER_P8 (0x1u << 8) +#define PIO_OER_P9 (0x1u << 9) +#define PIO_OER_P10 (0x1u << 10) +#define PIO_OER_P11 (0x1u << 11) +#define PIO_OER_P12 (0x1u << 12) +#define PIO_OER_P13 (0x1u << 13) +#define PIO_OER_P14 (0x1u << 14) +#define PIO_OER_P15 (0x1u << 15) +#define PIO_OER_P16 (0x1u << 16) +#define PIO_OER_P17 (0x1u << 17) +#define PIO_OER_P18 (0x1u << 18) +#define PIO_OER_P19 (0x1u << 19) +#define PIO_OER_P20 (0x1u << 20) +#define PIO_OER_P21 (0x1u << 21) +#define PIO_OER_P22 (0x1u << 22) +#define PIO_OER_P23 (0x1u << 23) +#define PIO_OER_P24 (0x1u << 24) +#define PIO_OER_P25 (0x1u << 25) +#define PIO_OER_P26 (0x1u << 26) +#define PIO_OER_P27 (0x1u << 27) +#define PIO_OER_P28 (0x1u << 28) +#define PIO_OER_P29 (0x1u << 29) +#define PIO_OER_P30 (0x1u << 30) +#define PIO_OER_P31 (0x1u << 31) + +#define PIO_ODR_P0 (0x1u << 0) +#define PIO_ODR_P1 (0x1u << 1) +#define PIO_ODR_P2 (0x1u << 2) +#define PIO_ODR_P3 (0x1u << 3) +#define PIO_ODR_P4 (0x1u << 4) +#define PIO_ODR_P5 (0x1u << 5) +#define PIO_ODR_P6 (0x1u << 6) +#define PIO_ODR_P7 (0x1u << 7) +#define PIO_ODR_P8 (0x1u << 8) +#define PIO_ODR_P9 (0x1u << 9) +#define PIO_ODR_P10 (0x1u << 10) +#define PIO_ODR_P11 (0x1u << 11) +#define PIO_ODR_P12 (0x1u << 12) +#define PIO_ODR_P13 (0x1u << 13) +#define PIO_ODR_P14 (0x1u << 14) +#define PIO_ODR_P15 (0x1u << 15) +#define PIO_ODR_P16 (0x1u << 16) +#define PIO_ODR_P17 (0x1u << 17) +#define PIO_ODR_P18 (0x1u << 18) +#define PIO_ODR_P19 (0x1u << 19) +#define PIO_ODR_P20 (0x1u << 20) +#define PIO_ODR_P21 (0x1u << 21) +#define PIO_ODR_P22 (0x1u << 22) +#define PIO_ODR_P23 (0x1u << 23) +#define PIO_ODR_P24 (0x1u << 24) +#define PIO_ODR_P25 (0x1u << 25) +#define PIO_ODR_P26 (0x1u << 26) +#define PIO_ODR_P27 (0x1u << 27) +#define PIO_ODR_P28 (0x1u << 28) +#define PIO_ODR_P29 (0x1u << 29) +#define PIO_ODR_P30 (0x1u << 30) +#define PIO_ODR_P31 (0x1u << 31) + +#define PIO_OSR_P0 (0x1u << 0) +#define PIO_OSR_P1 (0x1u << 1) +#define PIO_OSR_P2 (0x1u << 2) +#define PIO_OSR_P3 (0x1u << 3) +#define PIO_OSR_P4 (0x1u << 4) +#define PIO_OSR_P5 (0x1u << 5) +#define PIO_OSR_P6 (0x1u << 6) +#define PIO_OSR_P7 (0x1u << 7) +#define PIO_OSR_P8 (0x1u << 8) +#define PIO_OSR_P9 (0x1u << 9) +#define PIO_OSR_P10 (0x1u << 10) +#define PIO_OSR_P11 (0x1u << 11) +#define PIO_OSR_P12 (0x1u << 12) +#define PIO_OSR_P13 (0x1u << 13) +#define PIO_OSR_P14 (0x1u << 14) +#define PIO_OSR_P15 (0x1u << 15) +#define PIO_OSR_P16 (0x1u << 16) +#define PIO_OSR_P17 (0x1u << 17) +#define PIO_OSR_P18 (0x1u << 18) +#define PIO_OSR_P19 (0x1u << 19) +#define PIO_OSR_P20 (0x1u << 20) +#define PIO_OSR_P21 (0x1u << 21) +#define PIO_OSR_P22 (0x1u << 22) +#define PIO_OSR_P23 (0x1u << 23) +#define PIO_OSR_P24 (0x1u << 24) +#define PIO_OSR_P25 (0x1u << 25) +#define PIO_OSR_P26 (0x1u << 26) +#define PIO_OSR_P27 (0x1u << 27) +#define PIO_OSR_P28 (0x1u << 28) +#define PIO_OSR_P29 (0x1u << 29) +#define PIO_OSR_P30 (0x1u << 30) +#define PIO_OSR_P31 (0x1u << 31) + +#define PIO_IFER_P0 (0x1u << 0) +#define PIO_IFER_P1 (0x1u << 1) +#define PIO_IFER_P2 (0x1u << 2) +#define PIO_IFER_P3 (0x1u << 3) +#define PIO_IFER_P4 (0x1u << 4) +#define PIO_IFER_P5 (0x1u << 5) +#define PIO_IFER_P6 (0x1u << 6) +#define PIO_IFER_P7 (0x1u << 7) +#define PIO_IFER_P8 (0x1u << 8) +#define PIO_IFER_P9 (0x1u << 9) +#define PIO_IFER_P10 (0x1u << 10) +#define PIO_IFER_P11 (0x1u << 11) +#define PIO_IFER_P12 (0x1u << 12) +#define PIO_IFER_P13 (0x1u << 13) +#define PIO_IFER_P14 (0x1u << 14) +#define PIO_IFER_P15 (0x1u << 15) +#define PIO_IFER_P16 (0x1u << 16) +#define PIO_IFER_P17 (0x1u << 17) +#define PIO_IFER_P18 (0x1u << 18) +#define PIO_IFER_P19 (0x1u << 19) +#define PIO_IFER_P20 (0x1u << 20) +#define PIO_IFER_P21 (0x1u << 21) +#define PIO_IFER_P22 (0x1u << 22) +#define PIO_IFER_P23 (0x1u << 23) +#define PIO_IFER_P24 (0x1u << 24) +#define PIO_IFER_P25 (0x1u << 25) +#define PIO_IFER_P26 (0x1u << 26) +#define PIO_IFER_P27 (0x1u << 27) +#define PIO_IFER_P28 (0x1u << 28) +#define PIO_IFER_P29 (0x1u << 29) +#define PIO_IFER_P30 (0x1u << 30) +#define PIO_IFER_P31 (0x1u << 31) + +#define PIO_IFDR_P0 (0x1u << 0) +#define PIO_IFDR_P1 (0x1u << 1) +#define PIO_IFDR_P2 (0x1u << 2) +#define PIO_IFDR_P3 (0x1u << 3) +#define PIO_IFDR_P4 (0x1u << 4) +#define PIO_IFDR_P5 (0x1u << 5) +#define PIO_IFDR_P6 (0x1u << 6) +#define PIO_IFDR_P7 (0x1u << 7) +#define PIO_IFDR_P8 (0x1u << 8) +#define PIO_IFDR_P9 (0x1u << 9) +#define PIO_IFDR_P10 (0x1u << 10) +#define PIO_IFDR_P11 (0x1u << 11) +#define PIO_IFDR_P12 (0x1u << 12) +#define PIO_IFDR_P13 (0x1u << 13) +#define PIO_IFDR_P14 (0x1u << 14) +#define PIO_IFDR_P15 (0x1u << 15) +#define PIO_IFDR_P16 (0x1u << 16) +#define PIO_IFDR_P17 (0x1u << 17) +#define PIO_IFDR_P18 (0x1u << 18) +#define PIO_IFDR_P19 (0x1u << 19) +#define PIO_IFDR_P20 (0x1u << 20) +#define PIO_IFDR_P21 (0x1u << 21) +#define PIO_IFDR_P22 (0x1u << 22) +#define PIO_IFDR_P23 (0x1u << 23) +#define PIO_IFDR_P24 (0x1u << 24) +#define PIO_IFDR_P25 (0x1u << 25) +#define PIO_IFDR_P26 (0x1u << 26) +#define PIO_IFDR_P27 (0x1u << 27) +#define PIO_IFDR_P28 (0x1u << 28) +#define PIO_IFDR_P29 (0x1u << 29) +#define PIO_IFDR_P30 (0x1u << 30) +#define PIO_IFDR_P31 (0x1u << 31) + +#define PIO_IFSR_P0 (0x1u << 0) +#define PIO_IFSR_P1 (0x1u << 1) +#define PIO_IFSR_P2 (0x1u << 2) +#define PIO_IFSR_P3 (0x1u << 3) +#define PIO_IFSR_P4 (0x1u << 4) +#define PIO_IFSR_P5 (0x1u << 5) +#define PIO_IFSR_P6 (0x1u << 6) +#define PIO_IFSR_P7 (0x1u << 7) +#define PIO_IFSR_P8 (0x1u << 8) +#define PIO_IFSR_P9 (0x1u << 9) +#define PIO_IFSR_P10 (0x1u << 10) +#define PIO_IFSR_P11 (0x1u << 11) +#define PIO_IFSR_P12 (0x1u << 12) +#define PIO_IFSR_P13 (0x1u << 13) +#define PIO_IFSR_P14 (0x1u << 14) +#define PIO_IFSR_P15 (0x1u << 15) +#define PIO_IFSR_P16 (0x1u << 16) +#define PIO_IFSR_P17 (0x1u << 17) +#define PIO_IFSR_P18 (0x1u << 18) +#define PIO_IFSR_P19 (0x1u << 19) +#define PIO_IFSR_P20 (0x1u << 20) +#define PIO_IFSR_P21 (0x1u << 21) +#define PIO_IFSR_P22 (0x1u << 22) +#define PIO_IFSR_P23 (0x1u << 23) +#define PIO_IFSR_P24 (0x1u << 24) +#define PIO_IFSR_P25 (0x1u << 25) +#define PIO_IFSR_P26 (0x1u << 26) +#define PIO_IFSR_P27 (0x1u << 27) +#define PIO_IFSR_P28 (0x1u << 28) +#define PIO_IFSR_P29 (0x1u << 29) +#define PIO_IFSR_P30 (0x1u << 30) +#define PIO_IFSR_P31 (0x1u << 31) + +#define PIO_SODR_P0 (0x1u << 0) +#define PIO_SODR_P1 (0x1u << 1) +#define PIO_SODR_P2 (0x1u << 2) +#define PIO_SODR_P3 (0x1u << 3) +#define PIO_SODR_P4 (0x1u << 4) +#define PIO_SODR_P5 (0x1u << 5) +#define PIO_SODR_P6 (0x1u << 6) +#define PIO_SODR_P7 (0x1u << 7) +#define PIO_SODR_P8 (0x1u << 8) +#define PIO_SODR_P9 (0x1u << 9) +#define PIO_SODR_P10 (0x1u << 10) +#define PIO_SODR_P11 (0x1u << 11) +#define PIO_SODR_P12 (0x1u << 12) +#define PIO_SODR_P13 (0x1u << 13) +#define PIO_SODR_P14 (0x1u << 14) +#define PIO_SODR_P15 (0x1u << 15) +#define PIO_SODR_P16 (0x1u << 16) +#define PIO_SODR_P17 (0x1u << 17) +#define PIO_SODR_P18 (0x1u << 18) +#define PIO_SODR_P19 (0x1u << 19) +#define PIO_SODR_P20 (0x1u << 20) +#define PIO_SODR_P21 (0x1u << 21) +#define PIO_SODR_P22 (0x1u << 22) +#define PIO_SODR_P23 (0x1u << 23) +#define PIO_SODR_P24 (0x1u << 24) +#define PIO_SODR_P25 (0x1u << 25) +#define PIO_SODR_P26 (0x1u << 26) +#define PIO_SODR_P27 (0x1u << 27) +#define PIO_SODR_P28 (0x1u << 28) +#define PIO_SODR_P29 (0x1u << 29) +#define PIO_SODR_P30 (0x1u << 30) +#define PIO_SODR_P31 (0x1u << 31) + +#define PIO_CODR_P0 (0x1u << 0) +#define PIO_CODR_P1 (0x1u << 1) +#define PIO_CODR_P2 (0x1u << 2) +#define PIO_CODR_P3 (0x1u << 3) +#define PIO_CODR_P4 (0x1u << 4) +#define PIO_CODR_P5 (0x1u << 5) +#define PIO_CODR_P6 (0x1u << 6) +#define PIO_CODR_P7 (0x1u << 7) +#define PIO_CODR_P8 (0x1u << 8) +#define PIO_CODR_P9 (0x1u << 9) +#define PIO_CODR_P10 (0x1u << 10) +#define PIO_CODR_P11 (0x1u << 11) +#define PIO_CODR_P12 (0x1u << 12) +#define PIO_CODR_P13 (0x1u << 13) +#define PIO_CODR_P14 (0x1u << 14) +#define PIO_CODR_P15 (0x1u << 15) +#define PIO_CODR_P16 (0x1u << 16) +#define PIO_CODR_P17 (0x1u << 17) +#define PIO_CODR_P18 (0x1u << 18) +#define PIO_CODR_P19 (0x1u << 19) +#define PIO_CODR_P20 (0x1u << 20) +#define PIO_CODR_P21 (0x1u << 21) +#define PIO_CODR_P22 (0x1u << 22) +#define PIO_CODR_P23 (0x1u << 23) +#define PIO_CODR_P24 (0x1u << 24) +#define PIO_CODR_P25 (0x1u << 25) +#define PIO_CODR_P26 (0x1u << 26) +#define PIO_CODR_P27 (0x1u << 27) +#define PIO_CODR_P28 (0x1u << 28) +#define PIO_CODR_P29 (0x1u << 29) +#define PIO_CODR_P30 (0x1u << 30) +#define PIO_CODR_P31 (0x1u << 31) + +#define PIO_ODSR_P0 (0x1u << 0) +#define PIO_ODSR_P1 (0x1u << 1) +#define PIO_ODSR_P2 (0x1u << 2) +#define PIO_ODSR_P3 (0x1u << 3) +#define PIO_ODSR_P4 (0x1u << 4) +#define PIO_ODSR_P5 (0x1u << 5) +#define PIO_ODSR_P6 (0x1u << 6) +#define PIO_ODSR_P7 (0x1u << 7) +#define PIO_ODSR_P8 (0x1u << 8) +#define PIO_ODSR_P9 (0x1u << 9) +#define PIO_ODSR_P10 (0x1u << 10) +#define PIO_ODSR_P11 (0x1u << 11) +#define PIO_ODSR_P12 (0x1u << 12) +#define PIO_ODSR_P13 (0x1u << 13) +#define PIO_ODSR_P14 (0x1u << 14) +#define PIO_ODSR_P15 (0x1u << 15) +#define PIO_ODSR_P16 (0x1u << 16) +#define PIO_ODSR_P17 (0x1u << 17) +#define PIO_ODSR_P18 (0x1u << 18) +#define PIO_ODSR_P19 (0x1u << 19) +#define PIO_ODSR_P20 (0x1u << 20) +#define PIO_ODSR_P21 (0x1u << 21) +#define PIO_ODSR_P22 (0x1u << 22) +#define PIO_ODSR_P23 (0x1u << 23) +#define PIO_ODSR_P24 (0x1u << 24) +#define PIO_ODSR_P25 (0x1u << 25) +#define PIO_ODSR_P26 (0x1u << 26) +#define PIO_ODSR_P27 (0x1u << 27) +#define PIO_ODSR_P28 (0x1u << 28) +#define PIO_ODSR_P29 (0x1u << 29) +#define PIO_ODSR_P30 (0x1u << 30) +#define PIO_ODSR_P31 (0x1u << 31) + +#define PIO_PDSR_P0 (0x1u << 0) +#define PIO_PDSR_P1 (0x1u << 1) +#define PIO_PDSR_P2 (0x1u << 2) +#define PIO_PDSR_P3 (0x1u << 3) +#define PIO_PDSR_P4 (0x1u << 4) +#define PIO_PDSR_P5 (0x1u << 5) +#define PIO_PDSR_P6 (0x1u << 6) +#define PIO_PDSR_P7 (0x1u << 7) +#define PIO_PDSR_P8 (0x1u << 8) +#define PIO_PDSR_P9 (0x1u << 9) +#define PIO_PDSR_P10 (0x1u << 10) +#define PIO_PDSR_P11 (0x1u << 11) +#define PIO_PDSR_P12 (0x1u << 12) +#define PIO_PDSR_P13 (0x1u << 13) +#define PIO_PDSR_P14 (0x1u << 14) +#define PIO_PDSR_P15 (0x1u << 15) +#define PIO_PDSR_P16 (0x1u << 16) +#define PIO_PDSR_P17 (0x1u << 17) +#define PIO_PDSR_P18 (0x1u << 18) +#define PIO_PDSR_P19 (0x1u << 19) +#define PIO_PDSR_P20 (0x1u << 20) +#define PIO_PDSR_P21 (0x1u << 21) +#define PIO_PDSR_P22 (0x1u << 22) +#define PIO_PDSR_P23 (0x1u << 23) +#define PIO_PDSR_P24 (0x1u << 24) +#define PIO_PDSR_P25 (0x1u << 25) +#define PIO_PDSR_P26 (0x1u << 26) +#define PIO_PDSR_P27 (0x1u << 27) +#define PIO_PDSR_P28 (0x1u << 28) +#define PIO_PDSR_P29 (0x1u << 29) +#define PIO_PDSR_P30 (0x1u << 30) +#define PIO_PDSR_P31 (0x1u << 31) + +#define PIO_IER_P0 (0x1u << 0) +#define PIO_IER_P1 (0x1u << 1) +#define PIO_IER_P2 (0x1u << 2) +#define PIO_IER_P3 (0x1u << 3) +#define PIO_IER_P4 (0x1u << 4) +#define PIO_IER_P5 (0x1u << 5) +#define PIO_IER_P6 (0x1u << 6) +#define PIO_IER_P7 (0x1u << 7) +#define PIO_IER_P8 (0x1u << 8) +#define PIO_IER_P9 (0x1u << 9) +#define PIO_IER_P10 (0x1u << 10) +#define PIO_IER_P11 (0x1u << 11) +#define PIO_IER_P12 (0x1u << 12) +#define PIO_IER_P13 (0x1u << 13) +#define PIO_IER_P14 (0x1u << 14) +#define PIO_IER_P15 (0x1u << 15) +#define PIO_IER_P16 (0x1u << 16) +#define PIO_IER_P17 (0x1u << 17) +#define PIO_IER_P18 (0x1u << 18) +#define PIO_IER_P19 (0x1u << 19) +#define PIO_IER_P20 (0x1u << 20) +#define PIO_IER_P21 (0x1u << 21) +#define PIO_IER_P22 (0x1u << 22) +#define PIO_IER_P23 (0x1u << 23) +#define PIO_IER_P24 (0x1u << 24) +#define PIO_IER_P25 (0x1u << 25) +#define PIO_IER_P26 (0x1u << 26) +#define PIO_IER_P27 (0x1u << 27) +#define PIO_IER_P28 (0x1u << 28) +#define PIO_IER_P29 (0x1u << 29) +#define PIO_IER_P30 (0x1u << 30) +#define PIO_IER_P31 (0x1u << 31) + +#define PIO_IDR_P0 (0x1u << 0) +#define PIO_IDR_P1 (0x1u << 1) +#define PIO_IDR_P2 (0x1u << 2) +#define PIO_IDR_P3 (0x1u << 3) +#define PIO_IDR_P4 (0x1u << 4) +#define PIO_IDR_P5 (0x1u << 5) +#define PIO_IDR_P6 (0x1u << 6) +#define PIO_IDR_P7 (0x1u << 7) +#define PIO_IDR_P8 (0x1u << 8) +#define PIO_IDR_P9 (0x1u << 9) +#define PIO_IDR_P10 (0x1u << 10) +#define PIO_IDR_P11 (0x1u << 11) +#define PIO_IDR_P12 (0x1u << 12) +#define PIO_IDR_P13 (0x1u << 13) +#define PIO_IDR_P14 (0x1u << 14) +#define PIO_IDR_P15 (0x1u << 15) +#define PIO_IDR_P16 (0x1u << 16) +#define PIO_IDR_P17 (0x1u << 17) +#define PIO_IDR_P18 (0x1u << 18) +#define PIO_IDR_P19 (0x1u << 19) +#define PIO_IDR_P20 (0x1u << 20) +#define PIO_IDR_P21 (0x1u << 21) +#define PIO_IDR_P22 (0x1u << 22) +#define PIO_IDR_P23 (0x1u << 23) +#define PIO_IDR_P24 (0x1u << 24) +#define PIO_IDR_P25 (0x1u << 25) +#define PIO_IDR_P26 (0x1u << 26) +#define PIO_IDR_P27 (0x1u << 27) +#define PIO_IDR_P28 (0x1u << 28) +#define PIO_IDR_P29 (0x1u << 29) +#define PIO_IDR_P30 (0x1u << 30) +#define PIO_IDR_P31 (0x1u << 31) + +#define PIO_IMR_P0 (0x1u << 0) +#define PIO_IMR_P1 (0x1u << 1) +#define PIO_IMR_P2 (0x1u << 2) +#define PIO_IMR_P3 (0x1u << 3) +#define PIO_IMR_P4 (0x1u << 4) +#define PIO_IMR_P5 (0x1u << 5) +#define PIO_IMR_P6 (0x1u << 6) +#define PIO_IMR_P7 (0x1u << 7) +#define PIO_IMR_P8 (0x1u << 8) +#define PIO_IMR_P9 (0x1u << 9) +#define PIO_IMR_P10 (0x1u << 10) +#define PIO_IMR_P11 (0x1u << 11) +#define PIO_IMR_P12 (0x1u << 12) +#define PIO_IMR_P13 (0x1u << 13) +#define PIO_IMR_P14 (0x1u << 14) +#define PIO_IMR_P15 (0x1u << 15) +#define PIO_IMR_P16 (0x1u << 16) +#define PIO_IMR_P17 (0x1u << 17) +#define PIO_IMR_P18 (0x1u << 18) +#define PIO_IMR_P19 (0x1u << 19) +#define PIO_IMR_P20 (0x1u << 20) +#define PIO_IMR_P21 (0x1u << 21) +#define PIO_IMR_P22 (0x1u << 22) +#define PIO_IMR_P23 (0x1u << 23) +#define PIO_IMR_P24 (0x1u << 24) +#define PIO_IMR_P25 (0x1u << 25) +#define PIO_IMR_P26 (0x1u << 26) +#define PIO_IMR_P27 (0x1u << 27) +#define PIO_IMR_P28 (0x1u << 28) +#define PIO_IMR_P29 (0x1u << 29) +#define PIO_IMR_P30 (0x1u << 30) +#define PIO_IMR_P31 (0x1u << 31) + +#define PIO_ISR_P0 (0x1u << 0) +#define PIO_ISR_P1 (0x1u << 1) +#define PIO_ISR_P2 (0x1u << 2) +#define PIO_ISR_P3 (0x1u << 3) +#define PIO_ISR_P4 (0x1u << 4) +#define PIO_ISR_P5 (0x1u << 5) +#define PIO_ISR_P6 (0x1u << 6) +#define PIO_ISR_P7 (0x1u << 7) +#define PIO_ISR_P8 (0x1u << 8) +#define PIO_ISR_P9 (0x1u << 9) +#define PIO_ISR_P10 (0x1u << 10) +#define PIO_ISR_P11 (0x1u << 11) +#define PIO_ISR_P12 (0x1u << 12) +#define PIO_ISR_P13 (0x1u << 13) +#define PIO_ISR_P14 (0x1u << 14) +#define PIO_ISR_P15 (0x1u << 15) +#define PIO_ISR_P16 (0x1u << 16) +#define PIO_ISR_P17 (0x1u << 17) +#define PIO_ISR_P18 (0x1u << 18) +#define PIO_ISR_P19 (0x1u << 19) +#define PIO_ISR_P20 (0x1u << 20) +#define PIO_ISR_P21 (0x1u << 21) +#define PIO_ISR_P22 (0x1u << 22) +#define PIO_ISR_P23 (0x1u << 23) +#define PIO_ISR_P24 (0x1u << 24) +#define PIO_ISR_P25 (0x1u << 25) +#define PIO_ISR_P26 (0x1u << 26) +#define PIO_ISR_P27 (0x1u << 27) +#define PIO_ISR_P28 (0x1u << 28) +#define PIO_ISR_P29 (0x1u << 29) +#define PIO_ISR_P30 (0x1u << 30) +#define PIO_ISR_P31 (0x1u << 31) + +#define PIO_MDER_P0 (0x1u << 0) +#define PIO_MDER_P1 (0x1u << 1) +#define PIO_MDER_P2 (0x1u << 2) +#define PIO_MDER_P3 (0x1u << 3) +#define PIO_MDER_P4 (0x1u << 4) +#define PIO_MDER_P5 (0x1u << 5) +#define PIO_MDER_P6 (0x1u << 6) +#define PIO_MDER_P7 (0x1u << 7) +#define PIO_MDER_P8 (0x1u << 8) +#define PIO_MDER_P9 (0x1u << 9) +#define PIO_MDER_P10 (0x1u << 10) +#define PIO_MDER_P11 (0x1u << 11) +#define PIO_MDER_P12 (0x1u << 12) +#define PIO_MDER_P13 (0x1u << 13) +#define PIO_MDER_P14 (0x1u << 14) +#define PIO_MDER_P15 (0x1u << 15) +#define PIO_MDER_P16 (0x1u << 16) +#define PIO_MDER_P17 (0x1u << 17) +#define PIO_MDER_P18 (0x1u << 18) +#define PIO_MDER_P19 (0x1u << 19) +#define PIO_MDER_P20 (0x1u << 20) +#define PIO_MDER_P21 (0x1u << 21) +#define PIO_MDER_P22 (0x1u << 22) +#define PIO_MDER_P23 (0x1u << 23) +#define PIO_MDER_P24 (0x1u << 24) +#define PIO_MDER_P25 (0x1u << 25) +#define PIO_MDER_P26 (0x1u << 26) +#define PIO_MDER_P27 (0x1u << 27) +#define PIO_MDER_P28 (0x1u << 28) +#define PIO_MDER_P29 (0x1u << 29) +#define PIO_MDER_P30 (0x1u << 30) +#define PIO_MDER_P31 (0x1u << 31) + +#define PIO_MDDR_P0 (0x1u << 0) +#define PIO_MDDR_P1 (0x1u << 1) +#define PIO_MDDR_P2 (0x1u << 2) +#define PIO_MDDR_P3 (0x1u << 3) +#define PIO_MDDR_P4 (0x1u << 4) +#define PIO_MDDR_P5 (0x1u << 5) +#define PIO_MDDR_P6 (0x1u << 6) +#define PIO_MDDR_P7 (0x1u << 7) +#define PIO_MDDR_P8 (0x1u << 8) +#define PIO_MDDR_P9 (0x1u << 9) +#define PIO_MDDR_P10 (0x1u << 10) +#define PIO_MDDR_P11 (0x1u << 11) +#define PIO_MDDR_P12 (0x1u << 12) +#define PIO_MDDR_P13 (0x1u << 13) +#define PIO_MDDR_P14 (0x1u << 14) +#define PIO_MDDR_P15 (0x1u << 15) +#define PIO_MDDR_P16 (0x1u << 16) +#define PIO_MDDR_P17 (0x1u << 17) +#define PIO_MDDR_P18 (0x1u << 18) +#define PIO_MDDR_P19 (0x1u << 19) +#define PIO_MDDR_P20 (0x1u << 20) +#define PIO_MDDR_P21 (0x1u << 21) +#define PIO_MDDR_P22 (0x1u << 22) +#define PIO_MDDR_P23 (0x1u << 23) +#define PIO_MDDR_P24 (0x1u << 24) +#define PIO_MDDR_P25 (0x1u << 25) +#define PIO_MDDR_P26 (0x1u << 26) +#define PIO_MDDR_P27 (0x1u << 27) +#define PIO_MDDR_P28 (0x1u << 28) +#define PIO_MDDR_P29 (0x1u << 29) +#define PIO_MDDR_P30 (0x1u << 30) +#define PIO_MDDR_P31 (0x1u << 31) + +#define PIO_MDSR_P0 (0x1u << 0) +#define PIO_MDSR_P1 (0x1u << 1) +#define PIO_MDSR_P2 (0x1u << 2) +#define PIO_MDSR_P3 (0x1u << 3) +#define PIO_MDSR_P4 (0x1u << 4) +#define PIO_MDSR_P5 (0x1u << 5) +#define PIO_MDSR_P6 (0x1u << 6) +#define PIO_MDSR_P7 (0x1u << 7) +#define PIO_MDSR_P8 (0x1u << 8) +#define PIO_MDSR_P9 (0x1u << 9) +#define PIO_MDSR_P10 (0x1u << 10) +#define PIO_MDSR_P11 (0x1u << 11) +#define PIO_MDSR_P12 (0x1u << 12) +#define PIO_MDSR_P13 (0x1u << 13) +#define PIO_MDSR_P14 (0x1u << 14) +#define PIO_MDSR_P15 (0x1u << 15) +#define PIO_MDSR_P16 (0x1u << 16) +#define PIO_MDSR_P17 (0x1u << 17) +#define PIO_MDSR_P18 (0x1u << 18) +#define PIO_MDSR_P19 (0x1u << 19) +#define PIO_MDSR_P20 (0x1u << 20) +#define PIO_MDSR_P21 (0x1u << 21) +#define PIO_MDSR_P22 (0x1u << 22) +#define PIO_MDSR_P23 (0x1u << 23) +#define PIO_MDSR_P24 (0x1u << 24) +#define PIO_MDSR_P25 (0x1u << 25) +#define PIO_MDSR_P26 (0x1u << 26) +#define PIO_MDSR_P27 (0x1u << 27) +#define PIO_MDSR_P28 (0x1u << 28) +#define PIO_MDSR_P29 (0x1u << 29) +#define PIO_MDSR_P30 (0x1u << 30) +#define PIO_MDSR_P31 (0x1u << 31) + +#define PIO_PUDR_P0 (0x1u << 0) +#define PIO_PUDR_P1 (0x1u << 1) +#define PIO_PUDR_P2 (0x1u << 2) +#define PIO_PUDR_P3 (0x1u << 3) +#define PIO_PUDR_P4 (0x1u << 4) +#define PIO_PUDR_P5 (0x1u << 5) +#define PIO_PUDR_P6 (0x1u << 6) +#define PIO_PUDR_P7 (0x1u << 7) +#define PIO_PUDR_P8 (0x1u << 8) +#define PIO_PUDR_P9 (0x1u << 9) +#define PIO_PUDR_P10 (0x1u << 10) +#define PIO_PUDR_P11 (0x1u << 11) +#define PIO_PUDR_P12 (0x1u << 12) +#define PIO_PUDR_P13 (0x1u << 13) +#define PIO_PUDR_P14 (0x1u << 14) +#define PIO_PUDR_P15 (0x1u << 15) +#define PIO_PUDR_P16 (0x1u << 16) +#define PIO_PUDR_P17 (0x1u << 17) +#define PIO_PUDR_P18 (0x1u << 18) +#define PIO_PUDR_P19 (0x1u << 19) +#define PIO_PUDR_P20 (0x1u << 20) +#define PIO_PUDR_P21 (0x1u << 21) +#define PIO_PUDR_P22 (0x1u << 22) +#define PIO_PUDR_P23 (0x1u << 23) +#define PIO_PUDR_P24 (0x1u << 24) +#define PIO_PUDR_P25 (0x1u << 25) +#define PIO_PUDR_P26 (0x1u << 26) +#define PIO_PUDR_P27 (0x1u << 27) +#define PIO_PUDR_P28 (0x1u << 28) +#define PIO_PUDR_P29 (0x1u << 29) +#define PIO_PUDR_P30 (0x1u << 30) +#define PIO_PUDR_P31 (0x1u << 31) + +#define PIO_PUER_P0 (0x1u << 0) +#define PIO_PUER_P1 (0x1u << 1) +#define PIO_PUER_P2 (0x1u << 2) +#define PIO_PUER_P3 (0x1u << 3) +#define PIO_PUER_P4 (0x1u << 4) +#define PIO_PUER_P5 (0x1u << 5) +#define PIO_PUER_P6 (0x1u << 6) +#define PIO_PUER_P7 (0x1u << 7) +#define PIO_PUER_P8 (0x1u << 8) +#define PIO_PUER_P9 (0x1u << 9) +#define PIO_PUER_P10 (0x1u << 10) +#define PIO_PUER_P11 (0x1u << 11) +#define PIO_PUER_P12 (0x1u << 12) +#define PIO_PUER_P13 (0x1u << 13) +#define PIO_PUER_P14 (0x1u << 14) +#define PIO_PUER_P15 (0x1u << 15) +#define PIO_PUER_P16 (0x1u << 16) +#define PIO_PUER_P17 (0x1u << 17) +#define PIO_PUER_P18 (0x1u << 18) +#define PIO_PUER_P19 (0x1u << 19) +#define PIO_PUER_P20 (0x1u << 20) +#define PIO_PUER_P21 (0x1u << 21) +#define PIO_PUER_P22 (0x1u << 22) +#define PIO_PUER_P23 (0x1u << 23) +#define PIO_PUER_P24 (0x1u << 24) +#define PIO_PUER_P25 (0x1u << 25) +#define PIO_PUER_P26 (0x1u << 26) +#define PIO_PUER_P27 (0x1u << 27) +#define PIO_PUER_P28 (0x1u << 28) +#define PIO_PUER_P29 (0x1u << 29) +#define PIO_PUER_P30 (0x1u << 30) +#define PIO_PUER_P31 (0x1u << 31) + +#define PIO_PUSR_P0 (0x1u << 0) +#define PIO_PUSR_P1 (0x1u << 1) +#define PIO_PUSR_P2 (0x1u << 2) +#define PIO_PUSR_P3 (0x1u << 3) +#define PIO_PUSR_P4 (0x1u << 4) +#define PIO_PUSR_P5 (0x1u << 5) +#define PIO_PUSR_P6 (0x1u << 6) +#define PIO_PUSR_P7 (0x1u << 7) +#define PIO_PUSR_P8 (0x1u << 8) +#define PIO_PUSR_P9 (0x1u << 9) +#define PIO_PUSR_P10 (0x1u << 10) +#define PIO_PUSR_P11 (0x1u << 11) +#define PIO_PUSR_P12 (0x1u << 12) +#define PIO_PUSR_P13 (0x1u << 13) +#define PIO_PUSR_P14 (0x1u << 14) +#define PIO_PUSR_P15 (0x1u << 15) +#define PIO_PUSR_P16 (0x1u << 16) +#define PIO_PUSR_P17 (0x1u << 17) +#define PIO_PUSR_P18 (0x1u << 18) +#define PIO_PUSR_P19 (0x1u << 19) +#define PIO_PUSR_P20 (0x1u << 20) +#define PIO_PUSR_P21 (0x1u << 21) +#define PIO_PUSR_P22 (0x1u << 22) +#define PIO_PUSR_P23 (0x1u << 23) +#define PIO_PUSR_P24 (0x1u << 24) +#define PIO_PUSR_P25 (0x1u << 25) +#define PIO_PUSR_P26 (0x1u << 26) +#define PIO_PUSR_P27 (0x1u << 27) +#define PIO_PUSR_P28 (0x1u << 28) +#define PIO_PUSR_P29 (0x1u << 29) +#define PIO_PUSR_P30 (0x1u << 30) +#define PIO_PUSR_P31 (0x1u << 31) + +#define PIO_ABSR_P0 (0x1u << 0) +#define PIO_ABSR_P1 (0x1u << 1) +#define PIO_ABSR_P2 (0x1u << 2) +#define PIO_ABSR_P3 (0x1u << 3) +#define PIO_ABSR_P4 (0x1u << 4) +#define PIO_ABSR_P5 (0x1u << 5) +#define PIO_ABSR_P6 (0x1u << 6) +#define PIO_ABSR_P7 (0x1u << 7) +#define PIO_ABSR_P8 (0x1u << 8) +#define PIO_ABSR_P9 (0x1u << 9) +#define PIO_ABSR_P10 (0x1u << 10) +#define PIO_ABSR_P11 (0x1u << 11) +#define PIO_ABSR_P12 (0x1u << 12) +#define PIO_ABSR_P13 (0x1u << 13) +#define PIO_ABSR_P14 (0x1u << 14) +#define PIO_ABSR_P15 (0x1u << 15) +#define PIO_ABSR_P16 (0x1u << 16) +#define PIO_ABSR_P17 (0x1u << 17) +#define PIO_ABSR_P18 (0x1u << 18) +#define PIO_ABSR_P19 (0x1u << 19) +#define PIO_ABSR_P20 (0x1u << 20) +#define PIO_ABSR_P21 (0x1u << 21) +#define PIO_ABSR_P22 (0x1u << 22) +#define PIO_ABSR_P23 (0x1u << 23) +#define PIO_ABSR_P24 (0x1u << 24) +#define PIO_ABSR_P25 (0x1u << 25) +#define PIO_ABSR_P26 (0x1u << 26) +#define PIO_ABSR_P27 (0x1u << 27) +#define PIO_ABSR_P28 (0x1u << 28) +#define PIO_ABSR_P29 (0x1u << 29) +#define PIO_ABSR_P30 (0x1u << 30) +#define PIO_ABSR_P31 (0x1u << 31) + +#define PIO_SCIFSR_P0 (0x1u << 0) +#define PIO_SCIFSR_P1 (0x1u << 1) +#define PIO_SCIFSR_P2 (0x1u << 2) +#define PIO_SCIFSR_P3 (0x1u << 3) +#define PIO_SCIFSR_P4 (0x1u << 4) +#define PIO_SCIFSR_P5 (0x1u << 5) +#define PIO_SCIFSR_P6 (0x1u << 6) +#define PIO_SCIFSR_P7 (0x1u << 7) +#define PIO_SCIFSR_P8 (0x1u << 8) +#define PIO_SCIFSR_P9 (0x1u << 9) +#define PIO_SCIFSR_P10 (0x1u << 10) +#define PIO_SCIFSR_P11 (0x1u << 11) +#define PIO_SCIFSR_P12 (0x1u << 12) +#define PIO_SCIFSR_P13 (0x1u << 13) +#define PIO_SCIFSR_P14 (0x1u << 14) +#define PIO_SCIFSR_P15 (0x1u << 15) +#define PIO_SCIFSR_P16 (0x1u << 16) +#define PIO_SCIFSR_P17 (0x1u << 17) +#define PIO_SCIFSR_P18 (0x1u << 18) +#define PIO_SCIFSR_P19 (0x1u << 19) +#define PIO_SCIFSR_P20 (0x1u << 20) +#define PIO_SCIFSR_P21 (0x1u << 21) +#define PIO_SCIFSR_P22 (0x1u << 22) +#define PIO_SCIFSR_P23 (0x1u << 23) +#define PIO_SCIFSR_P24 (0x1u << 24) +#define PIO_SCIFSR_P25 (0x1u << 25) +#define PIO_SCIFSR_P26 (0x1u << 26) +#define PIO_SCIFSR_P27 (0x1u << 27) +#define PIO_SCIFSR_P28 (0x1u << 28) +#define PIO_SCIFSR_P29 (0x1u << 29) +#define PIO_SCIFSR_P30 (0x1u << 30) +#define PIO_SCIFSR_P31 (0x1u << 31) + +#define PIO_DIFSR_P0 (0x1u << 0) +#define PIO_DIFSR_P1 (0x1u << 1) +#define PIO_DIFSR_P2 (0x1u << 2) +#define PIO_DIFSR_P3 (0x1u << 3) +#define PIO_DIFSR_P4 (0x1u << 4) +#define PIO_DIFSR_P5 (0x1u << 5) +#define PIO_DIFSR_P6 (0x1u << 6) +#define PIO_DIFSR_P7 (0x1u << 7) +#define PIO_DIFSR_P8 (0x1u << 8) +#define PIO_DIFSR_P9 (0x1u << 9) +#define PIO_DIFSR_P10 (0x1u << 10) +#define PIO_DIFSR_P11 (0x1u << 11) +#define PIO_DIFSR_P12 (0x1u << 12) +#define PIO_DIFSR_P13 (0x1u << 13) +#define PIO_DIFSR_P14 (0x1u << 14) +#define PIO_DIFSR_P15 (0x1u << 15) +#define PIO_DIFSR_P16 (0x1u << 16) +#define PIO_DIFSR_P17 (0x1u << 17) +#define PIO_DIFSR_P18 (0x1u << 18) +#define PIO_DIFSR_P19 (0x1u << 19) +#define PIO_DIFSR_P20 (0x1u << 20) +#define PIO_DIFSR_P21 (0x1u << 21) +#define PIO_DIFSR_P22 (0x1u << 22) +#define PIO_DIFSR_P23 (0x1u << 23) +#define PIO_DIFSR_P24 (0x1u << 24) +#define PIO_DIFSR_P25 (0x1u << 25) +#define PIO_DIFSR_P26 (0x1u << 26) +#define PIO_DIFSR_P27 (0x1u << 27) +#define PIO_DIFSR_P28 (0x1u << 28) +#define PIO_DIFSR_P29 (0x1u << 29) +#define PIO_DIFSR_P30 (0x1u << 30) +#define PIO_DIFSR_P31 (0x1u << 31) + +#define PIO_IFDGSR_P0 (0x1u << 0) +#define PIO_IFDGSR_P1 (0x1u << 1) +#define PIO_IFDGSR_P2 (0x1u << 2) +#define PIO_IFDGSR_P3 (0x1u << 3) +#define PIO_IFDGSR_P4 (0x1u << 4) +#define PIO_IFDGSR_P5 (0x1u << 5) +#define PIO_IFDGSR_P6 (0x1u << 6) +#define PIO_IFDGSR_P7 (0x1u << 7) +#define PIO_IFDGSR_P8 (0x1u << 8) +#define PIO_IFDGSR_P9 (0x1u << 9) +#define PIO_IFDGSR_P10 (0x1u << 10) +#define PIO_IFDGSR_P11 (0x1u << 11) +#define PIO_IFDGSR_P12 (0x1u << 12) +#define PIO_IFDGSR_P13 (0x1u << 13) +#define PIO_IFDGSR_P14 (0x1u << 14) +#define PIO_IFDGSR_P15 (0x1u << 15) +#define PIO_IFDGSR_P16 (0x1u << 16) +#define PIO_IFDGSR_P17 (0x1u << 17) +#define PIO_IFDGSR_P18 (0x1u << 18) +#define PIO_IFDGSR_P19 (0x1u << 19) +#define PIO_IFDGSR_P20 (0x1u << 20) +#define PIO_IFDGSR_P21 (0x1u << 21) +#define PIO_IFDGSR_P22 (0x1u << 22) +#define PIO_IFDGSR_P23 (0x1u << 23) +#define PIO_IFDGSR_P24 (0x1u << 24) +#define PIO_IFDGSR_P25 (0x1u << 25) +#define PIO_IFDGSR_P26 (0x1u << 26) +#define PIO_IFDGSR_P27 (0x1u << 27) +#define PIO_IFDGSR_P28 (0x1u << 28) +#define PIO_IFDGSR_P29 (0x1u << 29) +#define PIO_IFDGSR_P30 (0x1u << 30) +#define PIO_IFDGSR_P31 (0x1u << 31) + +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) + +#define PIO_OWER_P0 (0x1u << 0) +#define PIO_OWER_P1 (0x1u << 1) +#define PIO_OWER_P2 (0x1u << 2) +#define PIO_OWER_P3 (0x1u << 3) +#define PIO_OWER_P4 (0x1u << 4) +#define PIO_OWER_P5 (0x1u << 5) +#define PIO_OWER_P6 (0x1u << 6) +#define PIO_OWER_P7 (0x1u << 7) +#define PIO_OWER_P8 (0x1u << 8) +#define PIO_OWER_P9 (0x1u << 9) +#define PIO_OWER_P10 (0x1u << 10) +#define PIO_OWER_P11 (0x1u << 11) +#define PIO_OWER_P12 (0x1u << 12) +#define PIO_OWER_P13 (0x1u << 13) +#define PIO_OWER_P14 (0x1u << 14) +#define PIO_OWER_P15 (0x1u << 15) +#define PIO_OWER_P16 (0x1u << 16) +#define PIO_OWER_P17 (0x1u << 17) +#define PIO_OWER_P18 (0x1u << 18) +#define PIO_OWER_P19 (0x1u << 19) +#define PIO_OWER_P20 (0x1u << 20) +#define PIO_OWER_P21 (0x1u << 21) +#define PIO_OWER_P22 (0x1u << 22) +#define PIO_OWER_P23 (0x1u << 23) +#define PIO_OWER_P24 (0x1u << 24) +#define PIO_OWER_P25 (0x1u << 25) +#define PIO_OWER_P26 (0x1u << 26) +#define PIO_OWER_P27 (0x1u << 27) +#define PIO_OWER_P28 (0x1u << 28) +#define PIO_OWER_P29 (0x1u << 29) +#define PIO_OWER_P30 (0x1u << 30) +#define PIO_OWER_P31 (0x1u << 31) + +#define PIO_OWDR_P0 (0x1u << 0) +#define PIO_OWDR_P1 (0x1u << 1) +#define PIO_OWDR_P2 (0x1u << 2) +#define PIO_OWDR_P3 (0x1u << 3) +#define PIO_OWDR_P4 (0x1u << 4) +#define PIO_OWDR_P5 (0x1u << 5) +#define PIO_OWDR_P6 (0x1u << 6) +#define PIO_OWDR_P7 (0x1u << 7) +#define PIO_OWDR_P8 (0x1u << 8) +#define PIO_OWDR_P9 (0x1u << 9) +#define PIO_OWDR_P10 (0x1u << 10) +#define PIO_OWDR_P11 (0x1u << 11) +#define PIO_OWDR_P12 (0x1u << 12) +#define PIO_OWDR_P13 (0x1u << 13) +#define PIO_OWDR_P14 (0x1u << 14) +#define PIO_OWDR_P15 (0x1u << 15) +#define PIO_OWDR_P16 (0x1u << 16) +#define PIO_OWDR_P17 (0x1u << 17) +#define PIO_OWDR_P18 (0x1u << 18) +#define PIO_OWDR_P19 (0x1u << 19) +#define PIO_OWDR_P20 (0x1u << 20) +#define PIO_OWDR_P21 (0x1u << 21) +#define PIO_OWDR_P22 (0x1u << 22) +#define PIO_OWDR_P23 (0x1u << 23) +#define PIO_OWDR_P24 (0x1u << 24) +#define PIO_OWDR_P25 (0x1u << 25) +#define PIO_OWDR_P26 (0x1u << 26) +#define PIO_OWDR_P27 (0x1u << 27) +#define PIO_OWDR_P28 (0x1u << 28) +#define PIO_OWDR_P29 (0x1u << 29) +#define PIO_OWDR_P30 (0x1u << 30) +#define PIO_OWDR_P31 (0x1u << 31) + +#define PIO_OWSR_P0 (0x1u << 0) +#define PIO_OWSR_P1 (0x1u << 1) +#define PIO_OWSR_P2 (0x1u << 2) +#define PIO_OWSR_P3 (0x1u << 3) +#define PIO_OWSR_P4 (0x1u << 4) +#define PIO_OWSR_P5 (0x1u << 5) +#define PIO_OWSR_P6 (0x1u << 6) +#define PIO_OWSR_P7 (0x1u << 7) +#define PIO_OWSR_P8 (0x1u << 8) +#define PIO_OWSR_P9 (0x1u << 9) +#define PIO_OWSR_P10 (0x1u << 10) +#define PIO_OWSR_P11 (0x1u << 11) +#define PIO_OWSR_P12 (0x1u << 12) +#define PIO_OWSR_P13 (0x1u << 13) +#define PIO_OWSR_P14 (0x1u << 14) +#define PIO_OWSR_P15 (0x1u << 15) +#define PIO_OWSR_P16 (0x1u << 16) +#define PIO_OWSR_P17 (0x1u << 17) +#define PIO_OWSR_P18 (0x1u << 18) +#define PIO_OWSR_P19 (0x1u << 19) +#define PIO_OWSR_P20 (0x1u << 20) +#define PIO_OWSR_P21 (0x1u << 21) +#define PIO_OWSR_P22 (0x1u << 22) +#define PIO_OWSR_P23 (0x1u << 23) +#define PIO_OWSR_P24 (0x1u << 24) +#define PIO_OWSR_P25 (0x1u << 25) +#define PIO_OWSR_P26 (0x1u << 26) +#define PIO_OWSR_P27 (0x1u << 27) +#define PIO_OWSR_P28 (0x1u << 28) +#define PIO_OWSR_P29 (0x1u << 29) +#define PIO_OWSR_P30 (0x1u << 30) +#define PIO_OWSR_P31 (0x1u << 31) + +#define PIO_AIMER_P0 (0x1u << 0) +#define PIO_AIMER_P1 (0x1u << 1) +#define PIO_AIMER_P2 (0x1u << 2) +#define PIO_AIMER_P3 (0x1u << 3) +#define PIO_AIMER_P4 (0x1u << 4) +#define PIO_AIMER_P5 (0x1u << 5) +#define PIO_AIMER_P6 (0x1u << 6) +#define PIO_AIMER_P7 (0x1u << 7) +#define PIO_AIMER_P8 (0x1u << 8) +#define PIO_AIMER_P9 (0x1u << 9) +#define PIO_AIMER_P10 (0x1u << 10) +#define PIO_AIMER_P11 (0x1u << 11) +#define PIO_AIMER_P12 (0x1u << 12) +#define PIO_AIMER_P13 (0x1u << 13) +#define PIO_AIMER_P14 (0x1u << 14) +#define PIO_AIMER_P15 (0x1u << 15) +#define PIO_AIMER_P16 (0x1u << 16) +#define PIO_AIMER_P17 (0x1u << 17) +#define PIO_AIMER_P18 (0x1u << 18) +#define PIO_AIMER_P19 (0x1u << 19) +#define PIO_AIMER_P20 (0x1u << 20) +#define PIO_AIMER_P21 (0x1u << 21) +#define PIO_AIMER_P22 (0x1u << 22) +#define PIO_AIMER_P23 (0x1u << 23) +#define PIO_AIMER_P24 (0x1u << 24) +#define PIO_AIMER_P25 (0x1u << 25) +#define PIO_AIMER_P26 (0x1u << 26) +#define PIO_AIMER_P27 (0x1u << 27) +#define PIO_AIMER_P28 (0x1u << 28) +#define PIO_AIMER_P29 (0x1u << 29) +#define PIO_AIMER_P30 (0x1u << 30) +#define PIO_AIMER_P31 (0x1u << 31) + +#define PIO_AIMDR_P0 (0x1u << 0) +#define PIO_AIMDR_P1 (0x1u << 1) +#define PIO_AIMDR_P2 (0x1u << 2) +#define PIO_AIMDR_P3 (0x1u << 3) +#define PIO_AIMDR_P4 (0x1u << 4) +#define PIO_AIMDR_P5 (0x1u << 5) +#define PIO_AIMDR_P6 (0x1u << 6) +#define PIO_AIMDR_P7 (0x1u << 7) +#define PIO_AIMDR_P8 (0x1u << 8) +#define PIO_AIMDR_P9 (0x1u << 9) +#define PIO_AIMDR_P10 (0x1u << 10) +#define PIO_AIMDR_P11 (0x1u << 11) +#define PIO_AIMDR_P12 (0x1u << 12) +#define PIO_AIMDR_P13 (0x1u << 13) +#define PIO_AIMDR_P14 (0x1u << 14) +#define PIO_AIMDR_P15 (0x1u << 15) +#define PIO_AIMDR_P16 (0x1u << 16) +#define PIO_AIMDR_P17 (0x1u << 17) +#define PIO_AIMDR_P18 (0x1u << 18) +#define PIO_AIMDR_P19 (0x1u << 19) +#define PIO_AIMDR_P20 (0x1u << 20) +#define PIO_AIMDR_P21 (0x1u << 21) +#define PIO_AIMDR_P22 (0x1u << 22) +#define PIO_AIMDR_P23 (0x1u << 23) +#define PIO_AIMDR_P24 (0x1u << 24) +#define PIO_AIMDR_P25 (0x1u << 25) +#define PIO_AIMDR_P26 (0x1u << 26) +#define PIO_AIMDR_P27 (0x1u << 27) +#define PIO_AIMDR_P28 (0x1u << 28) +#define PIO_AIMDR_P29 (0x1u << 29) +#define PIO_AIMDR_P30 (0x1u << 30) +#define PIO_AIMDR_P31 (0x1u << 31) + +#define PIO_AIMMR_P0 (0x1u << 0) +#define PIO_AIMMR_P1 (0x1u << 1) +#define PIO_AIMMR_P2 (0x1u << 2) +#define PIO_AIMMR_P3 (0x1u << 3) +#define PIO_AIMMR_P4 (0x1u << 4) +#define PIO_AIMMR_P5 (0x1u << 5) +#define PIO_AIMMR_P6 (0x1u << 6) +#define PIO_AIMMR_P7 (0x1u << 7) +#define PIO_AIMMR_P8 (0x1u << 8) +#define PIO_AIMMR_P9 (0x1u << 9) +#define PIO_AIMMR_P10 (0x1u << 10) +#define PIO_AIMMR_P11 (0x1u << 11) +#define PIO_AIMMR_P12 (0x1u << 12) +#define PIO_AIMMR_P13 (0x1u << 13) +#define PIO_AIMMR_P14 (0x1u << 14) +#define PIO_AIMMR_P15 (0x1u << 15) +#define PIO_AIMMR_P16 (0x1u << 16) +#define PIO_AIMMR_P17 (0x1u << 17) +#define PIO_AIMMR_P18 (0x1u << 18) +#define PIO_AIMMR_P19 (0x1u << 19) +#define PIO_AIMMR_P20 (0x1u << 20) +#define PIO_AIMMR_P21 (0x1u << 21) +#define PIO_AIMMR_P22 (0x1u << 22) +#define PIO_AIMMR_P23 (0x1u << 23) +#define PIO_AIMMR_P24 (0x1u << 24) +#define PIO_AIMMR_P25 (0x1u << 25) +#define PIO_AIMMR_P26 (0x1u << 26) +#define PIO_AIMMR_P27 (0x1u << 27) +#define PIO_AIMMR_P28 (0x1u << 28) +#define PIO_AIMMR_P29 (0x1u << 29) +#define PIO_AIMMR_P30 (0x1u << 30) +#define PIO_AIMMR_P31 (0x1u << 31) + +#define PIO_ESR_P0 (0x1u << 0) +#define PIO_ESR_P1 (0x1u << 1) +#define PIO_ESR_P2 (0x1u << 2) +#define PIO_ESR_P3 (0x1u << 3) +#define PIO_ESR_P4 (0x1u << 4) +#define PIO_ESR_P5 (0x1u << 5) +#define PIO_ESR_P6 (0x1u << 6) +#define PIO_ESR_P7 (0x1u << 7) +#define PIO_ESR_P8 (0x1u << 8) +#define PIO_ESR_P9 (0x1u << 9) +#define PIO_ESR_P10 (0x1u << 10) +#define PIO_ESR_P11 (0x1u << 11) +#define PIO_ESR_P12 (0x1u << 12) +#define PIO_ESR_P13 (0x1u << 13) +#define PIO_ESR_P14 (0x1u << 14) +#define PIO_ESR_P15 (0x1u << 15) +#define PIO_ESR_P16 (0x1u << 16) +#define PIO_ESR_P17 (0x1u << 17) +#define PIO_ESR_P18 (0x1u << 18) +#define PIO_ESR_P19 (0x1u << 19) +#define PIO_ESR_P20 (0x1u << 20) +#define PIO_ESR_P21 (0x1u << 21) +#define PIO_ESR_P22 (0x1u << 22) +#define PIO_ESR_P23 (0x1u << 23) +#define PIO_ESR_P24 (0x1u << 24) +#define PIO_ESR_P25 (0x1u << 25) +#define PIO_ESR_P26 (0x1u << 26) +#define PIO_ESR_P27 (0x1u << 27) +#define PIO_ESR_P28 (0x1u << 28) +#define PIO_ESR_P29 (0x1u << 29) +#define PIO_ESR_P30 (0x1u << 30) +#define PIO_ESR_P31 (0x1u << 31) + +#define PIO_LSR_P0 (0x1u << 0) +#define PIO_LSR_P1 (0x1u << 1) +#define PIO_LSR_P2 (0x1u << 2) +#define PIO_LSR_P3 (0x1u << 3) +#define PIO_LSR_P4 (0x1u << 4) +#define PIO_LSR_P5 (0x1u << 5) +#define PIO_LSR_P6 (0x1u << 6) +#define PIO_LSR_P7 (0x1u << 7) +#define PIO_LSR_P8 (0x1u << 8) +#define PIO_LSR_P9 (0x1u << 9) +#define PIO_LSR_P10 (0x1u << 10) +#define PIO_LSR_P11 (0x1u << 11) +#define PIO_LSR_P12 (0x1u << 12) +#define PIO_LSR_P13 (0x1u << 13) +#define PIO_LSR_P14 (0x1u << 14) +#define PIO_LSR_P15 (0x1u << 15) +#define PIO_LSR_P16 (0x1u << 16) +#define PIO_LSR_P17 (0x1u << 17) +#define PIO_LSR_P18 (0x1u << 18) +#define PIO_LSR_P19 (0x1u << 19) +#define PIO_LSR_P20 (0x1u << 20) +#define PIO_LSR_P21 (0x1u << 21) +#define PIO_LSR_P22 (0x1u << 22) +#define PIO_LSR_P23 (0x1u << 23) +#define PIO_LSR_P24 (0x1u << 24) +#define PIO_LSR_P25 (0x1u << 25) +#define PIO_LSR_P26 (0x1u << 26) +#define PIO_LSR_P27 (0x1u << 27) +#define PIO_LSR_P28 (0x1u << 28) +#define PIO_LSR_P29 (0x1u << 29) +#define PIO_LSR_P30 (0x1u << 30) +#define PIO_LSR_P31 (0x1u << 31) + +#define PIO_ELSR_P0 (0x1u << 0) +#define PIO_ELSR_P1 (0x1u << 1) +#define PIO_ELSR_P2 (0x1u << 2) +#define PIO_ELSR_P3 (0x1u << 3) +#define PIO_ELSR_P4 (0x1u << 4) +#define PIO_ELSR_P5 (0x1u << 5) +#define PIO_ELSR_P6 (0x1u << 6) +#define PIO_ELSR_P7 (0x1u << 7) +#define PIO_ELSR_P8 (0x1u << 8) +#define PIO_ELSR_P9 (0x1u << 9) +#define PIO_ELSR_P10 (0x1u << 10) +#define PIO_ELSR_P11 (0x1u << 11) +#define PIO_ELSR_P12 (0x1u << 12) +#define PIO_ELSR_P13 (0x1u << 13) +#define PIO_ELSR_P14 (0x1u << 14) +#define PIO_ELSR_P15 (0x1u << 15) +#define PIO_ELSR_P16 (0x1u << 16) +#define PIO_ELSR_P17 (0x1u << 17) +#define PIO_ELSR_P18 (0x1u << 18) +#define PIO_ELSR_P19 (0x1u << 19) +#define PIO_ELSR_P20 (0x1u << 20) +#define PIO_ELSR_P21 (0x1u << 21) +#define PIO_ELSR_P22 (0x1u << 22) +#define PIO_ELSR_P23 (0x1u << 23) +#define PIO_ELSR_P24 (0x1u << 24) +#define PIO_ELSR_P25 (0x1u << 25) +#define PIO_ELSR_P26 (0x1u << 26) +#define PIO_ELSR_P27 (0x1u << 27) +#define PIO_ELSR_P28 (0x1u << 28) +#define PIO_ELSR_P29 (0x1u << 29) +#define PIO_ELSR_P30 (0x1u << 30) +#define PIO_ELSR_P31 (0x1u << 31) + +#define PIO_FELLSR_P0 (0x1u << 0) +#define PIO_FELLSR_P1 (0x1u << 1) +#define PIO_FELLSR_P2 (0x1u << 2) +#define PIO_FELLSR_P3 (0x1u << 3) +#define PIO_FELLSR_P4 (0x1u << 4) +#define PIO_FELLSR_P5 (0x1u << 5) +#define PIO_FELLSR_P6 (0x1u << 6) +#define PIO_FELLSR_P7 (0x1u << 7) +#define PIO_FELLSR_P8 (0x1u << 8) +#define PIO_FELLSR_P9 (0x1u << 9) +#define PIO_FELLSR_P10 (0x1u << 10) +#define PIO_FELLSR_P11 (0x1u << 11) +#define PIO_FELLSR_P12 (0x1u << 12) +#define PIO_FELLSR_P13 (0x1u << 13) +#define PIO_FELLSR_P14 (0x1u << 14) +#define PIO_FELLSR_P15 (0x1u << 15) +#define PIO_FELLSR_P16 (0x1u << 16) +#define PIO_FELLSR_P17 (0x1u << 17) +#define PIO_FELLSR_P18 (0x1u << 18) +#define PIO_FELLSR_P19 (0x1u << 19) +#define PIO_FELLSR_P20 (0x1u << 20) +#define PIO_FELLSR_P21 (0x1u << 21) +#define PIO_FELLSR_P22 (0x1u << 22) +#define PIO_FELLSR_P23 (0x1u << 23) +#define PIO_FELLSR_P24 (0x1u << 24) +#define PIO_FELLSR_P25 (0x1u << 25) +#define PIO_FELLSR_P26 (0x1u << 26) +#define PIO_FELLSR_P27 (0x1u << 27) +#define PIO_FELLSR_P28 (0x1u << 28) +#define PIO_FELLSR_P29 (0x1u << 29) +#define PIO_FELLSR_P30 (0x1u << 30) +#define PIO_FELLSR_P31 (0x1u << 31) + +#define PIO_REHLSR_P0 (0x1u << 0) +#define PIO_REHLSR_P1 (0x1u << 1) +#define PIO_REHLSR_P2 (0x1u << 2) +#define PIO_REHLSR_P3 (0x1u << 3) +#define PIO_REHLSR_P4 (0x1u << 4) +#define PIO_REHLSR_P5 (0x1u << 5) +#define PIO_REHLSR_P6 (0x1u << 6) +#define PIO_REHLSR_P7 (0x1u << 7) +#define PIO_REHLSR_P8 (0x1u << 8) +#define PIO_REHLSR_P9 (0x1u << 9) +#define PIO_REHLSR_P10 (0x1u << 10) +#define PIO_REHLSR_P11 (0x1u << 11) +#define PIO_REHLSR_P12 (0x1u << 12) +#define PIO_REHLSR_P13 (0x1u << 13) +#define PIO_REHLSR_P14 (0x1u << 14) +#define PIO_REHLSR_P15 (0x1u << 15) +#define PIO_REHLSR_P16 (0x1u << 16) +#define PIO_REHLSR_P17 (0x1u << 17) +#define PIO_REHLSR_P18 (0x1u << 18) +#define PIO_REHLSR_P19 (0x1u << 19) +#define PIO_REHLSR_P20 (0x1u << 20) +#define PIO_REHLSR_P21 (0x1u << 21) +#define PIO_REHLSR_P22 (0x1u << 22) +#define PIO_REHLSR_P23 (0x1u << 23) +#define PIO_REHLSR_P24 (0x1u << 24) +#define PIO_REHLSR_P25 (0x1u << 25) +#define PIO_REHLSR_P26 (0x1u << 26) +#define PIO_REHLSR_P27 (0x1u << 27) +#define PIO_REHLSR_P28 (0x1u << 28) +#define PIO_REHLSR_P29 (0x1u << 29) +#define PIO_REHLSR_P30 (0x1u << 30) +#define PIO_REHLSR_P31 (0x1u << 31) + +#define PIO_FRLHSR_P0 (0x1u << 0) +#define PIO_FRLHSR_P1 (0x1u << 1) +#define PIO_FRLHSR_P2 (0x1u << 2) +#define PIO_FRLHSR_P3 (0x1u << 3) +#define PIO_FRLHSR_P4 (0x1u << 4) +#define PIO_FRLHSR_P5 (0x1u << 5) +#define PIO_FRLHSR_P6 (0x1u << 6) +#define PIO_FRLHSR_P7 (0x1u << 7) +#define PIO_FRLHSR_P8 (0x1u << 8) +#define PIO_FRLHSR_P9 (0x1u << 9) +#define PIO_FRLHSR_P10 (0x1u << 10) +#define PIO_FRLHSR_P11 (0x1u << 11) +#define PIO_FRLHSR_P12 (0x1u << 12) +#define PIO_FRLHSR_P13 (0x1u << 13) +#define PIO_FRLHSR_P14 (0x1u << 14) +#define PIO_FRLHSR_P15 (0x1u << 15) +#define PIO_FRLHSR_P16 (0x1u << 16) +#define PIO_FRLHSR_P17 (0x1u << 17) +#define PIO_FRLHSR_P18 (0x1u << 18) +#define PIO_FRLHSR_P19 (0x1u << 19) +#define PIO_FRLHSR_P20 (0x1u << 20) +#define PIO_FRLHSR_P21 (0x1u << 21) +#define PIO_FRLHSR_P22 (0x1u << 22) +#define PIO_FRLHSR_P23 (0x1u << 23) +#define PIO_FRLHSR_P24 (0x1u << 24) +#define PIO_FRLHSR_P25 (0x1u << 25) +#define PIO_FRLHSR_P26 (0x1u << 26) +#define PIO_FRLHSR_P27 (0x1u << 27) +#define PIO_FRLHSR_P28 (0x1u << 28) +#define PIO_FRLHSR_P29 (0x1u << 29) +#define PIO_FRLHSR_P30 (0x1u << 30) +#define PIO_FRLHSR_P31 (0x1u << 31) + +#define PIO_LOCKSR_P0 (0x1u << 0) +#define PIO_LOCKSR_P1 (0x1u << 1) +#define PIO_LOCKSR_P2 (0x1u << 2) +#define PIO_LOCKSR_P3 (0x1u << 3) +#define PIO_LOCKSR_P4 (0x1u << 4) +#define PIO_LOCKSR_P5 (0x1u << 5) +#define PIO_LOCKSR_P6 (0x1u << 6) +#define PIO_LOCKSR_P7 (0x1u << 7) +#define PIO_LOCKSR_P8 (0x1u << 8) +#define PIO_LOCKSR_P9 (0x1u << 9) +#define PIO_LOCKSR_P10 (0x1u << 10) +#define PIO_LOCKSR_P11 (0x1u << 11) +#define PIO_LOCKSR_P12 (0x1u << 12) +#define PIO_LOCKSR_P13 (0x1u << 13) +#define PIO_LOCKSR_P14 (0x1u << 14) +#define PIO_LOCKSR_P15 (0x1u << 15) +#define PIO_LOCKSR_P16 (0x1u << 16) +#define PIO_LOCKSR_P17 (0x1u << 17) +#define PIO_LOCKSR_P18 (0x1u << 18) +#define PIO_LOCKSR_P19 (0x1u << 19) +#define PIO_LOCKSR_P20 (0x1u << 20) +#define PIO_LOCKSR_P21 (0x1u << 21) +#define PIO_LOCKSR_P22 (0x1u << 22) +#define PIO_LOCKSR_P23 (0x1u << 23) +#define PIO_LOCKSR_P24 (0x1u << 24) +#define PIO_LOCKSR_P25 (0x1u << 25) +#define PIO_LOCKSR_P26 (0x1u << 26) +#define PIO_LOCKSR_P27 (0x1u << 27) +#define PIO_LOCKSR_P28 (0x1u << 28) +#define PIO_LOCKSR_P29 (0x1u << 29) +#define PIO_LOCKSR_P30 (0x1u << 30) +#define PIO_LOCKSR_P31 (0x1u << 31) + +#define PIO_WPMR_WPEN (0x1u << 0) +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) + +#define PIO_WPSR_WPVS (0x1u << 0) +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) +# 252 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_pmc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_pmc.h" +#define _SAM3U_PMC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_pmc.h" +typedef struct { + WoReg PMC_SCER; + WoReg PMC_SCDR; + RoReg PMC_SCSR; + RoReg Reserved1[1]; + WoReg PMC_PCER0; + WoReg PMC_PCDR0; + RoReg PMC_PCSR0; + RwReg CKGR_UCKR; + RwReg CKGR_MOR; + RoReg CKGR_MCFR; + RwReg CKGR_PLLAR; + RoReg Reserved2[1]; + RwReg PMC_MCKR; + RoReg Reserved3[3]; + RwReg PMC_PCK[3]; + RoReg Reserved4[5]; + WoReg PMC_IER; + WoReg PMC_IDR; + RoReg PMC_SR; + RoReg PMC_IMR; + RwReg PMC_FSMR; + RwReg PMC_FSPR; + WoReg PMC_FOCR; + RoReg Reserved5[26]; + RwReg PMC_WPMR; + RoReg PMC_WPSR; +} Pmc; + + +#define PMC_SCER_PCK0 (0x1u << 8) +#define PMC_SCER_PCK1 (0x1u << 9) +#define PMC_SCER_PCK2 (0x1u << 10) + +#define PMC_SCDR_PCK0 (0x1u << 8) +#define PMC_SCDR_PCK1 (0x1u << 9) +#define PMC_SCDR_PCK2 (0x1u << 10) + +#define PMC_SCSR_PCK0 (0x1u << 8) +#define PMC_SCSR_PCK1 (0x1u << 9) +#define PMC_SCSR_PCK2 (0x1u << 10) + +#define PMC_PCER0_PID2 (0x1u << 2) +#define PMC_PCER0_PID3 (0x1u << 3) +#define PMC_PCER0_PID4 (0x1u << 4) +#define PMC_PCER0_PID5 (0x1u << 5) +#define PMC_PCER0_PID6 (0x1u << 6) +#define PMC_PCER0_PID7 (0x1u << 7) +#define PMC_PCER0_PID8 (0x1u << 8) +#define PMC_PCER0_PID9 (0x1u << 9) +#define PMC_PCER0_PID10 (0x1u << 10) +#define PMC_PCER0_PID11 (0x1u << 11) +#define PMC_PCER0_PID12 (0x1u << 12) +#define PMC_PCER0_PID13 (0x1u << 13) +#define PMC_PCER0_PID14 (0x1u << 14) +#define PMC_PCER0_PID15 (0x1u << 15) +#define PMC_PCER0_PID16 (0x1u << 16) +#define PMC_PCER0_PID18 (0x1u << 18) +#define PMC_PCER0_PID19 (0x1u << 19) +#define PMC_PCER0_PID20 (0x1u << 20) +#define PMC_PCER0_PID21 (0x1u << 21) +#define PMC_PCER0_PID22 (0x1u << 22) +#define PMC_PCER0_PID23 (0x1u << 23) +#define PMC_PCER0_PID24 (0x1u << 24) +#define PMC_PCER0_PID25 (0x1u << 25) +#define PMC_PCER0_PID26 (0x1u << 26) +#define PMC_PCER0_PID27 (0x1u << 27) +#define PMC_PCER0_PID28 (0x1u << 28) +#define PMC_PCER0_PID29 (0x1u << 29) + +#define PMC_PCDR0_PID2 (0x1u << 2) +#define PMC_PCDR0_PID3 (0x1u << 3) +#define PMC_PCDR0_PID4 (0x1u << 4) +#define PMC_PCDR0_PID5 (0x1u << 5) +#define PMC_PCDR0_PID6 (0x1u << 6) +#define PMC_PCDR0_PID7 (0x1u << 7) +#define PMC_PCDR0_PID8 (0x1u << 8) +#define PMC_PCDR0_PID9 (0x1u << 9) +#define PMC_PCDR0_PID10 (0x1u << 10) +#define PMC_PCDR0_PID11 (0x1u << 11) +#define PMC_PCDR0_PID12 (0x1u << 12) +#define PMC_PCDR0_PID13 (0x1u << 13) +#define PMC_PCDR0_PID14 (0x1u << 14) +#define PMC_PCDR0_PID15 (0x1u << 15) +#define PMC_PCDR0_PID16 (0x1u << 16) +#define PMC_PCDR0_PID18 (0x1u << 18) +#define PMC_PCDR0_PID19 (0x1u << 19) +#define PMC_PCDR0_PID20 (0x1u << 20) +#define PMC_PCDR0_PID21 (0x1u << 21) +#define PMC_PCDR0_PID22 (0x1u << 22) +#define PMC_PCDR0_PID23 (0x1u << 23) +#define PMC_PCDR0_PID24 (0x1u << 24) +#define PMC_PCDR0_PID25 (0x1u << 25) +#define PMC_PCDR0_PID26 (0x1u << 26) +#define PMC_PCDR0_PID27 (0x1u << 27) +#define PMC_PCDR0_PID28 (0x1u << 28) +#define PMC_PCDR0_PID29 (0x1u << 29) + +#define PMC_PCSR0_PID2 (0x1u << 2) +#define PMC_PCSR0_PID3 (0x1u << 3) +#define PMC_PCSR0_PID4 (0x1u << 4) +#define PMC_PCSR0_PID5 (0x1u << 5) +#define PMC_PCSR0_PID6 (0x1u << 6) +#define PMC_PCSR0_PID7 (0x1u << 7) +#define PMC_PCSR0_PID8 (0x1u << 8) +#define PMC_PCSR0_PID9 (0x1u << 9) +#define PMC_PCSR0_PID10 (0x1u << 10) +#define PMC_PCSR0_PID11 (0x1u << 11) +#define PMC_PCSR0_PID12 (0x1u << 12) +#define PMC_PCSR0_PID13 (0x1u << 13) +#define PMC_PCSR0_PID14 (0x1u << 14) +#define PMC_PCSR0_PID15 (0x1u << 15) +#define PMC_PCSR0_PID16 (0x1u << 16) +#define PMC_PCSR0_PID18 (0x1u << 18) +#define PMC_PCSR0_PID19 (0x1u << 19) +#define PMC_PCSR0_PID20 (0x1u << 20) +#define PMC_PCSR0_PID21 (0x1u << 21) +#define PMC_PCSR0_PID22 (0x1u << 22) +#define PMC_PCSR0_PID23 (0x1u << 23) +#define PMC_PCSR0_PID24 (0x1u << 24) +#define PMC_PCSR0_PID25 (0x1u << 25) +#define PMC_PCSR0_PID26 (0x1u << 26) +#define PMC_PCSR0_PID27 (0x1u << 27) +#define PMC_PCSR0_PID28 (0x1u << 28) +#define PMC_PCSR0_PID29 (0x1u << 29) + +#define CKGR_UCKR_UPLLEN (0x1u << 16) +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) + +#define CKGR_MOR_MOSCXTEN (0x1u << 0) +#define CKGR_MOR_MOSCXTBY (0x1u << 1) +#define CKGR_MOR_MOSCRCEN (0x1u << 3) +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_MOSCSEL (0x1u << 24) +#define CKGR_MOR_CFDEN (0x1u << 25) + +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) + +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) + +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) +#define PMC_MCKR_PLLADIV2 (0x1u << 12) +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) + +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) +#define PMC_PCK_CSS_MCK (0x4u << 0) +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) + +#define PMC_IER_MOSCXTS (0x1u << 0) +#define PMC_IER_LOCKA (0x1u << 1) +#define PMC_IER_MCKRDY (0x1u << 3) +#define PMC_IER_LOCKU (0x1u << 6) +#define PMC_IER_PCKRDY0 (0x1u << 8) +#define PMC_IER_PCKRDY1 (0x1u << 9) +#define PMC_IER_PCKRDY2 (0x1u << 10) +#define PMC_IER_MOSCSELS (0x1u << 16) +#define PMC_IER_MOSCRCS (0x1u << 17) +#define PMC_IER_CFDEV (0x1u << 18) + +#define PMC_IDR_MOSCXTS (0x1u << 0) +#define PMC_IDR_LOCKA (0x1u << 1) +#define PMC_IDR_MCKRDY (0x1u << 3) +#define PMC_IDR_LOCKU (0x1u << 6) +#define PMC_IDR_PCKRDY0 (0x1u << 8) +#define PMC_IDR_PCKRDY1 (0x1u << 9) +#define PMC_IDR_PCKRDY2 (0x1u << 10) +#define PMC_IDR_MOSCSELS (0x1u << 16) +#define PMC_IDR_MOSCRCS (0x1u << 17) +#define PMC_IDR_CFDEV (0x1u << 18) + +#define PMC_SR_MOSCXTS (0x1u << 0) +#define PMC_SR_LOCKA (0x1u << 1) +#define PMC_SR_MCKRDY (0x1u << 3) +#define PMC_SR_LOCKU (0x1u << 6) +#define PMC_SR_OSCSELS (0x1u << 7) +#define PMC_SR_PCKRDY0 (0x1u << 8) +#define PMC_SR_PCKRDY1 (0x1u << 9) +#define PMC_SR_PCKRDY2 (0x1u << 10) +#define PMC_SR_MOSCSELS (0x1u << 16) +#define PMC_SR_MOSCRCS (0x1u << 17) +#define PMC_SR_CFDEV (0x1u << 18) +#define PMC_SR_CFDS (0x1u << 19) +#define PMC_SR_FOS (0x1u << 20) + +#define PMC_IMR_MOSCXTS (0x1u << 0) +#define PMC_IMR_LOCKA (0x1u << 1) +#define PMC_IMR_MCKRDY (0x1u << 3) +#define PMC_IMR_LOCKU (0x1u << 6) +#define PMC_IMR_PCKRDY0 (0x1u << 8) +#define PMC_IMR_PCKRDY1 (0x1u << 9) +#define PMC_IMR_PCKRDY2 (0x1u << 10) +#define PMC_IMR_MOSCSELS (0x1u << 16) +#define PMC_IMR_MOSCRCS (0x1u << 17) +#define PMC_IMR_CFDEV (0x1u << 18) + +#define PMC_FSMR_FSTT0 (0x1u << 0) +#define PMC_FSMR_FSTT1 (0x1u << 1) +#define PMC_FSMR_FSTT2 (0x1u << 2) +#define PMC_FSMR_FSTT3 (0x1u << 3) +#define PMC_FSMR_FSTT4 (0x1u << 4) +#define PMC_FSMR_FSTT5 (0x1u << 5) +#define PMC_FSMR_FSTT6 (0x1u << 6) +#define PMC_FSMR_FSTT7 (0x1u << 7) +#define PMC_FSMR_FSTT8 (0x1u << 8) +#define PMC_FSMR_FSTT9 (0x1u << 9) +#define PMC_FSMR_FSTT10 (0x1u << 10) +#define PMC_FSMR_FSTT11 (0x1u << 11) +#define PMC_FSMR_FSTT12 (0x1u << 12) +#define PMC_FSMR_FSTT13 (0x1u << 13) +#define PMC_FSMR_FSTT14 (0x1u << 14) +#define PMC_FSMR_FSTT15 (0x1u << 15) +#define PMC_FSMR_RTTAL (0x1u << 16) +#define PMC_FSMR_RTCAL (0x1u << 17) +#define PMC_FSMR_USBAL (0x1u << 18) +#define PMC_FSMR_LPM (0x1u << 20) + +#define PMC_FSPR_FSTP0 (0x1u << 0) +#define PMC_FSPR_FSTP1 (0x1u << 1) +#define PMC_FSPR_FSTP2 (0x1u << 2) +#define PMC_FSPR_FSTP3 (0x1u << 3) +#define PMC_FSPR_FSTP4 (0x1u << 4) +#define PMC_FSPR_FSTP5 (0x1u << 5) +#define PMC_FSPR_FSTP6 (0x1u << 6) +#define PMC_FSPR_FSTP7 (0x1u << 7) +#define PMC_FSPR_FSTP8 (0x1u << 8) +#define PMC_FSPR_FSTP9 (0x1u << 9) +#define PMC_FSPR_FSTP10 (0x1u << 10) +#define PMC_FSPR_FSTP11 (0x1u << 11) +#define PMC_FSPR_FSTP12 (0x1u << 12) +#define PMC_FSPR_FSTP13 (0x1u << 13) +#define PMC_FSPR_FSTP14 (0x1u << 14) +#define PMC_FSPR_FSTP15 (0x1u << 15) + +#define PMC_FOCR_FOCLR (0x1u << 0) + +#define PMC_WPMR_WPEN (0x1u << 0) +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) + +#define PMC_WPSR_WPVS (0x1u << 0) +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) +# 253 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_pwm.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_pwm.h" +#define _SAM3U_PWM_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_pwm.h" +typedef struct { + RwReg PWM_CMR; + RwReg PWM_CDTY; + RwReg PWM_CDTYUPD; + RwReg PWM_CPRD; + RwReg PWM_CPRDUPD; + RwReg PWM_CCNT; + RwReg PWM_DT; + RwReg PWM_DTUPD; +} PwmCh_num; + +typedef struct { + RwReg PWM_CMPV; + RwReg PWM_CMPVUPD; + RwReg PWM_CMPM; + RwReg PWM_CMPMUPD; +} PwmCmp; + +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + RwReg PWM_CLK; + WoReg PWM_ENA; + WoReg PWM_DIS; + RoReg PWM_SR; + WoReg PWM_IER1; + WoReg PWM_IDR1; + RoReg PWM_IMR1; + RoReg PWM_ISR1; + RwReg PWM_SCM; + RoReg Reserved1[1]; + RwReg PWM_SCUC; + RwReg PWM_SCUP; + WoReg PWM_SCUPUPD; + WoReg PWM_IER2; + WoReg PWM_IDR2; + RoReg PWM_IMR2; + RoReg PWM_ISR2; + RwReg PWM_OOV; + RwReg PWM_OS; + WoReg PWM_OSS; + WoReg PWM_OSC; + WoReg PWM_OSSUPD; + WoReg PWM_OSCUPD; + RwReg PWM_FMR; + RoReg PWM_FSR; + WoReg PWM_FCR; + RwReg PWM_FPV; + RwReg PWM_FPE; + RoReg Reserved2[3]; + RwReg PWM_ELMR[2]; + RoReg Reserved3[24]; + WoReg PWM_WPCR; + RoReg PWM_WPSR; + RoReg Reserved4[7]; + RwReg PWM_TPR; + RwReg PWM_TCR; + RoReg Reserved5[2]; + RwReg PWM_TNPR; + RwReg PWM_TNCR; + WoReg PWM_PTCR; + RoReg PWM_PTSR; + RoReg Reserved6[2]; + PwmCmp PWM_CMP[8]; + RoReg Reserved7[20]; + PwmCh_num PWM_CH_NUM[4]; +} Pwm; + + +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) + +#define PWM_ENA_CHID0 (0x1u << 0) +#define PWM_ENA_CHID1 (0x1u << 1) +#define PWM_ENA_CHID2 (0x1u << 2) +#define PWM_ENA_CHID3 (0x1u << 3) + +#define PWM_DIS_CHID0 (0x1u << 0) +#define PWM_DIS_CHID1 (0x1u << 1) +#define PWM_DIS_CHID2 (0x1u << 2) +#define PWM_DIS_CHID3 (0x1u << 3) + +#define PWM_SR_CHID0 (0x1u << 0) +#define PWM_SR_CHID1 (0x1u << 1) +#define PWM_SR_CHID2 (0x1u << 2) +#define PWM_SR_CHID3 (0x1u << 3) + +#define PWM_IER1_CHID0 (0x1u << 0) +#define PWM_IER1_CHID1 (0x1u << 1) +#define PWM_IER1_CHID2 (0x1u << 2) +#define PWM_IER1_CHID3 (0x1u << 3) +#define PWM_IER1_FCHID0 (0x1u << 16) +#define PWM_IER1_FCHID1 (0x1u << 17) +#define PWM_IER1_FCHID2 (0x1u << 18) +#define PWM_IER1_FCHID3 (0x1u << 19) + +#define PWM_IDR1_CHID0 (0x1u << 0) +#define PWM_IDR1_CHID1 (0x1u << 1) +#define PWM_IDR1_CHID2 (0x1u << 2) +#define PWM_IDR1_CHID3 (0x1u << 3) +#define PWM_IDR1_FCHID0 (0x1u << 16) +#define PWM_IDR1_FCHID1 (0x1u << 17) +#define PWM_IDR1_FCHID2 (0x1u << 18) +#define PWM_IDR1_FCHID3 (0x1u << 19) + +#define PWM_IMR1_CHID0 (0x1u << 0) +#define PWM_IMR1_CHID1 (0x1u << 1) +#define PWM_IMR1_CHID2 (0x1u << 2) +#define PWM_IMR1_CHID3 (0x1u << 3) +#define PWM_IMR1_FCHID0 (0x1u << 16) +#define PWM_IMR1_FCHID1 (0x1u << 17) +#define PWM_IMR1_FCHID2 (0x1u << 18) +#define PWM_IMR1_FCHID3 (0x1u << 19) + +#define PWM_ISR1_CHID0 (0x1u << 0) +#define PWM_ISR1_CHID1 (0x1u << 1) +#define PWM_ISR1_CHID2 (0x1u << 2) +#define PWM_ISR1_CHID3 (0x1u << 3) +#define PWM_ISR1_FCHID0 (0x1u << 16) +#define PWM_ISR1_FCHID1 (0x1u << 17) +#define PWM_ISR1_FCHID2 (0x1u << 18) +#define PWM_ISR1_FCHID3 (0x1u << 19) + +#define PWM_SCM_SYNC0 (0x1u << 0) +#define PWM_SCM_SYNC1 (0x1u << 1) +#define PWM_SCM_SYNC2 (0x1u << 2) +#define PWM_SCM_SYNC3 (0x1u << 3) +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) +#define PWM_SCM_PTRM (0x1u << 20) +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) + +#define PWM_SCUC_UPDULOCK (0x1u << 0) + +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) + +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) + +#define PWM_IER2_WRDY (0x1u << 0) +#define PWM_IER2_ENDTX (0x1u << 1) +#define PWM_IER2_TXBUFE (0x1u << 2) +#define PWM_IER2_UNRE (0x1u << 3) +#define PWM_IER2_CMPM0 (0x1u << 8) +#define PWM_IER2_CMPM1 (0x1u << 9) +#define PWM_IER2_CMPM2 (0x1u << 10) +#define PWM_IER2_CMPM3 (0x1u << 11) +#define PWM_IER2_CMPM4 (0x1u << 12) +#define PWM_IER2_CMPM5 (0x1u << 13) +#define PWM_IER2_CMPM6 (0x1u << 14) +#define PWM_IER2_CMPM7 (0x1u << 15) +#define PWM_IER2_CMPU0 (0x1u << 16) +#define PWM_IER2_CMPU1 (0x1u << 17) +#define PWM_IER2_CMPU2 (0x1u << 18) +#define PWM_IER2_CMPU3 (0x1u << 19) +#define PWM_IER2_CMPU4 (0x1u << 20) +#define PWM_IER2_CMPU5 (0x1u << 21) +#define PWM_IER2_CMPU6 (0x1u << 22) +#define PWM_IER2_CMPU7 (0x1u << 23) + +#define PWM_IDR2_WRDY (0x1u << 0) +#define PWM_IDR2_ENDTX (0x1u << 1) +#define PWM_IDR2_TXBUFE (0x1u << 2) +#define PWM_IDR2_UNRE (0x1u << 3) +#define PWM_IDR2_CMPM0 (0x1u << 8) +#define PWM_IDR2_CMPM1 (0x1u << 9) +#define PWM_IDR2_CMPM2 (0x1u << 10) +#define PWM_IDR2_CMPM3 (0x1u << 11) +#define PWM_IDR2_CMPM4 (0x1u << 12) +#define PWM_IDR2_CMPM5 (0x1u << 13) +#define PWM_IDR2_CMPM6 (0x1u << 14) +#define PWM_IDR2_CMPM7 (0x1u << 15) +#define PWM_IDR2_CMPU0 (0x1u << 16) +#define PWM_IDR2_CMPU1 (0x1u << 17) +#define PWM_IDR2_CMPU2 (0x1u << 18) +#define PWM_IDR2_CMPU3 (0x1u << 19) +#define PWM_IDR2_CMPU4 (0x1u << 20) +#define PWM_IDR2_CMPU5 (0x1u << 21) +#define PWM_IDR2_CMPU6 (0x1u << 22) +#define PWM_IDR2_CMPU7 (0x1u << 23) + +#define PWM_IMR2_WRDY (0x1u << 0) +#define PWM_IMR2_ENDTX (0x1u << 1) +#define PWM_IMR2_TXBUFE (0x1u << 2) +#define PWM_IMR2_UNRE (0x1u << 3) +#define PWM_IMR2_CMPM0 (0x1u << 8) +#define PWM_IMR2_CMPM1 (0x1u << 9) +#define PWM_IMR2_CMPM2 (0x1u << 10) +#define PWM_IMR2_CMPM3 (0x1u << 11) +#define PWM_IMR2_CMPM4 (0x1u << 12) +#define PWM_IMR2_CMPM5 (0x1u << 13) +#define PWM_IMR2_CMPM6 (0x1u << 14) +#define PWM_IMR2_CMPM7 (0x1u << 15) +#define PWM_IMR2_CMPU0 (0x1u << 16) +#define PWM_IMR2_CMPU1 (0x1u << 17) +#define PWM_IMR2_CMPU2 (0x1u << 18) +#define PWM_IMR2_CMPU3 (0x1u << 19) +#define PWM_IMR2_CMPU4 (0x1u << 20) +#define PWM_IMR2_CMPU5 (0x1u << 21) +#define PWM_IMR2_CMPU6 (0x1u << 22) +#define PWM_IMR2_CMPU7 (0x1u << 23) + +#define PWM_ISR2_WRDY (0x1u << 0) +#define PWM_ISR2_ENDTX (0x1u << 1) +#define PWM_ISR2_TXBUFE (0x1u << 2) +#define PWM_ISR2_UNRE (0x1u << 3) +#define PWM_ISR2_CMPM0 (0x1u << 8) +#define PWM_ISR2_CMPM1 (0x1u << 9) +#define PWM_ISR2_CMPM2 (0x1u << 10) +#define PWM_ISR2_CMPM3 (0x1u << 11) +#define PWM_ISR2_CMPM4 (0x1u << 12) +#define PWM_ISR2_CMPM5 (0x1u << 13) +#define PWM_ISR2_CMPM6 (0x1u << 14) +#define PWM_ISR2_CMPM7 (0x1u << 15) +#define PWM_ISR2_CMPU0 (0x1u << 16) +#define PWM_ISR2_CMPU1 (0x1u << 17) +#define PWM_ISR2_CMPU2 (0x1u << 18) +#define PWM_ISR2_CMPU3 (0x1u << 19) +#define PWM_ISR2_CMPU4 (0x1u << 20) +#define PWM_ISR2_CMPU5 (0x1u << 21) +#define PWM_ISR2_CMPU6 (0x1u << 22) +#define PWM_ISR2_CMPU7 (0x1u << 23) + +#define PWM_OOV_OOVH0 (0x1u << 0) +#define PWM_OOV_OOVH1 (0x1u << 1) +#define PWM_OOV_OOVH2 (0x1u << 2) +#define PWM_OOV_OOVH3 (0x1u << 3) +#define PWM_OOV_OOVL0 (0x1u << 16) +#define PWM_OOV_OOVL1 (0x1u << 17) +#define PWM_OOV_OOVL2 (0x1u << 18) +#define PWM_OOV_OOVL3 (0x1u << 19) + +#define PWM_OS_OSH0 (0x1u << 0) +#define PWM_OS_OSH1 (0x1u << 1) +#define PWM_OS_OSH2 (0x1u << 2) +#define PWM_OS_OSH3 (0x1u << 3) +#define PWM_OS_OSL0 (0x1u << 16) +#define PWM_OS_OSL1 (0x1u << 17) +#define PWM_OS_OSL2 (0x1u << 18) +#define PWM_OS_OSL3 (0x1u << 19) + +#define PWM_OSS_OSSH0 (0x1u << 0) +#define PWM_OSS_OSSH1 (0x1u << 1) +#define PWM_OSS_OSSH2 (0x1u << 2) +#define PWM_OSS_OSSH3 (0x1u << 3) +#define PWM_OSS_OSSL0 (0x1u << 16) +#define PWM_OSS_OSSL1 (0x1u << 17) +#define PWM_OSS_OSSL2 (0x1u << 18) +#define PWM_OSS_OSSL3 (0x1u << 19) + +#define PWM_OSC_OSCH0 (0x1u << 0) +#define PWM_OSC_OSCH1 (0x1u << 1) +#define PWM_OSC_OSCH2 (0x1u << 2) +#define PWM_OSC_OSCH3 (0x1u << 3) +#define PWM_OSC_OSCL0 (0x1u << 16) +#define PWM_OSC_OSCL1 (0x1u << 17) +#define PWM_OSC_OSCL2 (0x1u << 18) +#define PWM_OSC_OSCL3 (0x1u << 19) + +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) + +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) + +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) + +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) + +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) + +#define PWM_FPV_FPVH0 (0x1u << 0) +#define PWM_FPV_FPVH1 (0x1u << 1) +#define PWM_FPV_FPVH2 (0x1u << 2) +#define PWM_FPV_FPVH3 (0x1u << 3) +#define PWM_FPV_FPVL0 (0x1u << 16) +#define PWM_FPV_FPVL1 (0x1u << 17) +#define PWM_FPV_FPVL2 (0x1u << 18) +#define PWM_FPV_FPVL3 (0x1u << 19) + +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) + +#define PWM_ELMR_CSEL0 (0x1u << 0) +#define PWM_ELMR_CSEL1 (0x1u << 1) +#define PWM_ELMR_CSEL2 (0x1u << 2) +#define PWM_ELMR_CSEL3 (0x1u << 3) +#define PWM_ELMR_CSEL4 (0x1u << 4) +#define PWM_ELMR_CSEL5 (0x1u << 5) +#define PWM_ELMR_CSEL6 (0x1u << 6) +#define PWM_ELMR_CSEL7 (0x1u << 7) + +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPRG0 (0x1u << 2) +#define PWM_WPCR_WPRG1 (0x1u << 3) +#define PWM_WPCR_WPRG2 (0x1u << 4) +#define PWM_WPCR_WPRG3 (0x1u << 5) +#define PWM_WPCR_WPRG4 (0x1u << 6) +#define PWM_WPCR_WPRG5 (0x1u << 7) +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) + +#define PWM_WPSR_WPSWS0 (0x1u << 0) +#define PWM_WPSR_WPSWS1 (0x1u << 1) +#define PWM_WPSR_WPSWS2 (0x1u << 2) +#define PWM_WPSR_WPSWS3 (0x1u << 3) +#define PWM_WPSR_WPSWS4 (0x1u << 4) +#define PWM_WPSR_WPSWS5 (0x1u << 5) +#define PWM_WPSR_WPVS (0x1u << 7) +#define PWM_WPSR_WPHWS0 (0x1u << 8) +#define PWM_WPSR_WPHWS1 (0x1u << 9) +#define PWM_WPSR_WPHWS2 (0x1u << 10) +#define PWM_WPSR_WPHWS3 (0x1u << 11) +#define PWM_WPSR_WPHWS4 (0x1u << 12) +#define PWM_WPSR_WPHWS5 (0x1u << 13) +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) + +#define PWM_TPR_TXPTR_Pos 0 +#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) +#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos))) + +#define PWM_TCR_TXCTR_Pos 0 +#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) +#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos))) + +#define PWM_TNPR_TXNPTR_Pos 0 +#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) +#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos))) + +#define PWM_TNCR_TXNCTR_Pos 0 +#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) +#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos))) + +#define PWM_PTCR_RXTEN (0x1u << 0) +#define PWM_PTCR_RXTDIS (0x1u << 1) +#define PWM_PTCR_TXTEN (0x1u << 8) +#define PWM_PTCR_TXTDIS (0x1u << 9) + +#define PWM_PTSR_RXTEN (0x1u << 0) +#define PWM_PTSR_TXTEN (0x1u << 8) + +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) + +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) + +#define PWM_CMPM_CEN (0x1u << 0) +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) + +#define PWM_CMPMUPD_CENUPD (0x1u << 0) +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) + +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) +#define PWM_CMR_CPRE_MCK (0x0u << 0) +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) +#define PWM_CMR_CPRE_CLKA (0xBu << 0) +#define PWM_CMR_CPRE_CLKB (0xCu << 0) +#define PWM_CMR_CALG (0x1u << 8) +#define PWM_CMR_CPOL (0x1u << 9) +#define PWM_CMR_CES (0x1u << 10) +#define PWM_CMR_DTE (0x1u << 16) +#define PWM_CMR_DTHI (0x1u << 17) +#define PWM_CMR_DTLI (0x1u << 18) + +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) + +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) + +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) + +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) + +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) + +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) + +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +# 254 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_rstc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_rstc.h" +#define _SAM3U_RSTC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_rstc.h" +typedef struct { + WoReg RSTC_CR; + RoReg RSTC_SR; + RwReg RSTC_MR; +} Rstc; + + +#define RSTC_CR_PROCRST (0x1u << 0) +#define RSTC_CR_PERRST (0x1u << 2) +#define RSTC_CR_EXTRST (0x1u << 3) +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) + +#define RSTC_SR_URSTS (0x1u << 0) +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) +#define RSTC_SR_NRSTL (0x1u << 16) +#define RSTC_SR_SRCMP (0x1u << 17) + +#define RSTC_MR_URSTEN (0x1u << 0) +#define RSTC_MR_URSTIEN (0x1u << 4) +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +# 255 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_rtc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_rtc.h" +#define _SAM3U_RTC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_rtc.h" +typedef struct { + RwReg RTC_CR; + RwReg RTC_MR; + RwReg RTC_TIMR; + RwReg RTC_CALR; + RwReg RTC_TIMALR; + RwReg RTC_CALALR; + RoReg RTC_SR; + WoReg RTC_SCCR; + WoReg RTC_IER; + WoReg RTC_IDR; + RoReg RTC_IMR; + RoReg RTC_VER; + RoReg Reserved1[45]; + RwReg RTC_WPMR; +} Rtc; + + +#define RTC_CR_UPDTIM (0x1u << 0) +#define RTC_CR_UPDCAL (0x1u << 1) +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) + +#define RTC_MR_HRMOD (0x1u << 0) + +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) + +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) + +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) +#define RTC_TIMALR_HOUREN (0x1u << 23) + +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) + +#define RTC_SR_ACKUPD (0x1u << 0) +#define RTC_SR_ALARM (0x1u << 1) +#define RTC_SR_SEC (0x1u << 2) +#define RTC_SR_TIMEV (0x1u << 3) +#define RTC_SR_CALEV (0x1u << 4) + +#define RTC_SCCR_ACKCLR (0x1u << 0) +#define RTC_SCCR_ALRCLR (0x1u << 1) +#define RTC_SCCR_SECCLR (0x1u << 2) +#define RTC_SCCR_TIMCLR (0x1u << 3) +#define RTC_SCCR_CALCLR (0x1u << 4) + +#define RTC_IER_ACKEN (0x1u << 0) +#define RTC_IER_ALREN (0x1u << 1) +#define RTC_IER_SECEN (0x1u << 2) +#define RTC_IER_TIMEN (0x1u << 3) +#define RTC_IER_CALEN (0x1u << 4) + +#define RTC_IDR_ACKDIS (0x1u << 0) +#define RTC_IDR_ALRDIS (0x1u << 1) +#define RTC_IDR_SECDIS (0x1u << 2) +#define RTC_IDR_TIMDIS (0x1u << 3) +#define RTC_IDR_CALDIS (0x1u << 4) + +#define RTC_IMR_ACK (0x1u << 0) +#define RTC_IMR_ALR (0x1u << 1) +#define RTC_IMR_SEC (0x1u << 2) +#define RTC_IMR_TIM (0x1u << 3) +#define RTC_IMR_CAL (0x1u << 4) + +#define RTC_VER_NVTIM (0x1u << 0) +#define RTC_VER_NVCAL (0x1u << 1) +#define RTC_VER_NVTIMALR (0x1u << 2) +#define RTC_VER_NVCALALR (0x1u << 3) + +#define RTC_WPMR_WPEN (0x1u << 0) +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +# 256 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_rtt.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_rtt.h" +#define _SAM3U_RTT_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_rtt.h" +typedef struct { + RwReg RTT_MR; + RwReg RTT_AR; + RoReg RTT_VR; + RoReg RTT_SR; +} Rtt; + + +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) +#define RTT_MR_RTTINCIEN (0x1u << 17) +#define RTT_MR_RTTRST (0x1u << 18) + +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) + +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) + +#define RTT_SR_ALMS (0x1u << 0) +#define RTT_SR_RTTINC (0x1u << 1) +# 257 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_smc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_smc.h" +#define _SAM3U_SMC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_smc.h" +typedef struct { + RwReg SMC_SETUP; + RwReg SMC_PULSE; + RwReg SMC_CYCLE; + RwReg SMC_TIMINGS; + RwReg SMC_MODE; +} SmcCs_number; + +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + RwReg SMC_CFG; + WoReg SMC_CTRL; + RoReg SMC_SR; + WoReg SMC_IER; + WoReg SMC_IDR; + RoReg SMC_IMR; + RwReg SMC_ADDR; + RwReg SMC_BANK; + WoReg SMC_ECC_CTRL; + RwReg SMC_ECC_MD; + RoReg SMC_ECC_SR1; + RoReg SMC_ECC_PR0; + RoReg SMC_ECC_PR1; + RoReg SMC_ECC_SR2; + RoReg SMC_ECC_PR2; + RoReg SMC_ECC_PR3; + RoReg SMC_ECC_PR4; + RoReg SMC_ECC_PR5; + RoReg SMC_ECC_PR6; + RoReg SMC_ECC_PR7; + RoReg SMC_ECC_PR8; + RoReg SMC_ECC_PR9; + RoReg SMC_ECC_PR10; + RoReg SMC_ECC_PR11; + RoReg SMC_ECC_PR12; + RoReg SMC_ECC_PR13; + RoReg SMC_ECC_PR14; + RoReg SMC_ECC_PR15; + SmcCs_number SMC_CS_NUMBER[4]; + RoReg Reserved1[20]; + RwReg SMC_OCMS; + WoReg SMC_KEY1; + WoReg SMC_KEY2; + RoReg Reserved2[50]; + WoReg SMC_WPCR; + RoReg SMC_WPSR; +} Smc; + + +#define SMC_CFG_PAGESIZE_Pos 0 +#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) +#define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) +#define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) +#define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) +#define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) +#define SMC_CFG_WSPARE (0x1u << 8) +#define SMC_CFG_RSPARE (0x1u << 9) +#define SMC_CFG_EDGECTRL (0x1u << 12) +#define SMC_CFG_RBEDGE (0x1u << 13) +#define SMC_CFG_DTOCYC_Pos 16 +#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) +#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos))) +#define SMC_CFG_DTOMUL_Pos 20 +#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) +#define SMC_CFG_DTOMUL_X1 (0x0u << 20) +#define SMC_CFG_DTOMUL_X16 (0x1u << 20) +#define SMC_CFG_DTOMUL_X128 (0x2u << 20) +#define SMC_CFG_DTOMUL_X256 (0x3u << 20) +#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) +#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) +#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) +#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) + +#define SMC_CTRL_NFCEN (0x1u << 0) +#define SMC_CTRL_NFCDIS (0x1u << 1) + +#define SMC_SR_SMCSTS (0x1u << 0) +#define SMC_SR_RB_RISE (0x1u << 4) +#define SMC_SR_RB_FALL (0x1u << 5) +#define SMC_SR_NFCBUSY (0x1u << 8) +#define SMC_SR_NFCWR (0x1u << 11) +#define SMC_SR_NFCSID_Pos 12 +#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) +#define SMC_SR_XFRDONE (0x1u << 16) +#define SMC_SR_CMDDONE (0x1u << 17) +#define SMC_SR_DTOE (0x1u << 20) +#define SMC_SR_UNDEF (0x1u << 21) +#define SMC_SR_AWB (0x1u << 22) +#define SMC_SR_NFCASE (0x1u << 23) +#define SMC_SR_RB_EDGE0 (0x1u << 24) + +#define SMC_IER_RB_RISE (0x1u << 4) +#define SMC_IER_RB_FALL (0x1u << 5) +#define SMC_IER_XFRDONE (0x1u << 16) +#define SMC_IER_CMDDONE (0x1u << 17) +#define SMC_IER_DTOE (0x1u << 20) +#define SMC_IER_UNDEF (0x1u << 21) +#define SMC_IER_AWB (0x1u << 22) +#define SMC_IER_NFCASE (0x1u << 23) +#define SMC_IER_RB_EDGE0 (0x1u << 24) + +#define SMC_IDR_RB_RISE (0x1u << 4) +#define SMC_IDR_RB_FALL (0x1u << 5) +#define SMC_IDR_XFRDONE (0x1u << 16) +#define SMC_IDR_CMDDONE (0x1u << 17) +#define SMC_IDR_DTOE (0x1u << 20) +#define SMC_IDR_UNDEF (0x1u << 21) +#define SMC_IDR_AWB (0x1u << 22) +#define SMC_IDR_NFCASE (0x1u << 23) +#define SMC_IDR_RB_EDGE0 (0x1u << 24) + +#define SMC_IMR_RB_RISE (0x1u << 4) +#define SMC_IMR_RB_FALL (0x1u << 5) +#define SMC_IMR_XFRDONE (0x1u << 16) +#define SMC_IMR_CMDDONE (0x1u << 17) +#define SMC_IMR_DTOE (0x1u << 20) +#define SMC_IMR_UNDEF (0x1u << 21) +#define SMC_IMR_AWB (0x1u << 22) +#define SMC_IMR_NFCASE (0x1u << 23) +#define SMC_IMR_RB_EDGE0 (0x1u << 24) + +#define SMC_ADDR_ADDR_CYCLE0_Pos 0 +#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) +#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos))) + +#define SMC_BANK_BANK_Pos 0 +#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) +#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos))) + +#define SMC_ECC_CTRL_RST (0x1u << 0) +#define SMC_ECC_CTRL_SWRST (0x1u << 1) + +#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0 +#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) +#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) +#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) +#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) +#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) +#define SMC_ECC_MD_TYPCORREC_Pos 4 +#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) +#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) +#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) +#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) + +#define SMC_ECC_SR1_RECERR0 (0x1u << 0) +#define SMC_ECC_SR1_ECCERR0_Pos 1 +#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) +#define SMC_ECC_SR1_RECERR1 (0x1u << 4) +#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) +#define SMC_ECC_SR1_MULERR1 (0x1u << 6) +#define SMC_ECC_SR1_RECERR2 (0x1u << 8) +#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) +#define SMC_ECC_SR1_MULERR2 (0x1u << 10) +#define SMC_ECC_SR1_RECERR3 (0x1u << 12) +#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) +#define SMC_ECC_SR1_MULERR3 (0x1u << 14) +#define SMC_ECC_SR1_RECERR4 (0x1u << 16) +#define SMC_ECC_SR1_ECCERR4_Pos 17 +#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) +#define SMC_ECC_SR1_RECERR5 (0x1u << 20) +#define SMC_ECC_SR1_ECCERR5_Pos 21 +#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) +#define SMC_ECC_SR1_RECERR6 (0x1u << 24) +#define SMC_ECC_SR1_ECCERR6_Pos 25 +#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) +#define SMC_ECC_SR1_RECERR7 (0x1u << 28) +#define SMC_ECC_SR1_ECCERR7_Pos 29 +#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) + +#define SMC_ECC_PR0_BITADDR_Pos 0 +#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) +#define SMC_ECC_PR0_WORDADDR_Pos 4 +#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) +#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0 +#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) +#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3 +#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) +#define SMC_ECC_PR0_NPARITY_Pos 12 +#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) +#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0 +#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) +#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR1_NPARITY_Pos 0 +#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) +#define SMC_ECC_PR1_BITADDR_Pos 0 +#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) +#define SMC_ECC_PR1_WORDADDR_Pos 3 +#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) +#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12 +#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) +#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) + +#define SMC_ECC_SR2_RECERR8 (0x1u << 0) +#define SMC_ECC_SR2_ECCERR8_Pos 1 +#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) +#define SMC_ECC_SR2_RECERR9 (0x1u << 4) +#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) +#define SMC_ECC_SR2_MULERR9 (0x1u << 6) +#define SMC_ECC_SR2_RECERR10 (0x1u << 8) +#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) +#define SMC_ECC_SR2_MULERR10 (0x1u << 10) +#define SMC_ECC_SR2_RECERR11 (0x1u << 12) +#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) +#define SMC_ECC_SR2_MULERR11 (0x1u << 14) +#define SMC_ECC_SR2_RECERR12 (0x1u << 16) +#define SMC_ECC_SR2_ECCERR12_Pos 17 +#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) +#define SMC_ECC_SR2_RECERR13 (0x1u << 20) +#define SMC_ECC_SR2_ECCERR13_Pos 21 +#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) +#define SMC_ECC_SR2_RECERR14 (0x1u << 24) +#define SMC_ECC_SR2_ECCERR14_Pos 25 +#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) +#define SMC_ECC_SR2_RECERR15 (0x1u << 28) +#define SMC_ECC_SR2_ECCERR15_Pos 29 +#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) + +#define SMC_ECC_PR2_BITADDR_Pos 0 +#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) +#define SMC_ECC_PR2_WORDADDR_Pos 3 +#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) +#define SMC_ECC_PR2_NPARITY_Pos 12 +#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) +#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR3_BITADDR_Pos 0 +#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) +#define SMC_ECC_PR3_WORDADDR_Pos 3 +#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) +#define SMC_ECC_PR3_NPARITY_Pos 12 +#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) +#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR4_BITADDR_Pos 0 +#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) +#define SMC_ECC_PR4_WORDADDR_Pos 3 +#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) +#define SMC_ECC_PR4_NPARITY_Pos 12 +#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) +#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR5_BITADDR_Pos 0 +#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) +#define SMC_ECC_PR5_WORDADDR_Pos 3 +#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) +#define SMC_ECC_PR5_NPARITY_Pos 12 +#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) +#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR6_BITADDR_Pos 0 +#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) +#define SMC_ECC_PR6_WORDADDR_Pos 3 +#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) +#define SMC_ECC_PR6_NPARITY_Pos 12 +#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) +#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR7_BITADDR_Pos 0 +#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) +#define SMC_ECC_PR7_WORDADDR_Pos 3 +#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) +#define SMC_ECC_PR7_NPARITY_Pos 12 +#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) +#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) +#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) + +#define SMC_ECC_PR8_BITADDR_Pos 0 +#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) +#define SMC_ECC_PR8_WORDADDR_Pos 3 +#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) +#define SMC_ECC_PR8_NPARITY_Pos 12 +#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) + +#define SMC_ECC_PR9_BITADDR_Pos 0 +#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) +#define SMC_ECC_PR9_WORDADDR_Pos 3 +#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) +#define SMC_ECC_PR9_NPARITY_Pos 12 +#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) + +#define SMC_ECC_PR10_BITADDR_Pos 0 +#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) +#define SMC_ECC_PR10_WORDADDR_Pos 3 +#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) +#define SMC_ECC_PR10_NPARITY_Pos 12 +#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) + +#define SMC_ECC_PR11_BITADDR_Pos 0 +#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) +#define SMC_ECC_PR11_WORDADDR_Pos 3 +#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) +#define SMC_ECC_PR11_NPARITY_Pos 12 +#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) + +#define SMC_ECC_PR12_BITADDR_Pos 0 +#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) +#define SMC_ECC_PR12_WORDADDR_Pos 3 +#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) +#define SMC_ECC_PR12_NPARITY_Pos 12 +#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) + +#define SMC_ECC_PR13_BITADDR_Pos 0 +#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) +#define SMC_ECC_PR13_WORDADDR_Pos 3 +#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) +#define SMC_ECC_PR13_NPARITY_Pos 12 +#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) + +#define SMC_ECC_PR14_BITADDR_Pos 0 +#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) +#define SMC_ECC_PR14_WORDADDR_Pos 3 +#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) +#define SMC_ECC_PR14_NPARITY_Pos 12 +#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) + +#define SMC_ECC_PR15_BITADDR_Pos 0 +#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) +#define SMC_ECC_PR15_WORDADDR_Pos 3 +#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) +#define SMC_ECC_PR15_NPARITY_Pos 12 +#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) + +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) + +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) + +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) + +#define SMC_TIMINGS_TCLR_Pos 0 +#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) +#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos))) +#define SMC_TIMINGS_TADL_Pos 4 +#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) +#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos))) +#define SMC_TIMINGS_TAR_Pos 8 +#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) +#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos))) +#define SMC_TIMINGS_OCMS (0x1u << 12) +#define SMC_TIMINGS_TRR_Pos 16 +#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) +#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos))) +#define SMC_TIMINGS_TWB_Pos 24 +#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) +#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos))) +#define SMC_TIMINGS_RBNSEL_Pos 28 +#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) +#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos))) +#define SMC_TIMINGS_NFSEL (0x1u << 31) + +#define SMC_MODE_READ_MODE (0x1u << 0) +#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) +#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) +#define SMC_MODE_WRITE_MODE (0x1u << 1) +#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) +#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) +#define SMC_MODE_BAT (0x1u << 8) +#define SMC_MODE_DBW (0x1u << 12) +#define SMC_MODE_DBW_BIT_8 (0x0u << 12) +#define SMC_MODE_DBW_BIT_16 (0x1u << 12) +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) + +#define SMC_OCMS_SMSE (0x1u << 0) +#define SMC_OCMS_SRSE (0x1u << 1) + +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) + +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) + +#define SMC_WPCR_WP_EN (0x1u << 0) +#define SMC_WPCR_WP_KEY_Pos 8 +#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) +#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos))) + +#define SMC_WPSR_WP_VS_Pos 0 +#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) +#define SMC_WPSR_WP_VSRC_Pos 8 +#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) +# 258 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_spi.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_spi.h" +#define _SAM3U_SPI_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_spi.h" +typedef struct { + WoReg SPI_CR; + RwReg SPI_MR; + RoReg SPI_RDR; + WoReg SPI_TDR; + RoReg SPI_SR; + WoReg SPI_IER; + WoReg SPI_IDR; + RoReg SPI_IMR; + RoReg Reserved1[4]; + RwReg SPI_CSR[4]; + RoReg Reserved2[41]; + RwReg SPI_WPMR; + RoReg SPI_WPSR; +} Spi; + + +#define SPI_CR_SPIEN (0x1u << 0) +#define SPI_CR_SPIDIS (0x1u << 1) +#define SPI_CR_SWRST (0x1u << 7) +#define SPI_CR_LASTXFER (0x1u << 24) + +#define SPI_MR_MSTR (0x1u << 0) +#define SPI_MR_PS (0x1u << 1) +#define SPI_MR_PCSDEC (0x1u << 2) +#define SPI_MR_MODFDIS (0x1u << 4) +#define SPI_MR_WDRBT (0x1u << 5) +#define SPI_MR_LLB (0x1u << 7) +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) + +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) + +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) + +#define SPI_SR_RDRF (0x1u << 0) +#define SPI_SR_TDRE (0x1u << 1) +#define SPI_SR_MODF (0x1u << 2) +#define SPI_SR_OVRES (0x1u << 3) +#define SPI_SR_NSSR (0x1u << 8) +#define SPI_SR_TXEMPTY (0x1u << 9) +#define SPI_SR_UNDES (0x1u << 10) +#define SPI_SR_SPIENS (0x1u << 16) + +#define SPI_IER_RDRF (0x1u << 0) +#define SPI_IER_TDRE (0x1u << 1) +#define SPI_IER_MODF (0x1u << 2) +#define SPI_IER_OVRES (0x1u << 3) +#define SPI_IER_NSSR (0x1u << 8) +#define SPI_IER_TXEMPTY (0x1u << 9) +#define SPI_IER_UNDES (0x1u << 10) + +#define SPI_IDR_RDRF (0x1u << 0) +#define SPI_IDR_TDRE (0x1u << 1) +#define SPI_IDR_MODF (0x1u << 2) +#define SPI_IDR_OVRES (0x1u << 3) +#define SPI_IDR_NSSR (0x1u << 8) +#define SPI_IDR_TXEMPTY (0x1u << 9) +#define SPI_IDR_UNDES (0x1u << 10) + +#define SPI_IMR_RDRF (0x1u << 0) +#define SPI_IMR_TDRE (0x1u << 1) +#define SPI_IMR_MODF (0x1u << 2) +#define SPI_IMR_OVRES (0x1u << 3) +#define SPI_IMR_NSSR (0x1u << 8) +#define SPI_IMR_TXEMPTY (0x1u << 9) +#define SPI_IMR_UNDES (0x1u << 10) + +#define SPI_CSR_CPOL (0x1u << 0) +#define SPI_CSR_NCPHA (0x1u << 1) +#define SPI_CSR_CSNAAT (0x1u << 2) +#define SPI_CSR_CSAAT (0x1u << 3) +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) +#define SPI_CSR_BITS_9_BIT (0x1u << 4) +#define SPI_CSR_BITS_10_BIT (0x2u << 4) +#define SPI_CSR_BITS_11_BIT (0x3u << 4) +#define SPI_CSR_BITS_12_BIT (0x4u << 4) +#define SPI_CSR_BITS_13_BIT (0x5u << 4) +#define SPI_CSR_BITS_14_BIT (0x6u << 4) +#define SPI_CSR_BITS_15_BIT (0x7u << 4) +#define SPI_CSR_BITS_16_BIT (0x8u << 4) +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) + +#define SPI_WPMR_WPEN (0x1u << 0) +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) + +#define SPI_WPSR_WPVS (0x7u << 0) +#define SPI_WPSR_WPVS_Pos 0 +#define SPI_WPSR_WPVS_Msk (0x1u << SPI_WPSR_WPVS_Pos) +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) +# 259 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_ssc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_ssc.h" +#define _SAM3U_SSC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_ssc.h" +typedef struct { + WoReg SSC_CR; + RwReg SSC_CMR; + RoReg Reserved1[2]; + RwReg SSC_RCMR; + RwReg SSC_RFMR; + RwReg SSC_TCMR; + RwReg SSC_TFMR; + RoReg SSC_RHR; + WoReg SSC_THR; + RoReg Reserved2[2]; + RoReg SSC_RSHR; + RwReg SSC_TSHR; + RwReg SSC_RC0R; + RwReg SSC_RC1R; + RoReg SSC_SR; + WoReg SSC_IER; + WoReg SSC_IDR; + RoReg SSC_IMR; + RoReg Reserved3[37]; + RwReg SSC_WPMR; + RoReg SSC_WPSR; +} Ssc; + + +#define SSC_CR_RXEN (0x1u << 0) +#define SSC_CR_RXDIS (0x1u << 1) +#define SSC_CR_TXEN (0x1u << 8) +#define SSC_CR_TXDIS (0x1u << 9) +#define SSC_CR_SWRST (0x1u << 15) + +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) + +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) +#define SSC_RCMR_CKS_MCK (0x0u << 0) +#define SSC_RCMR_CKS_TK (0x1u << 0) +#define SSC_RCMR_CKS_RK (0x2u << 0) +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) +#define SSC_RCMR_CKO_NONE (0x0u << 2) +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) +#define SSC_RCMR_CKI (0x1u << 5) +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) +#define SSC_RCMR_CKG_NONE (0x0u << 6) +#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) +#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) +#define SSC_RCMR_START_RF_LOW (0x2u << 8) +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) +#define SSC_RCMR_START_RF_RISING (0x5u << 8) +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) +#define SSC_RCMR_START_CMP_0 (0x8u << 8) +#define SSC_RCMR_STOP (0x1u << 12) +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) + +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) +#define SSC_RFMR_MSBF (0x1u << 7) +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) +#define SSC_RFMR_FSOS_LOW (0x3u << 20) +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) +#define SSC_RFMR_FSEDGE (0x1u << 24) +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) + +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) +#define SSC_TCMR_CKS_MCK (0x0u << 0) +#define SSC_TCMR_CKS_TK (0x1u << 0) +#define SSC_TCMR_CKS_RK (0x2u << 0) +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) +#define SSC_TCMR_CKO_NONE (0x0u << 2) +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) +#define SSC_TCMR_CKI (0x1u << 5) +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) +#define SSC_TCMR_CKG_NONE (0x0u << 6) +#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) +#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) +#define SSC_TCMR_START_RECEIVE (0x1u << 8) +#define SSC_TCMR_START_RF_LOW (0x2u << 8) +#define SSC_TCMR_START_RF_HIGH (0x3u << 8) +#define SSC_TCMR_START_RF_FALLING (0x4u << 8) +#define SSC_TCMR_START_RF_RISING (0x5u << 8) +#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) +#define SSC_TCMR_START_RF_EDGE (0x7u << 8) +#define SSC_TCMR_START_CMP_0 (0x8u << 8) +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) + +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) +#define SSC_TFMR_MSBF (0x1u << 7) +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) +#define SSC_TFMR_FSOS_LOW (0x3u << 20) +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) +#define SSC_TFMR_FSDEN (0x1u << 23) +#define SSC_TFMR_FSEDGE (0x1u << 24) +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) + +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) + +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) + +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) + +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) + +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) + +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) + +#define SSC_SR_TXRDY (0x1u << 0) +#define SSC_SR_TXEMPTY (0x1u << 1) +#define SSC_SR_RXRDY (0x1u << 4) +#define SSC_SR_OVRUN (0x1u << 5) +#define SSC_SR_CP0 (0x1u << 8) +#define SSC_SR_CP1 (0x1u << 9) +#define SSC_SR_TXSYN (0x1u << 10) +#define SSC_SR_RXSYN (0x1u << 11) +#define SSC_SR_TXEN (0x1u << 16) +#define SSC_SR_RXEN (0x1u << 17) + +#define SSC_IER_TXRDY (0x1u << 0) +#define SSC_IER_TXEMPTY (0x1u << 1) +#define SSC_IER_RXRDY (0x1u << 4) +#define SSC_IER_OVRUN (0x1u << 5) +#define SSC_IER_CP0 (0x1u << 8) +#define SSC_IER_CP1 (0x1u << 9) +#define SSC_IER_TXSYN (0x1u << 10) +#define SSC_IER_RXSYN (0x1u << 11) + +#define SSC_IDR_TXRDY (0x1u << 0) +#define SSC_IDR_TXEMPTY (0x1u << 1) +#define SSC_IDR_RXRDY (0x1u << 4) +#define SSC_IDR_OVRUN (0x1u << 5) +#define SSC_IDR_CP0 (0x1u << 8) +#define SSC_IDR_CP1 (0x1u << 9) +#define SSC_IDR_TXSYN (0x1u << 10) +#define SSC_IDR_RXSYN (0x1u << 11) + +#define SSC_IMR_TXRDY (0x1u << 0) +#define SSC_IMR_TXEMPTY (0x1u << 1) +#define SSC_IMR_RXRDY (0x1u << 4) +#define SSC_IMR_OVRUN (0x1u << 5) +#define SSC_IMR_CP0 (0x1u << 8) +#define SSC_IMR_CP1 (0x1u << 9) +#define SSC_IMR_TXSYN (0x1u << 10) +#define SSC_IMR_RXSYN (0x1u << 11) + +#define SSC_WPMR_WPEN (0x1u << 0) +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) + +#define SSC_WPSR_WPVS (0x1u << 0) +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) +# 260 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_supc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_supc.h" +#define _SAM3U_SUPC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_supc.h" +typedef struct { + WoReg SUPC_CR; + RwReg SUPC_SMMR; + RwReg SUPC_MR; + RwReg SUPC_WUMR; + RwReg SUPC_WUIR; + RoReg SUPC_SR; +} Supc; + + +#define SUPC_CR_VROFF (0x1u << 2) +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) +#define SUPC_CR_XTALSEL (0x1u << 3) +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) + +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) +#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) +#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) +#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) +#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) +#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) +#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) +#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) +#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) +#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) +#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) +#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) +#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) +#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) +#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) +#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) +#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) +#define SUPC_SMMR_SMRSTEN (0x1u << 12) +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) +#define SUPC_SMMR_SMIEN (0x1u << 13) +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) + +#define SUPC_MR_BODRSTEN (0x1u << 12) +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) +#define SUPC_MR_BODDIS (0x1u << 13) +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) +#define SUPC_MR_VDDIORDYONREG (0x1u << 14) +#define SUPC_MR_OSCBYPASS (0x1u << 20) +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) + +#define SUPC_WUMR_FWUPEN (0x1u << 0) +#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) +#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) +#define SUPC_WUMR_SMEN (0x1u << 1) +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) +#define SUPC_WUMR_RTTEN (0x1u << 2) +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) +#define SUPC_WUMR_RTCEN (0x1u << 3) +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) +#define SUPC_WUMR_FWUPDBC_Pos 8 +#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) +#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) +#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) +#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) +#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) +#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) +#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) +#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) +#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) +#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) +#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) +#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) + +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) +#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) +#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) +#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) +#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) +#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) +#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) +#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) +#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) +#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) +#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) +#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) +#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) +#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) +#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) +#define SUPC_WUIR_WKUPEN14 (0x1u << 14) +#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) +#define SUPC_WUIR_WKUPEN15 (0x1u << 15) +#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) +#define SUPC_WUIR_WKUPT0 (0x1u << 16) +#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) +#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) +#define SUPC_WUIR_WKUPT1 (0x1u << 17) +#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) +#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) +#define SUPC_WUIR_WKUPT2 (0x1u << 18) +#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) +#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) +#define SUPC_WUIR_WKUPT3 (0x1u << 19) +#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) +#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) +#define SUPC_WUIR_WKUPT4 (0x1u << 20) +#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) +#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) +#define SUPC_WUIR_WKUPT5 (0x1u << 21) +#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) +#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) +#define SUPC_WUIR_WKUPT6 (0x1u << 22) +#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) +#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) +#define SUPC_WUIR_WKUPT7 (0x1u << 23) +#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) +#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) +#define SUPC_WUIR_WKUPT8 (0x1u << 24) +#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) +#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) +#define SUPC_WUIR_WKUPT9 (0x1u << 25) +#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) +#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) +#define SUPC_WUIR_WKUPT10 (0x1u << 26) +#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) +#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) +#define SUPC_WUIR_WKUPT11 (0x1u << 27) +#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) +#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) +#define SUPC_WUIR_WKUPT12 (0x1u << 28) +#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) +#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) +#define SUPC_WUIR_WKUPT13 (0x1u << 29) +#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) +#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) +#define SUPC_WUIR_WKUPT14 (0x1u << 30) +#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) +#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) +#define SUPC_WUIR_WKUPT15 (0x1u << 31) +#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) +#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) + +#define SUPC_SR_FWUPS (0x1u << 0) +#define SUPC_SR_FWUPS_NO (0x0u << 0) +#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) +#define SUPC_SR_WKUPS (0x1u << 1) +#define SUPC_SR_WKUPS_NO (0x0u << 1) +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) +#define SUPC_SR_SMWS (0x1u << 2) +#define SUPC_SR_SMWS_NO (0x0u << 2) +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) +#define SUPC_SR_BODRSTS (0x1u << 3) +#define SUPC_SR_BODRSTS_NO (0x0u << 3) +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) +#define SUPC_SR_SMRSTS (0x1u << 4) +#define SUPC_SR_SMRSTS_NO (0x0u << 4) +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) +#define SUPC_SR_SMS (0x1u << 5) +#define SUPC_SR_SMS_NO (0x0u << 5) +#define SUPC_SR_SMS_PRESENT (0x1u << 5) +#define SUPC_SR_SMOS (0x1u << 6) +#define SUPC_SR_SMOS_HIGH (0x0u << 6) +#define SUPC_SR_SMOS_LOW (0x1u << 6) +#define SUPC_SR_OSCSEL (0x1u << 7) +#define SUPC_SR_OSCSEL_RC (0x0u << 7) +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) +#define SUPC_SR_FWUPIS (0x1u << 12) +#define SUPC_SR_FWUPIS_LOW (0x0u << 12) +#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) +#define SUPC_SR_WKUPIS0 (0x1u << 16) +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) +#define SUPC_SR_WKUPIS1 (0x1u << 17) +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) +#define SUPC_SR_WKUPIS2 (0x1u << 18) +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) +#define SUPC_SR_WKUPIS3 (0x1u << 19) +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) +#define SUPC_SR_WKUPIS4 (0x1u << 20) +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) +#define SUPC_SR_WKUPIS5 (0x1u << 21) +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) +#define SUPC_SR_WKUPIS6 (0x1u << 22) +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) +#define SUPC_SR_WKUPIS7 (0x1u << 23) +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) +#define SUPC_SR_WKUPIS8 (0x1u << 24) +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) +#define SUPC_SR_WKUPIS9 (0x1u << 25) +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) +#define SUPC_SR_WKUPIS10 (0x1u << 26) +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) +#define SUPC_SR_WKUPIS11 (0x1u << 27) +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) +#define SUPC_SR_WKUPIS12 (0x1u << 28) +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) +#define SUPC_SR_WKUPIS13 (0x1u << 29) +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) +#define SUPC_SR_WKUPIS14 (0x1u << 30) +#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) +#define SUPC_SR_WKUPIS14_EN (0x1u << 30) +#define SUPC_SR_WKUPIS15 (0x1u << 31) +#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) +#define SUPC_SR_WKUPIS15_EN (0x1u << 31) +# 261 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_tc.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_tc.h" +#define _SAM3U_TC_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_tc.h" +typedef struct { + RwReg TC_CCR; + RwReg TC_CMR; + RoReg Reserved1[2]; + RwReg TC_CV; + RwReg TC_RA; + RwReg TC_RB; + RwReg TC_RC; + RwReg TC_SR; + RwReg TC_IER; + RwReg TC_IDR; + RwReg TC_IMR; + RoReg Reserved2[4]; +} TcChannel; + +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[3]; + WoReg TC_BCR; + RwReg TC_BMR; + WoReg TC_QIER; + WoReg TC_QIDR; + RoReg TC_QIMR; + RoReg TC_QISR; +} Tc; + + +#define TC_CCR_CLKEN (0x1u << 0) +#define TC_CCR_CLKDIS (0x1u << 1) +#define TC_CCR_SWTRG (0x1u << 2) + +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) +#define TC_CMR_CLKI (0x1u << 3) +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) +#define TC_CMR_BURST_NONE (0x0u << 4) +#define TC_CMR_BURST_XC0 (0x1u << 4) +#define TC_CMR_BURST_XC1 (0x2u << 4) +#define TC_CMR_BURST_XC2 (0x3u << 4) +#define TC_CMR_LDBSTOP (0x1u << 6) +#define TC_CMR_LDBDIS (0x1u << 7) +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) +#define TC_CMR_ABETRG (0x1u << 10) +#define TC_CMR_CPCTRG (0x1u << 14) +#define TC_CMR_WAVE (0x1u << 15) +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) +#define TC_CMR_LDRA_NONE (0x0u << 16) +#define TC_CMR_LDRA_RISING (0x1u << 16) +#define TC_CMR_LDRA_FALLING (0x2u << 16) +#define TC_CMR_LDRA_EDGE (0x3u << 16) +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) +#define TC_CMR_LDRB_NONE (0x0u << 18) +#define TC_CMR_LDRB_RISING (0x1u << 18) +#define TC_CMR_LDRB_FALLING (0x2u << 18) +#define TC_CMR_LDRB_EDGE (0x3u << 18) +#define TC_CMR_CPCSTOP (0x1u << 6) +#define TC_CMR_CPCDIS (0x1u << 7) +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) +#define TC_CMR_EEVT_TIOB (0x0u << 10) +#define TC_CMR_EEVT_XC0 (0x1u << 10) +#define TC_CMR_EEVT_XC1 (0x2u << 10) +#define TC_CMR_EEVT_XC2 (0x3u << 10) +#define TC_CMR_ENETRG (0x1u << 12) +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) +#define TC_CMR_WAVSEL_UP (0x0u << 13) +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) +#define TC_CMR_ACPA_NONE (0x0u << 16) +#define TC_CMR_ACPA_SET (0x1u << 16) +#define TC_CMR_ACPA_CLEAR (0x2u << 16) +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) +#define TC_CMR_ACPC_NONE (0x0u << 18) +#define TC_CMR_ACPC_SET (0x1u << 18) +#define TC_CMR_ACPC_CLEAR (0x2u << 18) +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) +#define TC_CMR_AEEVT_NONE (0x0u << 20) +#define TC_CMR_AEEVT_SET (0x1u << 20) +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) +#define TC_CMR_ASWTRG_SET (0x1u << 22) +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) +#define TC_CMR_BCPB_NONE (0x0u << 24) +#define TC_CMR_BCPB_SET (0x1u << 24) +#define TC_CMR_BCPB_CLEAR (0x2u << 24) +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) +#define TC_CMR_BCPC_NONE (0x0u << 26) +#define TC_CMR_BCPC_SET (0x1u << 26) +#define TC_CMR_BCPC_CLEAR (0x2u << 26) +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) +#define TC_CMR_BEEVT_NONE (0x0u << 28) +#define TC_CMR_BEEVT_SET (0x1u << 28) +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) +#define TC_CMR_BSWTRG_SET (0x1u << 30) +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) + +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) + +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) + +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) + +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) + +#define TC_SR_COVFS (0x1u << 0) +#define TC_SR_LOVRS (0x1u << 1) +#define TC_SR_CPAS (0x1u << 2) +#define TC_SR_CPBS (0x1u << 3) +#define TC_SR_CPCS (0x1u << 4) +#define TC_SR_LDRAS (0x1u << 5) +#define TC_SR_LDRBS (0x1u << 6) +#define TC_SR_ETRGS (0x1u << 7) +#define TC_SR_CLKSTA (0x1u << 16) +#define TC_SR_MTIOA (0x1u << 17) +#define TC_SR_MTIOB (0x1u << 18) + +#define TC_IER_COVFS (0x1u << 0) +#define TC_IER_LOVRS (0x1u << 1) +#define TC_IER_CPAS (0x1u << 2) +#define TC_IER_CPBS (0x1u << 3) +#define TC_IER_CPCS (0x1u << 4) +#define TC_IER_LDRAS (0x1u << 5) +#define TC_IER_LDRBS (0x1u << 6) +#define TC_IER_ETRGS (0x1u << 7) + +#define TC_IDR_COVFS (0x1u << 0) +#define TC_IDR_LOVRS (0x1u << 1) +#define TC_IDR_CPAS (0x1u << 2) +#define TC_IDR_CPBS (0x1u << 3) +#define TC_IDR_CPCS (0x1u << 4) +#define TC_IDR_LDRAS (0x1u << 5) +#define TC_IDR_LDRBS (0x1u << 6) +#define TC_IDR_ETRGS (0x1u << 7) + +#define TC_IMR_COVFS (0x1u << 0) +#define TC_IMR_LOVRS (0x1u << 1) +#define TC_IMR_CPAS (0x1u << 2) +#define TC_IMR_CPBS (0x1u << 3) +#define TC_IMR_CPCS (0x1u << 4) +#define TC_IMR_LDRAS (0x1u << 5) +#define TC_IMR_LDRBS (0x1u << 6) +#define TC_IMR_ETRGS (0x1u << 7) + +#define TC_BCR_SYNC (0x1u << 0) + +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) +#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) +#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) +#define TC_BMR_QDEN (0x1u << 8) +#define TC_BMR_POSEN (0x1u << 9) +#define TC_BMR_SPEEDEN (0x1u << 10) +#define TC_BMR_QDTRANS (0x1u << 11) +#define TC_BMR_EDGPHA (0x1u << 12) +#define TC_BMR_INVA (0x1u << 13) +#define TC_BMR_INVB (0x1u << 14) +#define TC_BMR_INVIDX (0x1u << 15) +#define TC_BMR_SWAP (0x1u << 16) +#define TC_BMR_IDXPHB (0x1u << 17) +#define TC_BMR_FILTER (0x1u << 19) +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) + +#define TC_QIER_IDX (0x1u << 0) +#define TC_QIER_DIRCHG (0x1u << 1) +#define TC_QIER_QERR (0x1u << 2) + +#define TC_QIDR_IDX (0x1u << 0) +#define TC_QIDR_DIRCHG (0x1u << 1) +#define TC_QIDR_QERR (0x1u << 2) + +#define TC_QIMR_IDX (0x1u << 0) +#define TC_QIMR_DIRCHG (0x1u << 1) +#define TC_QIMR_QERR (0x1u << 2) + +#define TC_QISR_IDX (0x1u << 0) +#define TC_QISR_DIRCHG (0x1u << 1) +#define TC_QISR_QERR (0x1u << 2) +#define TC_QISR_DIR (0x1u << 8) +# 262 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_twi.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_twi.h" +#define _SAM3U_TWI_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_twi.h" +typedef struct { + WoReg TWI_CR; + RwReg TWI_MMR; + RwReg TWI_SMR; + RwReg TWI_IADR; + RwReg TWI_CWGR; + RoReg Reserved1[3]; + RoReg TWI_SR; + WoReg TWI_IER; + WoReg TWI_IDR; + RoReg TWI_IMR; + RoReg TWI_RHR; + WoReg TWI_THR; + RoReg Reserved2[50]; + RwReg TWI_RPR; + RwReg TWI_RCR; + RwReg TWI_TPR; + RwReg TWI_TCR; + RwReg TWI_RNPR; + RwReg TWI_RNCR; + RwReg TWI_TNPR; + RwReg TWI_TNCR; + WoReg TWI_PTCR; + RoReg TWI_PTSR; +} Twi; + + +#define TWI_CR_START (0x1u << 0) +#define TWI_CR_STOP (0x1u << 1) +#define TWI_CR_MSEN (0x1u << 2) +#define TWI_CR_MSDIS (0x1u << 3) +#define TWI_CR_SVEN (0x1u << 4) +#define TWI_CR_SVDIS (0x1u << 5) +#define TWI_CR_QUICK (0x1u << 6) +#define TWI_CR_SWRST (0x1u << 7) + +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) +#define TWI_MMR_MREAD (0x1u << 12) +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) + +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) + +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) + +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) + +#define TWI_SR_TXCOMP (0x1u << 0) +#define TWI_SR_RXRDY (0x1u << 1) +#define TWI_SR_TXRDY (0x1u << 2) +#define TWI_SR_SVREAD (0x1u << 3) +#define TWI_SR_SVACC (0x1u << 4) +#define TWI_SR_GACC (0x1u << 5) +#define TWI_SR_OVRE (0x1u << 6) +#define TWI_SR_NACK (0x1u << 8) +#define TWI_SR_ARBLST (0x1u << 9) +#define TWI_SR_SCLWS (0x1u << 10) +#define TWI_SR_EOSACC (0x1u << 11) +#define TWI_SR_ENDRX (0x1u << 12) +#define TWI_SR_ENDTX (0x1u << 13) +#define TWI_SR_RXBUFF (0x1u << 14) +#define TWI_SR_TXBUFE (0x1u << 15) + +#define TWI_IER_TXCOMP (0x1u << 0) +#define TWI_IER_RXRDY (0x1u << 1) +#define TWI_IER_TXRDY (0x1u << 2) +#define TWI_IER_SVACC (0x1u << 4) +#define TWI_IER_GACC (0x1u << 5) +#define TWI_IER_OVRE (0x1u << 6) +#define TWI_IER_NACK (0x1u << 8) +#define TWI_IER_ARBLST (0x1u << 9) +#define TWI_IER_SCL_WS (0x1u << 10) +#define TWI_IER_EOSACC (0x1u << 11) +#define TWI_IER_ENDRX (0x1u << 12) +#define TWI_IER_ENDTX (0x1u << 13) +#define TWI_IER_RXBUFF (0x1u << 14) +#define TWI_IER_TXBUFE (0x1u << 15) + +#define TWI_IDR_TXCOMP (0x1u << 0) +#define TWI_IDR_RXRDY (0x1u << 1) +#define TWI_IDR_TXRDY (0x1u << 2) +#define TWI_IDR_SVACC (0x1u << 4) +#define TWI_IDR_GACC (0x1u << 5) +#define TWI_IDR_OVRE (0x1u << 6) +#define TWI_IDR_NACK (0x1u << 8) +#define TWI_IDR_ARBLST (0x1u << 9) +#define TWI_IDR_SCL_WS (0x1u << 10) +#define TWI_IDR_EOSACC (0x1u << 11) +#define TWI_IDR_ENDRX (0x1u << 12) +#define TWI_IDR_ENDTX (0x1u << 13) +#define TWI_IDR_RXBUFF (0x1u << 14) +#define TWI_IDR_TXBUFE (0x1u << 15) + +#define TWI_IMR_TXCOMP (0x1u << 0) +#define TWI_IMR_RXRDY (0x1u << 1) +#define TWI_IMR_TXRDY (0x1u << 2) +#define TWI_IMR_SVACC (0x1u << 4) +#define TWI_IMR_GACC (0x1u << 5) +#define TWI_IMR_OVRE (0x1u << 6) +#define TWI_IMR_NACK (0x1u << 8) +#define TWI_IMR_ARBLST (0x1u << 9) +#define TWI_IMR_SCL_WS (0x1u << 10) +#define TWI_IMR_EOSACC (0x1u << 11) +#define TWI_IMR_ENDRX (0x1u << 12) +#define TWI_IMR_ENDTX (0x1u << 13) +#define TWI_IMR_RXBUFF (0x1u << 14) +#define TWI_IMR_TXBUFE (0x1u << 15) + +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) + +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) + +#define TWI_RPR_RXPTR_Pos 0 +#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) +#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) + +#define TWI_RCR_RXCTR_Pos 0 +#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) +#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) + +#define TWI_TPR_TXPTR_Pos 0 +#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) +#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) + +#define TWI_TCR_TXCTR_Pos 0 +#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) +#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) + +#define TWI_RNPR_RXNPTR_Pos 0 +#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) +#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) + +#define TWI_RNCR_RXNCTR_Pos 0 +#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) +#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) + +#define TWI_TNPR_TXNPTR_Pos 0 +#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) +#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) + +#define TWI_TNCR_TXNCTR_Pos 0 +#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) +#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) + +#define TWI_PTCR_RXTEN (0x1u << 0) +#define TWI_PTCR_RXTDIS (0x1u << 1) +#define TWI_PTCR_TXTEN (0x1u << 8) +#define TWI_PTCR_TXTDIS (0x1u << 9) + +#define TWI_PTSR_RXTEN (0x1u << 0) +#define TWI_PTSR_TXTEN (0x1u << 8) +# 263 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_uart.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_uart.h" +#define _SAM3U_UART_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_uart.h" +typedef struct { + WoReg UART_CR; + RwReg UART_MR; + WoReg UART_IER; + WoReg UART_IDR; + RoReg UART_IMR; + RoReg UART_SR; + RoReg UART_RHR; + WoReg UART_THR; + RwReg UART_BRGR; + RoReg Reserved1[55]; + RwReg UART_RPR; + RwReg UART_RCR; + RwReg UART_TPR; + RwReg UART_TCR; + RwReg UART_RNPR; + RwReg UART_RNCR; + RwReg UART_TNPR; + RwReg UART_TNCR; + WoReg UART_PTCR; + RoReg UART_PTSR; +} Uart; + + +#define UART_CR_RSTRX (0x1u << 2) +#define UART_CR_RSTTX (0x1u << 3) +#define UART_CR_RXEN (0x1u << 4) +#define UART_CR_RXDIS (0x1u << 5) +#define UART_CR_TXEN (0x1u << 6) +#define UART_CR_TXDIS (0x1u << 7) +#define UART_CR_RSTSTA (0x1u << 8) + +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) +#define UART_MR_PAR_EVEN (0x0u << 9) +#define UART_MR_PAR_ODD (0x1u << 9) +#define UART_MR_PAR_SPACE (0x2u << 9) +#define UART_MR_PAR_MARK (0x3u << 9) +#define UART_MR_PAR_NO (0x4u << 9) +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) + +#define UART_IER_RXRDY (0x1u << 0) +#define UART_IER_TXRDY (0x1u << 1) +#define UART_IER_ENDRX (0x1u << 3) +#define UART_IER_ENDTX (0x1u << 4) +#define UART_IER_OVRE (0x1u << 5) +#define UART_IER_FRAME (0x1u << 6) +#define UART_IER_PARE (0x1u << 7) +#define UART_IER_TXEMPTY (0x1u << 9) +#define UART_IER_TXBUFE (0x1u << 11) +#define UART_IER_RXBUFF (0x1u << 12) + +#define UART_IDR_RXRDY (0x1u << 0) +#define UART_IDR_TXRDY (0x1u << 1) +#define UART_IDR_ENDRX (0x1u << 3) +#define UART_IDR_ENDTX (0x1u << 4) +#define UART_IDR_OVRE (0x1u << 5) +#define UART_IDR_FRAME (0x1u << 6) +#define UART_IDR_PARE (0x1u << 7) +#define UART_IDR_TXEMPTY (0x1u << 9) +#define UART_IDR_TXBUFE (0x1u << 11) +#define UART_IDR_RXBUFF (0x1u << 12) + +#define UART_IMR_RXRDY (0x1u << 0) +#define UART_IMR_TXRDY (0x1u << 1) +#define UART_IMR_ENDRX (0x1u << 3) +#define UART_IMR_ENDTX (0x1u << 4) +#define UART_IMR_OVRE (0x1u << 5) +#define UART_IMR_FRAME (0x1u << 6) +#define UART_IMR_PARE (0x1u << 7) +#define UART_IMR_TXEMPTY (0x1u << 9) +#define UART_IMR_TXBUFE (0x1u << 11) +#define UART_IMR_RXBUFF (0x1u << 12) + +#define UART_SR_RXRDY (0x1u << 0) +#define UART_SR_TXRDY (0x1u << 1) +#define UART_SR_ENDRX (0x1u << 3) +#define UART_SR_ENDTX (0x1u << 4) +#define UART_SR_OVRE (0x1u << 5) +#define UART_SR_FRAME (0x1u << 6) +#define UART_SR_PARE (0x1u << 7) +#define UART_SR_TXEMPTY (0x1u << 9) +#define UART_SR_TXBUFE (0x1u << 11) +#define UART_SR_RXBUFF (0x1u << 12) + +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) + +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) + +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) + +#define UART_RPR_RXPTR_Pos 0 +#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) +#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) + +#define UART_RCR_RXCTR_Pos 0 +#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) +#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) + +#define UART_TPR_TXPTR_Pos 0 +#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) +#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) + +#define UART_TCR_TXCTR_Pos 0 +#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) +#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) + +#define UART_RNPR_RXNPTR_Pos 0 +#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) +#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) + +#define UART_RNCR_RXNCTR_Pos 0 +#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) +#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) + +#define UART_TNPR_TXNPTR_Pos 0 +#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) +#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) + +#define UART_TNCR_TXNCTR_Pos 0 +#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) +#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) + +#define UART_PTCR_RXTEN (0x1u << 0) +#define UART_PTCR_RXTDIS (0x1u << 1) +#define UART_PTCR_TXTEN (0x1u << 8) +#define UART_PTCR_TXTDIS (0x1u << 9) + +#define UART_PTSR_RXTEN (0x1u << 0) +#define UART_PTSR_TXTEN (0x1u << 8) +# 264 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_udphs.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_udphs.h" +#define _SAM3U_UDPHS_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_udphs.h" +typedef struct { + RwReg UDPHS_DMANXTDSC; + RwReg UDPHS_DMAADDRESS; + RwReg UDPHS_DMACONTROL; + RwReg UDPHS_DMASTATUS; +} UdphsDma; + +typedef struct { + RwReg UDPHS_EPTCFG; + RwReg UDPHS_EPTCTLENB; + RwReg UDPHS_EPTCTLDIS; + RwReg UDPHS_EPTCTL; + RoReg Reserved1[1]; + RwReg UDPHS_EPTSETSTA; + RwReg UDPHS_EPTCLRSTA; + RwReg UDPHS_EPTSTA; +} UdphsEpt; + +#define UDPHSEPT_NUMBER 7 +#define UDPHSDMA_NUMBER 6 +typedef struct { + RwReg UDPHS_CTRL; + RoReg UDPHS_FNUM; + RoReg Reserved1[2]; + RwReg UDPHS_IEN; + RoReg UDPHS_INTSTA; + WoReg UDPHS_CLRINT; + WoReg UDPHS_EPTRST; + RoReg Reserved2[48]; + RwReg UDPHS_TST; + RoReg Reserved3[3]; + RoReg UDPHS_IPNAME1; + RoReg UDPHS_IPNAME2; + RoReg UDPHS_IPFEATURES; + RoReg Reserved4[1]; + UdphsEpt UDPHS_EPT[7]; + RoReg Reserved5[72]; + UdphsDma UDPHS_DMA[6]; +} Udphs; + + +#define UDPHS_CTRL_DEV_ADDR_Pos 0 +#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) +#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos))) +#define UDPHS_CTRL_FADDR_EN (0x1u << 7) +#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) +#define UDPHS_CTRL_DETACH (0x1u << 9) +#define UDPHS_CTRL_REWAKEUP (0x1u << 10) +#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) + +#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0 +#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) +#define UDPHS_FNUM_FRAME_NUMBER_Pos 3 +#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) +#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) + +#define UDPHS_IEN_DET_SUSPD (0x1u << 1) +#define UDPHS_IEN_MICRO_SOF (0x1u << 2) +#define UDPHS_IEN_INT_SOF (0x1u << 3) +#define UDPHS_IEN_ENDRESET (0x1u << 4) +#define UDPHS_IEN_WAKE_UP (0x1u << 5) +#define UDPHS_IEN_ENDOFRSM (0x1u << 6) +#define UDPHS_IEN_UPSTR_RES (0x1u << 7) +#define UDPHS_IEN_EPT_0 (0x1u << 8) +#define UDPHS_IEN_EPT_1 (0x1u << 9) +#define UDPHS_IEN_EPT_2 (0x1u << 10) +#define UDPHS_IEN_EPT_3 (0x1u << 11) +#define UDPHS_IEN_EPT_4 (0x1u << 12) +#define UDPHS_IEN_EPT_5 (0x1u << 13) +#define UDPHS_IEN_EPT_6 (0x1u << 14) +#define UDPHS_IEN_DMA_1 (0x1u << 25) +#define UDPHS_IEN_DMA_2 (0x1u << 26) +#define UDPHS_IEN_DMA_3 (0x1u << 27) +#define UDPHS_IEN_DMA_4 (0x1u << 28) +#define UDPHS_IEN_DMA_5 (0x1u << 29) +#define UDPHS_IEN_DMA_6 (0x1u << 30) + +#define UDPHS_INTSTA_SPEED (0x1u << 0) +#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) +#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) +#define UDPHS_INTSTA_INT_SOF (0x1u << 3) +#define UDPHS_INTSTA_ENDRESET (0x1u << 4) +#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) +#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) +#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) +#define UDPHS_INTSTA_EPT_0 (0x1u << 8) +#define UDPHS_INTSTA_EPT_1 (0x1u << 9) +#define UDPHS_INTSTA_EPT_2 (0x1u << 10) +#define UDPHS_INTSTA_EPT_3 (0x1u << 11) +#define UDPHS_INTSTA_EPT_4 (0x1u << 12) +#define UDPHS_INTSTA_EPT_5 (0x1u << 13) +#define UDPHS_INTSTA_EPT_6 (0x1u << 14) +#define UDPHS_INTSTA_DMA_1 (0x1u << 25) +#define UDPHS_INTSTA_DMA_2 (0x1u << 26) +#define UDPHS_INTSTA_DMA_3 (0x1u << 27) +#define UDPHS_INTSTA_DMA_4 (0x1u << 28) +#define UDPHS_INTSTA_DMA_5 (0x1u << 29) +#define UDPHS_INTSTA_DMA_6 (0x1u << 30) + +#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) +#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) +#define UDPHS_CLRINT_INT_SOF (0x1u << 3) +#define UDPHS_CLRINT_ENDRESET (0x1u << 4) +#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) +#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) +#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) + +#define UDPHS_EPTRST_EPT_0 (0x1u << 0) +#define UDPHS_EPTRST_EPT_1 (0x1u << 1) +#define UDPHS_EPTRST_EPT_2 (0x1u << 2) +#define UDPHS_EPTRST_EPT_3 (0x1u << 3) +#define UDPHS_EPTRST_EPT_4 (0x1u << 4) +#define UDPHS_EPTRST_EPT_5 (0x1u << 5) +#define UDPHS_EPTRST_EPT_6 (0x1u << 6) + +#define UDPHS_TST_SPEED_CFG_Pos 0 +#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) +#define UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) +#define UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) +#define UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) +#define UDPHS_TST_TST_J (0x1u << 2) +#define UDPHS_TST_TST_K (0x1u << 3) +#define UDPHS_TST_TST_PKT (0x1u << 4) +#define UDPHS_TST_OPMODE2 (0x1u << 5) + +#define UDPHS_IPNAME1_IP_NAME1_Pos 0 +#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) + +#define UDPHS_IPNAME2_IP_NAME2_Pos 0 +#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) + +#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0 +#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) +#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4 +#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) +#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) +#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8 +#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) +#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12 +#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) +#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) +#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) +#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) +#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) +#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) +#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) +#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) +#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) +#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) +#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) +#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) +#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) +#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) +#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) +#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) +#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) +#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) + +#define UDPHS_EPTCFG_EPT_SIZE_Pos 0 +#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) +#define UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) +#define UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) +#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) +#define UDPHS_EPTCFG_EPT_TYPE_Pos 4 +#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) +#define UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) +#define UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) +#define UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) +#define UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) +#define UDPHS_EPTCFG_BK_NUMBER_Pos 6 +#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) +#define UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) +#define UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) +#define UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) +#define UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) +#define UDPHS_EPTCFG_NB_TRANS_Pos 8 +#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) +#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos))) +#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) + +#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) +#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) +#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) +#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) +#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) +#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) +#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) +#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) +#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) +#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) +#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) +#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) +#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) +#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) +#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) +#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) +#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) +#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) +#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) +#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) +#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) + +#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) +#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) +#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) +#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) +#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) +#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) +#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) +#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) +#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) +#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) +#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) +#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) +#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) +#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) +#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) +#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) +#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) +#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) +#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) +#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) +#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) + +#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) +#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) +#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) +#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) +#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) +#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) +#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) +#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) +#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) +#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) +#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) +#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) +#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) +#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) +#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) +#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) +#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) +#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) +#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) +#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) +#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) + +#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) +#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) +#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) + +#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) +#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) +#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) +#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) +#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) +#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) +#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) +#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) +#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) +#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) +#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) + +#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) +#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6 +#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) +#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) +#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) +#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) +#define UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) +#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) +#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) +#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) +#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) +#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) +#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) +#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) +#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) +#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) +#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) +#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) +#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) +#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) +#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) +#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16 +#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) +#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16 +#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) +#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18 +#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) +#define UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) +#define UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) +#define UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) +#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20 +#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) +#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) + +#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) +#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos))) + +#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0 +#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) +#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos))) + +#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) +#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) +#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) +#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) +#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) +#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) +#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) +#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) +#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16 +#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) +#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos))) + +#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) +#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) +#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) +#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) +#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) +#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16 +#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) +#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos))) +# 265 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_usart.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_usart.h" +#define _SAM3U_USART_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_usart.h" +typedef struct { + WoReg US_CR; + RwReg US_MR; + WoReg US_IER; + WoReg US_IDR; + RoReg US_IMR; + RoReg US_CSR; + RoReg US_RHR; + WoReg US_THR; + RwReg US_BRGR; + RwReg US_RTOR; + RwReg US_TTGR; + RoReg Reserved1[5]; + RwReg US_FIDI; + RoReg US_NER; + RoReg Reserved2[1]; + RwReg US_IF; + RwReg US_MAN; + RoReg Reserved3[36]; + RwReg US_WPMR; + RoReg US_WPSR; + RoReg Reserved4[5]; + RwReg US_RPR; + RwReg US_RCR; + RwReg US_TPR; + RwReg US_TCR; + RwReg US_RNPR; + RwReg US_RNCR; + RwReg US_TNPR; + RwReg US_TNCR; + WoReg US_PTCR; + RoReg US_PTSR; +} Usart; + + +#define US_CR_RSTRX (0x1u << 2) +#define US_CR_RSTTX (0x1u << 3) +#define US_CR_RXEN (0x1u << 4) +#define US_CR_RXDIS (0x1u << 5) +#define US_CR_TXEN (0x1u << 6) +#define US_CR_TXDIS (0x1u << 7) +#define US_CR_RSTSTA (0x1u << 8) +#define US_CR_STTBRK (0x1u << 9) +#define US_CR_STPBRK (0x1u << 10) +#define US_CR_STTTO (0x1u << 11) +#define US_CR_SENDA (0x1u << 12) +#define US_CR_RSTIT (0x1u << 13) +#define US_CR_RSTNACK (0x1u << 14) +#define US_CR_RETTO (0x1u << 15) +#define US_CR_DTREN (0x1u << 16) +#define US_CR_DTRDIS (0x1u << 17) +#define US_CR_RTSEN (0x1u << 18) +#define US_CR_FCS (0x1u << 18) +#define US_CR_RTSDIS (0x1u << 19) +#define US_CR_RCS (0x1u << 19) + +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) +#define US_MR_USART_MODE_RS485 (0x1u << 0) +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) +#define US_MR_USART_MODE_MODEM (0x3u << 0) +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) +#define US_MR_USART_MODE_IRDA (0x8u << 0) +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) +#define US_MR_USCLKS_MCK (0x0u << 4) +#define US_MR_USCLKS_DIV (0x1u << 4) +#define US_MR_USCLKS_SCK (0x3u << 4) +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) +#define US_MR_CHRL_5_BIT (0x0u << 6) +#define US_MR_CHRL_6_BIT (0x1u << 6) +#define US_MR_CHRL_7_BIT (0x2u << 6) +#define US_MR_CHRL_8_BIT (0x3u << 6) +#define US_MR_SYNC (0x1u << 8) +#define US_MR_CPHA (0x1u << 8) +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) +#define US_MR_PAR_EVEN (0x0u << 9) +#define US_MR_PAR_ODD (0x1u << 9) +#define US_MR_PAR_SPACE (0x2u << 9) +#define US_MR_PAR_MARK (0x3u << 9) +#define US_MR_PAR_NO (0x4u << 9) +#define US_MR_PAR_MULTIDROP (0x6u << 9) +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) +#define US_MR_NBSTOP_2_BIT (0x2u << 12) +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) +#define US_MR_CHMODE_NORMAL (0x0u << 14) +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) +#define US_MR_MSBF (0x1u << 16) +#define US_MR_CPOL (0x1u << 16) +#define US_MR_MODE9 (0x1u << 17) +#define US_MR_CLKO (0x1u << 18) +#define US_MR_OVER (0x1u << 19) +#define US_MR_INACK (0x1u << 20) +#define US_MR_DSNACK (0x1u << 21) +#define US_MR_VAR_SYNC (0x1u << 22) +#define US_MR_INVDATA (0x1u << 23) +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) +#define US_MR_MAN (0x1u << 29) +#define US_MR_MODSYNC (0x1u << 30) +#define US_MR_ONEBIT (0x1u << 31) + +#define US_IER_RXRDY (0x1u << 0) +#define US_IER_TXRDY (0x1u << 1) +#define US_IER_RXBRK (0x1u << 2) +#define US_IER_ENDRX (0x1u << 3) +#define US_IER_ENDTX (0x1u << 4) +#define US_IER_OVRE (0x1u << 5) +#define US_IER_FRAME (0x1u << 6) +#define US_IER_PARE (0x1u << 7) +#define US_IER_TIMEOUT (0x1u << 8) +#define US_IER_TXEMPTY (0x1u << 9) +#define US_IER_ITER (0x1u << 10) +#define US_IER_UNRE (0x1u << 10) +#define US_IER_TXBUFE (0x1u << 11) +#define US_IER_RXBUFF (0x1u << 12) +#define US_IER_NACK (0x1u << 13) +#define US_IER_RIIC (0x1u << 16) +#define US_IER_DSRIC (0x1u << 17) +#define US_IER_DCDIC (0x1u << 18) +#define US_IER_CTSIC (0x1u << 19) +#define US_IER_MANE (0x1u << 24) + +#define US_IDR_RXRDY (0x1u << 0) +#define US_IDR_TXRDY (0x1u << 1) +#define US_IDR_RXBRK (0x1u << 2) +#define US_IDR_ENDRX (0x1u << 3) +#define US_IDR_ENDTX (0x1u << 4) +#define US_IDR_OVRE (0x1u << 5) +#define US_IDR_FRAME (0x1u << 6) +#define US_IDR_PARE (0x1u << 7) +#define US_IDR_TIMEOUT (0x1u << 8) +#define US_IDR_TXEMPTY (0x1u << 9) +#define US_IDR_ITER (0x1u << 10) +#define US_IDR_UNRE (0x1u << 10) +#define US_IDR_TXBUFE (0x1u << 11) +#define US_IDR_RXBUFF (0x1u << 12) +#define US_IDR_NACK (0x1u << 13) +#define US_IDR_RIIC (0x1u << 16) +#define US_IDR_DSRIC (0x1u << 17) +#define US_IDR_DCDIC (0x1u << 18) +#define US_IDR_CTSIC (0x1u << 19) +#define US_IDR_MANE (0x1u << 24) + +#define US_IMR_RXRDY (0x1u << 0) +#define US_IMR_TXRDY (0x1u << 1) +#define US_IMR_RXBRK (0x1u << 2) +#define US_IMR_ENDRX (0x1u << 3) +#define US_IMR_ENDTX (0x1u << 4) +#define US_IMR_OVRE (0x1u << 5) +#define US_IMR_FRAME (0x1u << 6) +#define US_IMR_PARE (0x1u << 7) +#define US_IMR_TIMEOUT (0x1u << 8) +#define US_IMR_TXEMPTY (0x1u << 9) +#define US_IMR_ITER (0x1u << 10) +#define US_IMR_UNRE (0x1u << 10) +#define US_IMR_TXBUFE (0x1u << 11) +#define US_IMR_RXBUFF (0x1u << 12) +#define US_IMR_NACK (0x1u << 13) +#define US_IMR_RIIC (0x1u << 16) +#define US_IMR_DSRIC (0x1u << 17) +#define US_IMR_DCDIC (0x1u << 18) +#define US_IMR_CTSIC (0x1u << 19) +#define US_IMR_MANE (0x1u << 24) + +#define US_CSR_RXRDY (0x1u << 0) +#define US_CSR_TXRDY (0x1u << 1) +#define US_CSR_RXBRK (0x1u << 2) +#define US_CSR_ENDRX (0x1u << 3) +#define US_CSR_ENDTX (0x1u << 4) +#define US_CSR_OVRE (0x1u << 5) +#define US_CSR_FRAME (0x1u << 6) +#define US_CSR_PARE (0x1u << 7) +#define US_CSR_TIMEOUT (0x1u << 8) +#define US_CSR_TXEMPTY (0x1u << 9) +#define US_CSR_ITER (0x1u << 10) +#define US_CSR_UNRE (0x1u << 10) +#define US_CSR_TXBUFE (0x1u << 11) +#define US_CSR_RXBUFF (0x1u << 12) +#define US_CSR_NACK (0x1u << 13) +#define US_CSR_RIIC (0x1u << 16) +#define US_CSR_DSRIC (0x1u << 17) +#define US_CSR_DCDIC (0x1u << 18) +#define US_CSR_CTSIC (0x1u << 19) +#define US_CSR_RI (0x1u << 20) +#define US_CSR_DSR (0x1u << 21) +#define US_CSR_DCD (0x1u << 22) +#define US_CSR_CTS (0x1u << 23) +#define US_CSR_MANERR (0x1u << 24) + +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) +#define US_RHR_RXSYNH (0x1u << 15) + +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) + +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) + +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) + +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) + +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) + +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) + +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) + +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) +#define US_MAN_TX_MPOL (0x1u << 12) +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) +#define US_MAN_RX_MPOL (0x1u << 28) +#define US_MAN_STUCKTO1 (0x1u << 29) +#define US_MAN_DRIFT (0x1u << 30) + +#define US_WPMR_WPEN (0x1u << 0) +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) + +#define US_WPSR_WPVS (0x1u << 0) +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) + +#define US_RPR_RXPTR_Pos 0 +#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) +#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) + +#define US_RCR_RXCTR_Pos 0 +#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) +#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) + +#define US_TPR_TXPTR_Pos 0 +#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) +#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) + +#define US_TCR_TXCTR_Pos 0 +#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) +#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) + +#define US_RNPR_RXNPTR_Pos 0 +#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) +#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) + +#define US_RNCR_RXNCTR_Pos 0 +#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) +#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) + +#define US_TNPR_TXNPTR_Pos 0 +#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) +#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) + +#define US_TNCR_TXNCTR_Pos 0 +#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) +#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) + +#define US_PTCR_RXTEN (0x1u << 0) +#define US_PTCR_RXTDIS (0x1u << 1) +#define US_PTCR_TXTEN (0x1u << 8) +#define US_PTCR_TXTDIS (0x1u << 9) + +#define US_PTSR_RXTEN (0x1u << 0) +#define US_PTSR_TXTEN (0x1u << 8) +# 266 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/component/component_wdt.h" 1 +# 43 "naeusb/sam3u_hal/inc/component/component_wdt.h" +#define _SAM3U_WDT_COMPONENT_ +# 53 "naeusb/sam3u_hal/inc/component/component_wdt.h" +typedef struct { + WoReg WDT_CR; + RwReg WDT_MR; + RoReg WDT_SR; +} Wdt; + + +#define WDT_CR_WDRSTT (0x1u << 0) +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) + +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) +#define WDT_MR_WDRSTEN (0x1u << 13) +#define WDT_MR_WDRPROC (0x1u << 14) +#define WDT_MR_WDDIS (0x1u << 15) +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) +#define WDT_MR_WDIDLEHLT (0x1u << 29) + +#define WDT_SR_WDUNF (0x1u << 0) +#define WDT_SR_WDERR (0x1u << 1) +# 267 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 275 "naeusb/sam3u_hal/inc/sam3u2c.h" +# 1 "naeusb/sam3u_hal/inc/instance/instance_hsmci.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_hsmci.h" +#define _SAM3U_HSMCI_INSTANCE_ +# 68 "naeusb/sam3u_hal/inc/instance/instance_hsmci.h" +#define REG_HSMCI_CR (*(WoReg*)0x40000000U) +#define REG_HSMCI_MR (*(RwReg*)0x40000004U) +#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) +#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) +#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) +#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) +#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) +#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) +#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) +#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) +#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) +#define REG_HSMCI_SR (*(RoReg*)0x40000040U) +#define REG_HSMCI_IER (*(WoReg*)0x40000044U) +#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) +#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) +#define REG_HSMCI_DMA (*(RwReg*)0x40000050U) +#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) +#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) +#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) +#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) +# 276 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_ssc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_ssc.h" +#define _SAM3U_SSC_INSTANCE_ +# 66 "naeusb/sam3u_hal/inc/instance/instance_ssc.h" +#define REG_SSC_CR (*(WoReg*)0x40004000U) +#define REG_SSC_CMR (*(RwReg*)0x40004004U) +#define REG_SSC_RCMR (*(RwReg*)0x40004010U) +#define REG_SSC_RFMR (*(RwReg*)0x40004014U) +#define REG_SSC_TCMR (*(RwReg*)0x40004018U) +#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) +#define REG_SSC_RHR (*(RoReg*)0x40004020U) +#define REG_SSC_THR (*(WoReg*)0x40004024U) +#define REG_SSC_RSHR (*(RoReg*)0x40004030U) +#define REG_SSC_TSHR (*(RwReg*)0x40004034U) +#define REG_SSC_RC0R (*(RwReg*)0x40004038U) +#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) +#define REG_SSC_SR (*(RoReg*)0x40004040U) +#define REG_SSC_IER (*(WoReg*)0x40004044U) +#define REG_SSC_IDR (*(WoReg*)0x40004048U) +#define REG_SSC_IMR (*(RoReg*)0x4000404CU) +#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) +#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) +# 277 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_spi.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_spi.h" +#define _SAM3U_SPI_INSTANCE_ +# 59 "naeusb/sam3u_hal/inc/instance/instance_spi.h" +#define REG_SPI_CR (*(WoReg*)0x40008000U) +#define REG_SPI_MR (*(RwReg*)0x40008004U) +#define REG_SPI_RDR (*(RoReg*)0x40008008U) +#define REG_SPI_TDR (*(WoReg*)0x4000800CU) +#define REG_SPI_SR (*(RoReg*)0x40008010U) +#define REG_SPI_IER (*(WoReg*)0x40008014U) +#define REG_SPI_IDR (*(WoReg*)0x40008018U) +#define REG_SPI_IMR (*(RoReg*)0x4000801CU) +#define REG_SPI_CSR (*(RwReg*)0x40008030U) +#define REG_SPI_WPMR (*(RwReg*)0x400080E4U) +#define REG_SPI_WPSR (*(RoReg*)0x400080E8U) +# 278 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_tc0.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_tc0.h" +#define _SAM3U_TC0_INSTANCE_ +# 84 "naeusb/sam3u_hal/inc/instance/instance_tc0.h" +#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) +#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) +#define REG_TC0_CV0 (*(RoReg*)0x40080010U) +#define REG_TC0_RA0 (*(RwReg*)0x40080014U) +#define REG_TC0_RB0 (*(RwReg*)0x40080018U) +#define REG_TC0_RC0 (*(RwReg*)0x4008001CU) +#define REG_TC0_SR0 (*(RoReg*)0x40080020U) +#define REG_TC0_IER0 (*(WoReg*)0x40080024U) +#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) +#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) +#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) +#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) +#define REG_TC0_CV1 (*(RoReg*)0x40080050U) +#define REG_TC0_RA1 (*(RwReg*)0x40080054U) +#define REG_TC0_RB1 (*(RwReg*)0x40080058U) +#define REG_TC0_RC1 (*(RwReg*)0x4008005CU) +#define REG_TC0_SR1 (*(RoReg*)0x40080060U) +#define REG_TC0_IER1 (*(WoReg*)0x40080064U) +#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) +#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) +#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) +#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) +#define REG_TC0_CV2 (*(RoReg*)0x40080090U) +#define REG_TC0_RA2 (*(RwReg*)0x40080094U) +#define REG_TC0_RB2 (*(RwReg*)0x40080098U) +#define REG_TC0_RC2 (*(RwReg*)0x4008009CU) +#define REG_TC0_SR2 (*(RoReg*)0x400800A0U) +#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) +#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) +#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) +#define REG_TC0_BCR (*(WoReg*)0x400800C0U) +#define REG_TC0_BMR (*(RwReg*)0x400800C4U) +#define REG_TC0_QIER (*(WoReg*)0x400800C8U) +#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) +#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) +#define REG_TC0_QISR (*(RoReg*)0x400800D4U) +# 279 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_twi0.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_twi0.h" +#define _SAM3U_TWI0_INSTANCE_ +# 69 "naeusb/sam3u_hal/inc/instance/instance_twi0.h" +#define REG_TWI0_CR (*(WoReg*)0x40084000U) +#define REG_TWI0_MMR (*(RwReg*)0x40084004U) +#define REG_TWI0_SMR (*(RwReg*)0x40084008U) +#define REG_TWI0_IADR (*(RwReg*)0x4008400CU) +#define REG_TWI0_CWGR (*(RwReg*)0x40084010U) +#define REG_TWI0_SR (*(RoReg*)0x40084020U) +#define REG_TWI0_IER (*(WoReg*)0x40084024U) +#define REG_TWI0_IDR (*(WoReg*)0x40084028U) +#define REG_TWI0_IMR (*(RoReg*)0x4008402CU) +#define REG_TWI0_RHR (*(RoReg*)0x40084030U) +#define REG_TWI0_THR (*(WoReg*)0x40084034U) +#define REG_TWI0_RPR (*(RwReg*)0x40084100U) +#define REG_TWI0_RCR (*(RwReg*)0x40084104U) +#define REG_TWI0_TPR (*(RwReg*)0x40084108U) +#define REG_TWI0_TCR (*(RwReg*)0x4008410CU) +#define REG_TWI0_RNPR (*(RwReg*)0x40084110U) +#define REG_TWI0_RNCR (*(RwReg*)0x40084114U) +#define REG_TWI0_TNPR (*(RwReg*)0x40084118U) +#define REG_TWI0_TNCR (*(RwReg*)0x4008411CU) +#define REG_TWI0_PTCR (*(WoReg*)0x40084120U) +#define REG_TWI0_PTSR (*(RoReg*)0x40084124U) +# 280 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_twi1.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_twi1.h" +#define _SAM3U_TWI1_INSTANCE_ +# 69 "naeusb/sam3u_hal/inc/instance/instance_twi1.h" +#define REG_TWI1_CR (*(WoReg*)0x40088000U) +#define REG_TWI1_MMR (*(RwReg*)0x40088004U) +#define REG_TWI1_SMR (*(RwReg*)0x40088008U) +#define REG_TWI1_IADR (*(RwReg*)0x4008800CU) +#define REG_TWI1_CWGR (*(RwReg*)0x40088010U) +#define REG_TWI1_SR (*(RoReg*)0x40088020U) +#define REG_TWI1_IER (*(WoReg*)0x40088024U) +#define REG_TWI1_IDR (*(WoReg*)0x40088028U) +#define REG_TWI1_IMR (*(RoReg*)0x4008802CU) +#define REG_TWI1_RHR (*(RoReg*)0x40088030U) +#define REG_TWI1_THR (*(WoReg*)0x40088034U) +#define REG_TWI1_RPR (*(RwReg*)0x40088100U) +#define REG_TWI1_RCR (*(RwReg*)0x40088104U) +#define REG_TWI1_TPR (*(RwReg*)0x40088108U) +#define REG_TWI1_TCR (*(RwReg*)0x4008810CU) +#define REG_TWI1_RNPR (*(RwReg*)0x40088110U) +#define REG_TWI1_RNCR (*(RwReg*)0x40088114U) +#define REG_TWI1_TNPR (*(RwReg*)0x40088118U) +#define REG_TWI1_TNCR (*(RwReg*)0x4008811CU) +#define REG_TWI1_PTCR (*(WoReg*)0x40088120U) +#define REG_TWI1_PTSR (*(RoReg*)0x40088124U) +# 281 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_pwm.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_pwm.h" +#define _SAM3U_PWM_INSTANCE_ +# 148 "naeusb/sam3u_hal/inc/instance/instance_pwm.h" +#define REG_PWM_CLK (*(RwReg*)0x4008C000U) +#define REG_PWM_ENA (*(WoReg*)0x4008C004U) +#define REG_PWM_DIS (*(WoReg*)0x4008C008U) +#define REG_PWM_SR (*(RoReg*)0x4008C00CU) +#define REG_PWM_IER1 (*(WoReg*)0x4008C010U) +#define REG_PWM_IDR1 (*(WoReg*)0x4008C014U) +#define REG_PWM_IMR1 (*(RoReg*)0x4008C018U) +#define REG_PWM_ISR1 (*(RoReg*)0x4008C01CU) +#define REG_PWM_SCM (*(RwReg*)0x4008C020U) +#define REG_PWM_SCUC (*(RwReg*)0x4008C028U) +#define REG_PWM_SCUP (*(RwReg*)0x4008C02CU) +#define REG_PWM_SCUPUPD (*(WoReg*)0x4008C030U) +#define REG_PWM_IER2 (*(WoReg*)0x4008C034U) +#define REG_PWM_IDR2 (*(WoReg*)0x4008C038U) +#define REG_PWM_IMR2 (*(RoReg*)0x4008C03CU) +#define REG_PWM_ISR2 (*(RoReg*)0x4008C040U) +#define REG_PWM_OOV (*(RwReg*)0x4008C044U) +#define REG_PWM_OS (*(RwReg*)0x4008C048U) +#define REG_PWM_OSS (*(WoReg*)0x4008C04CU) +#define REG_PWM_OSC (*(WoReg*)0x4008C050U) +#define REG_PWM_OSSUPD (*(WoReg*)0x4008C054U) +#define REG_PWM_OSCUPD (*(WoReg*)0x4008C058U) +#define REG_PWM_FMR (*(RwReg*)0x4008C05CU) +#define REG_PWM_FSR (*(RoReg*)0x4008C060U) +#define REG_PWM_FCR (*(WoReg*)0x4008C064U) +#define REG_PWM_FPV (*(RwReg*)0x4008C068U) +#define REG_PWM_FPE (*(RwReg*)0x4008C06CU) +#define REG_PWM_ELMR (*(RwReg*)0x4008C07CU) +#define REG_PWM_WPCR (*(WoReg*)0x4008C0E4U) +#define REG_PWM_WPSR (*(RoReg*)0x4008C0E8U) +#define REG_PWM_TPR (*(RwReg*)0x4008C108U) +#define REG_PWM_TCR (*(RwReg*)0x4008C10CU) +#define REG_PWM_TNPR (*(RwReg*)0x4008C118U) +#define REG_PWM_TNCR (*(RwReg*)0x4008C11CU) +#define REG_PWM_PTCR (*(WoReg*)0x4008C120U) +#define REG_PWM_PTSR (*(RoReg*)0x4008C124U) +#define REG_PWM_CMPV0 (*(RwReg*)0x4008C130U) +#define REG_PWM_CMPVUPD0 (*(WoReg*)0x4008C134U) +#define REG_PWM_CMPM0 (*(RwReg*)0x4008C138U) +#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4008C13CU) +#define REG_PWM_CMPV1 (*(RwReg*)0x4008C140U) +#define REG_PWM_CMPVUPD1 (*(WoReg*)0x4008C144U) +#define REG_PWM_CMPM1 (*(RwReg*)0x4008C148U) +#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4008C14CU) +#define REG_PWM_CMPV2 (*(RwReg*)0x4008C150U) +#define REG_PWM_CMPVUPD2 (*(WoReg*)0x4008C154U) +#define REG_PWM_CMPM2 (*(RwReg*)0x4008C158U) +#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4008C15CU) +#define REG_PWM_CMPV3 (*(RwReg*)0x4008C160U) +#define REG_PWM_CMPVUPD3 (*(WoReg*)0x4008C164U) +#define REG_PWM_CMPM3 (*(RwReg*)0x4008C168U) +#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4008C16CU) +#define REG_PWM_CMPV4 (*(RwReg*)0x4008C170U) +#define REG_PWM_CMPVUPD4 (*(WoReg*)0x4008C174U) +#define REG_PWM_CMPM4 (*(RwReg*)0x4008C178U) +#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4008C17CU) +#define REG_PWM_CMPV5 (*(RwReg*)0x4008C180U) +#define REG_PWM_CMPVUPD5 (*(WoReg*)0x4008C184U) +#define REG_PWM_CMPM5 (*(RwReg*)0x4008C188U) +#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4008C18CU) +#define REG_PWM_CMPV6 (*(RwReg*)0x4008C190U) +#define REG_PWM_CMPVUPD6 (*(WoReg*)0x4008C194U) +#define REG_PWM_CMPM6 (*(RwReg*)0x4008C198U) +#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4008C19CU) +#define REG_PWM_CMPV7 (*(RwReg*)0x4008C1A0U) +#define REG_PWM_CMPVUPD7 (*(WoReg*)0x4008C1A4U) +#define REG_PWM_CMPM7 (*(RwReg*)0x4008C1A8U) +#define REG_PWM_CMPMUPD7 (*(WoReg*)0x4008C1ACU) +#define REG_PWM_CMR0 (*(RwReg*)0x4008C200U) +#define REG_PWM_CDTY0 (*(RwReg*)0x4008C204U) +#define REG_PWM_CDTYUPD0 (*(WoReg*)0x4008C208U) +#define REG_PWM_CPRD0 (*(RwReg*)0x4008C20CU) +#define REG_PWM_CPRDUPD0 (*(WoReg*)0x4008C210U) +#define REG_PWM_CCNT0 (*(RoReg*)0x4008C214U) +#define REG_PWM_DT0 (*(RwReg*)0x4008C218U) +#define REG_PWM_DTUPD0 (*(WoReg*)0x4008C21CU) +#define REG_PWM_CMR1 (*(RwReg*)0x4008C220U) +#define REG_PWM_CDTY1 (*(RwReg*)0x4008C224U) +#define REG_PWM_CDTYUPD1 (*(WoReg*)0x4008C228U) +#define REG_PWM_CPRD1 (*(RwReg*)0x4008C22CU) +#define REG_PWM_CPRDUPD1 (*(WoReg*)0x4008C230U) +#define REG_PWM_CCNT1 (*(RoReg*)0x4008C234U) +#define REG_PWM_DT1 (*(RwReg*)0x4008C238U) +#define REG_PWM_DTUPD1 (*(WoReg*)0x4008C23CU) +#define REG_PWM_CMR2 (*(RwReg*)0x4008C240U) +#define REG_PWM_CDTY2 (*(RwReg*)0x4008C244U) +#define REG_PWM_CDTYUPD2 (*(WoReg*)0x4008C248U) +#define REG_PWM_CPRD2 (*(RwReg*)0x4008C24CU) +#define REG_PWM_CPRDUPD2 (*(WoReg*)0x4008C250U) +#define REG_PWM_CCNT2 (*(RoReg*)0x4008C254U) +#define REG_PWM_DT2 (*(RwReg*)0x4008C258U) +#define REG_PWM_DTUPD2 (*(WoReg*)0x4008C25CU) +#define REG_PWM_CMR3 (*(RwReg*)0x4008C260U) +#define REG_PWM_CDTY3 (*(RwReg*)0x4008C264U) +#define REG_PWM_CDTYUPD3 (*(WoReg*)0x4008C268U) +#define REG_PWM_CPRD3 (*(RwReg*)0x4008C26CU) +#define REG_PWM_CPRDUPD3 (*(WoReg*)0x4008C270U) +#define REG_PWM_CCNT3 (*(RoReg*)0x4008C274U) +#define REG_PWM_DT3 (*(RwReg*)0x4008C278U) +#define REG_PWM_DTUPD3 (*(WoReg*)0x4008C27CU) +# 282 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_usart0.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_usart0.h" +#define _SAM3U_USART0_INSTANCE_ +# 75 "naeusb/sam3u_hal/inc/instance/instance_usart0.h" +#define REG_USART0_CR (*(WoReg*)0x40090000U) +#define REG_USART0_MR (*(RwReg*)0x40090004U) +#define REG_USART0_IER (*(WoReg*)0x40090008U) +#define REG_USART0_IDR (*(WoReg*)0x4009000CU) +#define REG_USART0_IMR (*(RoReg*)0x40090010U) +#define REG_USART0_CSR (*(RoReg*)0x40090014U) +#define REG_USART0_RHR (*(RoReg*)0x40090018U) +#define REG_USART0_THR (*(WoReg*)0x4009001CU) +#define REG_USART0_BRGR (*(RwReg*)0x40090020U) +#define REG_USART0_RTOR (*(RwReg*)0x40090024U) +#define REG_USART0_TTGR (*(RwReg*)0x40090028U) +#define REG_USART0_FIDI (*(RwReg*)0x40090040U) +#define REG_USART0_NER (*(RoReg*)0x40090044U) +#define REG_USART0_IF (*(RwReg*)0x4009004CU) +#define REG_USART0_MAN (*(RwReg*)0x40090050U) +#define REG_USART0_WPMR (*(RwReg*)0x400900E4U) +#define REG_USART0_WPSR (*(RoReg*)0x400900E8U) +#define REG_USART0_RPR (*(RwReg*)0x40090100U) +#define REG_USART0_RCR (*(RwReg*)0x40090104U) +#define REG_USART0_TPR (*(RwReg*)0x40090108U) +#define REG_USART0_TCR (*(RwReg*)0x4009010CU) +#define REG_USART0_RNPR (*(RwReg*)0x40090110U) +#define REG_USART0_RNCR (*(RwReg*)0x40090114U) +#define REG_USART0_TNPR (*(RwReg*)0x40090118U) +#define REG_USART0_TNCR (*(RwReg*)0x4009011CU) +#define REG_USART0_PTCR (*(WoReg*)0x40090120U) +#define REG_USART0_PTSR (*(RoReg*)0x40090124U) +# 283 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_usart1.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_usart1.h" +#define _SAM3U_USART1_INSTANCE_ +# 75 "naeusb/sam3u_hal/inc/instance/instance_usart1.h" +#define REG_USART1_CR (*(WoReg*)0x40094000U) +#define REG_USART1_MR (*(RwReg*)0x40094004U) +#define REG_USART1_IER (*(WoReg*)0x40094008U) +#define REG_USART1_IDR (*(WoReg*)0x4009400CU) +#define REG_USART1_IMR (*(RoReg*)0x40094010U) +#define REG_USART1_CSR (*(RoReg*)0x40094014U) +#define REG_USART1_RHR (*(RoReg*)0x40094018U) +#define REG_USART1_THR (*(WoReg*)0x4009401CU) +#define REG_USART1_BRGR (*(RwReg*)0x40094020U) +#define REG_USART1_RTOR (*(RwReg*)0x40094024U) +#define REG_USART1_TTGR (*(RwReg*)0x40094028U) +#define REG_USART1_FIDI (*(RwReg*)0x40094040U) +#define REG_USART1_NER (*(RoReg*)0x40094044U) +#define REG_USART1_IF (*(RwReg*)0x4009404CU) +#define REG_USART1_MAN (*(RwReg*)0x40094050U) +#define REG_USART1_WPMR (*(RwReg*)0x400940E4U) +#define REG_USART1_WPSR (*(RoReg*)0x400940E8U) +#define REG_USART1_RPR (*(RwReg*)0x40094100U) +#define REG_USART1_RCR (*(RwReg*)0x40094104U) +#define REG_USART1_TPR (*(RwReg*)0x40094108U) +#define REG_USART1_TCR (*(RwReg*)0x4009410CU) +#define REG_USART1_RNPR (*(RwReg*)0x40094110U) +#define REG_USART1_RNCR (*(RwReg*)0x40094114U) +#define REG_USART1_TNPR (*(RwReg*)0x40094118U) +#define REG_USART1_TNCR (*(RwReg*)0x4009411CU) +#define REG_USART1_PTCR (*(WoReg*)0x40094120U) +#define REG_USART1_PTSR (*(RoReg*)0x40094124U) +# 284 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_usart2.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_usart2.h" +#define _SAM3U_USART2_INSTANCE_ +# 75 "naeusb/sam3u_hal/inc/instance/instance_usart2.h" +#define REG_USART2_CR (*(WoReg*)0x40098000U) +#define REG_USART2_MR (*(RwReg*)0x40098004U) +#define REG_USART2_IER (*(WoReg*)0x40098008U) +#define REG_USART2_IDR (*(WoReg*)0x4009800CU) +#define REG_USART2_IMR (*(RoReg*)0x40098010U) +#define REG_USART2_CSR (*(RoReg*)0x40098014U) +#define REG_USART2_RHR (*(RoReg*)0x40098018U) +#define REG_USART2_THR (*(WoReg*)0x4009801CU) +#define REG_USART2_BRGR (*(RwReg*)0x40098020U) +#define REG_USART2_RTOR (*(RwReg*)0x40098024U) +#define REG_USART2_TTGR (*(RwReg*)0x40098028U) +#define REG_USART2_FIDI (*(RwReg*)0x40098040U) +#define REG_USART2_NER (*(RoReg*)0x40098044U) +#define REG_USART2_IF (*(RwReg*)0x4009804CU) +#define REG_USART2_MAN (*(RwReg*)0x40098050U) +#define REG_USART2_WPMR (*(RwReg*)0x400980E4U) +#define REG_USART2_WPSR (*(RoReg*)0x400980E8U) +#define REG_USART2_RPR (*(RwReg*)0x40098100U) +#define REG_USART2_RCR (*(RwReg*)0x40098104U) +#define REG_USART2_TPR (*(RwReg*)0x40098108U) +#define REG_USART2_TCR (*(RwReg*)0x4009810CU) +#define REG_USART2_RNPR (*(RwReg*)0x40098110U) +#define REG_USART2_RNCR (*(RwReg*)0x40098114U) +#define REG_USART2_TNPR (*(RwReg*)0x40098118U) +#define REG_USART2_TNCR (*(RwReg*)0x4009811CU) +#define REG_USART2_PTCR (*(WoReg*)0x40098120U) +#define REG_USART2_PTSR (*(RoReg*)0x40098124U) +# 285 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_udphs.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_udphs.h" +#define _SAM3U_UDPHS_INSTANCE_ +# 131 "naeusb/sam3u_hal/inc/instance/instance_udphs.h" +#define REG_UDPHS_CTRL (*(RwReg*)0x400A4000U) +#define REG_UDPHS_FNUM (*(RoReg*)0x400A4004U) +#define REG_UDPHS_IEN (*(RwReg*)0x400A4010U) +#define REG_UDPHS_INTSTA (*(RoReg*)0x400A4014U) +#define REG_UDPHS_CLRINT (*(WoReg*)0x400A4018U) +#define REG_UDPHS_EPTRST (*(WoReg*)0x400A401CU) +#define REG_UDPHS_TST (*(RwReg*)0x400A40E0U) +#define REG_UDPHS_IPNAME1 (*(RoReg*)0x400A40F0U) +#define REG_UDPHS_IPNAME2 (*(RoReg*)0x400A40F4U) +#define REG_UDPHS_IPFEATURES (*(RoReg*)0x400A40F8U) +#define REG_UDPHS_EPTCFG0 (*(RwReg*)0x400A4100U) +#define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0x400A4104U) +#define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0x400A4108U) +#define REG_UDPHS_EPTCTL0 (*(RoReg*)0x400A410CU) +#define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0x400A4114U) +#define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0x400A4118U) +#define REG_UDPHS_EPTSTA0 (*(RoReg*)0x400A411CU) +#define REG_UDPHS_EPTCFG1 (*(RwReg*)0x400A4120U) +#define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0x400A4124U) +#define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0x400A4128U) +#define REG_UDPHS_EPTCTL1 (*(RoReg*)0x400A412CU) +#define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0x400A4134U) +#define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0x400A4138U) +#define REG_UDPHS_EPTSTA1 (*(RoReg*)0x400A413CU) +#define REG_UDPHS_EPTCFG2 (*(RwReg*)0x400A4140U) +#define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0x400A4144U) +#define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0x400A4148U) +#define REG_UDPHS_EPTCTL2 (*(RoReg*)0x400A414CU) +#define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0x400A4154U) +#define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0x400A4158U) +#define REG_UDPHS_EPTSTA2 (*(RoReg*)0x400A415CU) +#define REG_UDPHS_EPTCFG3 (*(RwReg*)0x400A4160U) +#define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0x400A4164U) +#define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0x400A4168U) +#define REG_UDPHS_EPTCTL3 (*(RoReg*)0x400A416CU) +#define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0x400A4174U) +#define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0x400A4178U) +#define REG_UDPHS_EPTSTA3 (*(RoReg*)0x400A417CU) +#define REG_UDPHS_EPTCFG4 (*(RwReg*)0x400A4180U) +#define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0x400A4184U) +#define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0x400A4188U) +#define REG_UDPHS_EPTCTL4 (*(RoReg*)0x400A418CU) +#define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0x400A4194U) +#define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0x400A4198U) +#define REG_UDPHS_EPTSTA4 (*(RoReg*)0x400A419CU) +#define REG_UDPHS_EPTCFG5 (*(RwReg*)0x400A41A0U) +#define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0x400A41A4U) +#define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0x400A41A8U) +#define REG_UDPHS_EPTCTL5 (*(RoReg*)0x400A41ACU) +#define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0x400A41B4U) +#define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0x400A41B8U) +#define REG_UDPHS_EPTSTA5 (*(RoReg*)0x400A41BCU) +#define REG_UDPHS_EPTCFG6 (*(RwReg*)0x400A41C0U) +#define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0x400A41C4U) +#define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0x400A41C8U) +#define REG_UDPHS_EPTCTL6 (*(RoReg*)0x400A41CCU) +#define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0x400A41D4U) +#define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0x400A41D8U) +#define REG_UDPHS_EPTSTA6 (*(RoReg*)0x400A41DCU) +#define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0x400A4300U) +#define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) +#define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) +#define REG_UDPHS_DMASTATUS0 (*(RwReg*)0x400A430CU) +#define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0x400A4310U) +#define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) +#define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) +#define REG_UDPHS_DMASTATUS1 (*(RwReg*)0x400A431CU) +#define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0x400A4320U) +#define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) +#define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) +#define REG_UDPHS_DMASTATUS2 (*(RwReg*)0x400A432CU) +#define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0x400A4330U) +#define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) +#define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) +#define REG_UDPHS_DMASTATUS3 (*(RwReg*)0x400A433CU) +#define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0x400A4340U) +#define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) +#define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) +#define REG_UDPHS_DMASTATUS4 (*(RwReg*)0x400A434CU) +#define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0x400A4350U) +#define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) +#define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) +#define REG_UDPHS_DMASTATUS5 (*(RwReg*)0x400A435CU) +# 286 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_adc12b.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_adc12b.h" +#define _SAM3U_ADC12B_INSTANCE_ +# 67 "naeusb/sam3u_hal/inc/instance/instance_adc12b.h" +#define REG_ADC12B_CR (*(WoReg*)0x400A8000U) +#define REG_ADC12B_MR (*(RwReg*)0x400A8004U) +#define REG_ADC12B_CHER (*(WoReg*)0x400A8010U) +#define REG_ADC12B_CHDR (*(WoReg*)0x400A8014U) +#define REG_ADC12B_CHSR (*(RoReg*)0x400A8018U) +#define REG_ADC12B_SR (*(RoReg*)0x400A801CU) +#define REG_ADC12B_LCDR (*(RoReg*)0x400A8020U) +#define REG_ADC12B_IER (*(WoReg*)0x400A8024U) +#define REG_ADC12B_IDR (*(WoReg*)0x400A8028U) +#define REG_ADC12B_IMR (*(RoReg*)0x400A802CU) +#define REG_ADC12B_CDR (*(RoReg*)0x400A8030U) +#define REG_ADC12B_ACR (*(RwReg*)0x400A8064U) +#define REG_ADC12B_EMR (*(RwReg*)0x400A8068U) +#define REG_ADC12B_RPR (*(RwReg*)0x400A8100U) +#define REG_ADC12B_RCR (*(RwReg*)0x400A8104U) +#define REG_ADC12B_RNPR (*(RwReg*)0x400A8110U) +#define REG_ADC12B_RNCR (*(RwReg*)0x400A8114U) +#define REG_ADC12B_PTCR (*(WoReg*)0x400A8120U) +#define REG_ADC12B_PTSR (*(RoReg*)0x400A8124U) +# 287 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_adc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_adc.h" +#define _SAM3U_ADC_INSTANCE_ +# 65 "naeusb/sam3u_hal/inc/instance/instance_adc.h" +#define REG_ADC_CR (*(WoReg*)0x400AC000U) +#define REG_ADC_MR (*(RwReg*)0x400AC004U) +#define REG_ADC_CHER (*(WoReg*)0x400AC010U) +#define REG_ADC_CHDR (*(WoReg*)0x400AC014U) +#define REG_ADC_CHSR (*(RoReg*)0x400AC018U) +#define REG_ADC_SR (*(RoReg*)0x400AC01CU) +#define REG_ADC_LCDR (*(RoReg*)0x400AC020U) +#define REG_ADC_IER (*(WoReg*)0x400AC024U) +#define REG_ADC_IDR (*(WoReg*)0x400AC028U) +#define REG_ADC_IMR (*(RoReg*)0x400AC02CU) +#define REG_ADC_CDR (*(RoReg*)0x400AC030U) +#define REG_ADC_RPR (*(RwReg*)0x400AC100U) +#define REG_ADC_RCR (*(RwReg*)0x400AC104U) +#define REG_ADC_RNPR (*(RwReg*)0x400AC110U) +#define REG_ADC_RNCR (*(RwReg*)0x400AC114U) +#define REG_ADC_PTCR (*(WoReg*)0x400AC120U) +#define REG_ADC_PTSR (*(RoReg*)0x400AC124U) +# 288 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_dmac.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_dmac.h" +#define _SAM3U_DMAC_INSTANCE_ +# 86 "naeusb/sam3u_hal/inc/instance/instance_dmac.h" +#define REG_DMAC_GCFG (*(RwReg*)0x400B0000U) +#define REG_DMAC_EN (*(RwReg*)0x400B0004U) +#define REG_DMAC_SREQ (*(RwReg*)0x400B0008U) +#define REG_DMAC_CREQ (*(RwReg*)0x400B000CU) +#define REG_DMAC_LAST (*(RwReg*)0x400B0010U) +#define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U) +#define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU) +#define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U) +#define REG_DMAC_EBCISR (*(RoReg*)0x400B0024U) +#define REG_DMAC_CHER (*(WoReg*)0x400B0028U) +#define REG_DMAC_CHDR (*(WoReg*)0x400B002CU) +#define REG_DMAC_CHSR (*(RoReg*)0x400B0030U) +#define REG_DMAC_SADDR0 (*(RwReg*)0x400B003CU) +#define REG_DMAC_DADDR0 (*(RwReg*)0x400B0040U) +#define REG_DMAC_DSCR0 (*(RwReg*)0x400B0044U) +#define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U) +#define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU) +#define REG_DMAC_CFG0 (*(RwReg*)0x400B0050U) +#define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U) +#define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U) +#define REG_DMAC_DSCR1 (*(RwReg*)0x400B006CU) +#define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U) +#define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U) +#define REG_DMAC_CFG1 (*(RwReg*)0x400B0078U) +#define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU) +#define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U) +#define REG_DMAC_DSCR2 (*(RwReg*)0x400B0094U) +#define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U) +#define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU) +#define REG_DMAC_CFG2 (*(RwReg*)0x400B00A0U) +#define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U) +#define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U) +#define REG_DMAC_DSCR3 (*(RwReg*)0x400B00BCU) +#define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U) +#define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U) +#define REG_DMAC_CFG3 (*(RwReg*)0x400B00C8U) +#define REG_DMAC_WPMR (*(RwReg*)0x400B01E4U) +#define REG_DMAC_WPSR (*(RoReg*)0x400B01E8U) +# 289 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_smc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_smc.h" +#define _SAM3U_SMC_INSTANCE_ +# 101 "naeusb/sam3u_hal/inc/instance/instance_smc.h" +#define REG_SMC_CFG (*(RwReg*)0x400E0000U) +#define REG_SMC_CTRL (*(WoReg*)0x400E0004U) +#define REG_SMC_SR (*(RoReg*)0x400E0008U) +#define REG_SMC_IER (*(WoReg*)0x400E000CU) +#define REG_SMC_IDR (*(WoReg*)0x400E0010U) +#define REG_SMC_IMR (*(RoReg*)0x400E0014U) +#define REG_SMC_ADDR (*(RwReg*)0x400E0018U) +#define REG_SMC_BANK (*(RwReg*)0x400E001CU) +#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) +#define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U) +#define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U) +#define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU) +#define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U) +#define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U) +#define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U) +#define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU) +#define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U) +#define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U) +#define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U) +#define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU) +#define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U) +#define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U) +#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) +#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) +#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) +#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) +#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) +#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) +#define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U) +#define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U) +#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U) +#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) +#define REG_SMC_MODE0 (*(RwReg*)0x400E0080U) +#define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U) +#define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U) +#define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU) +#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) +#define REG_SMC_MODE1 (*(RwReg*)0x400E0094U) +#define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U) +#define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU) +#define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U) +#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) +#define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U) +#define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU) +#define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U) +#define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U) +#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) +#define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU) +#define REG_SMC_OCMS (*(RwReg*)0x400E0110U) +#define REG_SMC_KEY1 (*(WoReg*)0x400E0114U) +#define REG_SMC_KEY2 (*(WoReg*)0x400E0118U) +#define REG_SMC_WPCR (*(WoReg*)0x400E01E4U) +#define REG_SMC_WPSR (*(RoReg*)0x400E01E8U) +# 290 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_matrix.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_matrix.h" +#define _SAM3U_MATRIX_INSTANCE_ +# 63 "naeusb/sam3u_hal/inc/instance/instance_matrix.h" +#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) +#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) +#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) +#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) +#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) +#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) +#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) +#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E02A8U) +#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E02B0U) +#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E02B8U) +#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E02C0U) +#define REG_MATRIX_PRAS9 (*(RwReg*)0x400E02C8U) +#define REG_MATRIX_MRCR (*(RwReg*)0x400E0300U) +#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) +#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) +# 291 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_pmc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_pmc.h" +#define _SAM3U_PMC_INSTANCE_ +# 69 "naeusb/sam3u_hal/inc/instance/instance_pmc.h" +#define REG_PMC_SCER (*(WoReg*)0x400E0400U) +#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) +#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) +#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) +#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) +#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) +#define REG_CKGR_UCKR (*(RwReg*)0x400E041CU) +#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) +#define REG_CKGR_MCFR (*(RoReg*)0x400E0424U) +#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) +#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) +#define REG_PMC_PCK (*(RwReg*)0x400E0440U) +#define REG_PMC_IER (*(WoReg*)0x400E0460U) +#define REG_PMC_IDR (*(WoReg*)0x400E0464U) +#define REG_PMC_SR (*(RoReg*)0x400E0468U) +#define REG_PMC_IMR (*(RoReg*)0x400E046CU) +#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) +#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) +#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) +#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) +#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) +# 292 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_uart.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_uart.h" +#define _SAM3U_UART_INSTANCE_ +# 67 "naeusb/sam3u_hal/inc/instance/instance_uart.h" +#define REG_UART_CR (*(WoReg*)0x400E0600U) +#define REG_UART_MR (*(RwReg*)0x400E0604U) +#define REG_UART_IER (*(WoReg*)0x400E0608U) +#define REG_UART_IDR (*(WoReg*)0x400E060CU) +#define REG_UART_IMR (*(RoReg*)0x400E0610U) +#define REG_UART_SR (*(RoReg*)0x400E0614U) +#define REG_UART_RHR (*(RoReg*)0x400E0618U) +#define REG_UART_THR (*(WoReg*)0x400E061CU) +#define REG_UART_BRGR (*(RwReg*)0x400E0620U) +#define REG_UART_RPR (*(RwReg*)0x400E0700U) +#define REG_UART_RCR (*(RwReg*)0x400E0704U) +#define REG_UART_TPR (*(RwReg*)0x400E0708U) +#define REG_UART_TCR (*(RwReg*)0x400E070CU) +#define REG_UART_RNPR (*(RwReg*)0x400E0710U) +#define REG_UART_RNCR (*(RwReg*)0x400E0714U) +#define REG_UART_TNPR (*(RwReg*)0x400E0718U) +#define REG_UART_TNCR (*(RwReg*)0x400E071CU) +#define REG_UART_PTCR (*(WoReg*)0x400E0720U) +#define REG_UART_PTSR (*(RoReg*)0x400E0724U) +# 293 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_chipid.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_chipid.h" +#define _SAM3U_CHIPID_INSTANCE_ + + + + + + +#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) +#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) +# 294 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_efc0.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_efc0.h" +#define _SAM3U_EFC0_INSTANCE_ +# 52 "naeusb/sam3u_hal/inc/instance/instance_efc0.h" +#define REG_EFC0_FMR (*(RwReg*)0x400E0800U) +#define REG_EFC0_FCR (*(WoReg*)0x400E0804U) +#define REG_EFC0_FSR (*(RoReg*)0x400E0808U) +#define REG_EFC0_FRR (*(RoReg*)0x400E080CU) +# 295 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_efc1.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_efc1.h" +#define _SAM3U_EFC1_INSTANCE_ +# 52 "naeusb/sam3u_hal/inc/instance/instance_efc1.h" +#define REG_EFC1_FMR (*(RwReg*)0x400E0A00U) +#define REG_EFC1_FCR (*(WoReg*)0x400E0A04U) +#define REG_EFC1_FSR (*(RoReg*)0x400E0A08U) +#define REG_EFC1_FRR (*(RoReg*)0x400E0A0CU) +# 296 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_pioa.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_pioa.h" +#define _SAM3U_PIOA_INSTANCE_ +# 91 "naeusb/sam3u_hal/inc/instance/instance_pioa.h" +#define REG_PIOA_PER (*(WoReg*)0x400E0C00U) +#define REG_PIOA_PDR (*(WoReg*)0x400E0C04U) +#define REG_PIOA_PSR (*(RoReg*)0x400E0C08U) +#define REG_PIOA_OER (*(WoReg*)0x400E0C10U) +#define REG_PIOA_ODR (*(WoReg*)0x400E0C14U) +#define REG_PIOA_OSR (*(RoReg*)0x400E0C18U) +#define REG_PIOA_IFER (*(WoReg*)0x400E0C20U) +#define REG_PIOA_IFDR (*(WoReg*)0x400E0C24U) +#define REG_PIOA_IFSR (*(RoReg*)0x400E0C28U) +#define REG_PIOA_SODR (*(WoReg*)0x400E0C30U) +#define REG_PIOA_CODR (*(WoReg*)0x400E0C34U) +#define REG_PIOA_ODSR (*(RwReg*)0x400E0C38U) +#define REG_PIOA_PDSR (*(RoReg*)0x400E0C3CU) +#define REG_PIOA_IER (*(WoReg*)0x400E0C40U) +#define REG_PIOA_IDR (*(WoReg*)0x400E0C44U) +#define REG_PIOA_IMR (*(RoReg*)0x400E0C48U) +#define REG_PIOA_ISR (*(RoReg*)0x400E0C4CU) +#define REG_PIOA_MDER (*(WoReg*)0x400E0C50U) +#define REG_PIOA_MDDR (*(WoReg*)0x400E0C54U) +#define REG_PIOA_MDSR (*(RoReg*)0x400E0C58U) +#define REG_PIOA_PUDR (*(WoReg*)0x400E0C60U) +#define REG_PIOA_PUER (*(WoReg*)0x400E0C64U) +#define REG_PIOA_PUSR (*(RoReg*)0x400E0C68U) +#define REG_PIOA_ABSR (*(RwReg*)0x400E0C70U) +#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0C80U) +#define REG_PIOA_DIFSR (*(WoReg*)0x400E0C84U) +#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0C88U) +#define REG_PIOA_SCDR (*(RwReg*)0x400E0C8CU) +#define REG_PIOA_OWER (*(WoReg*)0x400E0CA0U) +#define REG_PIOA_OWDR (*(WoReg*)0x400E0CA4U) +#define REG_PIOA_OWSR (*(RoReg*)0x400E0CA8U) +#define REG_PIOA_AIMER (*(WoReg*)0x400E0CB0U) +#define REG_PIOA_AIMDR (*(WoReg*)0x400E0CB4U) +#define REG_PIOA_AIMMR (*(RoReg*)0x400E0CB8U) +#define REG_PIOA_ESR (*(WoReg*)0x400E0CC0U) +#define REG_PIOA_LSR (*(WoReg*)0x400E0CC4U) +#define REG_PIOA_ELSR (*(RoReg*)0x400E0CC8U) +#define REG_PIOA_FELLSR (*(WoReg*)0x400E0CD0U) +#define REG_PIOA_REHLSR (*(WoReg*)0x400E0CD4U) +#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0CD8U) +#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0CE0U) +#define REG_PIOA_WPMR (*(RwReg*)0x400E0CE4U) +#define REG_PIOA_WPSR (*(RoReg*)0x400E0CE8U) +# 297 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_piob.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_piob.h" +#define _SAM3U_PIOB_INSTANCE_ +# 91 "naeusb/sam3u_hal/inc/instance/instance_piob.h" +#define REG_PIOB_PER (*(WoReg*)0x400E0E00U) +#define REG_PIOB_PDR (*(WoReg*)0x400E0E04U) +#define REG_PIOB_PSR (*(RoReg*)0x400E0E08U) +#define REG_PIOB_OER (*(WoReg*)0x400E0E10U) +#define REG_PIOB_ODR (*(WoReg*)0x400E0E14U) +#define REG_PIOB_OSR (*(RoReg*)0x400E0E18U) +#define REG_PIOB_IFER (*(WoReg*)0x400E0E20U) +#define REG_PIOB_IFDR (*(WoReg*)0x400E0E24U) +#define REG_PIOB_IFSR (*(RoReg*)0x400E0E28U) +#define REG_PIOB_SODR (*(WoReg*)0x400E0E30U) +#define REG_PIOB_CODR (*(WoReg*)0x400E0E34U) +#define REG_PIOB_ODSR (*(RwReg*)0x400E0E38U) +#define REG_PIOB_PDSR (*(RoReg*)0x400E0E3CU) +#define REG_PIOB_IER (*(WoReg*)0x400E0E40U) +#define REG_PIOB_IDR (*(WoReg*)0x400E0E44U) +#define REG_PIOB_IMR (*(RoReg*)0x400E0E48U) +#define REG_PIOB_ISR (*(RoReg*)0x400E0E4CU) +#define REG_PIOB_MDER (*(WoReg*)0x400E0E50U) +#define REG_PIOB_MDDR (*(WoReg*)0x400E0E54U) +#define REG_PIOB_MDSR (*(RoReg*)0x400E0E58U) +#define REG_PIOB_PUDR (*(WoReg*)0x400E0E60U) +#define REG_PIOB_PUER (*(WoReg*)0x400E0E64U) +#define REG_PIOB_PUSR (*(RoReg*)0x400E0E68U) +#define REG_PIOB_ABSR (*(RwReg*)0x400E0E70U) +#define REG_PIOB_SCIFSR (*(WoReg*)0x400E0E80U) +#define REG_PIOB_DIFSR (*(WoReg*)0x400E0E84U) +#define REG_PIOB_IFDGSR (*(RoReg*)0x400E0E88U) +#define REG_PIOB_SCDR (*(RwReg*)0x400E0E8CU) +#define REG_PIOB_OWER (*(WoReg*)0x400E0EA0U) +#define REG_PIOB_OWDR (*(WoReg*)0x400E0EA4U) +#define REG_PIOB_OWSR (*(RoReg*)0x400E0EA8U) +#define REG_PIOB_AIMER (*(WoReg*)0x400E0EB0U) +#define REG_PIOB_AIMDR (*(WoReg*)0x400E0EB4U) +#define REG_PIOB_AIMMR (*(RoReg*)0x400E0EB8U) +#define REG_PIOB_ESR (*(WoReg*)0x400E0EC0U) +#define REG_PIOB_LSR (*(WoReg*)0x400E0EC4U) +#define REG_PIOB_ELSR (*(RoReg*)0x400E0EC8U) +#define REG_PIOB_FELLSR (*(WoReg*)0x400E0ED0U) +#define REG_PIOB_REHLSR (*(WoReg*)0x400E0ED4U) +#define REG_PIOB_FRLHSR (*(RoReg*)0x400E0ED8U) +#define REG_PIOB_LOCKSR (*(RoReg*)0x400E0EE0U) +#define REG_PIOB_WPMR (*(RwReg*)0x400E0EE4U) +#define REG_PIOB_WPSR (*(RoReg*)0x400E0EE8U) +# 298 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_rstc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_rstc.h" +#define _SAM3U_RSTC_INSTANCE_ + + + + + + + +#define REG_RSTC_CR (*(WoReg*)0x400E1200U) +#define REG_RSTC_SR (*(RoReg*)0x400E1204U) +#define REG_RSTC_MR (*(RwReg*)0x400E1208U) +# 299 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_supc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_supc.h" +#define _SAM3U_SUPC_INSTANCE_ +# 54 "naeusb/sam3u_hal/inc/instance/instance_supc.h" +#define REG_SUPC_CR (*(WoReg*)0x400E1210U) +#define REG_SUPC_SMMR (*(RwReg*)0x400E1214U) +#define REG_SUPC_MR (*(RwReg*)0x400E1218U) +#define REG_SUPC_WUMR (*(RwReg*)0x400E121CU) +#define REG_SUPC_WUIR (*(RwReg*)0x400E1220U) +#define REG_SUPC_SR (*(RoReg*)0x400E1224U) +# 300 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_rtt.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_rtt.h" +#define _SAM3U_RTT_INSTANCE_ +# 52 "naeusb/sam3u_hal/inc/instance/instance_rtt.h" +#define REG_RTT_MR (*(RwReg*)0x400E1230U) +#define REG_RTT_AR (*(RwReg*)0x400E1234U) +#define REG_RTT_VR (*(RoReg*)0x400E1238U) +#define REG_RTT_SR (*(RoReg*)0x400E123CU) +# 301 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_wdt.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_wdt.h" +#define _SAM3U_WDT_INSTANCE_ + + + + + + + +#define REG_WDT_CR (*(WoReg*)0x400E1250U) +#define REG_WDT_MR (*(RwReg*)0x400E1254U) +#define REG_WDT_SR (*(RoReg*)0x400E1258U) +# 302 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_rtc.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_rtc.h" +#define _SAM3U_RTC_INSTANCE_ +# 61 "naeusb/sam3u_hal/inc/instance/instance_rtc.h" +#define REG_RTC_CR (*(RwReg*)0x400E1260U) +#define REG_RTC_MR (*(RwReg*)0x400E1264U) +#define REG_RTC_TIMR (*(RwReg*)0x400E1268U) +#define REG_RTC_CALR (*(RwReg*)0x400E126CU) +#define REG_RTC_TIMALR (*(RwReg*)0x400E1270U) +#define REG_RTC_CALALR (*(RwReg*)0x400E1274U) +#define REG_RTC_SR (*(RoReg*)0x400E1278U) +#define REG_RTC_SCCR (*(WoReg*)0x400E127CU) +#define REG_RTC_IER (*(WoReg*)0x400E1280U) +#define REG_RTC_IDR (*(WoReg*)0x400E1284U) +#define REG_RTC_IMR (*(RoReg*)0x400E1288U) +#define REG_RTC_VER (*(RoReg*)0x400E128CU) +#define REG_RTC_WPMR (*(RwReg*)0x400E1344U) +# 303 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 1 "naeusb/sam3u_hal/inc/instance/instance_gpbr.h" 1 +# 43 "naeusb/sam3u_hal/inc/instance/instance_gpbr.h" +#define _SAM3U_GPBR_INSTANCE_ + + + + + +#define REG_GPBR_GPBR (*(RwReg*)0x400E1290U) +# 304 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 +# 312 "naeusb/sam3u_hal/inc/sam3u2c.h" +#define ID_SUPC ( 0) +#define ID_RSTC ( 1) +#define ID_RTC ( 2) +#define ID_RTT ( 3) +#define ID_WDT ( 4) +#define ID_PMC ( 5) +#define ID_EFC0 ( 6) +#define ID_EFC1 ( 7) +#define ID_UART ( 8) +#define ID_SMC ( 9) +#define ID_PIOA (10) +#define ID_PIOB (11) +#define ID_USART0 (13) +#define ID_USART1 (14) +#define ID_USART2 (15) +#define ID_HSMCI (17) +#define ID_TWI0 (18) +#define ID_TWI1 (19) +#define ID_SPI (20) +#define ID_SSC (21) +#define ID_TC0 (22) +#define ID_TC1 (23) +#define ID_TC2 (24) +#define ID_PWM (25) +#define ID_ADC12B (26) +#define ID_ADC (27) +#define ID_DMAC (28) +#define ID_UDPHS (29) +# 388 "naeusb/sam3u_hal/inc/sam3u2c.h" +#define HSMCI ((Hsmci *)0x40000000U) +#define SSC ((Ssc *)0x40004000U) +#define SPI ((Spi *)0x40008000U) +#define TC0 ((Tc *)0x40080000U) +#define TWI0 ((Twi *)0x40084000U) +#define PDC_TWI0 ((Pdc *)0x40084100U) +#define TWI1 ((Twi *)0x40088000U) +#define PDC_TWI1 ((Pdc *)0x40088100U) +#define PWM ((Pwm *)0x4008C000U) +#define PDC_PWM ((Pdc *)0x4008C100U) +#define USART0 ((Usart *)0x40090000U) +#define PDC_USART0 ((Pdc *)0x40090100U) +#define USART1 ((Usart *)0x40094000U) +#define PDC_USART1 ((Pdc *)0x40094100U) +#define USART2 ((Usart *)0x40098000U) +#define PDC_USART2 ((Pdc *)0x40098100U) +#define UDPHS ((Udphs *)0x400A4000U) +#define ADC12B ((Adc12b *)0x400A8000U) +#define PDC_ADC12B ((Pdc *)0x400A8100U) +#define ADC ((Adc *)0x400AC000U) +#define PDC_ADC ((Pdc *)0x400AC100U) +#define DMAC ((Dmac *)0x400B0000U) +#define SMC ((Smc *)0x400E0000U) +#define MATRIX ((Matrix *)0x400E0200U) +#define PMC ((Pmc *)0x400E0400U) +#define UART ((Uart *)0x400E0600U) +#define PDC_UART ((Pdc *)0x400E0700U) +#define CHIPID ((Chipid *)0x400E0740U) +#define EFC0 ((Efc *)0x400E0800U) +#define EFC1 ((Efc *)0x400E0A00U) +#define PIOA ((Pio *)0x400E0C00U) +#define PIOB ((Pio *)0x400E0E00U) +#define RSTC ((Rstc *)0x400E1200U) +#define SUPC ((Supc *)0x400E1210U) +#define RTT ((Rtt *)0x400E1230U) +#define WDT ((Wdt *)0x400E1250U) +#define RTC ((Rtc *)0x400E1260U) +#define GPBR ((Gpbr *)0x400E1290U) +# 435 "naeusb/sam3u_hal/inc/sam3u2c.h" +# 1 "naeusb/sam3u_hal/inc/pio/pio_sam3u2c.h" 1 +# 43 "naeusb/sam3u_hal/inc/pio/pio_sam3u2c.h" +#define _SAM3U2C_PIO_ + +#define PIO_PA0 (1u << 0) +#define PIO_PA1 (1u << 1) +#define PIO_PA2 (1u << 2) +#define PIO_PA3 (1u << 3) +#define PIO_PA4 (1u << 4) +#define PIO_PA5 (1u << 5) +#define PIO_PA6 (1u << 6) +#define PIO_PA7 (1u << 7) +#define PIO_PA8 (1u << 8) +#define PIO_PA9 (1u << 9) +#define PIO_PA10 (1u << 10) +#define PIO_PA11 (1u << 11) +#define PIO_PA12 (1u << 12) +#define PIO_PA13 (1u << 13) +#define PIO_PA14 (1u << 14) +#define PIO_PA15 (1u << 15) +#define PIO_PA16 (1u << 16) +#define PIO_PA17 (1u << 17) +#define PIO_PA18 (1u << 18) +#define PIO_PA19 (1u << 19) +#define PIO_PA20 (1u << 20) +#define PIO_PA21 (1u << 21) +#define PIO_PA22 (1u << 22) +#define PIO_PA23 (1u << 23) +#define PIO_PA24 (1u << 24) +#define PIO_PA25 (1u << 25) +#define PIO_PA26 (1u << 26) +#define PIO_PA27 (1u << 27) +#define PIO_PA28 (1u << 28) +#define PIO_PA29 (1u << 29) +#define PIO_PA30 (1u << 30) +#define PIO_PA31 (1u << 31) +#define PIO_PB0 (1u << 0) +#define PIO_PB1 (1u << 1) +#define PIO_PB2 (1u << 2) +#define PIO_PB3 (1u << 3) +#define PIO_PB4 (1u << 4) +#define PIO_PB5 (1u << 5) +#define PIO_PB6 (1u << 6) +#define PIO_PB7 (1u << 7) +#define PIO_PB8 (1u << 8) +#define PIO_PB9 (1u << 9) +#define PIO_PB10 (1u << 10) +#define PIO_PB11 (1u << 11) +#define PIO_PB12 (1u << 12) +#define PIO_PB13 (1u << 13) +#define PIO_PB14 (1u << 14) +#define PIO_PB15 (1u << 15) +#define PIO_PB16 (1u << 16) +#define PIO_PB17 (1u << 17) +#define PIO_PB18 (1u << 18) +#define PIO_PB19 (1u << 19) +#define PIO_PB20 (1u << 20) +#define PIO_PB21 (1u << 21) +#define PIO_PB22 (1u << 22) +#define PIO_PB23 (1u << 23) +#define PIO_PB24 (1u << 24) + +#define PIO_PB5X1_AD0 (1u << 5) +#define PIO_PB6X1_AD1 (1u << 6) +#define PIO_PB7X1_AD2 (1u << 7) +#define PIO_PB8X1_AD3 (1u << 8) +#define PIO_PC28X1_AD4 (1u << 28) +#define PIO_PC29X1_AD5 (1u << 29) +#define PIO_PC30X1_AD6 (1u << 30) +#define PIO_PC31X1_AD7 (1u << 31) +#define PIO_PA17B_ADTRG (1u << 17) + +#define PIO_PA22X1_AD12B0 (1u << 22) +#define PIO_PA30X1_AD12B1 (1u << 30) +#define PIO_PB3X1_AD12B2 (1u << 3) +#define PIO_PB4X1_AD12B3 (1u << 4) +#define PIO_PC15X1_AD12B4 (1u << 15) +#define PIO_PC16X1_AD12B5 (1u << 16) +#define PIO_PC17X1_AD12B6 (1u << 17) +#define PIO_PC18X1_AD12B7 (1u << 18) +#define PIO_PA2B_AD12BTRG (1u << 2) + +#define PIO_PB7B_A0 (1u << 7) +#define PIO_PB7B_NBS0 (1u << 7) +#define PIO_PB8B_A1 (1u << 8) +#define PIO_PC8A_A10 (1u << 8) +#define PIO_PC9A_A11 (1u << 9) +#define PIO_PC10A_A12 (1u << 10) +#define PIO_PC11A_A13 (1u << 11) +#define PIO_PC20A_A14 (1u << 20) +#define PIO_PC21A_A15 (1u << 21) +#define PIO_PC22A_A16 (1u << 22) +#define PIO_PC23A_A17 (1u << 23) +#define PIO_PC24A_A18 (1u << 24) +#define PIO_PC25A_A19 (1u << 25) +#define PIO_PB0B_A2 (1u << 0) +#define PIO_PC0A_A2 (1u << 0) +#define PIO_PC13A_A2 (1u << 13) +#define PIO_PC26A_A20 (1u << 26) +#define PIO_PB21A_A21 (1u << 21) +#define PIO_PB21A_NANDALE (1u << 21) +#define PIO_PB22A_A22 (1u << 22) +#define PIO_PB22A_NANDCLE (1u << 22) +#define PIO_PC27A_A23 (1u << 27) +#define PIO_PB1B_A3 (1u << 1) +#define PIO_PC1A_A3 (1u << 1) +#define PIO_PC14A_A3 (1u << 14) +#define PIO_PB2B_A4 (1u << 2) +#define PIO_PC2A_A4 (1u << 2) +#define PIO_PB3B_A5 (1u << 3) +#define PIO_PC3A_A5 (1u << 3) +#define PIO_PB4B_A6 (1u << 4) +#define PIO_PC4A_A6 (1u << 4) +#define PIO_PB5B_A7 (1u << 5) +#define PIO_PC5A_A7 (1u << 5) +#define PIO_PC6A_A8 (1u << 6) +#define PIO_PC7A_A9 (1u << 7) +#define PIO_PB9A_D0 (1u << 9) +#define PIO_PB10A_D1 (1u << 10) +#define PIO_PB27A_D10 (1u << 27) +#define PIO_PB28A_D11 (1u << 28) +#define PIO_PB29A_D12 (1u << 29) +#define PIO_PB30A_D13 (1u << 30) +#define PIO_PB31A_D14 (1u << 31) +#define PIO_PB6B_D15 (1u << 6) +#define PIO_PB11A_D2 (1u << 11) +#define PIO_PB12A_D3 (1u << 12) +#define PIO_PB13A_D4 (1u << 13) +#define PIO_PB14A_D5 (1u << 14) +#define PIO_PB15A_D6 (1u << 15) +#define PIO_PB16A_D7 (1u << 16) +#define PIO_PB25A_D8 (1u << 25) +#define PIO_PB26A_D9 (1u << 26) +#define PIO_PB17A_NANDOE (1u << 17) +#define PIO_PB24A_NANDRDY (1u << 24) +#define PIO_PB18A_NANDWE (1u << 18) +#define PIO_PB20A_NCS0 (1u << 20) +#define PIO_PA16B_NCS1 (1u << 16) +#define PIO_PC12A_NCS1 (1u << 12) +#define PIO_PC16A_NCS2 (1u << 16) +#define PIO_PC17A_NCS3 (1u << 17) +#define PIO_PB19A_NRD (1u << 19) +#define PIO_PC18A_NWAIT (1u << 18) +#define PIO_PB23A_NWR0 (1u << 23) +#define PIO_PB23A_NWE (1u << 23) +#define PIO_PC15A_NWR1 (1u << 15) +#define PIO_PC15A_NBS1 (1u << 15) + +#define PIO_PA4A_MCCDA (1u << 4) +#define PIO_PA3A_MCCK (1u << 3) +#define PIO_PA5A_MCDA0 (1u << 5) +#define PIO_PA6A_MCDA1 (1u << 6) +#define PIO_PA7A_MCDA2 (1u << 7) +#define PIO_PA8A_MCDA3 (1u << 8) +#define PIO_PC28B_MCDA4 (1u << 28) +#define PIO_PC29B_MCDA5 (1u << 29) +#define PIO_PC30B_MCDA6 (1u << 30) +#define PIO_PC31B_MCDA7 (1u << 31) + +#define PIO_PA21B_PCK0 (1u << 21) +#define PIO_PA27B_PCK0 (1u << 27) +#define PIO_PA3B_PCK1 (1u << 3) +#define PIO_PB24B_PCK1 (1u << 24) +#define PIO_PB23B_PCK2 (1u << 23) + +#define PIO_PA11B_PWMFI0 (1u << 11) +#define PIO_PA12B_PWMFI1 (1u << 12) +#define PIO_PA18B_PWMFI2 (1u << 18) +#define PIO_PA4B_PWMH0 (1u << 4) +#define PIO_PA28B_PWMH0 (1u << 28) +#define PIO_PB0A_PWMH0 (1u << 0) +#define PIO_PB13B_PWMH0 (1u << 13) +#define PIO_PC24B_PWMH0 (1u << 24) +#define PIO_PA5B_PWMH1 (1u << 5) +#define PIO_PA29B_PWMH1 (1u << 29) +#define PIO_PB1A_PWMH1 (1u << 1) +#define PIO_PB14B_PWMH1 (1u << 14) +#define PIO_PC25B_PWMH1 (1u << 25) +#define PIO_PA6B_PWMH2 (1u << 6) +#define PIO_PA15B_PWMH2 (1u << 15) +#define PIO_PB2A_PWMH2 (1u << 2) +#define PIO_PB15B_PWMH2 (1u << 15) +#define PIO_PC26B_PWMH2 (1u << 26) +#define PIO_PA20B_PWMH3 (1u << 20) +#define PIO_PB3A_PWMH3 (1u << 3) +#define PIO_PB16B_PWMH3 (1u << 16) +#define PIO_PC27B_PWMH3 (1u << 27) +#define PIO_PA7B_PWML0 (1u << 7) +#define PIO_PB17B_PWML0 (1u << 17) +#define PIO_PB25B_PWML0 (1u << 25) +#define PIO_PC6B_PWML0 (1u << 6) +#define PIO_PC29A_PWML0 (1u << 29) +#define PIO_PA8B_PWML1 (1u << 8) +#define PIO_PB18B_PWML1 (1u << 18) +#define PIO_PB26B_PWML1 (1u << 26) +#define PIO_PC7B_PWML1 (1u << 7) +#define PIO_PC30A_PWML1 (1u << 30) +#define PIO_PA9B_PWML2 (1u << 9) +#define PIO_PB19B_PWML2 (1u << 19) +#define PIO_PB27B_PWML2 (1u << 27) +#define PIO_PC8B_PWML2 (1u << 8) +#define PIO_PC31A_PWML2 (1u << 31) +#define PIO_PA10B_PWML3 (1u << 10) +#define PIO_PB20B_PWML3 (1u << 20) +#define PIO_PB28B_PWML3 (1u << 28) +#define PIO_PC9B_PWML3 (1u << 9) +#define PIO_PC16B_PWML3 (1u << 16) + +#define PIO_PA13A_MISO (1u << 13) +#define PIO_PA14A_MOSI (1u << 14) +#define PIO_PA16A_NPCS0 (1u << 16) +#define PIO_PA0B_NPCS1 (1u << 0) +#define PIO_PC3B_NPCS1 (1u << 3) +#define PIO_PC19B_NPCS1 (1u << 19) +#define PIO_PA1B_NPCS2 (1u << 1) +#define PIO_PC4B_NPCS2 (1u << 4) +#define PIO_PC14B_NPCS2 (1u << 14) +#define PIO_PA19B_NPCS3 (1u << 19) +#define PIO_PC5B_NPCS3 (1u << 5) +#define PIO_PA15A_SPCK (1u << 15) + +#define PIO_PA27A_RD (1u << 27) +#define PIO_PA31A_RF (1u << 31) +#define PIO_PA29A_RK (1u << 29) +#define PIO_PA26A_TD (1u << 26) +#define PIO_PA30A_TF (1u << 30) +#define PIO_PA28A_TK (1u << 28) + +#define PIO_PA2A_TCLK0 (1u << 2) +#define PIO_PB4A_TCLK1 (1u << 4) +#define PIO_PA26B_TCLK2 (1u << 26) +#define PIO_PA1A_TIOA0 (1u << 1) +#define PIO_PB5A_TIOA1 (1u << 5) +#define PIO_PA30B_TIOA2 (1u << 30) +#define PIO_PA0A_TIOB0 (1u << 0) +#define PIO_PB6A_TIOB1 (1u << 6) +#define PIO_PA31B_TIOB2 (1u << 31) + +#define PIO_PA10A_TWCK0 (1u << 10) +#define PIO_PA9A_TWD0 (1u << 9) + +#define PIO_PA25A_TWCK1 (1u << 25) +#define PIO_PA24A_TWD1 (1u << 24) + +#define PIO_PA11A_URXD (1u << 11) +#define PIO_PA12A_UTXD (1u << 12) + +#define PIO_PB8A_CTS0 (1u << 8) +#define PIO_PB11B_DCD0 (1u << 11) +#define PIO_PB10B_DSR0 (1u << 10) +#define PIO_PB9B_DTR0 (1u << 9) +#define PIO_PB12B_RI0 (1u << 12) +#define PIO_PB7A_RTS0 (1u << 7) +#define PIO_PA19A_RXD0 (1u << 19) +#define PIO_PA17A_SCK0 (1u << 17) +#define PIO_PA18A_TXD0 (1u << 18) + +#define PIO_PA23B_CTS1 (1u << 23) +#define PIO_PA22B_RTS1 (1u << 22) +#define PIO_PA21A_RXD1 (1u << 21) +#define PIO_PA24B_SCK1 (1u << 24) +#define PIO_PA20A_TXD1 (1u << 20) + +#define PIO_PB22B_CTS2 (1u << 22) +#define PIO_PB21B_RTS2 (1u << 21) +#define PIO_PA23A_RXD2 (1u << 23) +#define PIO_PA25B_SCK2 (1u << 25) +#define PIO_PA22A_TXD2 (1u << 22) + +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +# 436 "naeusb/sam3u_hal/inc/sam3u2c.h" 2 + + + + + + +#define IFLASH0_SIZE (0x20000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (8192u) +#define IFLASH0_NB_OF_PAGES (512u) +#define IRAM0_SIZE (0x4000u) +#define IRAM1_SIZE (0x4000u) +#define NFCRAM_SIZE (0x1000u) +#define IFLASH_SIZE (IFLASH0_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) +#define IROM_ADDR (0x00180000u) +#define IRAM0_ADDR (0x20000000u) +#define IRAM1_ADDR (0x20080000u) +#define NFC_RAM_ADDR (0x20100000u) +#define UDPHS_RAM_ADDR (0x20180000u) + + + + + + +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (96000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + + +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + + +#define CHIP_FREQ_FWS_0 (24000000UL) +#define CHIP_FREQ_FWS_1 (40000000UL) +#define CHIP_FREQ_FWS_2 (72000000UL) +#define CHIP_FREQ_FWS_3 (84000000UL) +# 51 "naeusb/sam3u_hal/inc/sam3u.h" 2 +# 63 "naeusb/sam3u_hal/inc/io.h" 2 +# 65 "naeusb/sam3u_hal/inc/compiler.h" 2 + + + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 1 3 +# 27 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +#define _STDIO_H_ + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_ansi.h" 1 3 + + + + + + + +#define _ANSIDECL_H_ + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\newlib.h" 1 3 + + + + + + + +#define __NEWLIB_H__ 1 +# 18 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\newlib.h" 3 +#define _WANT_IO_C99_FORMATS 1 + + +#define _WANT_IO_LONG_LONG 1 + + +#define _WANT_REGISTER_FINI 1 +# 37 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\newlib.h" 3 +#define _REENT_CHECK_VERIFY 1 + + + + + +#define _MB_LEN_MAX 1 +# 53 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\newlib.h" 3 +#define HAVE_INITFINI_ARRAY 1 + + + +#define _ATEXIT_DYNAMIC_ALLOC 1 + + +#define _HAVE_LONG_DOUBLE 1 + + +#define _HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1 + + +#define _LDBL_EQ_DBL 1 + + +#define _FVWRITE_IN_STREAMIO 1 + + +#define _FSEEK_OPTIMIZATION 1 + + +#define _WIDE_ORIENT 1 + + +#define _UNBUF_STREAM_OPT 1 +# 95 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\newlib.h" 3 +#define _RETARGETABLE_LOCKING 1 +# 11 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_ansi.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\config.h" 1 3 + +#define __SYS_CONFIG_H__ + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\ieeefp.h" 1 3 +# 77 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\ieeefp.h" 3 +#define __IEEE_LITTLE_ENDIAN +# 496 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\ieeefp.h" 3 +#define __OBSOLETE_MATH_DEFAULT 1 + + +#define __OBSOLETE_MATH __OBSOLETE_MATH_DEFAULT +# 5 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\config.h" 2 3 +# 224 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\config.h" 3 +#define _POINTER_INT long + + + + + +#undef __RAND_MAX + + + +#define __RAND_MAX 0x7fffffff +# 250 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\config.h" 3 +#define __EXPORT + + + +#define __IMPORT + + + + + + +#define _READ_WRITE_RETURN_TYPE int + + + + + +#define _READ_WRITE_BUFSIZE_TYPE int +# 12 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_ansi.h" 2 3 +# 31 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_ansi.h" 3 +#define _BEGIN_STD_C +#define _END_STD_C +#define _NOTHROW + + + +#define _LONG_DOUBLE long double + + + + + +#define _ATTRIBUTE(attrs) __attribute__ (attrs) +# 69 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_ansi.h" 3 +#define _ELIDABLE_INLINE static __inline__ + + + +#define _NOINLINE __attribute__ ((__noinline__)) +#define _NOINLINE_STATIC _NOINLINE static +# 30 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 + +#define _FSTDIO + +#define __need_size_t +#define __need_NULL +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 1 3 +# 43 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define _SYS_CDEFS_H_ + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 1 3 4 +# 155 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_ptrdiff_t +# 231 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_size_t +# 340 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_wchar_t +# 390 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef NULL + + + + +#define NULL ((void *)0) + + + + + +#undef __need_NULL + + + + +#define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) +# 48 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 2 3 + +#define __PMT(args) args +#define __DOTS , ... +#define __THROW + + +#define __ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cname + + +#define __ptr_t void * +#define __long_double_t long double + +#define __attribute_malloc__ +#define __attribute_pure__ +#define __attribute_format_strfmon__(a,b) +#define __flexarr [0] + + +#define __bounded +#define __unbounded +#define __ptrvalue +# 78 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __has_extension __has_feature + + +#define __has_feature(x) 0 +# 94 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __BEGIN_DECLS +#define __END_DECLS +# 107 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS + + + +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + + +#define __GNUCLIKE_CTOR_SECTION_HANDLING 1 + + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 + + + + + + +#define __GNUCLIKE_BUILTIN_VARARGS 1 +#define __GNUCLIKE_BUILTIN_STDARG 1 +#define __GNUCLIKE_BUILTIN_VAALIST 1 + + + +#define __GNUC_VA_LIST_COMPATIBILITY 1 + + + + + + +#define __compiler_membar() __asm __volatile(" " : : : "memory") + + + +#define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +#define __GNUCLIKE_MATH_BUILTIN_RELOPS + + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + + +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 +# 177 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __P(protos) protos +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x +#define __XSTRING(x) __STRING(x) + +#define __const const +#define __signed signed +#define __volatile volatile +# 230 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __weak_symbol __attribute__((__weak__)) +# 243 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) + + +#define __alloc_size(x) __attribute__((__alloc_size__(x))) +#define __alloc_size2(n,x) __attribute__((__alloc_size__(n, x))) + + + + + +#define __alloc_align(x) __attribute__((__alloc_align__(x))) +# 280 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define _Alignas(x) __aligned(x) + + + + + + +#define _Alignof(x) __alignof(x) +# 302 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define _Noreturn __dead2 +# 331 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define _Thread_local __thread +# 351 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no) +# 366 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __min_size(x) static (x) + + + + + +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) + + + + + + +#define __always_inline __inline__ __attribute__((__always_inline__)) + + + + + +#define __noinline __attribute__ ((__noinline__)) + + + + + +#define __nonnull(x) __attribute__((__nonnull__ x)) +#define __nonnull_all __attribute__((__nonnull__)) + + + + + + +#define __fastcall __attribute__((__fastcall__)) +#define __result_use_check __attribute__((__warn_unused_result__)) + + + + + + +#define __returns_twice __attribute__((__returns_twice__)) + + + + + +#define __unreachable() __builtin_unreachable() +# 434 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __restrict restrict +# 467 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) + + + + + + +#define __null_sentinel __attribute__((__sentinel__)) +#define __exported __attribute__((__visibility__("default"))) + + +#define __hidden __attribute__((__visibility__("hidden"))) +# 489 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __offsetof(type,field) offsetof(type, field) +#define __rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start)) +# 500 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));}) +# 522 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg))) + +#define __scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) + +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) + +#define __strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +# 539 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __printf0like(fmtarg,firstvararg) + + + + +#define __strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) + + + + +#define __weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym) + + +#define __warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous") + + + +#define __sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid) + +#define __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid) +# 593 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __FBSDID(s) struct __hack + + + +#define __RCSID(s) struct __hack + + + +#define __RCSID_SOURCE(s) struct __hack + + + +#define __SCCSID(s) struct __hack + + + +#define __COPYRIGHT(s) struct __hack + + + +#define __DECONST(type,var) ((type)(__uintptr_t)(const void *)(var)) + + + +#define __DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var)) + + + +#define __DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var)) + + + + + + +#define _Nonnull +#define _Nullable +#define _Null_unspecified +#define __NULLABILITY_PRAGMA_PUSH +#define __NULLABILITY_PRAGMA_POP +# 653 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __arg_type_tag(arg_kind,arg_idx,type_tag_idx) +#define __datatype_type_tag(kind,type) +# 672 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __lock_annotate(x) + + + + + +#define __lockable __lock_annotate(lockable) + + +#define __locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__)) + +#define __locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__)) + + + +#define __trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__)) + +#define __trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__)) + + + +#define __unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__)) + + +#define __asserts_exclusive(...) __lock_annotate(assert_exclusive_lock(__VA_ARGS__)) + +#define __asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__)) + + + +#define __requires_exclusive(...) __lock_annotate(exclusive_locks_required(__VA_ARGS__)) + +#define __requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__)) + +#define __requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__)) + + + +#define __no_lock_analysis __lock_annotate(no_thread_safety_analysis) +# 721 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\cdefs.h" 3 +#define __nosanitizeaddress +#define __nosanitizethread + + + +#define __guarded_by(x) __lock_annotate(guarded_by(x)) +#define __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x)) +# 36 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 1 3 4 +# 37 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 + + +#define __need___va_list +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdarg.h" 1 3 4 +# 34 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdarg.h" 3 4 +#undef __need___va_list + + + + +#define __GNUC_VA_LIST + +# 40 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdarg.h" 3 4 +typedef __builtin_va_list __gnuc_va_list; +# 41 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 + + + + + +typedef __gnuc_va_list va_list; +#define _VA_LIST_DEFINED +# 60 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 1 3 +# 11 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +#define _SYS_REENT_H_ + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\_ansi.h" 1 3 +# 14 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 1 3 4 +# 15 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 1 3 +# 20 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 3 +#define _SYS__TYPES_H + +#define __need_size_t +#define __need_wint_t +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 1 3 4 +# 155 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_ptrdiff_t +# 231 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_size_t +# 340 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_wchar_t + + + + +#define _WINT_T + + + + +typedef unsigned int wint_t; + +#undef __need_wint_t +# 390 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef NULL + + + + +#define NULL ((void *)0) + + + + + +#undef __need_NULL + + + + +#define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) +# 25 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 2 3 + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_types.h" 1 3 + + + + + +#define _MACHINE__TYPES_H +# 28 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 2 3 + + +typedef long __blkcnt_t; + + + +typedef long __blksize_t; + + + +typedef __uint64_t __fsblkcnt_t; + + + +typedef __uint32_t __fsfilcnt_t; + + + +typedef long _off_t; + + + + + +typedef int __pid_t; + + + +typedef short __dev_t; + + + +typedef unsigned short __uid_t; + + +typedef unsigned short __gid_t; + + + +typedef __uint32_t __id_t; + + + + + + + +typedef unsigned short __ino_t; +# 90 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 3 +typedef __uint32_t __mode_t; + + + + + +__extension__ typedef long long _off64_t; + + + + + +typedef _off_t __off_t; + + +typedef _off64_t __loff_t; + + +typedef long __key_t; + + + + + + + +typedef long _fpos_t; +# 127 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 3 +#undef __size_t + + + +typedef unsigned int __size_t; +# 146 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 3 +#define unsigned signed +typedef signed int _ssize_t; +#undef unsigned +# 158 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_types.h" 3 +typedef _ssize_t __ssize_t; + + + +typedef struct +{ + int __count; + union + { + wint_t __wch; + unsigned char __wchb[4]; + } __value; +} _mbstate_t; + + + + +typedef void *_iconv_t; + + + +#define _CLOCK_T_ unsigned long + + +typedef unsigned long __clock_t; + + + + +#define _TIME_T_ __int_least64_t + +typedef __int_least64_t __time_t; + + +#define _CLOCKID_T_ unsigned long + + +typedef unsigned long __clockid_t; + +#define _TIMER_T_ unsigned long +typedef unsigned long __timer_t; + + +typedef __uint8_t __sa_family_t; + + + +typedef __uint32_t __socklen_t; + + +typedef int __nl_item; +typedef unsigned short __nlink_t; +typedef long __suseconds_t; +typedef unsigned long __useconds_t; + + + + + + + +typedef __builtin_va_list __va_list; +# 16 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 2 3 + +#define _NULL 0 + + + +#define __Long long +typedef unsigned long __ULong; +# 34 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\lock.h" 1 3 + +#define __SYS_LOCK_H__ +# 33 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\lock.h" 3 +struct __lock; +typedef struct __lock * _LOCK_T; +#define _LOCK_RECURSIVE_T _LOCK_T + +#define __LOCK_INIT(class,lock) extern struct __lock __lock_ ## lock; class _LOCK_T lock = &__lock_ ## lock + +#define __LOCK_INIT_RECURSIVE(class,lock) __LOCK_INIT(class,lock) + +extern void __retarget_lock_init(_LOCK_T *lock); +#define __lock_init(lock) __retarget_lock_init(&lock) +extern void __retarget_lock_init_recursive(_LOCK_T *lock); +#define __lock_init_recursive(lock) __retarget_lock_init_recursive(&lock) +extern void __retarget_lock_close(_LOCK_T lock); +#define __lock_close(lock) __retarget_lock_close(lock) +extern void __retarget_lock_close_recursive(_LOCK_T lock); +#define __lock_close_recursive(lock) __retarget_lock_close_recursive(lock) +extern void __retarget_lock_acquire(_LOCK_T lock); +#define __lock_acquire(lock) __retarget_lock_acquire(lock) +extern void __retarget_lock_acquire_recursive(_LOCK_T lock); +#define __lock_acquire_recursive(lock) __retarget_lock_acquire_recursive(lock) +extern int __retarget_lock_try_acquire(_LOCK_T lock); +#define __lock_try_acquire(lock) __retarget_lock_try_acquire(lock) +extern int __retarget_lock_try_acquire_recursive(_LOCK_T lock); +#define __lock_try_acquire_recursive(lock) __retarget_lock_try_acquire_recursive(lock) + +extern void __retarget_lock_release(_LOCK_T lock); +#define __lock_release(lock) __retarget_lock_release(lock) +extern void __retarget_lock_release_recursive(_LOCK_T lock); +#define __lock_release_recursive(lock) __retarget_lock_release_recursive(lock) +# 35 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 2 3 +typedef _LOCK_T _flock_t; + + + + + + + +struct _reent; + +struct __locale_t; + + + + + + +struct _Bigint +{ + struct _Bigint *_next; + int _k, _maxwds, _sign, _wds; + __ULong _x[1]; +}; + + +struct __tm +{ + int __tm_sec; + int __tm_min; + int __tm_hour; + int __tm_mday; + int __tm_mon; + int __tm_year; + int __tm_wday; + int __tm_yday; + int __tm_isdst; +}; + + + + + +#define _ATEXIT_SIZE 32 + +struct _on_exit_args { + void * _fnargs[32]; + void * _dso_handle[32]; + + __ULong _fntypes; + + + __ULong _is_cxa; +}; +# 98 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +struct _atexit { + struct _atexit *_next; + int _ind; + + void (*_fns[32])(void); + struct _on_exit_args _on_exit_args; +}; +#define _ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}} + + + + + +#define _REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT, +# 122 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +struct __sbuf { + unsigned char *_base; + int _size; +}; +# 183 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +#define _REENT_SMALL_CHECK_INIT(ptr) + + +struct __sFILE { + unsigned char *_p; + int _r; + int _w; + short _flags; + short _file; + struct __sbuf _bf; + int _lbfsize; + + + + + + + void * _cookie; + + int (*_read) (struct _reent *, void *, + char *, int); + int (*_write) (struct _reent *, void *, + const char *, + int); + _fpos_t (*_seek) (struct _reent *, void *, _fpos_t, int); + int (*_close) (struct _reent *, void *); + + + struct __sbuf _ub; + unsigned char *_up; + int _ur; + + + unsigned char _ubuf[3]; + unsigned char _nbuf[1]; + + + struct __sbuf _lb; + + + int _blksize; + _off_t _offset; + + + struct _reent *_data; + + + + _flock_t _lock; + + _mbstate_t _mbstate; + int _flags2; +}; +# 292 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +typedef struct __sFILE __FILE; + + + +struct _glue +{ + struct _glue *_next; + int _niobs; + __FILE *_iobs; +}; +# 317 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +#define _RAND48_SEED_0 (0x330e) +#define _RAND48_SEED_1 (0xabcd) +#define _RAND48_SEED_2 (0x1234) +#define _RAND48_MULT_0 (0xe66d) +#define _RAND48_MULT_1 (0xdeec) +#define _RAND48_MULT_2 (0x0005) +#define _RAND48_ADD (0x000b) +struct _rand48 { + unsigned short _seed[3]; + unsigned short _mult[3]; + unsigned short _add; + + + + +}; + + +#define _REENT_EMERGENCY_SIZE 25 +#define _REENT_ASCTIME_SIZE 26 +#define _REENT_SIGNAL_SIZE 24 +# 613 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +struct _reent +{ + int _errno; + + + + + __FILE *_stdin, *_stdout, *_stderr; + + int _inc; + char _emergency[25]; + + + int _unspecified_locale_info; + struct __locale_t *_locale; + + int __sdidinit; + + void (*__cleanup) (struct _reent *); + + + struct _Bigint *_result; + int _result_k; + struct _Bigint *_p5s; + struct _Bigint **_freelist; + + + int _cvtlen; + char *_cvtbuf; + + union + { + struct + { + unsigned int _unused_rand; + char * _strtok_last; + char _asctime_buf[26]; + struct __tm _localtime_buf; + int _gamma_signgam; + __extension__ unsigned long long _rand_next; + struct _rand48 _r48; + _mbstate_t _mblen_state; + _mbstate_t _mbtowc_state; + _mbstate_t _wctomb_state; + char _l64a_buf[8]; + char _signal_buf[24]; + int _getdate_err; + _mbstate_t _mbrlen_state; + _mbstate_t _mbrtowc_state; + _mbstate_t _mbsrtowcs_state; + _mbstate_t _wcrtomb_state; + _mbstate_t _wcsrtombs_state; + int _h_errno; + } _reent; + + + + struct + { +#define _N_LISTS 30 + unsigned char * _nextf[30]; + unsigned int _nmalloc[30]; + } _unused; + } _new; + + + + struct _atexit *_atexit; + struct _atexit _atexit0; + + + + void (**(_sig_func))(int); + + + + + struct _glue __sglue; + + __FILE __sf[3]; + +}; + + + + + +#define _REENT_STDIO_STREAM(var,index) &(var)->__sf[index] + + +#define _REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} } +# 751 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +#define _REENT_INIT_PTR_ZEROED(var) { (var)->_stdin = _REENT_STDIO_STREAM(var, 0); (var)->_stdout = _REENT_STDIO_STREAM(var, 1); (var)->_stderr = _REENT_STDIO_STREAM(var, 2); (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; } +# 765 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +#define _REENT_CHECK_RAND48(ptr) +#define _REENT_CHECK_MP(ptr) +#define _REENT_CHECK_TM(ptr) +#define _REENT_CHECK_ASCTIME_BUF(ptr) +#define _REENT_CHECK_EMERGENCY(ptr) +#define _REENT_CHECK_MISC(ptr) +#define _REENT_CHECK_SIGNAL_BUF(ptr) + +#define _REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam) +#define _REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next) +#define _REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed) +#define _REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult) +#define _REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add) +#define _REENT_MP_RESULT(ptr) ((ptr)->_result) +#define _REENT_MP_RESULT_K(ptr) ((ptr)->_result_k) +#define _REENT_MP_P5S(ptr) ((ptr)->_p5s) +#define _REENT_MP_FREELIST(ptr) ((ptr)->_freelist) +#define _REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf) +#define _REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf) +#define _REENT_EMERGENCY(ptr) ((ptr)->_emergency) +#define _REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last) +#define _REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state) +#define _REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state) +#define _REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state) +#define _REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state) +#define _REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state) +#define _REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state) +#define _REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state) +#define _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state) +#define _REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf) +#define _REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf) +#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err)) + + + +#define _REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); } + + + + + + + +#define _Kmax (sizeof (size_t) << 3) + + + + + + + +#define __ATTRIBUTE_IMPURE_PTR__ + + +extern struct _reent *_impure_ptr ; +extern struct _reent *const _global_impure_ptr ; + +void _reclaim_reent (struct _reent *); +# 832 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\reent.h" 3 +#define _REENT _impure_ptr + + +#define _GLOBAL_REENT _global_impure_ptr + + + + + +#define _GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit) +# 61 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 1 3 +# 28 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 3 +typedef __uint8_t u_int8_t; + + +typedef __uint16_t u_int16_t; + + +typedef __uint32_t u_int32_t; + + +typedef __uint64_t u_int64_t; + +typedef __intptr_t register_t; +#define __BIT_TYPES_DEFINED__ 1 + + + +#define _SYS_TYPES_H + + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\endian.h" 1 3 + +#define __MACHINE_ENDIAN_H__ + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_endian.h" 1 3 +# 31 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\_endian.h" 3 +#define _LITTLE_ENDIAN 1234 +#define _BIG_ENDIAN 4321 +#define _PDP_ENDIAN 3412 + + + + +#define _BYTE_ORDER _LITTLE_ENDIAN +# 7 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\endian.h" 2 3 + + +#define _QUAD_HIGHWORD 1 +#define _QUAD_LOWWORD 0 + + + + + + +#define LITTLE_ENDIAN _LITTLE_ENDIAN +#define BIG_ENDIAN _BIG_ENDIAN +#define PDP_ENDIAN _PDP_ENDIAN +#define BYTE_ORDER _BYTE_ORDER + + + +#define __bswap16(_x) __builtin_bswap16(_x) +#define __bswap32(_x) __builtin_bswap32(_x) +#define __bswap64(_x) __builtin_bswap64(_x) +# 57 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\endian.h" 3 +#define __htonl(_x) __bswap32(_x) +#define __htons(_x) __bswap16(_x) +#define __ntohl(_x) __bswap32(_x) +#define __ntohs(_x) __bswap16(_x) +# 50 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\select.h" 1 3 + +#define _SYS_SELECT_H +# 14 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\select.h" 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_sigset.h" 1 3 +# 39 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_sigset.h" 3 +#define _SYS__SIGSET_H_ + +typedef unsigned long __sigset_t; +# 15 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\select.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_timeval.h" 1 3 +# 32 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_timeval.h" 3 +#define _SYS__TIMEVAL_H_ + + + + +typedef __suseconds_t suseconds_t; +#define _SUSECONDS_T_DECLARED + + + +typedef __int_least64_t time_t; +#define __time_t_defined +#define _TIME_T_DECLARED + + + + +#define _TIMEVAL_DEFINED + + + + +struct timeval { + time_t tv_sec; + suseconds_t tv_usec; +}; +# 16 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\select.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\timespec.h" 1 3 +# 35 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\timespec.h" 3 +#define _SYS_TIMESPEC_H_ + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_timespec.h" 1 3 +# 37 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_timespec.h" 3 +#define _SYS__TIMESPEC_H_ +# 47 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_timespec.h" 3 +struct timespec { + time_t tv_sec; + long tv_nsec; +}; +# 39 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\timespec.h" 2 3 + + +#define TIMEVAL_TO_TIMESPEC(tv,ts) do { (ts)->tv_sec = (tv)->tv_sec; (ts)->tv_nsec = (tv)->tv_usec * 1000; } while (0) + + + + +#define TIMESPEC_TO_TIMEVAL(tv,ts) do { (tv)->tv_sec = (ts)->tv_sec; (tv)->tv_usec = (ts)->tv_nsec / 1000; } while (0) +# 58 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\timespec.h" 3 +struct itimerspec { + struct timespec it_interval; + struct timespec it_value; +}; +# 17 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\select.h" 2 3 + + +#define _SIGSET_T_DECLARED +typedef __sigset_t sigset_t; + + +#define _SYS_TYPES_FD_SET + + + + + + + +#define FD_SETSIZE 64 + + +typedef unsigned long __fd_mask; + +typedef __fd_mask fd_mask; + + +#define _NFDBITS ((int)sizeof(__fd_mask) * 8) + +#define NFDBITS _NFDBITS + + + +#define _howmany(x,y) (((x) + ((y) - 1)) / (y)) + + +typedef struct fd_set { + __fd_mask __fds_bits[(((64) + ((((int)sizeof(__fd_mask) * 8)) - 1)) / (((int)sizeof(__fd_mask) * 8)))]; +} fd_set; + +#define fds_bits __fds_bits + + +#define __fdset_mask(n) ((__fd_mask)1 << ((n) % _NFDBITS)) +#define FD_CLR(n,p) ((p)->__fds_bits[(n)/_NFDBITS] &= ~__fdset_mask(n)) + +#define FD_COPY(f,t) (void)(*(t) = *(f)) + +#define FD_ISSET(n,p) (((p)->__fds_bits[(n)/_NFDBITS] & __fdset_mask(n)) != 0) +#define FD_SET(n,p) ((p)->__fds_bits[(n)/_NFDBITS] |= __fdset_mask(n)) +#define FD_ZERO(p) do { fd_set *_p; __size_t _n; _p = (p); _n = _howmany(FD_SETSIZE, _NFDBITS); while (_n > 0) _p->__fds_bits[--_n] = 0; } while (0) +# 74 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\select.h" 3 + + +int select (int __n, fd_set *__readfds, fd_set *__writefds, fd_set *__exceptfds, struct timeval *__timeout) + ; + +int pselect (int __n, fd_set *__readfds, fd_set *__writefds, fd_set *__exceptfds, const struct timespec *__timeout, const sigset_t *__set) + + ; + + + +# 51 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 2 3 +#define physadr physadr_t +#define quad quad_t + + +typedef __uint32_t in_addr_t; +#define _IN_ADDR_T_DECLARED + + + +typedef __uint16_t in_port_t; +#define _IN_PORT_T_DECLARED + + +typedef __uintptr_t u_register_t; + + + + + + +typedef unsigned char u_char; +#define __u_char_defined + + +typedef unsigned short u_short; +#define __u_short_defined + + +typedef unsigned int u_int; +#define __u_int_defined + + +typedef unsigned long u_long; +#define __u_long_defined + +#define _BSDTYPES_DEFINED + + + + +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; + + + +typedef __blkcnt_t blkcnt_t; +#define _BLKCNT_T_DECLARED + + + +typedef __blksize_t blksize_t; +#define _BLKSIZE_T_DECLARED + + + +typedef unsigned long clock_t; +#define __clock_t_defined +#define _CLOCK_T_DECLARED +# 119 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 3 +typedef long daddr_t; +#define __daddr_t_defined + + +typedef char * caddr_t; +#define __caddr_t_defined + + + +typedef __fsblkcnt_t fsblkcnt_t; +typedef __fsfilcnt_t fsfilcnt_t; +#define _FSBLKCNT_T_DECLARED + + + +typedef __id_t id_t; +#define _ID_T_DECLARED + + + +typedef __ino_t ino_t; +#define _INO_T_DECLARED +# 157 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 3 +typedef __off_t off_t; +#define _OFF_T_DECLARED + + +typedef __dev_t dev_t; +#define _DEV_T_DECLARED + + +typedef __uid_t uid_t; +#define _UID_T_DECLARED + + +typedef __gid_t gid_t; +#define _GID_T_DECLARED + + + +typedef __pid_t pid_t; +#define _PID_T_DECLARED + + + +typedef __key_t key_t; +#define _KEY_T_DECLARED + + + +typedef _ssize_t ssize_t; +#define _SSIZE_T_DECLARED + + + +typedef __mode_t mode_t; +#define _MODE_T_DECLARED + + + +typedef __nlink_t nlink_t; +#define _NLINK_T_DECLARED + + + +typedef __clockid_t clockid_t; +#define __clockid_t_defined +#define _CLOCKID_T_DECLARED + + + +typedef __timer_t timer_t; +#define __timer_t_defined +#define _TIMER_T_DECLARED + + + +typedef __useconds_t useconds_t; +#define _USECONDS_T_DECLARED + + + + + + + +typedef __int64_t sbintime_t; + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 1 3 +# 19 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 3 +#define _SYS__PTHREADTYPES_H_ + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\sched.h" 1 3 +# 22 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\sched.h" 3 +#define _SYS_SCHED_H_ +# 35 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\sched.h" 3 +#define SCHED_OTHER 0 + + +#define SCHED_FIFO 1 +#define SCHED_RR 2 +# 48 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\sched.h" 3 +struct sched_param { + int sched_priority; +# 61 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\sched.h" 3 +}; +# 24 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 2 3 +# 32 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 3 +typedef __uint32_t pthread_t; + + + +#define PTHREAD_SCOPE_PROCESS 0 +#define PTHREAD_SCOPE_SYSTEM 1 + + +#define PTHREAD_INHERIT_SCHED 1 + + +#define PTHREAD_EXPLICIT_SCHED 2 + + +#define PTHREAD_CREATE_DETACHED 0 +#define PTHREAD_CREATE_JOINABLE 1 +# 61 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 3 +typedef struct { + int is_initialized; + void *stackaddr; + int stacksize; + int contentionscope; + int inheritsched; + int schedpolicy; + struct sched_param schedparam; + + + + + + int detachstate; +} pthread_attr_t; +# 154 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 3 +typedef __uint32_t pthread_mutex_t; + +typedef struct { + int is_initialized; +# 168 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\_pthreadtypes.h" 3 + int recursive; +} pthread_mutexattr_t; + + +#define _PTHREAD_MUTEX_INITIALIZER ((pthread_mutex_t) 0xFFFFFFFF) + + + +typedef __uint32_t pthread_cond_t; + +#define _PTHREAD_COND_INITIALIZER ((pthread_cond_t) 0xFFFFFFFF) + +typedef struct { + int is_initialized; + clock_t clock; + + + +} pthread_condattr_t; + + + +typedef __uint32_t pthread_key_t; + +typedef struct { + int is_initialized; + int init_executed; +} pthread_once_t; + +#define _PTHREAD_ONCE_INIT { 1, 0 } +# 224 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 2 3 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\types.h" 1 3 +# 225 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\types.h" 2 3 + + + +#undef __need_inttypes +# 62 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 + + + + +typedef __FILE FILE; +#define __FILE_defined + + + + + +typedef _fpos_t fpos_t; + + + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\stdio.h" 1 3 + +#define _NEWLIB_STDIO_H +# 13 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\sys\\stdio.h" 3 +#define _flockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_acquire_recursive((fp)->_lock)) + + + + + + + +#define _funlockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_release_recursive((fp)->_lock)) +# 80 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 2 3 + +#define __SLBF 0x0001 +#define __SNBF 0x0002 +#define __SRD 0x0004 +#define __SWR 0x0008 + +#define __SRW 0x0010 +#define __SEOF 0x0020 +#define __SERR 0x0040 +#define __SMBF 0x0080 +#define __SAPP 0x0100 +#define __SSTR 0x0200 +#define __SOPT 0x0400 +#define __SNPT 0x0800 +#define __SOFF 0x1000 +#define __SORD 0x2000 + + + +#define __SL64 0x8000 + + +#define __SNLK 0x0001 +#define __SWID 0x2000 +# 114 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +#define _IOFBF 0 +#define _IOLBF 1 +#define _IONBF 2 + +#define EOF (-1) + + + + +#define BUFSIZ 1024 + + + + + +#define FOPEN_MAX 20 + + + + + +#define FILENAME_MAX 1024 + + + + + +#define L_tmpnam FILENAME_MAX + + + +#define P_tmpdir "/tmp" + + + +#define SEEK_SET 0 + + +#define SEEK_CUR 1 + + +#define SEEK_END 2 + + +#define TMP_MAX 26 + +#define stdin (_REENT->_stdin) +#define stdout (_REENT->_stdout) +#define stderr (_REENT->_stderr) + +#define _stdin_r(x) ((x)->_stdin) +#define _stdout_r(x) ((x)->_stdout) +#define _stderr_r(x) ((x)->_stderr) + + + + + + + +#define __VALIST __gnuc_va_list + + + + + + +char * ctermid (char *); + + + + +FILE * tmpfile (void); +char * tmpnam (char *); + +char * tempnam (const char *, const char *) __attribute__((__malloc__)) __attribute__((__warn_unused_result__)); + +int fclose (FILE *); +int fflush (FILE *); +FILE * freopen (const char *restrict, const char *restrict, FILE *restrict); +void setbuf (FILE *restrict, char *restrict); +int setvbuf (FILE *restrict, char *restrict, int, size_t); +int fprintf (FILE *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +int fscanf (FILE *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__scanf__, 2, 3))); +int +# 200 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" + iprintf +# 200 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 + (const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 1, 2))); +int +# 202 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" + iscanf +# 202 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 + (const char *restrict, ...) + __attribute__ ((__format__ (__scanf__, 1, 2))); +int sscanf (const char *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__scanf__, 2, 3))); +int vfprintf (FILE *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int vprintf (const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 1, 0))); +int vsprintf (char *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int fgetc (FILE *); +char * fgets (char *restrict, int, FILE *restrict); +int fputc (int, FILE *); +int fputs (const char *restrict, FILE *restrict); +int getc (FILE *); +int getchar (void); +char * gets (char *); +int putc (int, FILE *); +int putchar (int); +int puts (const char *); +int ungetc (int, FILE *); +size_t fread (void *restrict, size_t _size, size_t _n, FILE *restrict); +size_t fwrite (const void *restrict , size_t _size, size_t _n, FILE *); + + + +int fgetpos (FILE *restrict, fpos_t *restrict); + +int fseek (FILE *, long, int); + + + +int fsetpos (FILE *, const fpos_t *); + +long ftell ( FILE *); +void rewind (FILE *); +void clearerr (FILE *); +int feof (FILE *); +int ferror (FILE *); +void perror (const char *); + +FILE * fopen (const char *restrict _name, const char *restrict _type); +int sprintf (char *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +int remove (const char *); +int rename (const char *, const char *); +# 257 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +int fseeko (FILE *, off_t, int); +off_t ftello (FILE *); + + + + + + + +int snprintf (char *restrict, size_t, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int vsnprintf (char *restrict, size_t, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int vfscanf (FILE *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 2, 0))); +int vscanf (const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 1, 0))); +int vsscanf (const char *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 2, 0))); +# 284 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +int asiprintf (char **, const char *, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +char * asniprintf (char *, size_t *, const char *, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +char * asnprintf (char *restrict, size_t *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); + +int diprintf (int, const char *, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); + +int fiprintf (FILE *, const char *, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +int fiscanf (FILE *, const char *, ...) + __attribute__ ((__format__ (__scanf__, 2, 3))); +int iprintf (const char *, ...) + __attribute__ ((__format__ (__printf__, 1, 2))); +int iscanf (const char *, ...) + __attribute__ ((__format__ (__scanf__, 1, 2))); +int siprintf (char *, const char *, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +int siscanf (const char *, const char *, ...) + __attribute__ ((__format__ (__scanf__, 2, 3))); +int sniprintf (char *, size_t, const char *, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int vasiprintf (char **, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +char * vasniprintf (char *, size_t *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +char * vasnprintf (char *, size_t *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int vdiprintf (int, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int vfiprintf (FILE *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int vfiscanf (FILE *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 2, 0))); +int viprintf (const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 1, 0))); +int viscanf (const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 1, 0))); +int vsiprintf (char *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int vsiscanf (const char *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 2, 0))); +int vsniprintf (char *, size_t, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +# 339 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +FILE * fdopen (int, const char *); + +int fileno (FILE *); + + +int pclose (FILE *); +FILE * popen (const char *, const char *); + + + +void setbuffer (FILE *, char *, int); +int setlinebuf (FILE *); + + + +int getw (FILE *); +int putw (int, FILE *); + + +int getc_unlocked (FILE *); +int getchar_unlocked (void); +void flockfile (FILE *); +int ftrylockfile (FILE *); +void funlockfile (FILE *); +int putc_unlocked (int, FILE *); +int putchar_unlocked (int); +# 374 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +int dprintf (int, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); + +FILE * fmemopen (void *restrict, size_t, const char *restrict); + + +FILE * open_memstream (char **, size_t *); +int vdprintf (int, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); + + + +int renameat (int, const char *, int, const char *); +# 396 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +int _asiprintf_r (struct _reent *, char **, const char *, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +char * _asniprintf_r (struct _reent *, char *, size_t *, const char *, ...) + __attribute__ ((__format__ (__printf__, 4, 5))); +char * _asnprintf_r (struct _reent *, char *restrict, size_t *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 4, 5))); +int _asprintf_r (struct _reent *, char **restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _diprintf_r (struct _reent *, int, const char *, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _dprintf_r (struct _reent *, int, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _fclose_r (struct _reent *, FILE *); +int _fcloseall_r (struct _reent *); +FILE * _fdopen_r (struct _reent *, int, const char *); +int _fflush_r (struct _reent *, FILE *); +int _fgetc_r (struct _reent *, FILE *); +int _fgetc_unlocked_r (struct _reent *, FILE *); +char * _fgets_r (struct _reent *, char *restrict, int, FILE *restrict); +char * _fgets_unlocked_r (struct _reent *, char *restrict, int, FILE *restrict); + + + + +int _fgetpos_r (struct _reent *, FILE *, fpos_t *); +int _fsetpos_r (struct _reent *, FILE *, const fpos_t *); + +int _fiprintf_r (struct _reent *, FILE *, const char *, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _fiscanf_r (struct _reent *, FILE *, const char *, ...) + __attribute__ ((__format__ (__scanf__, 3, 4))); +FILE * _fmemopen_r (struct _reent *, void *restrict, size_t, const char *restrict); +FILE * _fopen_r (struct _reent *, const char *restrict, const char *restrict); +FILE * _freopen_r (struct _reent *, const char *restrict, const char *restrict, FILE *restrict); +int _fprintf_r (struct _reent *, FILE *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _fpurge_r (struct _reent *, FILE *); +int _fputc_r (struct _reent *, int, FILE *); +int _fputc_unlocked_r (struct _reent *, int, FILE *); +int _fputs_r (struct _reent *, const char *restrict, FILE *restrict); +int _fputs_unlocked_r (struct _reent *, const char *restrict, FILE *restrict); +size_t _fread_r (struct _reent *, void *restrict, size_t _size, size_t _n, FILE *restrict); +size_t _fread_unlocked_r (struct _reent *, void *restrict, size_t _size, size_t _n, FILE *restrict); +int _fscanf_r (struct _reent *, FILE *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__scanf__, 3, 4))); +int _fseek_r (struct _reent *, FILE *, long, int); +int _fseeko_r (struct _reent *, FILE *, _off_t, int); +long _ftell_r (struct _reent *, FILE *); +_off_t _ftello_r (struct _reent *, FILE *); +void _rewind_r (struct _reent *, FILE *); +size_t _fwrite_r (struct _reent *, const void *restrict, size_t _size, size_t _n, FILE *restrict); +size_t _fwrite_unlocked_r (struct _reent *, const void *restrict, size_t _size, size_t _n, FILE *restrict); +int _getc_r (struct _reent *, FILE *); +int _getc_unlocked_r (struct _reent *, FILE *); +int _getchar_r (struct _reent *); +int _getchar_unlocked_r (struct _reent *); +char * _gets_r (struct _reent *, char *); +int _iprintf_r (struct _reent *, const char *, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +int _iscanf_r (struct _reent *, const char *, ...) + __attribute__ ((__format__ (__scanf__, 2, 3))); +FILE * _open_memstream_r (struct _reent *, char **, size_t *); +void _perror_r (struct _reent *, const char *); +int _printf_r (struct _reent *, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 2, 3))); +int _putc_r (struct _reent *, int, FILE *); +int _putc_unlocked_r (struct _reent *, int, FILE *); +int _putchar_unlocked_r (struct _reent *, int); +int _putchar_r (struct _reent *, int); +int _puts_r (struct _reent *, const char *); +int _remove_r (struct _reent *, const char *); +int _rename_r (struct _reent *, + const char *_old, const char *_new); +int _scanf_r (struct _reent *, const char *restrict, ...) + __attribute__ ((__format__ (__scanf__, 2, 3))); +int _siprintf_r (struct _reent *, char *, const char *, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _siscanf_r (struct _reent *, const char *, const char *, ...) + __attribute__ ((__format__ (__scanf__, 3, 4))); +int _sniprintf_r (struct _reent *, char *, size_t, const char *, ...) + __attribute__ ((__format__ (__printf__, 4, 5))); +int _snprintf_r (struct _reent *, char *restrict, size_t, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 4, 5))); +int _sprintf_r (struct _reent *, char *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__printf__, 3, 4))); +int _sscanf_r (struct _reent *, const char *restrict, const char *restrict, ...) + __attribute__ ((__format__ (__scanf__, 3, 4))); +char * _tempnam_r (struct _reent *, const char *, const char *); +FILE * _tmpfile_r (struct _reent *); +char * _tmpnam_r (struct _reent *, char *); +int _ungetc_r (struct _reent *, int, FILE *); +int _vasiprintf_r (struct _reent *, char **, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +char * _vasniprintf_r (struct _reent*, char *, size_t *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 4, 0))); +char * _vasnprintf_r (struct _reent*, char *, size_t *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 4, 0))); +int _vasprintf_r (struct _reent *, char **, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vdiprintf_r (struct _reent *, int, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vdprintf_r (struct _reent *, int, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vfiprintf_r (struct _reent *, FILE *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vfiscanf_r (struct _reent *, FILE *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 3, 0))); +int _vfprintf_r (struct _reent *, FILE *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vfscanf_r (struct _reent *, FILE *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 3, 0))); +int _viprintf_r (struct _reent *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int _viscanf_r (struct _reent *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 2, 0))); +int _vprintf_r (struct _reent *, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 2, 0))); +int _vscanf_r (struct _reent *, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 2, 0))); +int _vsiprintf_r (struct _reent *, char *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vsiscanf_r (struct _reent *, const char *, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 3, 0))); +int _vsniprintf_r (struct _reent *, char *, size_t, const char *, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 4, 0))); +int _vsnprintf_r (struct _reent *, char *restrict, size_t, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 4, 0))); +int _vsprintf_r (struct _reent *, char *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__printf__, 3, 0))); +int _vsscanf_r (struct _reent *, const char *restrict, const char *restrict, __gnuc_va_list) + __attribute__ ((__format__ (__scanf__, 3, 0))); + + + +int fpurge (FILE *); +ssize_t __getdelim (char **, size_t *, int, FILE *); +ssize_t __getline (char **, size_t *, FILE *); + + +void clearerr_unlocked (FILE *); +int feof_unlocked (FILE *); +int ferror_unlocked (FILE *); +int fileno_unlocked (FILE *); +int fflush_unlocked (FILE *); +int fgetc_unlocked (FILE *); +int fputc_unlocked (int, FILE *); +size_t fread_unlocked (void *restrict, size_t _size, size_t _n, FILE *restrict); +size_t fwrite_unlocked (const void *restrict , size_t _size, size_t _n, FILE *); +# 577 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +int __srget_r (struct _reent *, FILE *); +int __swbuf_r (struct _reent *, int, FILE *); +# 601 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +FILE *funopen (const void *__cookie, + int (*__readfn)(void *__cookie, char *__buf, + int __n), + int (*__writefn)(void *__cookie, const char *__buf, + int __n), + fpos_t (*__seekfn)(void *__cookie, fpos_t __off, int __whence), + int (*__closefn)(void *__cookie)); +FILE *_funopen_r (struct _reent *, const void *__cookie, + int (*__readfn)(void *__cookie, char *__buf, + int __n), + int (*__writefn)(void *__cookie, const char *__buf, + int __n), + fpos_t (*__seekfn)(void *__cookie, fpos_t __off, int __whence), + int (*__closefn)(void *__cookie)); + + +#define fropen(__cookie,__fn) funopen(__cookie, __fn, (int (*)())0, (fpos_t (*)())0, (int (*)())0) + +#define fwopen(__cookie,__fn) funopen(__cookie, (int (*)())0, __fn, (fpos_t (*)())0, (int (*)())0) +# 654 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +#define __sgetc_raw_r(__ptr,__f) (--(__f)->_r < 0 ? __srget_r(__ptr, __f) : (int)(*(__f)->_p++)) +# 683 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +#define __sgetc_r(__ptr,__p) __sgetc_raw_r(__ptr, __p) + + + +static __inline__ int __sputc_r(struct _reent *_ptr, int _c, FILE *_p) { + + + + + if (--_p->_w >= 0 || (_p->_w >= _p->_lbfsize && (char)_c != '\n')) + return (*_p->_p++ = _c); + else + return (__swbuf_r(_ptr, _c, _p)); +} +# 719 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +#define __sfeof(p) ((int)(((p)->_flags & __SEOF) != 0)) +#define __sferror(p) ((int)(((p)->_flags & __SERR) != 0)) +#define __sclearerr(p) ((void)((p)->_flags &= ~(__SERR|__SEOF))) +#define __sfileno(p) ((p)->_file) + + + +#define feof(p) __sfeof(p) +#define ferror(p) __sferror(p) +#define clearerr(p) __sclearerr(p) + + +#define feof_unlocked(p) __sfeof(p) +#define ferror_unlocked(p) __sferror(p) +#define clearerr_unlocked(p) __sclearerr(p) + + + + + + + +static __inline int +_getchar_unlocked(void) +{ + struct _reent *_ptr; + + _ptr = _impure_ptr; + return ((--(((_ptr)->_stdin))->_r < 0 ? __srget_r(_ptr, ((_ptr)->_stdin)) : (int)(*(((_ptr)->_stdin))->_p++))); +} + +static __inline int +_putchar_unlocked(int _c) +{ + struct _reent *_ptr; + + _ptr = _impure_ptr; + return (__sputc_r(_ptr, _c, ((_ptr)->_stdout))); +} +# 767 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 +#define getchar_unlocked() _getchar_unlocked() +#define putchar_unlocked(_c) _putchar_unlocked(_c) + + + + + +#define fast_putc(x,p) (--(p)->_w < 0 ? __swbuf_r(_REENT, (int)(x), p) == EOF : (*(p)->_p = (x), (p)->_p++, 0)) + + + + + + + +#define L_ctermid 16 +# 797 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdio.h" 3 + +# 71 "naeusb/sam3u_hal/inc/compiler.h" 2 +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdbool.h" 1 3 4 +# 29 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdbool.h" 3 4 +#define _STDBOOL_H + + + +#define bool _Bool +#define true 1 +#define false 0 +# 52 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stdbool.h" 3 4 +#define __bool_true_false_are_defined 1 +# 72 "naeusb/sam3u_hal/inc/compiler.h" 2 + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 1 3 + + + + + + + +#define _STDLIB_H_ + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\ieeefp.h" 1 3 +# 11 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 2 3 + + +#define __need_size_t +#define __need_wchar_t +#define __need_NULL +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 1 3 4 +# 155 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_ptrdiff_t +# 231 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_size_t +# 340 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef __need_wchar_t +# 390 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\lib\\gcc\\arm-none-eabi\\10.3.1\\include\\stddef.h" 3 4 +#undef NULL + + + + +#define NULL ((void *)0) + + + + + +#undef __need_NULL + + + + +#define offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) +# 17 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 2 3 + + + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\machine\\stdlib.h" 1 3 + +#define _MACHSTDLIB_H_ +# 21 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 2 3 + +# 1 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\alloca.h" 1 3 + + + + + + + +#define _NEWLIB_ALLOCA_H + + + + +#undef alloca + + +#define alloca(size) __builtin_alloca(size) +# 23 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 2 3 +# 33 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 3 + + +typedef struct +{ + int quot; + int rem; +} div_t; + +typedef struct +{ + long quot; + long rem; +} ldiv_t; + + +typedef struct +{ + long long int quot; + long long int rem; +} lldiv_t; + + + +#define __compar_fn_t_defined +typedef int (*__compar_fn_t) (const void *, const void *); + + +#define EXIT_FAILURE 1 +#define EXIT_SUCCESS 0 + +#define RAND_MAX __RAND_MAX + +int __locale_mb_cur_max (void); + +#define MB_CUR_MAX __locale_mb_cur_max() + +void abort (void) __attribute__ ((__noreturn__)); +int abs (int); + +__uint32_t arc4random (void); +__uint32_t arc4random_uniform (__uint32_t); +void arc4random_buf (void *, size_t); + +int atexit (void (*__func)(void)); +double atof (const char *__nptr); + +float atoff (const char *__nptr); + +int atoi (const char *__nptr); +int _atoi_r (struct _reent *, const char *__nptr); +long atol (const char *__nptr); +long _atol_r (struct _reent *, const char *__nptr); +void * bsearch (const void *__key, + const void *__base, + size_t __nmemb, + size_t __size, + __compar_fn_t _compar); +void *calloc(size_t, size_t) __attribute__((__malloc__)) __attribute__((__warn_unused_result__)) + __attribute__((__alloc_size__(1, 2))) ; +div_t div (int __numer, int __denom); +void exit (int __status) __attribute__ ((__noreturn__)); +void free (void *) ; +char * getenv (const char *__string); +char * _getenv_r (struct _reent *, const char *__string); + + + +char * _findenv (const char *, int *); +char * _findenv_r (struct _reent *, const char *, int *); + +extern char *suboptarg; +int getsubopt (char **, char * const *, char **); + +long labs (long); +ldiv_t ldiv (long __numer, long __denom); +void *malloc(size_t) __attribute__((__malloc__)) __attribute__((__warn_unused_result__)) __attribute__((__alloc_size__(1))) ; +int mblen (const char *, size_t); +int _mblen_r (struct _reent *, const char *, size_t, _mbstate_t *); +int mbtowc (wchar_t *restrict, const char *restrict, size_t); +int _mbtowc_r (struct _reent *, wchar_t *restrict, const char *restrict, size_t, _mbstate_t *); +int wctomb (char *, wchar_t); +int _wctomb_r (struct _reent *, char *, wchar_t, _mbstate_t *); +size_t mbstowcs (wchar_t *restrict, const char *restrict, size_t); +size_t _mbstowcs_r (struct _reent *, wchar_t *restrict, const char *restrict, size_t, _mbstate_t *); +size_t wcstombs (char *restrict, const wchar_t *restrict, size_t); +size_t _wcstombs_r (struct _reent *, char *restrict, const wchar_t *restrict, size_t, _mbstate_t *); + + +char * mkdtemp (char *); + + + + + + +int mkstemp (char *); + + +int mkstemps (char *, int); + + +char * mktemp (char *) __attribute__ ((__deprecated__("the use of `mktemp' is dangerous; use `mkstemp' instead"))); + + +char * _mkdtemp_r (struct _reent *, char *); +int _mkostemp_r (struct _reent *, char *, int); +int _mkostemps_r (struct _reent *, char *, int, int); +int _mkstemp_r (struct _reent *, char *); +int _mkstemps_r (struct _reent *, char *, int); +char * _mktemp_r (struct _reent *, char *) __attribute__ ((__deprecated__("the use of `mktemp' is dangerous; use `mkstemp' instead"))); +void qsort (void *__base, size_t __nmemb, size_t __size, __compar_fn_t _compar); +int rand (void); +void *realloc(void *, size_t) __attribute__((__warn_unused_result__)) __attribute__((__alloc_size__(2))) ; + +void *reallocarray(void *, size_t, size_t) __attribute__((__warn_unused_result__)) __attribute__((__alloc_size__(2, 3))); +void *reallocf(void *, size_t) __attribute__((__warn_unused_result__)) __attribute__((__alloc_size__(2))); + + +char * realpath (const char *restrict path, char *restrict resolved_path); + + +int rpmatch (const char *response); + + + + +void srand (unsigned __seed); +double strtod (const char *restrict __n, char **restrict __end_PTR); +double _strtod_r (struct _reent *,const char *restrict __n, char **restrict __end_PTR); + +float strtof (const char *restrict __n, char **restrict __end_PTR); + + + + +#define strtodf strtof + + +long strtol (const char *restrict __n, char **restrict __end_PTR, int __base); +long _strtol_r (struct _reent *,const char *restrict __n, char **restrict __end_PTR, int __base); +unsigned long strtoul (const char *restrict __n, char **restrict __end_PTR, int __base); +unsigned long _strtoul_r (struct _reent *,const char *restrict __n, char **restrict __end_PTR, int __base); +# 191 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 3 +int system (const char *__string); + + +long a64l (const char *__input); +char * l64a (long __input); +char * _l64a_r (struct _reent *,long __input); + + +int on_exit (void (*__func)(int, void *),void *__arg); + + +void _Exit (int __status) __attribute__ ((__noreturn__)); + + +int putenv (char *__string); + +int _putenv_r (struct _reent *, char *__string); +void * _reallocf_r (struct _reent *, void *, size_t); + +int setenv (const char *__string, const char *__value, int __overwrite); + +int _setenv_r (struct _reent *, const char *__string, const char *__value, int __overwrite); +# 224 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 3 +char * __itoa (int, char *, int); +char * __utoa (unsigned, char *, int); + +char * itoa (int, char *, int); +char * utoa (unsigned, char *, int); + + +int rand_r (unsigned *__seed); + + + +double drand48 (void); +double _drand48_r (struct _reent *); +double erand48 (unsigned short [3]); +double _erand48_r (struct _reent *, unsigned short [3]); +long jrand48 (unsigned short [3]); +long _jrand48_r (struct _reent *, unsigned short [3]); +void lcong48 (unsigned short [7]); +void _lcong48_r (struct _reent *, unsigned short [7]); +long lrand48 (void); +long _lrand48_r (struct _reent *); +long mrand48 (void); +long _mrand48_r (struct _reent *); +long nrand48 (unsigned short [3]); +long _nrand48_r (struct _reent *, unsigned short [3]); +unsigned short * + seed48 (unsigned short [3]); +unsigned short * + _seed48_r (struct _reent *, unsigned short [3]); +void srand48 (long); +void _srand48_r (struct _reent *, long); + + +char * initstate (unsigned, char *, size_t); +long random (void); +char * setstate (char *); +void srandom (unsigned); + + +long long atoll (const char *__nptr); + +long long _atoll_r (struct _reent *, const char *__nptr); + +long long llabs (long long); +lldiv_t lldiv (long long __numer, long long __denom); +long long strtoll (const char *restrict __n, char **restrict __end_PTR, int __base); + +long long _strtoll_r (struct _reent *, const char *restrict __n, char **restrict __end_PTR, int __base); + +unsigned long long strtoull (const char *restrict __n, char **restrict __end_PTR, int __base); + +unsigned long long _strtoull_r (struct _reent *, const char *restrict __n, char **restrict __end_PTR, int __base); + + + +void cfree (void *); + + +int unsetenv (const char *__string); + +int _unsetenv_r (struct _reent *, const char *__string); + + + +int posix_memalign (void **, size_t, size_t) __attribute__((__nonnull__ (1))) + __attribute__((__warn_unused_result__)); + + +char * _dtoa_r (struct _reent *, double, int, int, int *, int*, char**); + +void * _malloc_r (struct _reent *, size_t) ; +void * _calloc_r (struct _reent *, size_t, size_t) ; +void _free_r (struct _reent *, void *) ; +void * _realloc_r (struct _reent *, void *, size_t) ; +void _mstats_r (struct _reent *, char *); + +int _system_r (struct _reent *, const char *); + +void __eprintf (const char *, const char *, unsigned int, const char *); +# 312 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 3 +void qsort_r (void *__base, size_t __nmemb, size_t __size, void *__thunk, int (*_compar)(void *, const void *, const void *)) + __asm__ ("" "__bsd_qsort_r"); +# 322 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 3 +extern long double _strtold_r (struct _reent *, const char *restrict, char **restrict); + +extern long double strtold (const char *restrict, char **restrict); +# 339 "c:\\program files (x86)\\gnu arm embedded toolchain\\10 2021.10\\arm-none-eabi\\include\\stdlib.h" 3 + +# 74 "naeusb/sam3u_hal/inc/compiler.h" 2 +# 88 "naeusb/sam3u_hal/inc/compiler.h" +#define FUNC_PTR void * + + + + +#define UNUSED(v) (void)(v) + + + + + +#define unused(v) do { (void)(v); } while(0) + + + + + +#define barrier() __DMB() + + + + + + + +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + + + + + + +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + + + + + + +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + + + + + + +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +# 143 "naeusb/sam3u_hal/inc/compiler.h" +#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +# 156 "naeusb/sam3u_hal/inc/compiler.h" +#undef __always_inline + + + +#define __always_inline inline __attribute__((__always_inline__)) +# 175 "naeusb/sam3u_hal/inc/compiler.h" +#define __no_inline __attribute__((__noinline__)) +# 201 "naeusb/sam3u_hal/inc/compiler.h" +#define Assert(expr) ((void) 0) +# 210 "naeusb/sam3u_hal/inc/compiler.h" +#define WEAK __attribute__ ((weak)) +# 219 "naeusb/sam3u_hal/inc/compiler.h" +#define NO_INIT __attribute__((section(".no_init"))) +# 228 "naeusb/sam3u_hal/inc/compiler.h" +#define RAMFUNC __attribute__ ((section(".ramfunc"))) +# 237 "naeusb/sam3u_hal/inc/compiler.h" +#define OPTIMIZE_HIGH __attribute__((optimize("s"))) + + +# 1 "naeusb/sam3u_hal/inc/interrupt.h" 1 +# 44 "naeusb/sam3u_hal/inc/interrupt.h" +#define UTILS_INTERRUPT_H +# 53 "naeusb/sam3u_hal/inc/interrupt.h" +# 1 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" 1 +# 45 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" +#define UTILS_INTERRUPT_INTERRUPT_H +# 84 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" +#define ISR(func) void func (void) +# 96 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" +#define irq_initialize_vectors() do { } while(0) +# 117 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" +#define irq_register_handler(int_num,int_prio) NVIC_ClearPendingIRQ( (IRQn_Type)int_num); NVIC_SetPriority( (IRQn_Type)int_num, int_prio); NVIC_EnableIRQ( (IRQn_Type)int_num); + + + + + + +#define cpu_irq_enable() do { g_interrupt_enabled = true; __DMB(); __enable_irq(); } while (0) + + + + + +#define cpu_irq_disable() do { __disable_irq(); __DMB(); g_interrupt_enabled = false; } while (0) + + + + + + + +# 137 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" +typedef uint32_t irqflags_t; + + +extern volatile +# 140 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" 3 4 + _Bool +# 140 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" + g_interrupt_enabled; + + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + +static volatile uint32_t cpu_irq_critical_section_counter; +static volatile +# 146 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" 3 4 + _Bool +# 146 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" + cpu_irq_prev_interrupt_state; + +static inline irqflags_t cpu_irq_save(void) +{ + irqflags_t flags = (__get_PRIMASK() == 0); + do { __disable_irq(); __DMB(); g_interrupt_enabled = +# 151 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" 3 4 +0 +# 151 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" +; } while (0); + return flags; +} + +static inline +# 155 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" 3 4 + _Bool +# 155 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" + cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return (flags); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + if (cpu_irq_is_enabled_flags(flags)) + do { g_interrupt_enabled = +# 163 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" 3 4 + 1 +# 163 "naeusb/sam3u_hal/inc/interrupt/interrupt_sam_nvic.h" + ; __DMB(); __enable_irq(); } while (0); +} + +void cpu_irq_enter_critical(void); +void cpu_irq_leave_critical(void); + + + + + + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() +# 54 "naeusb/sam3u_hal/inc/interrupt.h" 2 +# 241 "naeusb/sam3u_hal/inc/compiler.h" 2 + + + + +typedef unsigned char Bool; + + + + + +typedef int8_t S8 ; +typedef uint8_t U8 ; +typedef int16_t S16; +typedef uint16_t U16; +typedef uint16_t le16_t; +typedef uint16_t be16_t; +typedef int32_t S32; +typedef uint32_t U32; +typedef uint32_t le32_t; +typedef uint32_t be32_t; +typedef int64_t S64; +typedef uint64_t U64; +typedef float F32; +typedef double F64; +typedef uint32_t iram_size_t; + + + + + + +typedef +# 272 "naeusb/sam3u_hal/inc/compiler.h" 3 4 + _Bool +# 272 "naeusb/sam3u_hal/inc/compiler.h" + Status_bool_t; +typedef U8 Status_t; +# 282 "naeusb/sam3u_hal/inc/compiler.h" +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + + +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + + +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + + +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + + +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + + +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + + +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + + +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + + +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + + +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + + +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; +# 425 "naeusb/sam3u_hal/inc/compiler.h" +#define DISABLE 0 +#define ENABLE 1 + + + + + + +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +# 450 "naeusb/sam3u_hal/inc/compiler.h" +#define likely(exp) (exp) + + + + + + + +#define unlikely(exp) (exp) +# 470 "naeusb/sam3u_hal/inc/compiler.h" +#define is_constant(exp) __builtin_constant_p(exp) +# 488 "naeusb/sam3u_hal/inc/compiler.h" +#define Rd_bits(value,mask) ((value) & (mask)) +# 498 "naeusb/sam3u_hal/inc/compiler.h" +#define Wr_bits(lvalue,mask,bits) ((lvalue) = ((lvalue) & ~(mask)) | ((bits ) & (mask))) +# 508 "naeusb/sam3u_hal/inc/compiler.h" +#define Tst_bits(value,mask) (Rd_bits(value, mask) != 0) +# 517 "naeusb/sam3u_hal/inc/compiler.h" +#define Clr_bits(lvalue,mask) ((lvalue) &= ~(mask)) +# 526 "naeusb/sam3u_hal/inc/compiler.h" +#define Set_bits(lvalue,mask) ((lvalue) |= (mask)) +# 535 "naeusb/sam3u_hal/inc/compiler.h" +#define Tgl_bits(lvalue,mask) ((lvalue) ^= (mask)) +# 544 "naeusb/sam3u_hal/inc/compiler.h" +#define Rd_bitfield(value,mask) (Rd_bits( value, mask) >> ctz(mask)) +# 554 "naeusb/sam3u_hal/inc/compiler.h" +#define Wr_bitfield(lvalue,mask,bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) +# 580 "naeusb/sam3u_hal/inc/compiler.h" +#define clz(u) __builtin_clz(u) +# 626 "naeusb/sam3u_hal/inc/compiler.h" +#define ctz(u) __builtin_ctz(u) +# 676 "naeusb/sam3u_hal/inc/compiler.h" +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + + + + + + + +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + + + + + + + +#define bit_reverse32(u32) __RBIT(u32) + + + + + + + +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) | ((U64)bit_reverse32((U64)(u64)) << 32))) +# 717 "naeusb/sam3u_hal/inc/compiler.h" +#define Test_align(val,n) (!Tst_bits( val, (n) - 1 ) ) +# 726 "naeusb/sam3u_hal/inc/compiler.h" +#define Get_align(val,n) ( Rd_bits( val, (n) - 1 ) ) +# 736 "naeusb/sam3u_hal/inc/compiler.h" +#define Set_align(lval,n,alg) ( Wr_bits(lval, (n) - 1, alg) ) +# 745 "naeusb/sam3u_hal/inc/compiler.h" +#define Align_up(val,n) (((val) + ((n) - 1)) & ~((n) - 1)) +# 754 "naeusb/sam3u_hal/inc/compiler.h" +#define Align_down(val,n) ( (val) & ~((n) - 1)) +# 780 "naeusb/sam3u_hal/inc/compiler.h" +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) +# 791 "naeusb/sam3u_hal/inc/compiler.h" +#define Min(a,b) (((a) < (b)) ? (a) : (b)) +# 802 "naeusb/sam3u_hal/inc/compiler.h" +#define Max(a,b) (((a) > (b)) ? (a) : (b)) +# 815 "naeusb/sam3u_hal/inc/compiler.h" +#define min(a,b) Min(a, b) +# 826 "naeusb/sam3u_hal/inc/compiler.h" +#define max(a,b) Max(a, b) +# 842 "naeusb/sam3u_hal/inc/compiler.h" +#define Long_call(addr) ((*(void (*)(void))(addr))()) + + + + + + +#define MSB(u16) (((U8 *)&(u16))[1]) +#define LSB(u16) (((U8 *)&(u16))[0]) + +#define MSH(u32) (((U16 *)&(u32))[1]) +#define LSH(u32) (((U16 *)&(u32))[0]) +#define MSB0W(u32) (((U8 *)&(u32))[3]) +#define MSB1W(u32) (((U8 *)&(u32))[2]) +#define MSB2W(u32) (((U8 *)&(u32))[1]) +#define MSB3W(u32) (((U8 *)&(u32))[0]) +#define LSB3W(u32) MSB0W(u32) +#define LSB2W(u32) MSB1W(u32) +#define LSB1W(u32) MSB2W(u32) +#define LSB0W(u32) MSB3W(u32) + +#define MSW(u64) (((U32 *)&(u64))[1]) +#define LSW(u64) (((U32 *)&(u64))[0]) +#define MSH0(u64) (((U16 *)&(u64))[3]) +#define MSH1(u64) (((U16 *)&(u64))[2]) +#define MSH2(u64) (((U16 *)&(u64))[1]) +#define MSH3(u64) (((U16 *)&(u64))[0]) +#define LSH3(u64) MSH0(u64) +#define LSH2(u64) MSH1(u64) +#define LSH1(u64) MSH2(u64) +#define LSH0(u64) MSH3(u64) +#define MSB0D(u64) (((U8 *)&(u64))[7]) +#define MSB1D(u64) (((U8 *)&(u64))[6]) +#define MSB2D(u64) (((U8 *)&(u64))[5]) +#define MSB3D(u64) (((U8 *)&(u64))[4]) +#define MSB4D(u64) (((U8 *)&(u64))[3]) +#define MSB5D(u64) (((U8 *)&(u64))[2]) +#define MSB6D(u64) (((U8 *)&(u64))[1]) +#define MSB7D(u64) (((U8 *)&(u64))[0]) +#define LSB7D(u64) MSB0D(u64) +#define LSB6D(u64) MSB1D(u64) +#define LSB5D(u64) MSB2D(u64) +#define LSB4D(u64) MSB3D(u64) +#define LSB3D(u64) MSB4D(u64) +#define LSB2D(u64) MSB5D(u64) +#define LSB1D(u64) MSB6D(u64) +#define LSB0D(u64) MSB7D(u64) + +#define BE16(x) Swap16(x) +#define LE16(x) (x) + +#define le16_to_cpu(x) (x) +#define cpu_to_le16(x) (x) +#define LE16_TO_CPU(x) (x) +#define CPU_TO_LE16(x) (x) + +#define be16_to_cpu(x) Swap16(x) +#define cpu_to_be16(x) Swap16(x) +#define BE16_TO_CPU(x) Swap16(x) +#define CPU_TO_BE16(x) Swap16(x) + +#define le32_to_cpu(x) (x) +#define cpu_to_le32(x) (x) +#define LE32_TO_CPU(x) (x) +#define CPU_TO_LE32(x) (x) + +#define be32_to_cpu(x) swap32(x) +#define cpu_to_be32(x) swap32(x) +#define BE32_TO_CPU(x) swap32(x) +#define CPU_TO_BE32(x) swap32(x) +# 935 "naeusb/sam3u_hal/inc/compiler.h" +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) | ((U16)(u16) << 8))) +# 946 "naeusb/sam3u_hal/inc/compiler.h" +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) | ((U32)Swap16((U32)(u32)) << 16))) +# 957 "naeusb/sam3u_hal/inc/compiler.h" +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) | ((U64)Swap32((U64)(u64)) << 32))) +# 968 "naeusb/sam3u_hal/inc/compiler.h" +#define swap16(u16) Swap16(u16) +# 979 "naeusb/sam3u_hal/inc/compiler.h" +#define swap32(u32) ((U32)__builtin_bswap32((U32)(u32))) +# 993 "naeusb/sam3u_hal/inc/compiler.h" +#define swap64(u64) ((U64)__builtin_bswap64((U64)(u64))) +# 1006 "naeusb/sam3u_hal/inc/compiler.h" +#define _GLOBEXT_ extern +#define _CONST_TYPE_ const +#define _MEM_TYPE_SLOW_ +#define _MEM_TYPE_MEDFAST_ +#define _MEM_TYPE_FAST_ + +typedef U8 Byte; + +#define memcmp_ram2ram memcmp +#define memcmp_code2ram memcmp +#define memcpy_ram2ram memcpy +#define memcpy_code2ram memcpy + +#define LSB0(u32) LSB0W(u32) +#define LSB1(u32) LSB1W(u32) +#define LSB2(u32) LSB2W(u32) +#define LSB3(u32) LSB3W(u32) +#define MSB3(u32) MSB3W(u32) +#define MSB2(u32) MSB2W(u32) +#define MSB1(u32) MSB1W(u32) +#define MSB0(u32) MSB0W(u32) +# 1039 "naeusb/sam3u_hal/inc/compiler.h" +#define div_ceil(a,b) (((a) + (b) - 1) / (b)) + + + + + + + +#define SHORTENUM __attribute__((packed)) + + + + + + +#define nop() (__NOP()) + + +#define FLASH_DECLARE(x) const x +#define FLASH_EXTERN(x) extern const x +#define PGM_READ_BYTE(x) *(x) +#define PGM_READ_WORD(x) *(x) +#define MEMCPY_ENDIAN memcpy +#define PGM_READ_BLOCK(dst,src,len) memcpy((dst), (src), (len)) + + +#define CMD_ID_OCTET (0) + + +#define CPU_ENDIAN_TO_LE16(x) (x) +#define CPU_ENDIAN_TO_LE32(x) (x) +#define CPU_ENDIAN_TO_LE64(x) (x) + + +#define LE16_TO_CPU_ENDIAN(x) (x) +#define LE32_TO_CPU_ENDIAN(x) (x) +#define LE64_TO_CPU_ENDIAN(x) (x) + + +#define CLE16_TO_CPU_ENDIAN(x) (x) +#define CLE32_TO_CPU_ENDIAN(x) (x) +#define CLE64_TO_CPU_ENDIAN(x) (x) + + +#define CCPU_ENDIAN_TO_LE16(x) (x) +#define CCPU_ENDIAN_TO_LE32(x) (x) +#define CCPU_ENDIAN_TO_LE64(x) (x) + +#define ADDR_COPY_DST_SRC_16(dst,src) ((dst) = (src)) +#define ADDR_COPY_DST_SRC_64(dst,src) ((dst) = (src)) +# 1097 "naeusb/sam3u_hal/inc/compiler.h" +static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) +{ + uint8_t val_index = 0; + + while (val_index < 8) + { + data[val_index++] = value & 0xFF; + value = value >> 8; + } +} +# 1115 "naeusb/sam3u_hal/inc/compiler.h" +static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + + +static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + + +static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} +# 1143 "naeusb/sam3u_hal/inc/compiler.h" +static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) +{ + return (data[0] | ((uint16_t)data[1] << 8)); +} + + +static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) +{ + union + { + uint32_t u32; + uint8_t u8[8]; + }long_addr; + uint8_t index; + for (index = 0; index < 4; index++) + { + long_addr.u8[index] = *data++; + } + return long_addr.u32; +} +# 1172 "naeusb/sam3u_hal/inc/compiler.h" +static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) +{ + union + { + uint64_t u64; + uint8_t u8[8]; + } long_addr; + + uint8_t val_index; + + for (val_index = 0; val_index < 8; val_index++) + { + long_addr.u8[val_index] = *data++; + } + + return long_addr.u64; +} +# 41 "./config/conf_usb.h" 2 + + + +#define NAEUSB_MPSSE_SUPPORT 1 + + +#define UDI_MPSSE_EP_BULK_IN (0x01 | USB_EP_DIR_IN) +#define UDI_MPSSE_EP_BULK_OUT (0x02 | USB_EP_DIR_OUT) + +#define UDI_COMPOSITE_DESC_T udi_vendor_desc_t udi_vendor; union { struct { usb_iad_desc_t udi_iad; udi_cdc_comm_desc_t udi_cdc_comm; udi_cdc_data_desc_t udi_cdc_data; };struct { udi_vendor_desc_t udi_vendor_mpsse; };}; +# 70 "./config/conf_usb.h" +#define USB_DEVICE_VENDOR_ID 0x2B3E +#define USB_DEVICE_PRODUCT_ID 0xACE5 + +#define USB_DEVICE_MAJOR_VERSION 9 +#define USB_DEVICE_MINOR_VERSION 0 +#define USB_DEVICE_POWER 500 +#define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) + + + + + + +#define USB_DEVICE_HS_SUPPORT 1 +extern char usb_serial_number[33]; + +#define USB_DEVICE_MANUFACTURE_NAME "NewAE Technology Inc." +#define USB_DEVICE_PRODUCT_NAME "ChipWhisperer Husky" +#define USB_DEVICE_GET_SERIAL_NAME_POINTER usb_serial_number +#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 + +#define FW_VER_MAJOR 1 +#define FW_VER_MINOR 5 +#define FW_VER_DEBUG 0 +# 104 "./config/conf_usb.h" +void main_sof_action(void); +void main_resume_action(void); +void main_suspend_action(void); +#define UDC_VBUS_EVENT(b_vbus_high) +#define UDC_SOF_EVENT() main_sof_action() +#define UDC_SUSPEND_EVENT() main_suspend_action() +#define UDC_RESUME_EVENT() main_resume_action() +# 130 "./config/conf_usb.h" +#define USB_DEVICE_EP_CTRL_SIZE 64 + + +#define USB_DEVICE_NB_INTERFACE 3 + + + + + +#define USB_DEVICE_MAX_EP 6 +# 156 "./config/conf_usb.h" +#define UDI_CDC_PORT_NB 1 + + +# 158 "./config/conf_usb.h" 3 4 +_Bool +# 158 "./config/conf_usb.h" + cdc_enable(uint8_t port); +void cdc_disable(uint8_t port); + +#define UDI_CDC_ENABLE_EXT(port) cdc_enable(port) +#define UDI_CDC_DISABLE_EXT(port) cdc_disable(port) + + +#define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port) +extern void my_callback_rx_notify(uint8_t port); +#define UDI_CDC_TX_EMPTY_NOTIFY(port) +# 1 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" 1 +# 37 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" +#define _USB_PROTOCOL_CDC_H_ + +# 1 "naeusb/sam3u_hal/inc/compiler.h" 1 +# 40 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" 2 +# 51 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" +#define CDC_CLASS_DEVICE 0x02 +#define CDC_CLASS_COMM 0x02 +#define CDC_CLASS_DATA 0x0A + + + + +#define CDC_SUBCLASS_DLCM 0x01 +#define CDC_SUBCLASS_ACM 0x02 +#define CDC_SUBCLASS_TCM 0x03 +#define CDC_SUBCLASS_MCCM 0x04 +#define CDC_SUBCLASS_CCM 0x05 +#define CDC_SUBCLASS_ETH 0x06 +#define CDC_SUBCLASS_ATM 0x07 + + + + +#define CDC_PROTOCOL_V25TER 0x01 + + + + +#define CDC_PROTOCOL_I430 0x30 +#define CDC_PROTOCOL_HDLC 0x31 +#define CDC_PROTOCOL_TRANS 0x32 +#define CDC_PROTOCOL_Q921M 0x50 +#define CDC_PROTOCOL_Q921 0x51 +#define CDC_PROTOCOL_Q921TM 0x52 +#define CDC_PROTOCOL_V42BIS 0x90 +#define CDC_PROTOCOL_Q931 0x91 +#define CDC_PROTOCOL_V120 0x92 +#define CDC_PROTOCOL_CAPI20 0x93 +#define CDC_PROTOCOL_HOST 0xFD + + + + +#define CDC_PROTOCOL_PUFD 0xFE + + + + +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + + + + +#define CDC_SCS_HEADER 0x00 +#define CDC_SCS_CALL_MGMT 0x01 +#define CDC_SCS_ACM 0x02 +#define CDC_SCS_UNION 0x06 + + + + +#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 +#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 +#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 +#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 +#define USB_REQ_CDC_SET_HOOK_STATE 0x11 +#define USB_REQ_CDC_PULSE_SETUP 0x12 +#define USB_REQ_CDC_SEND_PULSE 0x13 +#define USB_REQ_CDC_SET_PULSE_TIME 0x14 +#define USB_REQ_CDC_RING_AUX_JACK 0x15 +#define USB_REQ_CDC_SET_LINE_CODING 0x20 +#define USB_REQ_CDC_GET_LINE_CODING 0x21 +#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 +#define USB_REQ_CDC_SEND_BREAK 0x23 +#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 +#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 +#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 +#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 +#define USB_REQ_CDC_SET_LINE_PARMS 0x34 +#define USB_REQ_CDC_GET_LINE_PARMS 0x35 +#define USB_REQ_CDC_DIAL_DIGITS 0x36 +#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 +#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 +#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 +#define USB_REQ_CDC_GET_PROFILE 0x3A +#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 +#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 +#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 +#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 +#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 +#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 + +#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 +#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 +#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 + + + + + + + +# 154 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" +#pragma pack(1) +# 154 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" + + + + + + + +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + le16_t bcdCDC; +} usb_cdc_hdr_desc_t; + + +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} usb_cdc_call_mgmt_desc_t; + + +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} usb_cdc_acm_desc_t; + + +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bMasterInterface; + uint8_t bSlaveInterface0; +} usb_cdc_union_desc_t; + + + + + +#define CDC_CALL_MGMT_SUPPORTED (1 << 0) + +#define CDC_CALL_MGMT_OVER_DCI (1 << 1) + + + + + + +#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) + + + +#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) + +#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) + +#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) +# 225 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" +typedef struct { + le32_t dwDTERate; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} usb_cdc_line_coding_t; + +enum cdc_char_format { + CDC_STOP_BITS_1 = 0, + CDC_STOP_BITS_1_5 = 1, + CDC_STOP_BITS_2 = 2, +}; + +enum cdc_parity { + CDC_PAR_NONE = 0, + CDC_PAR_ODD = 1, + CDC_PAR_EVEN = 2, + CDC_PAR_MARK = 3, + CDC_PAR_SPACE = 4, +}; + + + + + + + +typedef struct { + uint16_t value; +} usb_cdc_control_signal_t; + + + + + + + +#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) + + +#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) + + + + + + + +typedef struct { + uint8_t bmRequestType; + uint8_t bNotification; + le16_t wValue; + le16_t wIndex; + le16_t wLength; +} usb_cdc_notify_msg_t; + + + + + +typedef struct { + usb_cdc_notify_msg_t header; + le16_t value; +} usb_cdc_notify_serial_state_t; + + + +#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1<<0)) +#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1<<1)) +#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1<<2)) +#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1<<3)) +#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1<<4)) +#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1<<5)) +#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1<<6)) + + + + + + +# 304 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" +#pragma pack() +# 304 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" + +# 169 "./config/conf_usb.h" 2 +extern void my_callback_config(uint8_t port, usb_cdc_line_coding_t * cfg); +#define UDI_CDC_SET_CODING_EXT(port,cfg) my_callback_config(port,cfg) + + +#define UDI_CDC_SET_DTR_EXT(port,set) +#define UDI_CDC_SET_RTS_EXT(port,set) +# 194 "./config/conf_usb.h" +#define UDI_CDC_LOW_RATE + + +#define UDI_CDC_DEFAULT_RATE 115200 +#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 +#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE +#define UDI_CDC_DEFAULT_DATABITS 8 +# 209 "./config/conf_usb.h" +#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) +#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) +#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) + + +#define UDI_CDC_COMM_IFACE_NUMBER_0 1 +#define UDI_CDC_DATA_IFACE_NUMBER_0 2 + + + + + + + +# 222 "./config/conf_usb.h" 3 4 +_Bool +# 222 "./config/conf_usb.h" + main_vendor_enable(void); +void main_vendor_disable(void); + +# 224 "./config/conf_usb.h" 3 4 +_Bool +# 224 "./config/conf_usb.h" + main_setup_out_received(void); + +# 225 "./config/conf_usb.h" 3 4 +_Bool +# 225 "./config/conf_usb.h" + main_setup_in_received(void); +#define UDI_VENDOR_ENABLE_EXT() main_vendor_enable() +#define UDI_VENDOR_DISABLE_EXT() main_vendor_disable() +#define UDI_VENDOR_SETUP_OUT_RECEIVED() main_setup_out_received() +#define UDI_VENDOR_SETUP_IN_RECEIVED() main_setup_in_received() + + + +#define UDI_VENDOR_EPS_SIZE_INT_FS 0 +#define UDI_VENDOR_EPS_SIZE_BULK_FS 64 + + + +#define UDI_VENDOR_EPS_SIZE_ISO_FS 0 + + + +#define UDI_VENDOR_EPS_SIZE_INT_HS 0 +#define UDI_VENDOR_EPS_SIZE_BULK_HS 512 +#define UDI_VENDOR_EPS_SIZE_ISO_HS 0 + + +#define UDI_VENDOR_EP_BULK_IN (0x05 | USB_EP_DIR_IN) +#define UDI_VENDOR_EP_BULK_OUT (0x06 | USB_EP_DIR_OUT) + + + + + + +#define UDI_VENDOR_EP_NB_INT ((UDI_VENDOR_EPS_SIZE_INT_FS)?2:0) +#define UDI_VENDOR_EP_NB_BULK ((UDI_VENDOR_EPS_SIZE_BULK_FS)?2:0) +#define UDI_VENDOR_EP_NB_ISO ((UDI_VENDOR_EPS_SIZE_ISO_FS)?2:0) + + +#define UDI_VENDOR_IFACE_NUMBER 0 +# 272 "./config/conf_usb.h" +#define UDI_COMPOSITE_DESC_FS .udi_vendor = UDI_VENDOR_DESC_FS, .udi_iad = UDI_CDC_IAD_DESC_0, .udi_cdc_comm = UDI_CDC_COMM_DESC_0, .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, + + + + + +#define UDI_COMPOSITE_DESC_HS .udi_vendor = UDI_VENDOR_DESC_HS, .udi_iad = UDI_CDC_IAD_DESC_0, .udi_cdc_comm = UDI_CDC_COMM_DESC_0, .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, + + + + + + +#define UDI_COMPOSITE_API &udi_api_vendor, &udi_api_cdc_comm, &udi_api_cdc_data, +# 295 "./config/conf_usb.h" +# 1 "naeusb/sam3u_hal/inc/udi_vendor.h" 1 +# 45 "naeusb/sam3u_hal/inc/udi_vendor.h" +#define _UDI_VENDOR_H_ + +# 1 "./conf_usb.h" 1 +# 48 "naeusb/sam3u_hal/inc/udi_vendor.h" 2 +# 1 "naeusb/sam3u_hal/inc/usb_protocol.h" 1 +# 48 "naeusb/sam3u_hal/inc/usb_protocol.h" +#define _USB_PROTOCOL_H_ + +# 1 "naeusb/sam3u_hal/inc/usb_atmel.h" 1 +# 45 "naeusb/sam3u_hal/inc/usb_atmel.h" +#define _USB_ATMEL_H_ +# 67 "naeusb/sam3u_hal/inc/usb_atmel.h" +#define USB_VID_ATMEL 0x03EB + + + + + + + +#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 +#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 +#define USB_PID_ATMEL_MEGA_CDC 0x2018 +#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 +#define USB_PID_ATMEL_MEGA_MS 0x201A +#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B +#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C +#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D +#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 +#define USB_PID_ATMEL_MEGA_MS_2 0x2029 +#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A +#define USB_PID_ATMEL_MEGA_MS_3 0x2032 +#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 + + + + +#define USB_PID_ATMEL_XPLAINED 0x2122 +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B + + + + +#define USB_PID_ATMEL_UC3_ENUM 0x2300 +#define USB_PID_ATMEL_UC3_MS 0x2301 +#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 +#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 +#define USB_PID_ATMEL_UC3_HID 0x2304 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 +#define USB_PID_ATMEL_UC3_CDC 0x2307 +#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 +#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 +#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 +#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 + + + + +#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 +#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 +#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 +#define USB_PID_ATMEL_ASF_MSC 0x2403 +#define USB_PID_ATMEL_ASF_CDC 0x2404 +#define USB_PID_ATMEL_ASF_PHDC 0x2405 +#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 +#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 +#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 +#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 +#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 +#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 +#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 +#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 +#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 + + + + + +#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 +#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 +#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 +#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 +#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA +#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB +#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC +#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD +#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE + +#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF +#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 +#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 +#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 +#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 +#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 +#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 +#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 +#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 +#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 +#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 +#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA +#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB +#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC +#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED +#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE +#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF +#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 +#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 +#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 +#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 +#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 +#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 +#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 +#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 +#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 +#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 +#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA +#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB +# 51 "naeusb/sam3u_hal/inc/usb_protocol.h" 2 +# 63 "naeusb/sam3u_hal/inc/usb_protocol.h" +#define USB_V2_0 0x0200 +#define USB_V2_1 0x0201 + + + + +#define NO_CLASS 0x00 +#define CLASS_VENDOR_SPECIFIC 0xFF +#define NO_SUBCLASS 0x00 +#define NO_PROTOCOL 0x00 + + + + +#define CLASS_IAD 0xEF +#define SUB_CLASS_IAD 0x02 +#define PROTOCOL_IAD 0x01 + + + + + +#define USB_REQ_DIR_OUT (0<<7) +#define USB_REQ_DIR_IN (1<<7) +#define USB_REQ_DIR_MASK (1<<7) + + + + +#define USB_REQ_TYPE_STANDARD (0<<5) +#define USB_REQ_TYPE_CLASS (1<<5) +#define USB_REQ_TYPE_VENDOR (2<<5) +#define USB_REQ_TYPE_MASK (3<<5) + + + + +#define USB_REQ_RECIP_DEVICE (0<<0) +#define USB_REQ_RECIP_INTERFACE (1<<0) +#define USB_REQ_RECIP_ENDPOINT (2<<0) +#define USB_REQ_RECIP_OTHER (3<<0) +#define USB_REQ_RECIP_MASK (0x1F) + + + + +enum usb_reqid { + USB_REQ_GET_STATUS = 0, + USB_REQ_CLEAR_FEATURE = 1, + USB_REQ_SET_FEATURE = 3, + USB_REQ_SET_ADDRESS = 5, + USB_REQ_GET_DESCRIPTOR = 6, + USB_REQ_SET_DESCRIPTOR = 7, + USB_REQ_GET_CONFIGURATION = 8, + USB_REQ_SET_CONFIGURATION = 9, + USB_REQ_GET_INTERFACE = 10, + USB_REQ_SET_INTERFACE = 11, + USB_REQ_SYNCH_FRAME = 12, +}; + + + + + +enum usb_device_status { + USB_DEV_STATUS_BUS_POWERED = 0, + USB_DEV_STATUS_SELF_POWERED = 1, + USB_DEV_STATUS_REMOTEWAKEUP = 2 +}; + + + + + +enum usb_interface_status { + USB_IFACE_STATUS_RESERVED = 0 +}; + + + + + +enum usb_endpoint_status { + USB_EP_STATUS_HALTED = 1, +}; + + + + + + +enum usb_device_feature { + USB_DEV_FEATURE_REMOTE_WAKEUP = 1, + USB_DEV_FEATURE_TEST_MODE = 2, + USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3, + USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4, + USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5 +}; + + + + + + +enum usb_device_hs_test_mode { + USB_DEV_TEST_MODE_J = 1, + USB_DEV_TEST_MODE_K = 2, + USB_DEV_TEST_MODE_SE0_NAK = 3, + USB_DEV_TEST_MODE_PACKET = 4, + USB_DEV_TEST_MODE_FORCE_ENABLE = 5, +}; + + + + +enum usb_endpoint_feature { + USB_EP_FEATURE_HALT = 0, +}; + + + + +enum usb_test_mode_selector { + USB_TEST_J = 0x01, + USB_TEST_K = 0x02, + USB_TEST_SE0_NAK = 0x03, + USB_TEST_PACKET = 0x04, + USB_TEST_FORCE_ENABLE = 0x05, +}; + + + + +enum usb_descriptor_type { + USB_DT_DEVICE = 1, + USB_DT_CONFIGURATION = 2, + USB_DT_STRING = 3, + USB_DT_INTERFACE = 4, + USB_DT_ENDPOINT = 5, + USB_DT_DEVICE_QUALIFIER = 6, + USB_DT_OTHER_SPEED_CONFIGURATION = 7, + USB_DT_INTERFACE_POWER = 8, + USB_DT_OTG = 9, + USB_DT_IAD = 0x0B, + USB_DT_BOS = 0x0F, + USB_DT_DEVICE_CAPABILITY = 0x10, +}; + + + + +enum usb_capability_type { + USB_DC_USB20_EXTENSION = 0x02, +}; + + + + + +enum usb_capability_extension_attr { + USB_DC_EXT_LPM = 0x00000002, + USB_DC_EXT_BESL = 0x00000004, + USB_DC_EXT_BESL_BASELINE_VALID = 0x00000008, + USB_DC_EXT_BESL_DEEP_VALID = 0x00000010, +}; +#define USB_DC_EXT_BESL_DEEP_OFFSET 8 +#define USB_DC_EXT_BESL_DEEP(besl) ((besl & 0xF) << USB_DC_EXT_BESL_DEEP_OFFSET) +#define USB_DC_EXT_BESL_BASELINE_OFFSET 12 +#define USB_DC_EXT_BESL_BASELINE(besl) ((besl & 0xF) << USB_DC_EXT_BESL_BASELINE_OFFSET) + +#define BESL_125_US 0 +#define BESL_150_US 1 +#define BESL_200_US 2 +#define BESL_300_US 3 +#define BESL_400_US 4 +#define BESL_500_US 5 +#define BESL_1000_US 6 +#define BESL_2000_US 7 +#define BESL_3000_US 8 +#define BESL_4000_US 9 +#define BESL_5000_US 10 +#define BESL_6000_US 11 +#define BESL_7000_US 12 +#define BESL_8000_US 13 +#define BESL_9000_US 14 +#define BESL_10000_US 15 + + +#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0) +#define USB_LPM_ATTRIBUT_BESL_MASK (0xF << 4) +#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8) +#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0) +#define USB_LPM_ATTRIBUT_BESL(value) ((value & 0xF) << 4) +#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8) +#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1) + + + + +enum usb_ep_type { + USB_EP_TYPE_CONTROL = 0x00, + USB_EP_TYPE_ISOCHRONOUS = 0x01, + USB_EP_TYPE_BULK = 0x02, + USB_EP_TYPE_INTERRUPT = 0x03, + USB_EP_TYPE_MASK = 0x03, +}; + + + + +enum usb_langid { + USB_LANGID_EN_US = 0x0409, +}; + + + + +#define USB_EP_ADDR_MASK 0x0f + + +typedef uint8_t usb_add_t; + + + + +#define USB_EP_DIR_IN 0x80 + + + + +#define USB_EP_DIR_OUT 0x00 + + +typedef uint8_t usb_ep_t; + + + + + + + +#define USB_MAX_DESC_LEN 255 + + + + + +# 309 "naeusb/sam3u_hal/inc/usb_protocol.h" +#pragma pack(1) +# 309 "naeusb/sam3u_hal/inc/usb_protocol.h" + + + + + + + +typedef struct { + uint8_t bmRequestType; + uint8_t bRequest; + le16_t wValue; + le16_t wIndex; + le16_t wLength; +} usb_setup_req_t; + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + le16_t idVendor; + le16_t idProduct; + le16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} usb_dev_desc_t; +# 352 "naeusb/sam3u_hal/inc/usb_protocol.h" +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} usb_dev_qual_desc_t; +# 376 "naeusb/sam3u_hal/inc/usb_protocol.h" +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumDeviceCaps; +} usb_dev_bos_desc_t; + + + + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + le32_t bmAttributes; +} usb_dev_capa_ext_desc_t; + + + + + + +typedef struct { + usb_dev_bos_desc_t bos; + usb_dev_capa_ext_desc_t capa_ext; +} usb_dev_lpm_desc_t; + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} usb_association_desc_t; + + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} usb_conf_desc_t; + + +#define USB_CONFIG_ATTR_MUST_SET (1 << 7) +#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) +#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) +#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) + +#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} usb_iad_desc_t; + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_iface_desc_t; + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + le16_t wMaxPacketSize; + uint8_t bInterval; +} usb_ep_desc_t; + + + + + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; +} usb_str_desc_t; + +typedef struct { + usb_str_desc_t desc; + le16_t string[1]; +} usb_str_lgid_desc_t; + + +# 498 "naeusb/sam3u_hal/inc/usb_protocol.h" +#pragma pack() +# 498 "naeusb/sam3u_hal/inc/usb_protocol.h" + +# 49 "naeusb/sam3u_hal/inc/udi_vendor.h" 2 +# 1 "naeusb/sam3u_hal/inc/usb_protocol_vendor.h" 1 +# 45 "naeusb/sam3u_hal/inc/usb_protocol_vendor.h" +#define _USB_PROTOCOL_VENDOR_H_ +# 58 "naeusb/sam3u_hal/inc/usb_protocol_vendor.h" +#define VENDOR_CLASS 0xFF +#define VENDOR_SUBCLASS 0xFF +#define VENDOR_PROTOCOL 0xFF +# 50 "naeusb/sam3u_hal/inc/udi_vendor.h" 2 +# 1 "naeusb/sam3u_hal/inc/udd.h" 1 +# 45 "naeusb/sam3u_hal/inc/udd.h" +#define _UDD_H_ + + +# 1 "naeusb/sam3u_hal/inc/udc_desc.h" 1 +# 45 "naeusb/sam3u_hal/inc/udc_desc.h" +#define _UDC_DESC_H_ + + + +# 1 "naeusb/sam3u_hal/inc/udi.h" 1 +# 45 "naeusb/sam3u_hal/inc/udi.h" +#define _UDI_H_ +# 71 "naeusb/sam3u_hal/inc/udi.h" +typedef struct { +# 82 "naeusb/sam3u_hal/inc/udi.h" + +# 82 "naeusb/sam3u_hal/inc/udi.h" 3 4 +_Bool +# 82 "naeusb/sam3u_hal/inc/udi.h" + (*enable) (void); +# 95 "naeusb/sam3u_hal/inc/udi.h" + void (*disable) (void); +# 108 "naeusb/sam3u_hal/inc/udi.h" + +# 108 "naeusb/sam3u_hal/inc/udi.h" 3 4 +_Bool +# 108 "naeusb/sam3u_hal/inc/udi.h" + (*setup) (void); +# 117 "naeusb/sam3u_hal/inc/udi.h" + uint8_t(*getsetting) (void); + + + + + void(*sof_notify) (void); +} udi_api_t; +# 50 "naeusb/sam3u_hal/inc/udc_desc.h" 2 +# 77 "naeusb/sam3u_hal/inc/udc_desc.h" +#define UDC_DESC_STORAGE +# 88 "naeusb/sam3u_hal/inc/udc_desc.h" +#define UDC_DATA(x) COMPILER_ALIGNED(x) +#define UDC_BSS(x) COMPILER_ALIGNED(x) + + + + + + + +typedef struct { + + usb_conf_desc_t *desc; + + udi_api_t * * udi_apis; +} udc_config_speed_t; + + + + + +typedef struct { + + usb_dev_desc_t *confdev_lsfs; + + udc_config_speed_t *conf_lsfs; + + + usb_dev_desc_t *confdev_hs; + + usb_dev_qual_desc_t *qualifier; + + udc_config_speed_t *conf_hs; + + usb_dev_bos_desc_t *conf_bos; +} udc_config_t; + + +extern udc_config_t udc_config; +# 49 "naeusb/sam3u_hal/inc/udd.h" 2 +# 66 "naeusb/sam3u_hal/inc/udd.h" +typedef uint8_t udd_ep_id_t; + + + +typedef enum { + UDD_EP_TRANSFER_OK = 0, + UDD_EP_TRANSFER_ABORT = 1, +} udd_ep_status_t; + + + + + + + +typedef struct { + + + usb_setup_req_t req; + + + + uint8_t *payload; + + + uint16_t payload_size; + + + void (*callback) (void); + + + + +# 98 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 98 "naeusb/sam3u_hal/inc/udd.h" + (*over_under_run) (void); +} udd_ctrl_request_t; +extern udd_ctrl_request_t udd_g_ctrlreq; + + +#define Udd_setup_is_in() (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK)) + + + +#define Udd_setup_is_out() (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK)) + + + +#define Udd_setup_type() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK) + + + +#define Udd_setup_recipient() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK) + + + + + + + +typedef void (*udd_callback_halt_cleared_t) (void); +# 134 "naeusb/sam3u_hal/inc/udd.h" +typedef void (*udd_callback_trans_t) (udd_ep_status_t status, + iram_size_t nb_transfered, udd_ep_id_t ep); + + + + + + + +# 142 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 142 "naeusb/sam3u_hal/inc/udd.h" + udd_include_vbus_monitoring(void); + + + + +void udd_enable(void); + + + + +void udd_disable(void); +# 161 "naeusb/sam3u_hal/inc/udd.h" +void udd_attach(void); + + + + + + +void udd_detach(void); + + + + + + + + +# 176 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 176 "naeusb/sam3u_hal/inc/udd.h" + udd_is_high_speed(void); + + + + + + +void udd_set_address(uint8_t address); + + + + + + +uint8_t udd_getaddress(void); + + + + + + +uint16_t udd_get_frame_number(void); + + + + + + +uint16_t udd_get_micro_frame_number(void); + + + +void udd_send_remotewakeup(void); + + + + + + + +void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size ); +# 239 "naeusb/sam3u_hal/inc/udd.h" + +# 239 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 239 "naeusb/sam3u_hal/inc/udd.h" + udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, + uint16_t MaxEndpointSize); + + + + + + +void udd_ep_free(udd_ep_id_t ep); +# 256 "naeusb/sam3u_hal/inc/udd.h" + +# 256 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 256 "naeusb/sam3u_hal/inc/udd.h" + udd_ep_is_halted(udd_ep_id_t ep); +# 269 "naeusb/sam3u_hal/inc/udd.h" + +# 269 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 269 "naeusb/sam3u_hal/inc/udd.h" + udd_ep_set_halt(udd_ep_id_t ep); +# 282 "naeusb/sam3u_hal/inc/udd.h" + +# 282 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 282 "naeusb/sam3u_hal/inc/udd.h" + udd_ep_clear_halt(udd_ep_id_t ep); +# 294 "naeusb/sam3u_hal/inc/udd.h" + +# 294 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 294 "naeusb/sam3u_hal/inc/udd.h" + udd_ep_wait_stall_clear(udd_ep_id_t ep, + udd_callback_halt_cleared_t callback); +# 321 "naeusb/sam3u_hal/inc/udd.h" + +# 321 "naeusb/sam3u_hal/inc/udd.h" 3 4 +_Bool +# 321 "naeusb/sam3u_hal/inc/udd.h" + udd_ep_run(udd_ep_id_t ep, +# 321 "naeusb/sam3u_hal/inc/udd.h" 3 4 + _Bool +# 321 "naeusb/sam3u_hal/inc/udd.h" + b_shortpacket, + uint8_t * buf, iram_size_t buf_size, + udd_callback_trans_t callback); +# 333 "naeusb/sam3u_hal/inc/udd.h" +void udd_ep_abort(udd_ep_id_t ep); +# 346 "naeusb/sam3u_hal/inc/udd.h" +void udd_test_mode_j(void); +void udd_test_mode_k(void); +void udd_test_mode_se0_nak(void); +void udd_test_mode_packet(void); +# 370 "naeusb/sam3u_hal/inc/udd.h" +extern +# 370 "naeusb/sam3u_hal/inc/udd.h" 3 4 + _Bool +# 370 "naeusb/sam3u_hal/inc/udd.h" + udc_process_setup(void); + + + + + + +extern void udc_reset(void); + + + + + + +extern void udc_sof_notify(void); +# 51 "naeusb/sam3u_hal/inc/udi_vendor.h" 2 +# 87 "naeusb/sam3u_hal/inc/udi_vendor.h" +extern udi_api_t udi_api_vendor; +# 125 "naeusb/sam3u_hal/inc/udi_vendor.h" +#define UDI_VENDOR_EPS_INT_DESC +#define UDI_VENDOR_EPS_INT_DESC_FS +#define UDI_VENDOR_EPS_INT_DESC_HS + + + +#define UDI_VENDOR_EPS_BULK_DESC .ep_bulk_in.bLength = sizeof(usb_ep_desc_t), .ep_bulk_in.bDescriptorType = USB_DT_ENDPOINT, .ep_bulk_in.bEndpointAddress = UDI_VENDOR_EP_BULK_IN, .ep_bulk_in.bmAttributes = USB_EP_TYPE_BULK, .ep_bulk_in.bInterval = 0, .ep_bulk_out.bLength = sizeof(usb_ep_desc_t), .ep_bulk_out.bDescriptorType = USB_DT_ENDPOINT, .ep_bulk_out.bEndpointAddress = UDI_VENDOR_EP_BULK_OUT, .ep_bulk_out.bmAttributes = USB_EP_TYPE_BULK, .ep_bulk_out.bInterval = 0, +# 143 "naeusb/sam3u_hal/inc/udi_vendor.h" +#define UDI_VENDOR_EPS_BULK_DESC_FS .ep_bulk_in.wMaxPacketSize = LE16(UDI_VENDOR_EPS_SIZE_BULK_FS), .ep_bulk_out.wMaxPacketSize = LE16(UDI_VENDOR_EPS_SIZE_BULK_FS), + + + +#define UDI_VENDOR_EPS_BULK_DESC_HS .ep_bulk_in.wMaxPacketSize = LE16(UDI_VENDOR_EPS_SIZE_BULK_HS), .ep_bulk_out.wMaxPacketSize = LE16(UDI_VENDOR_EPS_SIZE_BULK_HS), +# 179 "naeusb/sam3u_hal/inc/udi_vendor.h" +#define UDI_VENDOR_EPS_ISO_DESC +#define UDI_VENDOR_EPS_ISO_DESC_FS +#define UDI_VENDOR_EPS_ISO_DESC_HS + + + + + +typedef struct { + usb_iface_desc_t iface0; + + + + + + + usb_ep_desc_t ep_bulk_in; + usb_ep_desc_t ep_bulk_out; + + + + + +} udi_vendor_desc_t; + + + +#define UDI_VENDOR_STRING_ID 0 + + + +#define UDI_VENDOR_EP_NB_INT ((UDI_VENDOR_EPS_SIZE_INT_FS)?2:0) +#define UDI_VENDOR_EP_NB_BULK ((UDI_VENDOR_EPS_SIZE_BULK_FS)?2:0) +#define UDI_VENDOR_EP_NB_ISO ((UDI_VENDOR_EPS_SIZE_ISO_FS)?2:0) +#define UDI_VENDOR_EP_NB (UDI_VENDOR_EP_NB_INT+UDI_VENDOR_EP_NB_BULK+UDI_VENDOR_EP_NB_ISO) +# 229 "naeusb/sam3u_hal/inc/udi_vendor.h" +#define UDI_VENDOR_DESC .iface0.bLength = sizeof(usb_iface_desc_t), .iface0.bDescriptorType = USB_DT_INTERFACE, .iface0.bInterfaceNumber = UDI_VENDOR_IFACE_NUMBER, .iface0.bAlternateSetting = 0 , .iface0.bNumEndpoints = UDI_VENDOR_EP_NB, .iface0.bInterfaceClass = VENDOR_CLASS, .iface0.bInterfaceSubClass = VENDOR_SUBCLASS, .iface0.bInterfaceProtocol = VENDOR_PROTOCOL, .iface0.iInterface = UDI_VENDOR_STRING_ID, UDI_VENDOR_EPS_INT_DESC UDI_VENDOR_EPS_BULK_DESC UDI_VENDOR_EPS_ISO_DESC +# 244 "naeusb/sam3u_hal/inc/udi_vendor.h" +#define UDI_VENDOR_DESC_FS { UDI_VENDOR_DESC UDI_VENDOR_EPS_INT_DESC_FS UDI_VENDOR_EPS_BULK_DESC_FS UDI_VENDOR_EPS_ISO_DESC_FS } + + + + + + + +#define UDI_VENDOR_DESC_HS { UDI_VENDOR_DESC UDI_VENDOR_EPS_INT_DESC_HS UDI_VENDOR_EPS_BULK_DESC_HS UDI_VENDOR_EPS_ISO_DESC_HS } +# 321 "naeusb/sam3u_hal/inc/udi_vendor.h" + +# 321 "naeusb/sam3u_hal/inc/udi_vendor.h" 3 4 +_Bool +# 321 "naeusb/sam3u_hal/inc/udi_vendor.h" + udi_vendor_bulk_in_run(uint8_t * buf, iram_size_t buf_size, + udd_callback_trans_t callback); +# 337 "naeusb/sam3u_hal/inc/udi_vendor.h" + +# 337 "naeusb/sam3u_hal/inc/udi_vendor.h" 3 4 +_Bool +# 337 "naeusb/sam3u_hal/inc/udi_vendor.h" + udi_vendor_bulk_out_run(uint8_t * buf, iram_size_t buf_size, + udd_callback_trans_t callback); +# 296 "./config/conf_usb.h" 2 +# 1 "naeusb/sam3u_hal/inc/udi_cdc.h" 1 +# 38 "naeusb/sam3u_hal/inc/udi_cdc.h" +#define _UDI_CDC_H_ + + + +# 1 "naeusb/sam3u_hal/inc/usb_protocol_cdc.h" 1 +# 43 "naeusb/sam3u_hal/inc/udi_cdc.h" 2 +# 65 "naeusb/sam3u_hal/inc/udi_cdc.h" +extern udi_api_t udi_api_cdc_comm; +extern udi_api_t udi_api_cdc_data; +# 84 "naeusb/sam3u_hal/inc/udi_cdc.h" +typedef struct { + + usb_iface_desc_t iface; + + usb_cdc_hdr_desc_t header; + + usb_cdc_acm_desc_t acm; + + usb_cdc_union_desc_t union_desc; + + usb_cdc_call_mgmt_desc_t call_mgmt; + + usb_ep_desc_t ep_notify; +} udi_cdc_comm_desc_t; +# 106 "naeusb/sam3u_hal/inc/udi_cdc.h" +typedef struct { + + usb_iface_desc_t iface; + + usb_ep_desc_t ep_in; + usb_ep_desc_t ep_out; +} udi_cdc_data_desc_t; + + + +#define UDI_CDC_COMM_EP_SIZE 64 + +#define UDI_CDC_DATA_EPS_FS_SIZE 64 + +#define UDI_CDC_DATA_EPS_HS_SIZE 512 +# 129 "naeusb/sam3u_hal/inc/udi_cdc.h" +#define UDI_CDC_IAD_STRING_ID_0 0 + + +#define UDI_CDC_COMM_STRING_ID_0 0 + + +#define UDI_CDC_DATA_STRING_ID_0 0 + +#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0) +#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0) +#define UDI_CDC_DATA_DESC_0_FS UDI_CDC_DATA_DESC_FS(0) +#define UDI_CDC_DATA_DESC_0_HS UDI_CDC_DATA_DESC_HS(0) + + + +#define UDI_CDC_IAD_STRING_ID_1 0 + + +#define UDI_CDC_COMM_STRING_ID_1 0 + + +#define UDI_CDC_DATA_STRING_ID_1 0 + +#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1) +#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1) +#define UDI_CDC_DATA_DESC_1_FS UDI_CDC_DATA_DESC_FS(1) +#define UDI_CDC_DATA_DESC_1_HS UDI_CDC_DATA_DESC_HS(1) + + + +#define UDI_CDC_IAD_STRING_ID_2 0 + + +#define UDI_CDC_COMM_STRING_ID_2 0 + + +#define UDI_CDC_DATA_STRING_ID_2 0 + +#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2) +#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2) +#define UDI_CDC_DATA_DESC_2_FS UDI_CDC_DATA_DESC_FS(2) +#define UDI_CDC_DATA_DESC_2_HS UDI_CDC_DATA_DESC_HS(2) + + + +#define UDI_CDC_IAD_STRING_ID_3 0 + + +#define UDI_CDC_COMM_STRING_ID_3 0 + + +#define UDI_CDC_DATA_STRING_ID_3 0 + +#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3) +#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3) +#define UDI_CDC_DATA_DESC_3_FS UDI_CDC_DATA_DESC_FS(3) +#define UDI_CDC_DATA_DESC_3_HS UDI_CDC_DATA_DESC_HS(3) + + + +#define UDI_CDC_IAD_STRING_ID_4 0 + + +#define UDI_CDC_COMM_STRING_ID_4 0 + + +#define UDI_CDC_DATA_STRING_ID_4 0 + +#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4) +#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4) +#define UDI_CDC_DATA_DESC_4_FS UDI_CDC_DATA_DESC_FS(4) +#define UDI_CDC_DATA_DESC_4_HS UDI_CDC_DATA_DESC_HS(4) + + + +#define UDI_CDC_IAD_STRING_ID_5 0 + + +#define UDI_CDC_COMM_STRING_ID_5 0 + + +#define UDI_CDC_DATA_STRING_ID_5 0 + +#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5) +#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5) +#define UDI_CDC_DATA_DESC_5_FS UDI_CDC_DATA_DESC_FS(5) +#define UDI_CDC_DATA_DESC_5_HS UDI_CDC_DATA_DESC_HS(5) + + + +#define UDI_CDC_IAD_STRING_ID_6 0 + + +#define UDI_CDC_COMM_STRING_ID_6 0 + + +#define UDI_CDC_DATA_STRING_ID_6 0 + +#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6) +#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6) +#define UDI_CDC_DATA_DESC_6_FS UDI_CDC_DATA_DESC_FS(6) +#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6) + + + + +#define UDI_CDC_IAD_DESC(port) { .bLength = sizeof(usb_iad_desc_t), .bDescriptorType = USB_DT_IAD, .bInterfaceCount = 2, .bFunctionClass = CDC_CLASS_COMM, .bFunctionSubClass = CDC_SUBCLASS_ACM, .bFunctionProtocol = CDC_PROTOCOL_V25TER, .bFirstInterface = UDI_CDC_COMM_IFACE_NUMBER_ ##port, .iFunction = UDI_CDC_IAD_STRING_ID_ ##port, } +# 247 "naeusb/sam3u_hal/inc/udi_cdc.h" +#define UDI_CDC_COMM_DESC(port) { .iface.bLength = sizeof(usb_iface_desc_t), .iface.bDescriptorType = USB_DT_INTERFACE, .iface.bAlternateSetting = 0, .iface.bNumEndpoints = 1, .iface.bInterfaceClass = CDC_CLASS_COMM, .iface.bInterfaceSubClass = CDC_SUBCLASS_ACM, .iface.bInterfaceProtocol = CDC_PROTOCOL_V25TER, .header.bFunctionLength = sizeof(usb_cdc_hdr_desc_t), .header.bDescriptorType = CDC_CS_INTERFACE, .header.bDescriptorSubtype = CDC_SCS_HEADER, .header.bcdCDC = LE16(0x0110), .call_mgmt.bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t), .call_mgmt.bDescriptorType = CDC_CS_INTERFACE, .call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT, .call_mgmt.bmCapabilities = CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI, .acm.bFunctionLength = sizeof(usb_cdc_acm_desc_t), .acm.bDescriptorType = CDC_CS_INTERFACE, .acm.bDescriptorSubtype = CDC_SCS_ACM, .acm.bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS | CDC_ACM_SUPPORT_SENDBREAK_REQUESTS, .union_desc.bFunctionLength = sizeof(usb_cdc_union_desc_t), .union_desc.bDescriptorType = CDC_CS_INTERFACE, .union_desc.bDescriptorSubtype= CDC_SCS_UNION, .ep_notify.bLength = sizeof(usb_ep_desc_t), .ep_notify.bDescriptorType = USB_DT_ENDPOINT, .ep_notify.bmAttributes = USB_EP_TYPE_INTERRUPT, .ep_notify.wMaxPacketSize = LE16(UDI_CDC_COMM_EP_SIZE), .ep_notify.bInterval = 0x10, .ep_notify.bEndpointAddress = UDI_CDC_COMM_EP_ ##port, .iface.bInterfaceNumber = UDI_CDC_COMM_IFACE_NUMBER_ ##port, .call_mgmt.bDataInterface = UDI_CDC_DATA_IFACE_NUMBER_ ##port, .union_desc.bMasterInterface = UDI_CDC_COMM_IFACE_NUMBER_ ##port, .union_desc.bSlaveInterface0 = UDI_CDC_DATA_IFACE_NUMBER_ ##port, .iface.iInterface = UDI_CDC_COMM_STRING_ID_ ##port, } +# 285 "naeusb/sam3u_hal/inc/udi_cdc.h" +#define UDI_CDC_DATA_DESC_COMMON .iface.bLength = sizeof(usb_iface_desc_t), .iface.bDescriptorType = USB_DT_INTERFACE, .iface.bAlternateSetting = 0, .iface.bNumEndpoints = 2, .iface.bInterfaceClass = CDC_CLASS_DATA, .iface.bInterfaceSubClass = 0, .iface.bInterfaceProtocol = 0, .ep_in.bLength = sizeof(usb_ep_desc_t), .ep_in.bDescriptorType = USB_DT_ENDPOINT, .ep_in.bmAttributes = USB_EP_TYPE_BULK, .ep_in.bInterval = 0, .ep_out.bLength = sizeof(usb_ep_desc_t), .ep_out.bDescriptorType = USB_DT_ENDPOINT, .ep_out.bmAttributes = USB_EP_TYPE_BULK, .ep_out.bInterval = 0, +# 302 "naeusb/sam3u_hal/inc/udi_cdc.h" +#define UDI_CDC_DATA_DESC_FS(port) { UDI_CDC_DATA_DESC_COMMON .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE), .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE), .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_ ##port, .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_ ##port, .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_ ##port, .iface.iInterface = UDI_CDC_DATA_STRING_ID_ ##port, } +# 312 "naeusb/sam3u_hal/inc/udi_cdc.h" +#define UDI_CDC_DATA_DESC_HS(port) { UDI_CDC_DATA_DESC_COMMON .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE), .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE), .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_ ##port, .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_ ##port, .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_ ##port, .iface.iInterface = UDI_CDC_DATA_STRING_ID_ ##port, } +# 347 "naeusb/sam3u_hal/inc/udi_cdc.h" +void udi_cdc_ctrl_signal_dcd( +# 347 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 + _Bool +# 347 "naeusb/sam3u_hal/inc/udi_cdc.h" + b_set); + + + + + + +void udi_cdc_ctrl_signal_dsr( +# 354 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 + _Bool +# 354 "naeusb/sam3u_hal/inc/udi_cdc.h" + b_set); + + + + +void udi_cdc_signal_framing_error(void); + + + + +void udi_cdc_signal_parity_error(void); + + + + +void udi_cdc_signal_overrun(void); + + + + + + +iram_size_t udi_cdc_get_nb_received_data(void); + + + + + + + +# 383 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 +_Bool +# 383 "naeusb/sam3u_hal/inc/udi_cdc.h" + udi_cdc_is_rx_ready(void); + + + + + + +int udi_cdc_getc(void); +# 400 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size); +# 411 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size); + + + + + + +iram_size_t udi_cdc_get_free_tx_buffer(void); + + + + + + + + +# 426 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 +_Bool +# 426 "naeusb/sam3u_hal/inc/udi_cdc.h" + udi_cdc_is_tx_ready(void); +# 436 "naeusb/sam3u_hal/inc/udi_cdc.h" +int udi_cdc_putc(int value); +# 446 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size); +# 460 "naeusb/sam3u_hal/inc/udi_cdc.h" +void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, +# 460 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 + _Bool +# 460 "naeusb/sam3u_hal/inc/udi_cdc.h" + b_set); + + + + + + + +void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, +# 468 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 + _Bool +# 468 "naeusb/sam3u_hal/inc/udi_cdc.h" + b_set); + + + + + + +void udi_cdc_multi_signal_framing_error(uint8_t port); + + + + + + +void udi_cdc_multi_signal_parity_error(uint8_t port); + + + + + + +void udi_cdc_multi_signal_overrun(uint8_t port); +# 498 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port); +# 507 "naeusb/sam3u_hal/inc/udi_cdc.h" + +# 507 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 +_Bool +# 507 "naeusb/sam3u_hal/inc/udi_cdc.h" + udi_cdc_multi_is_rx_ready(uint8_t port); +# 516 "naeusb/sam3u_hal/inc/udi_cdc.h" +int udi_cdc_multi_getc(uint8_t port); +# 527 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size); +# 536 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port); +# 546 "naeusb/sam3u_hal/inc/udi_cdc.h" + +# 546 "naeusb/sam3u_hal/inc/udi_cdc.h" 3 4 +_Bool +# 546 "naeusb/sam3u_hal/inc/udi_cdc.h" + udi_cdc_multi_is_tx_ready(uint8_t port); +# 557 "naeusb/sam3u_hal/inc/udi_cdc.h" +int udi_cdc_multi_putc(uint8_t port, int value); +# 568 "naeusb/sam3u_hal/inc/udi_cdc.h" +iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size); +# 297 "./config/conf_usb.h" 2 diff --git a/ChipWhisperer-Husky/src/version.txt b/ChipWhisperer-Husky/src/version.txt new file mode 100644 index 0000000..e2fcb20 --- /dev/null +++ b/ChipWhisperer-Husky/src/version.txt @@ -0,0 +1,3 @@ +FW_VER_MAJOR 1 +FW_VER_MINOR 5 +FW_VER_DEBUG 0