From d303f6343db78a93b109ac8d7ac98631723cf0a2 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 26 Feb 2021 10:49:18 -0800 Subject: [PATCH] Update interpreter and text with finalized opcodes Opcodes were finalized in #452, this updates the interpreter and spec text to use these final opcodes. --- .../core/appendix/gen-index-instructions.py | 84 +++++++++-------- document/core/appendix/index-instructions.rst | 84 +++++++++-------- document/core/binary/instructions.rst | 86 +++++++++-------- document/core/syntax/instructions.rst | 1 - document/core/util/macros.def | 5 +- interpreter/binary/decode.ml | 94 +++++++++---------- interpreter/binary/encode.ml | 90 +++++++++--------- 7 files changed, 237 insertions(+), 207 deletions(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index 3094a30e2..82ae723c4 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -333,14 +333,6 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\LOAD\K{\_splat}~\memarg', r'\hex{FD}~~9', r'[\I32] \to [\V128]', r'valid-load-splat', r'exec-load-splat'), Instruction(r'\I64X2.\LOAD\K{\_splat}~\memarg', r'\hex{FD}~~10', r'[\I32] \to [\V128]', r'valid-load-splat', r'exec-load-splat'), Instruction(r'\V128.\STORE~\memarg', r'\hex{FD}~~11', r'[\I32~\V128] \to []', r'valid-store', r'exec-store'), - Instruction(r'\V128.\LOAD\K{8\_lane}~\memarg~\laneidx', r'\hex{FD}~~88', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), - Instruction(r'\V128.\LOAD\K{16\_lane}~\memarg~\laneidx', r'\hex{FD}~~89', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), - Instruction(r'\V128.\LOAD\K{32\_lane}~\memarg~\laneidx', r'\hex{FD}~~90', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), - Instruction(r'\V128.\LOAD\K{64\_lane}~\memarg~\laneidx', r'\hex{FD}~~91', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), - Instruction(r'\V128.\STORE\K{8\_lane}~\memarg~\laneidx', r'\hex{FD}~~92', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), - Instruction(r'\V128.\STORE\K{16\_lane}~\memarg~\laneidx', r'\hex{FD}~~93', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), - Instruction(r'\V128.\STORE\K{32\_lane}~\memarg~\laneidx', r'\hex{FD}~~94', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), - Instruction(r'\V128.\STORE\K{64\_lane}~\memarg~\laneidx', r'\hex{FD}~~95', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), Instruction(r'\V128.\VCONST~\i128', r'\hex{FD}~~12', r'[] \to [\V128]', r'valid-vconst', r'exec-vconst'), Instruction(r'\I8X16.\SHUFFLE~\laneidx^{16}', r'\hex{FD}~~13', r'[\V128~\V128~\V128] \to [\V128]', r'valid-simd-shuffle', r'exec-simd-shuffle'), Instruction(r'\I8X16.\SWIZZLE', r'\hex{FD}~~14', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-swizzle'), @@ -394,12 +386,6 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VLE\K{\_u}', r'\hex{FD}~~62', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ile_u'), Instruction(r'\I32X4.\VGE\K{\_s}', r'\hex{FD}~~63', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ige_s'), Instruction(r'\I32X4.\VGE\K{\_u}', r'\hex{FD}~~64', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ige_u'), - Instruction(r'\I64X2.\VEQ', r'\hex{FD}~~192', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ieq'), - Instruction(r'\I64X2.\VNE', r'\hex{FD}~~208', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ine'), - Instruction(r'\I64X2.\VLT\K{\_s}', r'\hex{FD}~~116', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ilt_s'), - Instruction(r'\I64X2.\VGT\K{\_s}', r'\hex{FD}~~122', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-igt_s'), - Instruction(r'\I64X2.\VLE\K{\_s}', r'\hex{FD}~~238', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ile_s'), - Instruction(r'\I64X2.\VGE\K{\_s}', r'\hex{FD}~~226', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ige_s'), Instruction(r'\F32X4.\VEQ', r'\hex{FD}~~65', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-feq'), Instruction(r'\F32X4.\VNE', r'\hex{FD}~~66', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fne'), Instruction(r'\F32X4.\VLT', r'\hex{FD}~~67', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-flt'), @@ -418,13 +404,30 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\V128.\VOR', r'\hex{FD}~~80', r'[\V128~\V128] \to [\V128]', r'valid-vsbinop', r'exec-vsbinop', r'op-ior'), Instruction(r'\V128.\VXOR', r'\hex{FD}~~81', r'[\V128~\V128] \to [\V128]', r'valid-vsbinop', r'exec-vsbinop', r'op-ixor'), Instruction(r'\V128.\BITSELECT', r'\hex{FD}~~82', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vsternop', r'exec-vsternop', r'op-ibitselect'), - Instruction(r'\V128.\ANYTRUE', r'\hex{FD}~~98', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), + Instruction(r'\V128.\ANYTRUE', r'\hex{FD}~~83', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), + Instruction(r'\V128.\LOAD\K{8\_lane}~\memarg~\laneidx', r'\hex{FD}~~84', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), + Instruction(r'\V128.\LOAD\K{16\_lane}~\memarg~\laneidx', r'\hex{FD}~~85', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), + Instruction(r'\V128.\LOAD\K{32\_lane}~\memarg~\laneidx', r'\hex{FD}~~86', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), + Instruction(r'\V128.\LOAD\K{64\_lane}~\memarg~\laneidx', r'\hex{FD}~~87', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), + Instruction(r'\V128.\STORE\K{8\_lane}~\memarg~\laneidx', r'\hex{FD}~~88', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), + Instruction(r'\V128.\STORE\K{16\_lane}~\memarg~\laneidx', r'\hex{FD}~~89', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), + Instruction(r'\V128.\STORE\K{32\_lane}~\memarg~\laneidx', r'\hex{FD}~~90', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), + Instruction(r'\V128.\STORE\K{64\_lane}~\memarg~\laneidx', r'\hex{FD}~~91', r'[\I32~\V128] \to [\V128]', r'valid-store-lane', r'exec-store-lane'), + Instruction(r'\V128.\LOAD\K{32\_zero}~\memarg~\laneidx', r'\hex{FD}~~92', r'[\I32] \to [\V128]', r'valid-load-zero', r'exec-load-zero'), + Instruction(r'\V128.\LOAD\K{64\_zero}~\memarg~\laneidx', r'\hex{FD}~~93', r'[\I32] \to [\V128]', r'valid-load-zero', r'exec-load-zero'), + Instruction(r'\F32X4.\VDEMOTE\K{\_f64x2\_zero}', r'\hex{FD}~~94', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-demote'), + Instruction(r'\F64X2.\VPROMOTE\K{\_low\_f32x4}', r'\hex{FD}~~95', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-promote'), Instruction(r'\I8X16.\VABS', r'\hex{FD}~~96', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'), Instruction(r'\I8X16.\VNEG', r'\hex{FD}~~97', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'), + Instruction(r'\I8X16.\VPOPCNT', r'\hex{FD}~~98', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ipopcnt'), Instruction(r'\I8X16.\ALLTRUE', r'\hex{FD}~~99', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), Instruction(r'\I8X16.\BITMASK', r'\hex{FD}~~100', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'), Instruction(r'\I8X16.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~101', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'), Instruction(r'\I8X16.\NARROW\K{\_i16x8\_u}', r'\hex{FD}~~102', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'), + Instruction(r'\F32X4.\VCEIL', r'\hex{FD}~~103', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fceil'), + Instruction(r'\F32X4.\VFLOOR', r'\hex{FD}~~104', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ffloor'), + Instruction(r'\F32X4.\VTRUNC', r'\hex{FD}~~105', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ftrunc'), + Instruction(r'\F32X4.\VNEAREST', r'\hex{FD}~~106', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fnearest'), Instruction(r'\I8X16.\VSHL', r'\hex{FD}~~107', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'), Instruction(r'\I8X16.\VSHR\K{\_s}', r'\hex{FD}~~108', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'), Instruction(r'\I8X16.\VSHR\K{\_u}', r'\hex{FD}~~109', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'), @@ -434,14 +437,21 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I8X16.\VSUB', r'\hex{FD}~~113', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub'), Instruction(r'\I8X16.\VSUB\K{\_sat\_s}', r'\hex{FD}~~114', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub_sat_s'), Instruction(r'\I8X16.\VSUB\K{\_sat\_u}', r'\hex{FD}~~115', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub_sat_u'), + Instruction(r'\F64X2.\VCEIL', r'\hex{FD}~~116', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fceil'), + Instruction(r'\F64X2.\VFLOOR', r'\hex{FD}~~117', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ffloor'), Instruction(r'\I8X16.\VMIN\K{\_s}', r'\hex{FD}~~118', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imin_s'), Instruction(r'\I8X16.\VMIN\K{\_u}', r'\hex{FD}~~119', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imin_u'), Instruction(r'\I8X16.\VMAX\K{\_s}', r'\hex{FD}~~120', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_s'), Instruction(r'\I8X16.\VMAX\K{\_u}', r'\hex{FD}~~121', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_u'), + Instruction(r'\F64X2.\VTRUNC', r'\hex{FD}~~122', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ftrunc'), Instruction(r'\I8X16.\AVGR\K{\_u}', r'\hex{FD}~~123', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-iavgr_u'), - Instruction(r'\I8X16.\VPOPCNT', r'\hex{FD}~~124', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ipopcnt'), + Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}', r'\hex{FD}~~124', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), + Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}', r'\hex{FD}~~125', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), + Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}', r'\hex{FD}~~126', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), + Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}', r'\hex{FD}~~127', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), Instruction(r'\I16X8.\VABS', r'\hex{FD}~~128', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'), Instruction(r'\I16X8.\VNEG', r'\hex{FD}~~129', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'), + Instruction(r'\I16X8.\Q15MULRSAT\K{\_s}', r'\hex{FD}~~130', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-iq15mulrsat_s'), Instruction(r'\I16X8.\ALLTRUE', r'\hex{FD}~~131', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), Instruction(r'\I16X8.\BITMASK', r'\hex{FD}~~132', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'), Instruction(r'\I16X8.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~133', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'), @@ -459,25 +469,21 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I16X8.\VSUB', r'\hex{FD}~~145', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub'), Instruction(r'\I16X8.\VSUB\K{\_sat\_s}', r'\hex{FD}~~146', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub_sat_s'), Instruction(r'\I16X8.\VSUB\K{\_sat\_u}', r'\hex{FD}~~147', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub_sat_u'), + Instruction(r'\F64X2.\VNEAREST', r'\hex{FD}~~148', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fnearest'), Instruction(r'\I16X8.\VMUL', r'\hex{FD}~~149', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imul'), Instruction(r'\I16X8.\VMIN\K{\_s}', r'\hex{FD}~~150', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imin_s'), Instruction(r'\I16X8.\VMIN\K{\_u}', r'\hex{FD}~~151', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imin_u'), Instruction(r'\I16X8.\VMAX\K{\_s}', r'\hex{FD}~~152', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_s'), Instruction(r'\I16X8.\VMAX\K{\_u}', r'\hex{FD}~~153', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_u'), Instruction(r'\I16X8.\AVGR\K{\_u}', r'\hex{FD}~~155', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-iavgr_u'), - Instruction(r'\I16X8.\Q15MULRSAT\K{\_s}', r'\hex{FD}~~156', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-iq15mulrsat_s'), - Instruction(r'\I16X8.\EXTMUL\K{\_low\_i8x16\_s}', r'\hex{FD}~~154', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I16X8.\EXTMUL\K{\_low\_i8x16\_s}', r'\hex{FD}~~156', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I16X8.\EXTMUL\K{\_high\_i8x16\_s}', r'\hex{FD}~~157', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I16X8.\EXTMUL\K{\_low\_i8x16\_u}', r'\hex{FD}~~158', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I16X8.\EXTMUL\K{\_high\_i8x16\_u}', r'\hex{FD}~~159', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), - Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}', r'\hex{FD}~~194', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), - Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}', r'\hex{FD}~~195', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), Instruction(r'\I32X4.\VABS', r'\hex{FD}~~160', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'), Instruction(r'\I32X4.\VNEG', r'\hex{FD}~~161', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'), Instruction(r'\I32X4.\ALLTRUE', r'\hex{FD}~~163', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'), - Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}', r'\hex{FD}~~165', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), - Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}', r'\hex{FD}~~166', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'), Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'), Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'), @@ -493,12 +499,13 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VMAX\K{\_s}', r'\hex{FD}~~184', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_s'), Instruction(r'\I32X4.\VMAX\K{\_u}', r'\hex{FD}~~185', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_u'), Instruction(r'\I32X4.\DOT\K{\_i16x8\_s}', r'\hex{FD}~~186', r'[\V128~\V128] \to [\V128]', r'valid-simd-dot', r'exec-simd-dot'), - Instruction(r'\I32X4.\EXTMUL\K{\_low\_i16x8\_s}', r'\hex{FD}~~187', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I32X4.\EXTMUL\K{\_low\_i16x8\_s}', r'\hex{FD}~~188', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I32X4.\EXTMUL\K{\_high\_i16x8\_s}', r'\hex{FD}~~189', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I32X4.\EXTMUL\K{\_low\_i16x8\_u}', r'\hex{FD}~~190', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I32X4.\EXTMUL\K{\_high\_i16x8\_u}', r'\hex{FD}~~191', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), - Instruction(r'\I64X2.\VABS', r'\hex{FD}~~162', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'), + Instruction(r'\I64X2.\VABS', r'\hex{FD}~~192', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'), Instruction(r'\I64X2.\VNEG', r'\hex{FD}~~193', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'), + Instruction(r'\I64X2.\ALLTRUE', r'\hex{FD}~~195', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), Instruction(r'\I64X2.\BITMASK', r'\hex{FD}~~196', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'), Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'), Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'), @@ -508,13 +515,18 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I64X2.\VSHR\K{\_s}', r'\hex{FD}~~204', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'), Instruction(r'\I64X2.\VSHR\K{\_u}', r'\hex{FD}~~205', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'), Instruction(r'\I64X2.\VADD', r'\hex{FD}~~206', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-iadd'), - Instruction(r'\I64X2.\ALLTRUE', r'\hex{FD}~~207', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), Instruction(r'\I64X2.\VSUB', r'\hex{FD}~~209', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub'), Instruction(r'\I64X2.\VMUL', r'\hex{FD}~~213', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imul'), - Instruction(r'\I64X2.\EXTMUL\K{\_low\_i32x4\_s}', r'\hex{FD}~~210', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), - Instruction(r'\I64X2.\EXTMUL\K{\_high\_i32x4\_s}', r'\hex{FD}~~211', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), - Instruction(r'\I64X2.\EXTMUL\K{\_low\_i32x4\_u}', r'\hex{FD}~~214', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), - Instruction(r'\I64X2.\EXTMUL\K{\_high\_i32x4\_u}', r'\hex{FD}~~215', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I64X2.\VEQ', r'\hex{FD}~~214', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ieq'), + Instruction(r'\I64X2.\VNE', r'\hex{FD}~~215', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ine'), + Instruction(r'\I64X2.\VLT\K{\_s}', r'\hex{FD}~~216', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ilt_s'), + Instruction(r'\I64X2.\VGT\K{\_s}', r'\hex{FD}~~217', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-igt_s'), + Instruction(r'\I64X2.\VLE\K{\_s}', r'\hex{FD}~~218', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ile_s'), + Instruction(r'\I64X2.\VGE\K{\_s}', r'\hex{FD}~~219', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-ige_s'), + Instruction(r'\I64X2.\EXTMUL\K{\_low\_i32x4\_s}', r'\hex{FD}~~220', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I64X2.\EXTMUL\K{\_high\_i32x4\_s}', r'\hex{FD}~~221', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I64X2.\EXTMUL\K{\_low\_i32x4\_u}', r'\hex{FD}~~222', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I64X2.\EXTMUL\K{\_high\_i32x4\_u}', r'\hex{FD}~~223', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\F32X4.\VABS', r'\hex{FD}~~224', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fabs'), Instruction(r'\F32X4.\VNEG', r'\hex{FD}~~225', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fneg'), Instruction(r'\F32X4.\VSQRT', r'\hex{FD}~~227', r'[\V128] \to [\I32]', r'valid-vunop', r'exec-vunop', r'op-fsqrt'), @@ -534,19 +546,17 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\F64X2.\VMUL', r'\hex{FD}~~242', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmul'), Instruction(r'\F64X2.\VDIV', r'\hex{FD}~~243', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fdiv'), Instruction(r'\F64X2.\VMIN', r'\hex{FD}~~244', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmin'), - Instruction(r'\F64X2.\VPMIN', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'), - Instruction(r'\F64X2.\VPMAX', r'\hex{FD}~~246', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'), Instruction(r'\F64X2.\VMAX', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmax'), + Instruction(r'\F64X2.\VPMIN', r'\hex{FD}~~246', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'), + Instruction(r'\F64X2.\VPMAX', r'\hex{FD}~~247', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'), Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_s}', r'\hex{FD}~~248', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_s'), Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_u}', r'\hex{FD}~~249', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), Instruction(r'\F32X4.\CONVERT\K{\_i32x4\_s}', r'\hex{FD}~~250', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), Instruction(r'\F32X4.\CONVERT\K{\_i32x4\_u}', r'\hex{FD}~~251', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), - Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}', r'\hex{FD}~~85', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_s'), - Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~86', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), - Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~83', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), - Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~84', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), - Instruction(r'\F32X4.\VDEMOTE\K{\_f64x2\_zero}', r'\hex{FD}~~87', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-demote'), - Instruction(r'\F64X2.\VPROMOTE\K{\_low\_f32x4}', r'\hex{FD}~~105', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-promote'), + Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}', r'\hex{FD}~~252', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_s'), + Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~253', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), + Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~254', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), + Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~255', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), ] def ColumnWidth(n): diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index 0dbff6236..d4944436f 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -281,14 +281,6 @@ Instruction Binary Opcode Type :math:`\I32X4.\LOAD\K{\_splat}~\memarg` :math:`\hex{FD}~~9` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I64X2.\LOAD\K{\_splat}~\memarg` :math:`\hex{FD}~~10` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~11` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~88` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~89` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~90` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~91` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~92` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~93` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~94` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~95` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~12` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~13` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~14` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` @@ -342,12 +334,6 @@ Instruction Binary Opcode Type :math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~62` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~63` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~64` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VEQ` :math:`\hex{FD}~~192` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNE` :math:`\hex{FD}~~208` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~116` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~122` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~238` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~226` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VEQ` :math:`\hex{FD}~~65` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VNE` :math:`\hex{FD}~~66` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VLT` :math:`\hex{FD}~~67` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` @@ -366,13 +352,30 @@ Instruction Binary Opcode Type :math:`\V128.\VOR` :math:`\hex{FD}~~80` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\VXOR` :math:`\hex{FD}~~81` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\BITSELECT` :math:`\hex{FD}~~82` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~98` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~83` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~84` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~85` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~86` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~87` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~88` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~89` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~90` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~91` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~92` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~93` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~94` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~95` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VABS` :math:`\hex{FD}~~96` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VNEG` :math:`\hex{FD}~~97` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~98` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~99` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I8X16.\BITMASK` :math:`\hex{FD}~~100` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~101` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~102` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~103` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~104` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~105` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~106` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VSHL` :math:`\hex{FD}~~107` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~108` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~109` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` @@ -382,14 +385,21 @@ Instruction Binary Opcode Type :math:`\I8X16.\VSUB` :math:`\hex{FD}~~113` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~114` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~115` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~116` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~117` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~118` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~119` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~120` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~121` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~122` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~123` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~124` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~124` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~125` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~126` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~127` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I16X8.\VABS` :math:`\hex{FD}~~128` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VNEG` :math:`\hex{FD}~~129` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~130` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~131` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I16X8.\BITMASK` :math:`\hex{FD}~~132` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I16X8.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~133` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` @@ -407,25 +417,21 @@ Instruction Binary Opcode Type :math:`\I16X8.\VSUB` :math:`\hex{FD}~~145` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~146` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~147` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~148` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VMUL` :math:`\hex{FD}~~149` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~150` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~151` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~152` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~153` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~155` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~156` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~154` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~156` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~157` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~158` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~159` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~194` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~195` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\VABS` :math:`\hex{FD}~~160` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\VNEG` :math:`\hex{FD}~~161` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~163` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\BITMASK` :math:`\hex{FD}~~164` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~165` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~166` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~167` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~168` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~169` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` @@ -441,12 +447,13 @@ Instruction Binary Opcode Type :math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~184` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~185` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~186` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~187` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~188` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~189` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~190` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~191` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VABS` :math:`\hex{FD}~~162` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VABS` :math:`\hex{FD}~~192` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I64X2.\VNEG` :math:`\hex{FD}~~193` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~195` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I64X2.\BITMASK` :math:`\hex{FD}~~196` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~199` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~200` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` @@ -456,13 +463,18 @@ Instruction Binary Opcode Type :math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~204` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~205` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I64X2.\VADD` :math:`\hex{FD}~~206` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~207` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\I64X2.\VSUB` :math:`\hex{FD}~~209` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I64X2.\VMUL` :math:`\hex{FD}~~213` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~210` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~211` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~214` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~215` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEQ` :math:`\hex{FD}~~214` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNE` :math:`\hex{FD}~~215` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~216` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~217` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~218` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~219` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~220` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~221` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~222` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~223` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\F32X4.\VABS` :math:`\hex{FD}~~224` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VNEG` :math:`\hex{FD}~~225` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VSQRT` :math:`\hex{FD}~~227` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` @@ -482,17 +494,15 @@ Instruction Binary Opcode Type :math:`\F64X2.\VMUL` :math:`\hex{FD}~~242` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VDIV` :math:`\hex{FD}~~243` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VMIN` :math:`\hex{FD}~~244` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~245` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~246` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VMAX` :math:`\hex{FD}~~245` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~246` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~247` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~248` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~249` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\CONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~250` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\CONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~251` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~85` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~86` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~83` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~84` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~87` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~105` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~252` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~253` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~254` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~255` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` ================================================= ===================== ============================================= ============================================= ================================================================== diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index 14f1247fc..dd3429e19 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -433,17 +433,17 @@ SIMD loads and stores are followed by the encoding of their |memarg| immediate. \hex{FD}~~8{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{16\_splat}~m \\ &&|& \hex{FD}~~9{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{32\_splat}~m \\ &&|& \hex{FD}~~10{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{64\_splat}~m \\ &&|& - \hex{FD}~~252{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{\_zero}~m \\ &&|& - \hex{FD}~~253{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{\_zero}~m \\ &&|& + \hex{FD}~~92{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{32\_zero}~m \\ &&|& + \hex{FD}~~93{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD\K{64\_zero}~m \\ &&|& \hex{FD}~~11{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\STORE~m \\ &&|& - \hex{FD}~~88{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{8\_lane}~m~l \\ &&|& - \hex{FD}~~89{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{16\_lane}~m~l \\ &&|& - \hex{FD}~~90{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{32\_lane}~m~l \\ &&|& - \hex{FD}~~91{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{64\_lane}~m~l \\ &&|& - \hex{FD}~~92{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{8\_lane}~m~l \\ &&|& - \hex{FD}~~93{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{16\_lane}~m~l \\ &&|& - \hex{FD}~~94{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{32\_lane}~m~l \\ &&|& - \hex{FD}~~95{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{64\_lane}~m~l \\ + \hex{FD}~~84{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{8\_lane}~m~l \\ &&|& + \hex{FD}~~85{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{16\_lane}~m~l \\ &&|& + \hex{FD}~~86{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{32\_lane}~m~l \\ &&|& + \hex{FD}~~87{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\LOAD\K{64\_lane}~m~l \\ &&|& + \hex{FD}~~88{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{8\_lane}~m~l \\ &&|& + \hex{FD}~~89{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{16\_lane}~m~l \\ &&|& + \hex{FD}~~90{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{32\_lane}~m~l \\ &&|& + \hex{FD}~~91{:}\Bu32~~m{:}\Bmemarg~l{:}\Blaneidx &\Rightarrow& \V128.\STORE\K{64\_lane}~m~l \\ \end{array} The |VCONST| instruction is followed by 16 immediate bytes, which are converted into a |i128| in |littleendian| byte order: @@ -550,12 +550,12 @@ All other SIMD instructions are plain opcodes without any immediates. .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& - \hex{FD}~~192{:}\Bu32 &\Rightarrow& \I64X2.\VEQ \\ &&|& - \hex{FD}~~208{:}\Bu32 &\Rightarrow& \I64X2.\VNE \\ &&|& - \hex{FD}~~116{:}\Bu32 &\Rightarrow& \I64X2.\VLT\K{\_s} \\ &&|& - \hex{FD}~~122{:}\Bu32 &\Rightarrow& \I64X2.\VGT\K{\_s} \\ &&|& - \hex{FD}~~238{:}\Bu32 &\Rightarrow& \I64X2.\VLE\K{\_s} \\ &&|& - \hex{FD}~~226{:}\Bu32 &\Rightarrow& \I64X2.\VGE\K{\_s} \\ &&|& + \hex{FD}~~214{:}\Bu32 &\Rightarrow& \I64X2.\VEQ \\ &&|& + \hex{FD}~~215{:}\Bu32 &\Rightarrow& \I64X2.\VNE \\ &&|& + \hex{FD}~~216{:}\Bu32 &\Rightarrow& \I64X2.\VLT\K{\_s} \\ &&|& + \hex{FD}~~217{:}\Bu32 &\Rightarrow& \I64X2.\VGT\K{\_s} \\ &&|& + \hex{FD}~~218{:}\Bu32 &\Rightarrow& \I64X2.\VLE\K{\_s} \\ &&|& + \hex{FD}~~219{:}\Bu32 &\Rightarrow& \I64X2.\VGE\K{\_s} \\ &&|& \end{array} .. _binary-vfrelop: @@ -595,7 +595,7 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~80{:}\Bu32 &\Rightarrow& \V128.\VOR \\ &&|& \hex{FD}~~81{:}\Bu32 &\Rightarrow& \V128.\VXOR \\ &&|& \hex{FD}~~82{:}\Bu32 &\Rightarrow& \V128.\BITSELECT \\ &&|& - \hex{FD}~~98{:}\Bu32 &\Rightarrow& \V128.\ANYTRUE \\ &&|& + \hex{FD}~~83{:}\Bu32 &\Rightarrow& \V128.\ANYTRUE \\ \end{array} .. _binary-vitestop: @@ -610,6 +610,7 @@ All other SIMD instructions are plain opcodes without any immediates. \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& \hex{FD}~~96{:}\Bu32 &\Rightarrow& \I8X16.\VABS \\ &&|& \hex{FD}~~97{:}\Bu32 &\Rightarrow& \I8X16.\VNEG \\ &&|& + \hex{FD}~~98{:}\Bu32 &\Rightarrow& \I8X16.\VPOPCNT \\ &&|& \hex{FD}~~99{:}\Bu32 &\Rightarrow& \I8X16.\ALLTRUE \\ &&|& \hex{FD}~~100{:}\Bu32 &\Rightarrow& \I8X16.\BITMASK \\ &&|& \hex{FD}~~101{:}\Bu32 &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_s} \\ &&|& @@ -627,15 +628,17 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~119{:}\Bu32 &\Rightarrow& \I8X16.\VMIN\K{\_u} \\ &&|& \hex{FD}~~120{:}\Bu32 &\Rightarrow& \I8X16.\VMAX\K{\_s} \\ &&|& \hex{FD}~~121{:}\Bu32 &\Rightarrow& \I8X16.\VMAX\K{\_u} \\ &&|& - \hex{FD}~~123{:}\Bu32 &\Rightarrow& \I8X16.\AVGR\K{\_u} \\ &&|& - \hex{FD}~~124{:}\Bu32 &\Rightarrow& \I8X16.\VPOPCNT \\ + \hex{FD}~~123{:}\Bu32 &\Rightarrow& \I8X16.\AVGR\K{\_u} \\ \end{array} .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& + \hex{FD}~~124{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|& + \hex{FD}~~125{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\ &&|& \hex{FD}~~128{:}\Bu32 &\Rightarrow& \I16X8.\VABS \\ &&|& \hex{FD}~~129{:}\Bu32 &\Rightarrow& \I16X8.\VNEG \\ &&|& + \hex{FD}~~130{:}\Bu32 &\Rightarrow& \I16X8.\Q15MULRSAT\K{\_s} \\ &&|& \hex{FD}~~131{:}\Bu32 &\Rightarrow& \I16X8.\ALLTRUE \\ &&|& \hex{FD}~~132{:}\Bu32 &\Rightarrow& \I16X8.\BITMASK \\ &&|& \hex{FD}~~133{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s} \\ &&|& @@ -659,24 +662,21 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~152{:}\Bu32 &\Rightarrow& \I16X8.\VMAX\K{\_s} \\ &&|& \hex{FD}~~153{:}\Bu32 &\Rightarrow& \I16X8.\VMAX\K{\_u} \\ &&|& \hex{FD}~~155{:}\Bu32 &\Rightarrow& \I16X8.\AVGR\K{\_u} \\ &&|& - \hex{FD}~~154{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_s}\\ &&|& - \hex{FD}~~156{:}\Bu32 &\Rightarrow& \I16X8.\Q15MULRSAT\K{\_s} \\ &&|& + \hex{FD}~~156{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_s}\\ &&|& \hex{FD}~~157{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_s}\\ &&|& \hex{FD}~~158{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_u}\\ &&|& - \hex{FD}~~159{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ &&|& - \hex{FD}~~194{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|& - \hex{FD}~~195{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\ + \hex{FD}~~159{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ \end{array} .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& + \hex{FD}~~126{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|& + \hex{FD}~~127{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}\\ &&|& \hex{FD}~~160{:}\Bu32 &\Rightarrow& \I32X4.\VABS \\ &&|& \hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|& \hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|& \hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|& - \hex{FD}~~165{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|& - \hex{FD}~~166{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}\\ &&|& \hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s} \\ &&|& \hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s} \\ &&|& \hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u} \\ &&|& @@ -692,7 +692,7 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~184{:}\Bu32 &\Rightarrow& \I32X4.\VMAX\K{\_s} \\ &&|& \hex{FD}~~185{:}\Bu32 &\Rightarrow& \I32X4.\VMAX\K{\_u} \\ &&|& \hex{FD}~~186{:}\Bu32 &\Rightarrow& \I32X4.\DOT\K{\_i16x8\_s}\\ &&|& - \hex{FD}~~187{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_s}\\ &&|& + \hex{FD}~~188{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_s}\\ &&|& \hex{FD}~~189{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_high\_i16x8\_s}\\ &&|& \hex{FD}~~190{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_u}\\ &&|& \hex{FD}~~191{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_high\_i16x8\_u}\\ @@ -701,8 +701,9 @@ All other SIMD instructions are plain opcodes without any immediates. .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& - \hex{FD}~~162{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|& + \hex{FD}~~192{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|& \hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|& + \hex{FD}~~195{:}\Bu32 &\Rightarrow& \I64X2.\ALLTRUE \\ &&|& \hex{FD}~~196{:}\Bu32 &\Rightarrow& \I64X2.\BITMASK \\ &&|& \hex{FD}~~199{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_low\_i32x4\_s} \\ &&|& \hex{FD}~~200{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_high\_i32x4\_s} \\ &&|& @@ -712,13 +713,12 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~204{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_s} \\ &&|& \hex{FD}~~205{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_u} \\ &&|& \hex{FD}~~206{:}\Bu32 &\Rightarrow& \I64X2.\VADD \\ &&|& - \hex{FD}~~207{:}\Bu32 &\Rightarrow& \I64X2.\ALLTRUE \\ &&|& \hex{FD}~~209{:}\Bu32 &\Rightarrow& \I64X2.\VSUB \\ &&|& \hex{FD}~~213{:}\Bu32 &\Rightarrow& \I64X2.\VMUL \\ &&|& - \hex{FD}~~210{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_low\_i32x4\_s}\\ &&|& - \hex{FD}~~211{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_high\_i32x4\_s}\\ &&|& - \hex{FD}~~214{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_low\_i32x4\_u}\\ &&|& - \hex{FD}~~215{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_high\_i32x4\_u}\\ + \hex{FD}~~220{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_low\_i32x4\_s}\\ &&|& + \hex{FD}~~221{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_high\_i32x4\_s}\\ &&|& + \hex{FD}~~222{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_low\_i32x4\_u}\\ &&|& + \hex{FD}~~223{:}\Bu32 &\Rightarrow& \I64X2.\EXTMUL\K{\_high\_i32x4\_u}\\ \end{array} .. _binary-vfunop: @@ -727,6 +727,10 @@ All other SIMD instructions are plain opcodes without any immediates. .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& + \hex{FD}~~103{:}\Bu32 &\Rightarrow& \F32X4.\VCEIL \\ &&|& + \hex{FD}~~104{:}\Bu32 &\Rightarrow& \F32X4.\VFLOOR \\ &&|& + \hex{FD}~~105{:}\Bu32 &\Rightarrow& \F32X4.\VTRUNC \\ &&|& + \hex{FD}~~106{:}\Bu32 &\Rightarrow& \F32X4.\VNEAREST \\ &&|& \hex{FD}~~224{:}\Bu32 &\Rightarrow& \F32X4.\VABS \\ &&|& \hex{FD}~~225{:}\Bu32 &\Rightarrow& \F32X4.\VNEG \\ &&|& \hex{FD}~~227{:}\Bu32 &\Rightarrow& \F32X4.\VSQRT \\ &&|& @@ -743,6 +747,10 @@ All other SIMD instructions are plain opcodes without any immediates. .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|& + \hex{FD}~~116{:}\Bu32 &\Rightarrow& \F64X2.\VCEIL \\ &&|& + \hex{FD}~~117{:}\Bu32 &\Rightarrow& \F64X2.\VFLOOR \\ &&|& + \hex{FD}~~122{:}\Bu32 &\Rightarrow& \F64X2.\VTRUNC \\ &&|& + \hex{FD}~~148{:}\Bu32 &\Rightarrow& \F64X2.\VNEAREST \\ &&|& \hex{FD}~~236{:}\Bu32 &\Rightarrow& \F64X2.\VABS \\ &&|& \hex{FD}~~237{:}\Bu32 &\Rightarrow& \F64X2.\VNEG \\ &&|& \hex{FD}~~239{:}\Bu32 &\Rightarrow& \F64X2.\VSQRT \\ &&|& @@ -763,12 +771,12 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~249{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_u} \\ &&|& \hex{FD}~~250{:}\Bu32 &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_s} \\ &&|& \hex{FD}~~251{:}\Bu32 &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_u} \\ &&|& - \hex{FD}~~85{:}\Bu32 &\Rightarrow& \I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}\\ &&|& - \hex{FD}~~86{:}\Bu32 &\Rightarrow& \I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}\\ &&|& - \hex{FD}~~83{:}\Bu32 &\Rightarrow& \F64X2.\VCONVERT\K{\_low\_i32x4\_s}\\ &&|& - \hex{FD}~~84{:}\Bu32 &\Rightarrow& \F64X2.\VCONVERT\K{\_low\_i32x4\_u}\\ &&|& - \hex{FD}~~87{:}\Bu32 &\Rightarrow& \F32X4.\VDEMOTE\K{\_f64x2\_zero}\\ &&|& - \hex{FD}~~105{:}\Bu32 &\Rightarrow& \F64X2.\VPROMOTE\K{\_low\_f32x4}\\ + \hex{FD}~~252{:}\Bu32 &\Rightarrow& \I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}\\ &&|& + \hex{FD}~~253{:}\Bu32 &\Rightarrow& \I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}\\ &&|& + \hex{FD}~~254{:}\Bu32 &\Rightarrow& \F64X2.\VCONVERT\K{\_low\_i32x4\_s}\\ &&|& + \hex{FD}~~255{:}\Bu32 &\Rightarrow& \F64X2.\VCONVERT\K{\_low\_i32x4\_u}\\ &&|& + \hex{FD}~~94{:}\Bu32 &\Rightarrow& \F32X4.\VDEMOTE\K{\_f64x2\_zero}\\ &&|& + \hex{FD}~~95{:}\Bu32 &\Rightarrow& \F64X2.\VPROMOTE\K{\_low\_f32x4}\\ \end{array} diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 67391aacc..3c10a990f 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -377,7 +377,6 @@ For the other SIMD instructions, the use of two's complement for the signed inte .. _syntax-vbinop: .. _syntax-vcvtop: .. _syntax-vextmul: -.. _syntax-vcvtop: Conventions ........... diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 2c056bf1e..a5add3372 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -407,6 +407,10 @@ .. |VGE| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{ge}} .. |VABS| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{abs}} .. |VNEG| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{neg}} +.. |VCEIL| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{ceil}} +.. |VFLOOR| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{floor}} +.. |VTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{trunc}} +.. |VNEAREST| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{nearest}} .. |VPOPCNT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{popcnt}} .. |ANYTRUE| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{any\_true}} .. |ALLTRUE| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{all\_true}} @@ -427,7 +431,6 @@ .. |AVGR| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{avgr}} .. |DOT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{dot}} .. |EXTMUL| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{extmul}} -.. |VTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{trunc}} .. |VCONVERT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{convert}} .. |Q15MULRSAT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{q15mulr\_sat}} .. |EXTADDPAIRWISE| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{extadd\_pairwise}} diff --git a/interpreter/binary/decode.ml b/interpreter/binary/decode.ml index 9a7d2f5e6..4678ff4b7 100644 --- a/interpreter/binary/decode.ml +++ b/interpreter/binary/decode.ml @@ -304,70 +304,78 @@ let simd_prefix s = | 0x50l -> v128_or | 0x51l -> v128_xor | 0x52l -> v128_bitselect - | 0x53l -> f64x2_convert_low_i32x4_s - | 0x54l -> f64x2_convert_low_i32x4_u - | 0x55l -> i32x4_trunc_sat_f64x2_s_zero - | 0x56l -> i32x4_trunc_sat_f64x2_u_zero - | 0x57l -> f32x4_demote_f64x2_zero - | 0x58l -> + | 0x53l -> v128_any_true + | 0x54l -> let a, o = memop s in let lane = u8 s in v128_load8_lane a o lane - | 0x59l -> + | 0x55l -> let a, o = memop s in let lane = u8 s in v128_load16_lane a o lane - | 0x5al -> + | 0x56l -> let a, o = memop s in let lane = u8 s in v128_load32_lane a o lane - | 0x5bl -> + | 0x57l -> let a, o = memop s in let lane = u8 s in v128_load64_lane a o lane - | 0x5cl -> + | 0x58l -> let a, o = memop s in let lane = u8 s in v128_store8_lane a o lane - | 0x5dl -> + | 0x59l -> let a, o = memop s in let lane = u8 s in v128_store16_lane a o lane - | 0x5el -> + | 0x5al -> let a, o = memop s in let lane = u8 s in v128_store32_lane a o lane - | 0x5fl -> + | 0x5bl -> let a, o = memop s in let lane = u8 s in v128_store64_lane a o lane + | 0x5cl -> let a, o = memop s in v128_load32_zero a o + | 0x5dl -> let a, o = memop s in v128_load64_zero a o + | 0x5el -> f32x4_demote_f64x2_zero + | 0x5fl -> f64x2_promote_low_f32x4 | 0x60l -> i8x16_abs | 0x61l -> i8x16_neg - | 0x62l -> v128_any_true + | 0x62l -> i8x16_popcnt | 0x63l -> i8x16_all_true | 0x64l -> i8x16_bitmask + | 0x65l -> i8x16_narrow_i16x8_s + | 0x66l -> i8x16_narrow_i16x8_u + | 0x67l -> f32x4_ceil + | 0x68l -> f32x4_floor + | 0x69l -> f32x4_trunc + | 0x6al -> f32x4_nearest | 0x6bl -> i8x16_shl | 0x6cl -> i8x16_shr_s | 0x6dl -> i8x16_shr_u - | 0x65l -> i8x16_narrow_i16x8_s - | 0x66l -> i8x16_narrow_i16x8_u - | 0x69l -> f64x2_promote_low_f32x4 | 0x6el -> i8x16_add | 0x6fl -> i8x16_add_sat_s | 0x70l -> i8x16_add_sat_u | 0x71l -> i8x16_sub | 0x72l -> i8x16_sub_sat_s | 0x73l -> i8x16_sub_sat_u - | 0x74l -> i64x2_lt_s + | 0x74l -> f64x2_ceil + | 0x75l -> f64x2_floor | 0x76l -> i8x16_min_s | 0x77l -> i8x16_min_u | 0x78l -> i8x16_max_s | 0x79l -> i8x16_max_u - | 0x7al -> i64x2_gt_s + | 0x7al -> f64x2_trunc | 0x7bl -> i8x16_avgr_u - | 0x7cl -> i8x16_popcnt + | 0x7cl -> i16x8_extadd_pairwise_i8x16_s + | 0x7dl -> i16x8_extadd_pairwise_i8x16_u + | 0x7el -> i32x4_extadd_pairwise_i16x8_s + | 0x7fl -> i32x4_extadd_pairwise_i16x8_u | 0x80l -> i16x8_abs | 0x81l -> i16x8_neg + | 0x82l -> i16x8_q15mulr_sat_s | 0x83l -> i16x8_all_true | 0x84l -> i16x8_bitmask | 0x85l -> i16x8_narrow_i32x4_s @@ -385,24 +393,21 @@ let simd_prefix s = | 0x91l -> i16x8_sub | 0x92l -> i16x8_sub_sat_s | 0x93l -> i16x8_sub_sat_u + | 0x94l -> f64x2_nearest | 0x95l -> i16x8_mul | 0x96l -> i16x8_min_s | 0x97l -> i16x8_min_u | 0x98l -> i16x8_max_s | 0x99l -> i16x8_max_u - | 0x9al -> i16x8_extmul_low_i8x16_s | 0x9bl -> i16x8_avgr_u - | 0x9cl -> i16x8_q15mulr_sat_s + | 0x9cl -> i16x8_extmul_low_i8x16_s | 0x9dl -> i16x8_extmul_high_i8x16_s | 0x9el -> i16x8_extmul_low_i8x16_u | 0x9fl -> i16x8_extmul_high_i8x16_u | 0xa0l -> i32x4_abs | 0xa1l -> i32x4_neg - | 0xa2l -> i64x2_abs | 0xa3l -> i32x4_all_true | 0xa4l -> i32x4_bitmask - | 0xa5l -> i32x4_extadd_pairwise_i16x8_s - | 0xa6l -> i32x4_extadd_pairwise_i16x8_u | 0xa7l -> i32x4_extend_low_i16x8_s | 0xa8l -> i32x4_extend_high_i16x8_s | 0xa9l -> i32x4_extend_low_i16x8_u @@ -418,14 +423,13 @@ let simd_prefix s = | 0xb8l -> i32x4_max_s | 0xb9l -> i32x4_max_u | 0xbal -> i32x4_dot_i16x8_s - | 0xbbl -> i32x4_extmul_low_i16x8_s + | 0xbcl -> i32x4_extmul_low_i16x8_s | 0xbdl -> i32x4_extmul_high_i16x8_s | 0xbel -> i32x4_extmul_low_i16x8_u | 0xbfl -> i32x4_extmul_high_i16x8_u - | 0xc0l -> i64x2_eq + | 0xc0l -> i64x2_abs | 0xc1l -> i64x2_neg - | 0xc2l -> i16x8_extadd_pairwise_i8x16_s - | 0xc3l -> i16x8_extadd_pairwise_i8x16_u + | 0xc3l -> i64x2_all_true | 0xc4l -> i64x2_bitmask | 0xc7l -> i64x2_extend_low_i32x4_s | 0xc8l -> i64x2_extend_high_i32x4_s @@ -435,25 +439,20 @@ let simd_prefix s = | 0xccl -> i64x2_shr_s | 0xcdl -> i64x2_shr_u | 0xcel -> i64x2_add - | 0xcfl -> i64x2_all_true - | 0xd0l -> i64x2_ne | 0xd1l -> i64x2_sub - | 0xd2l -> i64x2_extmul_low_i32x4_s - | 0xd3l -> i64x2_extmul_high_i32x4_s - | 0xd6l -> i64x2_extmul_low_i32x4_u - | 0xd7l -> i64x2_extmul_high_i32x4_u | 0xd5l -> i64x2_mul - | 0xd8l -> f32x4_ceil - | 0xd9l -> f32x4_floor - | 0xdal -> f32x4_trunc - | 0xdbl -> f32x4_nearest - | 0xdcl -> f64x2_ceil - | 0xddl -> f64x2_floor - | 0xdel -> f64x2_trunc - | 0xdfl -> f64x2_nearest + | 0xd6l -> i64x2_eq + | 0xd7l -> i64x2_ne + | 0xd8l -> i64x2_lt_s + | 0xd9l -> i64x2_gt_s + | 0xdal -> i64x2_le_s + | 0xdbl -> i64x2_ge_s + | 0xdcl -> i64x2_extmul_low_i32x4_s + | 0xddl -> i64x2_extmul_high_i32x4_s + | 0xdel -> i64x2_extmul_low_i32x4_u + | 0xdfl -> i64x2_extmul_high_i32x4_u | 0xe0l -> f32x4_abs | 0xe1l -> f32x4_neg - | 0xe2l -> i64x2_ge_s | 0xe3l -> f32x4_sqrt | 0xe4l -> f32x4_add | 0xe5l -> f32x4_sub @@ -465,7 +464,6 @@ let simd_prefix s = | 0xebl -> f32x4_pmax | 0xecl -> f64x2_abs | 0xedl -> f64x2_neg - | 0xeel -> i64x2_le_s | 0xefl -> f64x2_sqrt | 0xf0l -> f64x2_add | 0xf1l -> f64x2_sub @@ -479,8 +477,10 @@ let simd_prefix s = | 0xf9l -> i32x4_trunc_sat_f32x4_u | 0xfal -> f32x4_convert_i32x4_s | 0xfbl -> f32x4_convert_i32x4_u - | 0xfcl -> let a, o = memop s in v128_load32_zero a o - | 0xfdl -> let a, o = memop s in v128_load64_zero a o + | 0xfcl -> i32x4_trunc_sat_f64x2_s_zero + | 0xfdl -> i32x4_trunc_sat_f64x2_u_zero + | 0xfel -> f64x2_convert_low_i32x4_s + | 0xffl -> f64x2_convert_low_i32x4_u | n -> illegal s pos (I32.to_int_u n) let rec instr s = diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml index 926ccc0c1..cc0284e04 100644 --- a/interpreter/binary/encode.ml +++ b/interpreter/binary/encode.ml @@ -221,18 +221,18 @@ let encode m = | SimdLoad ({ty= V128Type; sz = Some (Pack64, PackSplat); _} as mo) -> simd_op 0x0al; memop mo | SimdLoad ({ty= V128Type; sz = Some (Pack32, PackZero); _} as mo) -> - simd_op 0xfcl; memop mo + simd_op 0x5cl; memop mo | SimdLoad ({ty= V128Type; sz = Some (Pack64, PackZero); _} as mo) -> - simd_op 0xfdl; memop mo + simd_op 0x5dl; memop mo | SimdLoadLane ({ty = V128Type; sz = Some Pack8; _} as mo, i) -> - simd_op 0x58l; memop mo; u8 i; + simd_op 0x54l; memop mo; u8 i; | SimdLoadLane ({ty = V128Type; sz = Some Pack16; _} as mo, i) -> - simd_op 0x59l; memop mo; u8 i; + simd_op 0x55l; memop mo; u8 i; | SimdLoadLane ({ty = V128Type; sz = Some Pack32; _} as mo, i) -> - simd_op 0x5al; memop mo; u8 i; + simd_op 0x56l; memop mo; u8 i; | SimdLoadLane ({ty = V128Type; sz = Some Pack64; _} as mo, i) -> - simd_op 0x5bl; memop mo; u8 i; + simd_op 0x57l; memop mo; u8 i; | Store ({ty = I32Type; sz = None; _} as mo) -> op 0x36; memop mo | Store ({ty = I64Type; sz = None; _} as mo) -> op 0x37; memop mo @@ -249,13 +249,13 @@ let encode m = | SimdStore ({ty = V128Type; _} as mo) -> simd_op 0x0bl; memop mo | SimdStoreLane ({ty = V128Type; sz = Some Pack8; _} as mo, i) -> - simd_op 0x5cl; memop mo; u8 i; + simd_op 0x58l; memop mo; u8 i; | SimdStoreLane ({ty = V128Type; sz = Some Pack16; _} as mo, i) -> - simd_op 0x5dl; memop mo; u8 i; + simd_op 0x59l; memop mo; u8 i; | SimdStoreLane ({ty = V128Type; sz = Some Pack32; _} as mo, i) -> - simd_op 0x5el; memop mo; u8 i; + simd_op 0x5al; memop mo; u8 i; | SimdStoreLane ({ty = V128Type; sz = Some Pack64; _} as mo, i) -> - simd_op 0x5fl; memop mo; u8 i; + simd_op 0x5bl; memop mo; u8 i; | MemorySize -> op 0x3f; u8 0x00 | MemoryGrow -> op 0x40; u8 0x00 @@ -270,11 +270,11 @@ let encode m = | Test (I64 I64Op.Eqz) -> op 0x50 | Test (F32 _) -> assert false | Test (F64 _) -> assert false - | Test (V128 V128Op.(V128 AnyTrue)) -> simd_op 0x62l + | Test (V128 V128Op.(V128 AnyTrue)) -> simd_op 0x53l | Test (V128 V128Op.(I8x16 AllTrue)) -> simd_op 0x63l | Test (V128 V128Op.(I16x8 AllTrue)) -> simd_op 0x83l | Test (V128 V128Op.(I32x4 AllTrue)) -> simd_op 0xa3l - | Test (V128 V128Op.(I64x2 AllTrue)) -> simd_op 0xcfl + | Test (V128 V128Op.(I64x2 AllTrue)) -> simd_op 0xc3l | Test (V128 _) -> assert false | Compare (I32 I32Op.Eq) -> op 0x46 @@ -347,37 +347,37 @@ let encode m = | Unary (V128 V128Op.(V128 Not)) -> simd_op 0x4dl | Unary (V128 V128Op.(I8x16 Abs)) -> simd_op 0x60l | Unary (V128 V128Op.(I8x16 Neg)) -> simd_op 0x61l - | Unary (V128 V128Op.(I8x16 Popcnt)) -> simd_op 0x7cl + | Unary (V128 V128Op.(I8x16 Popcnt)) -> simd_op 0x62l | Unary (V128 V128Op.(I16x8 Abs)) -> simd_op 0x80l | Unary (V128 V128Op.(I16x8 Neg)) -> simd_op 0x81l | Unary (V128 V128Op.(I16x8 ExtendLowS)) -> simd_op 0x87l | Unary (V128 V128Op.(I16x8 ExtendHighS)) -> simd_op 0x88l | Unary (V128 V128Op.(I16x8 ExtendLowU)) -> simd_op 0x89l | Unary (V128 V128Op.(I16x8 ExtendHighU)) -> simd_op 0x8al - | Unary (V128 V128Op.(I16x8 ExtAddPairwiseS)) -> simd_op 0xc2l - | Unary (V128 V128Op.(I16x8 ExtAddPairwiseU)) -> simd_op 0xc3l + | Unary (V128 V128Op.(I16x8 ExtAddPairwiseS)) -> simd_op 0x7cl + | Unary (V128 V128Op.(I16x8 ExtAddPairwiseU)) -> simd_op 0x7dl | Unary (V128 V128Op.(I32x4 Abs)) -> simd_op 0xa0l | Unary (V128 V128Op.(I32x4 Neg)) -> simd_op 0xa1l | Unary (V128 V128Op.(I32x4 ExtendLowS)) -> simd_op 0xa7l | Unary (V128 V128Op.(I32x4 ExtendHighS)) -> simd_op 0xa8l | Unary (V128 V128Op.(I32x4 ExtendLowU)) -> simd_op 0xa9l | Unary (V128 V128Op.(I32x4 ExtendHighU)) -> simd_op 0xaal - | Unary (V128 V128Op.(I32x4 ExtAddPairwiseS)) -> simd_op 0xa5l - | Unary (V128 V128Op.(I32x4 ExtAddPairwiseU)) -> simd_op 0xa6l - | Unary (V128 V128Op.(I64x2 Abs)) -> simd_op 0xa2l + | Unary (V128 V128Op.(I32x4 ExtAddPairwiseS)) -> simd_op 0x7el + | Unary (V128 V128Op.(I32x4 ExtAddPairwiseU)) -> simd_op 0x7fl + | Unary (V128 V128Op.(I64x2 Abs)) -> simd_op 0xc0l | Unary (V128 V128Op.(I64x2 Neg)) -> simd_op 0xc1l | Unary (V128 V128Op.(I64x2 ExtendLowS)) -> simd_op 0xc7l | Unary (V128 V128Op.(I64x2 ExtendHighS)) -> simd_op 0xc8l | Unary (V128 V128Op.(I64x2 ExtendLowU)) -> simd_op 0xc9l | Unary (V128 V128Op.(I64x2 ExtendHighU)) -> simd_op 0xcal - | Unary (V128 V128Op.(F32x4 Ceil)) -> simd_op 0xd8l - | Unary (V128 V128Op.(F32x4 Floor)) -> simd_op 0xd9l - | Unary (V128 V128Op.(F32x4 Trunc)) -> simd_op 0xdal - | Unary (V128 V128Op.(F32x4 Nearest)) -> simd_op 0xdbl - | Unary (V128 V128Op.(F64x2 Ceil)) -> simd_op 0xdcl - | Unary (V128 V128Op.(F64x2 Floor)) -> simd_op 0xddl - | Unary (V128 V128Op.(F64x2 Trunc)) -> simd_op 0xdel - | Unary (V128 V128Op.(F64x2 Nearest)) -> simd_op 0xdfl + | Unary (V128 V128Op.(F32x4 Ceil)) -> simd_op 0x67l + | Unary (V128 V128Op.(F32x4 Floor)) -> simd_op 0x68l + | Unary (V128 V128Op.(F32x4 Trunc)) -> simd_op 0x69l + | Unary (V128 V128Op.(F32x4 Nearest)) -> simd_op 0x6al + | Unary (V128 V128Op.(F64x2 Ceil)) -> simd_op 0x74l + | Unary (V128 V128Op.(F64x2 Floor)) -> simd_op 0x75l + | Unary (V128 V128Op.(F64x2 Trunc)) -> simd_op 0x7al + | Unary (V128 V128Op.(F64x2 Nearest)) -> simd_op 0x94l | Unary (V128 V128Op.(F32x4 Abs)) -> simd_op 0xe0l | Unary (V128 V128Op.(F32x4 Neg)) -> simd_op 0xe1l | Unary (V128 V128Op.(F32x4 Sqrt)) -> simd_op 0xe3l @@ -386,14 +386,14 @@ let encode m = | Unary (V128 V128Op.(F64x2 Sqrt)) -> simd_op 0xefl | Unary (V128 V128Op.(I32x4 TruncSatF32x4S)) -> simd_op 0xf8l | Unary (V128 V128Op.(I32x4 TruncSatF32x4U)) -> simd_op 0xf9l - | Unary (V128 V128Op.(I32x4 TruncSatF64x2SZero)) -> simd_op 0x55l - | Unary (V128 V128Op.(I32x4 TruncSatF64x2UZero)) -> simd_op 0x56l + | Unary (V128 V128Op.(I32x4 TruncSatF64x2SZero)) -> simd_op 0xfcl + | Unary (V128 V128Op.(I32x4 TruncSatF64x2UZero)) -> simd_op 0xfdl | Unary (V128 V128Op.(F32x4 ConvertI32x4S)) -> simd_op 0xfal | Unary (V128 V128Op.(F32x4 ConvertI32x4U)) -> simd_op 0xfbl - | Unary (V128 V128Op.(F32x4 DemoteF64x2Zero)) -> simd_op 0x57l - | Unary (V128 V128Op.(F64x2 PromoteLowF32x4)) -> simd_op 0x69l - | Unary (V128 V128Op.(F64x2 ConvertI32x4S)) -> simd_op 0x53l - | Unary (V128 V128Op.(F64x2 ConvertI32x4U)) -> simd_op 0x54l + | Unary (V128 V128Op.(F32x4 DemoteF64x2Zero)) -> simd_op 0x5el + | Unary (V128 V128Op.(F64x2 PromoteLowF32x4)) -> simd_op 0x5fl + | Unary (V128 V128Op.(F64x2 ConvertI32x4S)) -> simd_op 0xfel + | Unary (V128 V128Op.(F64x2 ConvertI32x4U)) -> simd_op 0xffl | Unary (V128 _) -> failwith "unimplemented V128 Unary op" | Binary (I32 I32Op.Add) -> op 0x6a @@ -493,11 +493,11 @@ let encode m = | Binary (V128 V128Op.(I16x8 MaxS)) -> simd_op 0x98l | Binary (V128 V128Op.(I16x8 MaxU)) -> simd_op 0x99l | Binary (V128 V128Op.(I16x8 AvgrU)) -> simd_op 0x9bl - | Binary (V128 V128Op.(I16x8 ExtMulLowS)) -> simd_op 0x9al + | Binary (V128 V128Op.(I16x8 ExtMulLowS)) -> simd_op 0x9cl | Binary (V128 V128Op.(I16x8 ExtMulHighS)) -> simd_op 0x9dl | Binary (V128 V128Op.(I16x8 ExtMulLowU)) -> simd_op 0x9el | Binary (V128 V128Op.(I16x8 ExtMulHighU)) -> simd_op 0x9fl - | Binary (V128 V128Op.(I16x8 Q15MulRSatS)) -> simd_op 0x9cl + | Binary (V128 V128Op.(I16x8 Q15MulRSatS)) -> simd_op 0x82l | Binary (V128 V128Op.(I32x4 Add)) -> simd_op 0xael | Binary (V128 V128Op.(I32x4 Sub)) -> simd_op 0xb1l | Binary (V128 V128Op.(I32x4 MinS)) -> simd_op 0xb6l @@ -516,23 +516,23 @@ let encode m = | Binary (V128 V128Op.(I32x4 LeU)) -> simd_op 0x3el | Binary (V128 V128Op.(I32x4 GeS)) -> simd_op 0x3fl | Binary (V128 V128Op.(I32x4 GeU)) -> simd_op 0x40l - | Binary (V128 V128Op.(I32x4 ExtMulLowS)) -> simd_op 0xbbl + | Binary (V128 V128Op.(I32x4 ExtMulLowS)) -> simd_op 0xbcl | Binary (V128 V128Op.(I32x4 ExtMulHighS)) -> simd_op 0xbdl | Binary (V128 V128Op.(I32x4 ExtMulLowU)) -> simd_op 0xbel | Binary (V128 V128Op.(I32x4 ExtMulHighU)) -> simd_op 0xbfl | Binary (V128 V128Op.(I64x2 Add)) -> simd_op 0xcel | Binary (V128 V128Op.(I64x2 Sub)) -> simd_op 0xd1l | Binary (V128 V128Op.(I64x2 Mul)) -> simd_op 0xd5l - | Binary (V128 V128Op.(I64x2 Eq)) -> simd_op 0xc0l - | Binary (V128 V128Op.(I64x2 Ne)) -> simd_op 0xd0l - | Binary (V128 V128Op.(I64x2 LtS)) -> simd_op 0x74l - | Binary (V128 V128Op.(I64x2 GtS)) -> simd_op 0x7al - | Binary (V128 V128Op.(I64x2 LeS)) -> simd_op 0xeel - | Binary (V128 V128Op.(I64x2 GeS)) -> simd_op 0xe2l - | Binary (V128 V128Op.(I64x2 ExtMulLowS)) -> simd_op 0xd2l - | Binary (V128 V128Op.(I64x2 ExtMulHighS)) -> simd_op 0xd3l - | Binary (V128 V128Op.(I64x2 ExtMulLowU)) -> simd_op 0xd6l - | Binary (V128 V128Op.(I64x2 ExtMulHighU)) -> simd_op 0xd7l + | Binary (V128 V128Op.(I64x2 Eq)) -> simd_op 0xd6l + | Binary (V128 V128Op.(I64x2 Ne)) -> simd_op 0xd7l + | Binary (V128 V128Op.(I64x2 LtS)) -> simd_op 0xd8l + | Binary (V128 V128Op.(I64x2 GtS)) -> simd_op 0xd9l + | Binary (V128 V128Op.(I64x2 LeS)) -> simd_op 0xdal + | Binary (V128 V128Op.(I64x2 GeS)) -> simd_op 0xdbl + | Binary (V128 V128Op.(I64x2 ExtMulLowS)) -> simd_op 0xdcl + | Binary (V128 V128Op.(I64x2 ExtMulHighS)) -> simd_op 0xddl + | Binary (V128 V128Op.(I64x2 ExtMulLowU)) -> simd_op 0xdel + | Binary (V128 V128Op.(I64x2 ExtMulHighU)) -> simd_op 0xdfl | Binary (V128 V128Op.(F32x4 Eq)) -> simd_op 0x41l | Binary (V128 V128Op.(F32x4 Ne)) -> simd_op 0x42l | Binary (V128 V128Op.(F32x4 Lt)) -> simd_op 0x43l