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GL backend hangs, wayland related? #517

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sl1pkn07 opened this issue Feb 3, 2022 · 6 comments
Open

GL backend hangs, wayland related? #517

sl1pkn07 opened this issue Feb 3, 2022 · 6 comments

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@sl1pkn07
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sl1pkn07 commented Feb 3, 2022 •
edited
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What version of hwloc are you using?

try to build 2.7.0 from tarball

Which operating system and hardware are you running on?

Linux sL1pKn07 5.15.13-arch1-1 #1 SMP PREEMPT Wed, 05 Jan 2022 16:20:59 +0000 x86_64 GNU/Linux

Dual Xeon E5-2650-V4 in Asus Z10PE-D8 with 128Gb DDR4 ram SKHynx HMA42GR7AFR4N-UH (8x16Gb)

Details of the problem

  • What happened?
    The unnittest paused in the test-fake-plugin test
  • How did you start your process?
    run make check after build
    • How did it fail?
      simply the proccess is freeze
    • Crash?
      No
    • Unexpected result?
      Yes

Additional information

the unnittest stops in this line of the script

hwloc/utils/hwloc/test-fake-plugin.sh.in

Line 40 in b88192a

test `$hcalc -N pu root` = 1

simply freeze, no crash. seeems wait to "do things" but never comes

the contains of the file test-fake-plugin.sh.log is:

Checking that the tweak phase restricts to a single PU and single NUMA

└───╼  ps -A |grep hwloc-calc
2614288 pts/6    00:00:00 lt-hwloc-calc

Screenshot_20220203_220923

running the command by hand works

┌─┤[$]|[sl1pkn07]|[sL1pKn07]|[~]|
└───╼  /tmp/makepkg/sl1-hwloc/src/build/utils/hwloc/.libs/lt-hwloc-calc -N pu root
48

the next command in the script also works

┌─┤[$]|[sl1pkn07]|[sL1pKn07]|[~]|
└───╼  /tmp/makepkg/sl1-hwloc/src/build/utils/hwloc/.libs/lt-hwloc-calc -N numa root
2

hwloc 2.5.0 (from tarball) also fails. idk what happen

greetings
@bgoglin
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bgoglin commented Feb 4, 2022

Hello, can you reconfigure with --enable-debug, go into the build directory and do

make
make check -C hwloc
export HWLOC_PLUGINS_PATH=hwloc/.libs
export HWLOC_COMPONENTS_VERBOSE=1
HWLOC_DEBUG_FAKE_COMPONENT_TWEAK=1
utils/lstopo/lstopo

and post the entire stdout of lstopo? We will see where it actually hangs inside hwloc. Thanks.

@sl1pkn07
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Author

sl1pkn07 commented Feb 4, 2022 •
edited
Loading

Hi

now the output of the test-fale-plugin.sh.log is

Checking that the tweak phase restricts to a single PU and single NUMA
hwloc verbose debug enabled, may be disabled with HWLOC_DEBUG_VERBOSE=0 in the environment.
CPU phase discovery...
CPU phase discovery in component linux...
hwloc verbose debug enabled, may be disabled with HWLOC_DEBUG_VERBOSE=0 in the environment.
Found sysfs cpu files under /sys/bus/cpu/devices with new topology filenames
Found sysfs node files under /sys/bus/node/devices


 * Topology extraction from /proc/cpuinfo *

processor 0
processor 1
processor 2
processor 3
processor 4
processor 5
processor 6
processor 7
processor 8
processor 9
processor 10
processor 11
processor 12
processor 13
processor 14
processor 15
processor 16
processor 17
processor 18
processor 19
processor 20
processor 21
processor 22
processor 23
processor 24
processor 25
processor 26
processor 27
processor 28
processor 29
processor 30
processor 31
processor 32
processor 33
processor 34
processor 35
processor 36
processor 37
processor 38
processor 39
processor 40
processor 41
processor 42
processor 43
processor 44
processor 45
processor 46
processor 47
Found cgroup2 mount point on /sys/fs/cgroup
Looking for `cpuset' controller in list `cpuset cpu io memory hugetlb pids rdma misc'
Found cgroup2/cpuset mount point on /sys/fs/cgroup
Found cgroup name `/'
Trying to read cgroup2 file </sys/fs/cgroup//cpuset.cpus.effective>
cpuset includes 0x0000ffff,0xffffffff
Trying to read cgroup2 file </sys/fs/cgroup//cpuset.mems.effective>
cpuset includes 0x00000003


 * Topology extraction from /sys/bus/cpu/devices *

online CPUs 0x0000ffff,0xffffffff
found 48 cpu topologies, cpuset 0x0000ffff,0xffffffff
os core 0 has cpuset 0x01000001
os package 0 has cpuset 0x0000000f,0xff000fff
thread 0 has cpuset 0x00000001
cache depth 1 has cpuset 0x01000001
cache depth 1 has cpuset 0x01000001
cache depth 2 has cpuset 0x01000001
cache depth 3 has cpuset 0x0000000f,0xff000fff
os core 1 has cpuset 0x02000002
thread 1 has cpuset 0x00000002
cache depth 1 has cpuset 0x02000002
cache depth 1 has cpuset 0x02000002
cache depth 2 has cpuset 0x02000002
os core 2 has cpuset 0x04000004
thread 2 has cpuset 0x00000004
cache depth 1 has cpuset 0x04000004
cache depth 1 has cpuset 0x04000004
cache depth 2 has cpuset 0x04000004
os core 3 has cpuset 0x08000008
thread 3 has cpuset 0x00000008
cache depth 1 has cpuset 0x08000008
cache depth 1 has cpuset 0x08000008
cache depth 2 has cpuset 0x08000008
os core 4 has cpuset 0x10000010
thread 4 has cpuset 0x00000010
cache depth 1 has cpuset 0x10000010
cache depth 1 has cpuset 0x10000010
cache depth 2 has cpuset 0x10000010
os core 5 has cpuset 0x20000020
thread 5 has cpuset 0x00000020
cache depth 1 has cpuset 0x20000020
cache depth 1 has cpuset 0x20000020
cache depth 2 has cpuset 0x20000020
os core 8 has cpuset 0x40000040
thread 6 has cpuset 0x00000040
cache depth 1 has cpuset 0x40000040
cache depth 1 has cpuset 0x40000040
cache depth 2 has cpuset 0x40000040
os core 9 has cpuset 0x80000080
thread 7 has cpuset 0x00000080
cache depth 1 has cpuset 0x80000080
cache depth 1 has cpuset 0x80000080
cache depth 2 has cpuset 0x80000080
os core 10 has cpuset 0x00000001,0x00000100
thread 8 has cpuset 0x00000100
cache depth 1 has cpuset 0x00000001,0x00000100
cache depth 1 has cpuset 0x00000001,0x00000100
cache depth 2 has cpuset 0x00000001,0x00000100
os core 11 has cpuset 0x00000002,0x00000200
thread 9 has cpuset 0x00000200
cache depth 1 has cpuset 0x00000002,0x00000200
cache depth 1 has cpuset 0x00000002,0x00000200
cache depth 2 has cpuset 0x00000002,0x00000200
os core 12 has cpuset 0x00000004,0x00000400
thread 10 has cpuset 0x00000400
cache depth 1 has cpuset 0x00000004,0x00000400
cache depth 1 has cpuset 0x00000004,0x00000400
cache depth 2 has cpuset 0x00000004,0x00000400
os core 13 has cpuset 0x00000008,0x00000800
thread 11 has cpuset 0x00000800
cache depth 1 has cpuset 0x00000008,0x00000800
cache depth 1 has cpuset 0x00000008,0x00000800
cache depth 2 has cpuset 0x00000008,0x00000800
os core 0 has cpuset 0x00000010,0x00001000
os package 1 has cpuset 0x0000fff0,0x00fff000
thread 12 has cpuset 0x00001000
cache depth 1 has cpuset 0x00000010,0x00001000
cache depth 1 has cpuset 0x00000010,0x00001000
cache depth 2 has cpuset 0x00000010,0x00001000
cache depth 3 has cpuset 0x0000fff0,0x00fff000
os core 1 has cpuset 0x00000020,0x00002000
thread 13 has cpuset 0x00002000
cache depth 1 has cpuset 0x00000020,0x00002000
cache depth 1 has cpuset 0x00000020,0x00002000
cache depth 2 has cpuset 0x00000020,0x00002000
os core 2 has cpuset 0x00000040,0x00004000
thread 14 has cpuset 0x00004000
cache depth 1 has cpuset 0x00000040,0x00004000
cache depth 1 has cpuset 0x00000040,0x00004000
cache depth 2 has cpuset 0x00000040,0x00004000
os core 3 has cpuset 0x00000080,0x00008000
thread 15 has cpuset 0x00008000
cache depth 1 has cpuset 0x00000080,0x00008000
cache depth 1 has cpuset 0x00000080,0x00008000
cache depth 2 has cpuset 0x00000080,0x00008000
os core 4 has cpuset 0x00000100,0x00010000
thread 16 has cpuset 0x00010000
cache depth 1 has cpuset 0x00000100,0x00010000
cache depth 1 has cpuset 0x00000100,0x00010000
cache depth 2 has cpuset 0x00000100,0x00010000
os core 5 has cpuset 0x00000200,0x00020000
thread 17 has cpuset 0x00020000
cache depth 1 has cpuset 0x00000200,0x00020000
cache depth 1 has cpuset 0x00000200,0x00020000
cache depth 2 has cpuset 0x00000200,0x00020000
os core 8 has cpuset 0x00000400,0x00040000
thread 18 has cpuset 0x00040000
cache depth 1 has cpuset 0x00000400,0x00040000
cache depth 1 has cpuset 0x00000400,0x00040000
cache depth 2 has cpuset 0x00000400,0x00040000
os core 9 has cpuset 0x00000800,0x00080000
thread 19 has cpuset 0x00080000
cache depth 1 has cpuset 0x00000800,0x00080000
cache depth 1 has cpuset 0x00000800,0x00080000
cache depth 2 has cpuset 0x00000800,0x00080000
os core 10 has cpuset 0x00001000,0x00100000
thread 20 has cpuset 0x00100000
cache depth 1 has cpuset 0x00001000,0x00100000
cache depth 1 has cpuset 0x00001000,0x00100000
cache depth 2 has cpuset 0x00001000,0x00100000
os core 11 has cpuset 0x00002000,0x00200000
thread 21 has cpuset 0x00200000
cache depth 1 has cpuset 0x00002000,0x00200000
cache depth 1 has cpuset 0x00002000,0x00200000
cache depth 2 has cpuset 0x00002000,0x00200000
os core 12 has cpuset 0x00004000,0x00400000
thread 22 has cpuset 0x00400000
cache depth 1 has cpuset 0x00004000,0x00400000
cache depth 1 has cpuset 0x00004000,0x00400000
cache depth 2 has cpuset 0x00004000,0x00400000
os core 13 has cpuset 0x00008000,0x00800000
thread 23 has cpuset 0x00800000
cache depth 1 has cpuset 0x00008000,0x00800000
cache depth 1 has cpuset 0x00008000,0x00800000
cache depth 2 has cpuset 0x00008000,0x00800000
thread 24 has cpuset 0x01000000
thread 25 has cpuset 0x02000000
thread 26 has cpuset 0x04000000
thread 27 has cpuset 0x08000000
thread 28 has cpuset 0x10000000
thread 29 has cpuset 0x20000000
thread 30 has cpuset 0x40000000
thread 31 has cpuset 0x80000000
thread 32 has cpuset 0x00000001,0x0
thread 33 has cpuset 0x00000002,0x0
thread 34 has cpuset 0x00000004,0x0
thread 35 has cpuset 0x00000008,0x0
thread 36 has cpuset 0x00000010,0x0
thread 37 has cpuset 0x00000020,0x0
thread 38 has cpuset 0x00000040,0x0
thread 39 has cpuset 0x00000080,0x0
thread 40 has cpuset 0x00000100,0x0
thread 41 has cpuset 0x00000200,0x0
thread 42 has cpuset 0x00000400,0x0
thread 43 has cpuset 0x00000800,0x0
thread 44 has cpuset 0x00001000,0x0
thread 45 has cpuset 0x00002000,0x0
thread 46 has cpuset 0x00004000,0x0
thread 47 has cpuset 0x00008000,0x0


 * Topology extraction from /sys/bus/node/devices *

possible NUMA nodes 0x00000003
NUMA indexes:  0 1
os node 0 has cpuset 0x0000000f,0xff000fff
os node 1 has cpuset 0x0000fff0,0x00fff000
found DMIProductName 'Z10PE-D8 WS'
found DMIProductVersion 'System Version'
found DMIBoardVendor 'ASUSTeK COMPUTER INC.'
found DMIBoardName 'Z10PE-D8 WS'
found DMIBoardVersion 'Rev 1.xx'
found DMIBoardAssetTag 'To be filled by O.E.M.'
found DMIChassisVendor 'To Be Filled By O.E.M.'
found DMIChassisType '3'
found DMIChassisVersion 'To Be Filled By O.E.M.'
found DMIChassisAssetTag 'To Be Filled By O.E.M.'
found DMIBIOSVendor 'American Megatrends Inc.'
found DMIBIOSVersion '3703'
found DMIBIOSDate '04/13/2018'
found DMISysVendor 'ASUSTeK COMPUTER INC.'
CPU phase discovery in component x86...
--- Package level has number 1

--- L3Cache level has number 2

--- L2Cache level has number 3

--- L1Cache level has number 4

--- L1iCache level has number 5

--- Core level has number 6

--- PU level has number 7

hwloc verbose debug enabled, may be disabled with HWLOC_DEBUG_VERBOSE=0 in the environment.
highest cpuid 14, cpuid type 0
highest extended cpuid 80000008
possible CPUs are 0x0000ffff,0xffffffff
binding to CPU0
APIC ID 0x00 legacy_max_log_proc 32
phys 0 legacy thread 0
thus 2 threads
this is thread 0 of core 0
x2APIC 00000000 0: nextshift 1 num  2 type 1 id  0
x2APIC 00000000 1: nextshift 5 num 24 type 2 id  0
x2APIC remainder: 0
this is thread 0 of core 0
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU1
APIC ID 0x02 legacy_max_log_proc 32
phys 0 legacy thread 2
thus 2 threads
this is thread 0 of core 1
x2APIC 00000002 0: nextshift 1 num  2 type 1 id  2
x2APIC 00000002 1: nextshift 5 num 24 type 2 id  1
x2APIC remainder: 0
this is thread 2 of core 1
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU2
APIC ID 0x04 legacy_max_log_proc 32
phys 0 legacy thread 4
thus 2 threads
this is thread 0 of core 2
x2APIC 00000004 0: nextshift 1 num  2 type 1 id  4
x2APIC 00000004 1: nextshift 5 num 24 type 2 id  2
x2APIC remainder: 0
this is thread 4 of core 2
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU3
APIC ID 0x06 legacy_max_log_proc 32
phys 0 legacy thread 6
thus 2 threads
this is thread 0 of core 3
x2APIC 00000006 0: nextshift 1 num  2 type 1 id  6
x2APIC 00000006 1: nextshift 5 num 24 type 2 id  3
x2APIC remainder: 0
this is thread 6 of core 3
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU4
APIC ID 0x08 legacy_max_log_proc 32
phys 0 legacy thread 8
thus 2 threads
this is thread 0 of core 4
x2APIC 00000008 0: nextshift 1 num  2 type 1 id  8
x2APIC 00000008 1: nextshift 5 num 24 type 2 id  4
x2APIC remainder: 0
this is thread 8 of core 4
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU5
APIC ID 0x0a legacy_max_log_proc 32
phys 0 legacy thread 10
thus 2 threads
this is thread 0 of core 5
x2APIC 0000000a 0: nextshift 1 num  2 type 1 id 10
x2APIC 0000000a 1: nextshift 5 num 24 type 2 id  5
x2APIC remainder: 0
this is thread 10 of core 5
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU6
APIC ID 0x10 legacy_max_log_proc 32
phys 0 legacy thread 16
thus 2 threads
this is thread 0 of core 8
x2APIC 00000010 0: nextshift 1 num  2 type 1 id 16
x2APIC 00000010 1: nextshift 5 num 24 type 2 id  8
x2APIC remainder: 0
this is thread 16 of core 8
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU7
APIC ID 0x12 legacy_max_log_proc 32
phys 0 legacy thread 18
thus 2 threads
this is thread 0 of core 9
x2APIC 00000012 0: nextshift 1 num  2 type 1 id 18
x2APIC 00000012 1: nextshift 5 num 24 type 2 id  9
x2APIC remainder: 0
this is thread 18 of core 9
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU8
APIC ID 0x14 legacy_max_log_proc 32
phys 0 legacy thread 20
thus 2 threads
this is thread 0 of core 10
x2APIC 00000014 0: nextshift 1 num  2 type 1 id 20
x2APIC 00000014 1: nextshift 5 num 24 type 2 id 10
x2APIC remainder: 0
this is thread 20 of core 10
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU9
APIC ID 0x16 legacy_max_log_proc 32
phys 0 legacy thread 22
thus 2 threads
this is thread 0 of core 11
x2APIC 00000016 0: nextshift 1 num  2 type 1 id 22
x2APIC 00000016 1: nextshift 5 num 24 type 2 id 11
x2APIC remainder: 0
this is thread 22 of core 11
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU10
APIC ID 0x18 legacy_max_log_proc 32
phys 0 legacy thread 24
thus 2 threads
this is thread 0 of core 12
x2APIC 00000018 0: nextshift 1 num  2 type 1 id 24
x2APIC 00000018 1: nextshift 5 num 24 type 2 id 12
x2APIC remainder: 0
this is thread 24 of core 12
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU11
APIC ID 0x1a legacy_max_log_proc 32
phys 0 legacy thread 26
thus 2 threads
this is thread 0 of core 13
x2APIC 0000001a 0: nextshift 1 num  2 type 1 id 26
x2APIC 0000001a 1: nextshift 5 num 24 type 2 id 13
x2APIC remainder: 0
this is thread 26 of core 13
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU12
APIC ID 0x20 legacy_max_log_proc 32
phys 1 legacy thread 0
thus 2 threads
this is thread 0 of core 0
x2APIC 00000020 0: nextshift 1 num  2 type 1 id  0
x2APIC 00000020 1: nextshift 5 num 24 type 2 id  0
x2APIC remainder: 1
this is thread 0 of core 0
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU13
APIC ID 0x22 legacy_max_log_proc 32
phys 1 legacy thread 2
thus 2 threads
this is thread 0 of core 1
x2APIC 00000022 0: nextshift 1 num  2 type 1 id  2
x2APIC 00000022 1: nextshift 5 num 24 type 2 id  1
x2APIC remainder: 1
this is thread 2 of core 1
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU14
APIC ID 0x24 legacy_max_log_proc 32
phys 1 legacy thread 4
thus 2 threads
this is thread 0 of core 2
x2APIC 00000024 0: nextshift 1 num  2 type 1 id  4
x2APIC 00000024 1: nextshift 5 num 24 type 2 id  2
x2APIC remainder: 1
this is thread 4 of core 2
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU15
APIC ID 0x26 legacy_max_log_proc 32
phys 1 legacy thread 6
thus 2 threads
this is thread 0 of core 3
x2APIC 00000026 0: nextshift 1 num  2 type 1 id  6
x2APIC 00000026 1: nextshift 5 num 24 type 2 id  3
x2APIC remainder: 1
this is thread 6 of core 3
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU16
APIC ID 0x28 legacy_max_log_proc 32
phys 1 legacy thread 8
thus 2 threads
this is thread 0 of core 4
x2APIC 00000028 0: nextshift 1 num  2 type 1 id  8
x2APIC 00000028 1: nextshift 5 num 24 type 2 id  4
x2APIC remainder: 1
this is thread 8 of core 4
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU17
APIC ID 0x2a legacy_max_log_proc 32
phys 1 legacy thread 10
thus 2 threads
this is thread 0 of core 5
x2APIC 0000002a 0: nextshift 1 num  2 type 1 id 10
x2APIC 0000002a 1: nextshift 5 num 24 type 2 id  5
x2APIC remainder: 1
this is thread 10 of core 5
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU18
APIC ID 0x30 legacy_max_log_proc 32
phys 1 legacy thread 16
thus 2 threads
this is thread 0 of core 8
x2APIC 00000030 0: nextshift 1 num  2 type 1 id 16
x2APIC 00000030 1: nextshift 5 num 24 type 2 id  8
x2APIC remainder: 1
this is thread 16 of core 8
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU19
APIC ID 0x32 legacy_max_log_proc 32
phys 1 legacy thread 18
thus 2 threads
this is thread 0 of core 9
x2APIC 00000032 0: nextshift 1 num  2 type 1 id 18
x2APIC 00000032 1: nextshift 5 num 24 type 2 id  9
x2APIC remainder: 1
this is thread 18 of core 9
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU20
APIC ID 0x34 legacy_max_log_proc 32
phys 1 legacy thread 20
thus 2 threads
this is thread 0 of core 10
x2APIC 00000034 0: nextshift 1 num  2 type 1 id 20
x2APIC 00000034 1: nextshift 5 num 24 type 2 id 10
x2APIC remainder: 1
this is thread 20 of core 10
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU21
APIC ID 0x36 legacy_max_log_proc 32
phys 1 legacy thread 22
thus 2 threads
this is thread 0 of core 11
x2APIC 00000036 0: nextshift 1 num  2 type 1 id 22
x2APIC 00000036 1: nextshift 5 num 24 type 2 id 11
x2APIC remainder: 1
this is thread 22 of core 11
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU22
APIC ID 0x38 legacy_max_log_proc 32
phys 1 legacy thread 24
thus 2 threads
this is thread 0 of core 12
x2APIC 00000038 0: nextshift 1 num  2 type 1 id 24
x2APIC 00000038 1: nextshift 5 num 24 type 2 id 12
x2APIC remainder: 1
this is thread 24 of core 12
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU23
APIC ID 0x3a legacy_max_log_proc 32
phys 1 legacy thread 26
thus 2 threads
this is thread 0 of core 13
x2APIC 0000003a 0: nextshift 1 num  2 type 1 id 26
x2APIC 0000003a 1: nextshift 5 num 24 type 2 id 13
x2APIC remainder: 1
this is thread 26 of core 13
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU24
APIC ID 0x01 legacy_max_log_proc 32
phys 0 legacy thread 1
thus 2 threads
this is thread 1 of core 0
x2APIC 00000001 0: nextshift 1 num  2 type 1 id  1
x2APIC 00000001 1: nextshift 5 num 24 type 2 id  0
x2APIC remainder: 0
this is thread 1 of core 0
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU25
APIC ID 0x03 legacy_max_log_proc 32
phys 0 legacy thread 3
thus 2 threads
this is thread 1 of core 1
x2APIC 00000003 0: nextshift 1 num  2 type 1 id  3
x2APIC 00000003 1: nextshift 5 num 24 type 2 id  1
x2APIC remainder: 0
this is thread 3 of core 1
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU26
APIC ID 0x05 legacy_max_log_proc 32
phys 0 legacy thread 5
thus 2 threads
this is thread 1 of core 2
x2APIC 00000005 0: nextshift 1 num  2 type 1 id  5
x2APIC 00000005 1: nextshift 5 num 24 type 2 id  2
x2APIC remainder: 0
this is thread 5 of core 2
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU27
APIC ID 0x07 legacy_max_log_proc 32
phys 0 legacy thread 7
thus 2 threads
this is thread 1 of core 3
x2APIC 00000007 0: nextshift 1 num  2 type 1 id  7
x2APIC 00000007 1: nextshift 5 num 24 type 2 id  3
x2APIC remainder: 0
this is thread 7 of core 3
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU28
APIC ID 0x09 legacy_max_log_proc 32
phys 0 legacy thread 9
thus 2 threads
this is thread 1 of core 4
x2APIC 00000009 0: nextshift 1 num  2 type 1 id  9
x2APIC 00000009 1: nextshift 5 num 24 type 2 id  4
x2APIC remainder: 0
this is thread 9 of core 4
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU29
APIC ID 0x0b legacy_max_log_proc 32
phys 0 legacy thread 11
thus 2 threads
this is thread 1 of core 5
x2APIC 0000000b 0: nextshift 1 num  2 type 1 id 11
x2APIC 0000000b 1: nextshift 5 num 24 type 2 id  5
x2APIC remainder: 0
this is thread 11 of core 5
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU30
APIC ID 0x11 legacy_max_log_proc 32
phys 0 legacy thread 17
thus 2 threads
this is thread 1 of core 8
x2APIC 00000011 0: nextshift 1 num  2 type 1 id 17
x2APIC 00000011 1: nextshift 5 num 24 type 2 id  8
x2APIC remainder: 0
this is thread 17 of core 8
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU31
APIC ID 0x13 legacy_max_log_proc 32
phys 0 legacy thread 19
thus 2 threads
this is thread 1 of core 9
x2APIC 00000013 0: nextshift 1 num  2 type 1 id 19
x2APIC 00000013 1: nextshift 5 num 24 type 2 id  9
x2APIC remainder: 0
this is thread 19 of core 9
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU32
APIC ID 0x15 legacy_max_log_proc 32
phys 0 legacy thread 21
thus 2 threads
this is thread 1 of core 10
x2APIC 00000015 0: nextshift 1 num  2 type 1 id 21
x2APIC 00000015 1: nextshift 5 num 24 type 2 id 10
x2APIC remainder: 0
this is thread 21 of core 10
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU33
APIC ID 0x17 legacy_max_log_proc 32
phys 0 legacy thread 23
thus 2 threads
this is thread 1 of core 11
x2APIC 00000017 0: nextshift 1 num  2 type 1 id 23
x2APIC 00000017 1: nextshift 5 num 24 type 2 id 11
x2APIC remainder: 0
this is thread 23 of core 11
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU34
APIC ID 0x19 legacy_max_log_proc 32
phys 0 legacy thread 25
thus 2 threads
this is thread 1 of core 12
x2APIC 00000019 0: nextshift 1 num  2 type 1 id 25
x2APIC 00000019 1: nextshift 5 num 24 type 2 id 12
x2APIC remainder: 0
this is thread 25 of core 12
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU35
APIC ID 0x1b legacy_max_log_proc 32
phys 0 legacy thread 27
thus 2 threads
this is thread 1 of core 13
x2APIC 0000001b 0: nextshift 1 num  2 type 1 id 27
x2APIC 0000001b 1: nextshift 5 num 24 type 2 id 13
x2APIC remainder: 0
this is thread 27 of core 13
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU36
APIC ID 0x21 legacy_max_log_proc 32
phys 1 legacy thread 1
thus 2 threads
this is thread 1 of core 0
x2APIC 00000021 0: nextshift 1 num  2 type 1 id  1
x2APIC 00000021 1: nextshift 5 num 24 type 2 id  0
x2APIC remainder: 1
this is thread 1 of core 0
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU37
APIC ID 0x23 legacy_max_log_proc 32
phys 1 legacy thread 3
thus 2 threads
this is thread 1 of core 1
x2APIC 00000023 0: nextshift 1 num  2 type 1 id  3
x2APIC 00000023 1: nextshift 5 num 24 type 2 id  1
x2APIC remainder: 1
this is thread 3 of core 1
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU38
APIC ID 0x25 legacy_max_log_proc 32
phys 1 legacy thread 5
thus 2 threads
this is thread 1 of core 2
x2APIC 00000025 0: nextshift 1 num  2 type 1 id  5
x2APIC 00000025 1: nextshift 5 num 24 type 2 id  2
x2APIC remainder: 1
this is thread 5 of core 2
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU39
APIC ID 0x27 legacy_max_log_proc 32
phys 1 legacy thread 7
thus 2 threads
this is thread 1 of core 3
x2APIC 00000027 0: nextshift 1 num  2 type 1 id  7
x2APIC 00000027 1: nextshift 5 num 24 type 2 id  3
x2APIC remainder: 1
this is thread 7 of core 3
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU40
APIC ID 0x29 legacy_max_log_proc 32
phys 1 legacy thread 9
thus 2 threads
this is thread 1 of core 4
x2APIC 00000029 0: nextshift 1 num  2 type 1 id  9
x2APIC 00000029 1: nextshift 5 num 24 type 2 id  4
x2APIC remainder: 1
this is thread 9 of core 4
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU41
APIC ID 0x2b legacy_max_log_proc 32
phys 1 legacy thread 11
thus 2 threads
this is thread 1 of core 5
x2APIC 0000002b 0: nextshift 1 num  2 type 1 id 11
x2APIC 0000002b 1: nextshift 5 num 24 type 2 id  5
x2APIC remainder: 1
this is thread 11 of core 5
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU42
APIC ID 0x31 legacy_max_log_proc 32
phys 1 legacy thread 17
thus 2 threads
this is thread 1 of core 8
x2APIC 00000031 0: nextshift 1 num  2 type 1 id 17
x2APIC 00000031 1: nextshift 5 num 24 type 2 id  8
x2APIC remainder: 1
this is thread 17 of core 8
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU43
APIC ID 0x33 legacy_max_log_proc 32
phys 1 legacy thread 19
thus 2 threads
this is thread 1 of core 9
x2APIC 00000033 0: nextshift 1 num  2 type 1 id 19
x2APIC 00000033 1: nextshift 5 num 24 type 2 id  9
x2APIC remainder: 1
this is thread 19 of core 9
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU44
APIC ID 0x35 legacy_max_log_proc 32
phys 1 legacy thread 21
thus 2 threads
this is thread 1 of core 10
x2APIC 00000035 0: nextshift 1 num  2 type 1 id 21
x2APIC 00000035 1: nextshift 5 num 24 type 2 id 10
x2APIC remainder: 1
this is thread 21 of core 10
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU45
APIC ID 0x37 legacy_max_log_proc 32
phys 1 legacy thread 23
thus 2 threads
this is thread 1 of core 11
x2APIC 00000037 0: nextshift 1 num  2 type 1 id 23
x2APIC 00000037 1: nextshift 5 num 24 type 2 id 11
x2APIC remainder: 1
this is thread 23 of core 11
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU46
APIC ID 0x39 legacy_max_log_proc 32
phys 1 legacy thread 25
thus 2 threads
this is thread 1 of core 12
x2APIC 00000039 0: nextshift 1 num  2 type 1 id 25
x2APIC 00000039 1: nextshift 5 num 24 type 2 id 12
x2APIC remainder: 1
this is thread 25 of core 12
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB
binding to CPU47
APIC ID 0x3b legacy_max_log_proc 32
phys 1 legacy thread 27
thus 2 threads
this is thread 1 of core 13
x2APIC 0000003b 0: nextshift 1 num  2 type 1 id 27
x2APIC 0000003b 1: nextshift 5 num 24 type 2 id 13
x2APIC remainder: 1
this is thread 27 of core 13
cache 0 type 1
cache 1 type 2
cache 2 type 3
cache 3 type 3
cache 4 type 0
cache 0 L1d t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 1 L1i t2 linesize 64 linepart 1 ways 8 sets 64, size 32KB
cache 2 L2u t2 linesize 64 linepart 1 ways 8 sets 512, size 256KB
cache 3 L3u t32 linesize 64 linepart 1 ways 20 sets 24576, size 30720KB

Summary of x86 CPUID topology:
PU 0 present=1 apicid=0 on PKG 0 CORE 0 DIE -1 NODE -1
PU 1 present=1 apicid=2 on PKG 0 CORE 1 DIE -1 NODE -1
PU 2 present=1 apicid=4 on PKG 0 CORE 2 DIE -1 NODE -1
PU 3 present=1 apicid=6 on PKG 0 CORE 3 DIE -1 NODE -1
PU 4 present=1 apicid=8 on PKG 0 CORE 4 DIE -1 NODE -1
PU 5 present=1 apicid=10 on PKG 0 CORE 5 DIE -1 NODE -1
PU 6 present=1 apicid=16 on PKG 0 CORE 8 DIE -1 NODE -1
PU 7 present=1 apicid=18 on PKG 0 CORE 9 DIE -1 NODE -1
PU 8 present=1 apicid=20 on PKG 0 CORE 10 DIE -1 NODE -1
PU 9 present=1 apicid=22 on PKG 0 CORE 11 DIE -1 NODE -1
PU 10 present=1 apicid=24 on PKG 0 CORE 12 DIE -1 NODE -1
PU 11 present=1 apicid=26 on PKG 0 CORE 13 DIE -1 NODE -1
PU 12 present=1 apicid=32 on PKG 1 CORE 0 DIE -1 NODE -1
PU 13 present=1 apicid=34 on PKG 1 CORE 1 DIE -1 NODE -1
PU 14 present=1 apicid=36 on PKG 1 CORE 2 DIE -1 NODE -1
PU 15 present=1 apicid=38 on PKG 1 CORE 3 DIE -1 NODE -1
PU 16 present=1 apicid=40 on PKG 1 CORE 4 DIE -1 NODE -1
PU 17 present=1 apicid=42 on PKG 1 CORE 5 DIE -1 NODE -1
PU 18 present=1 apicid=48 on PKG 1 CORE 8 DIE -1 NODE -1
PU 19 present=1 apicid=50 on PKG 1 CORE 9 DIE -1 NODE -1
PU 20 present=1 apicid=52 on PKG 1 CORE 10 DIE -1 NODE -1
PU 21 present=1 apicid=54 on PKG 1 CORE 11 DIE -1 NODE -1
PU 22 present=1 apicid=56 on PKG 1 CORE 12 DIE -1 NODE -1
PU 23 present=1 apicid=58 on PKG 1 CORE 13 DIE -1 NODE -1
PU 24 present=1 apicid=1 on PKG 0 CORE 0 DIE -1 NODE -1
PU 25 present=1 apicid=3 on PKG 0 CORE 1 DIE -1 NODE -1
PU 26 present=1 apicid=5 on PKG 0 CORE 2 DIE -1 NODE -1
PU 27 present=1 apicid=7 on PKG 0 CORE 3 DIE -1 NODE -1
PU 28 present=1 apicid=9 on PKG 0 CORE 4 DIE -1 NODE -1
PU 29 present=1 apicid=11 on PKG 0 CORE 5 DIE -1 NODE -1
PU 30 present=1 apicid=17 on PKG 0 CORE 8 DIE -1 NODE -1
PU 31 present=1 apicid=19 on PKG 0 CORE 9 DIE -1 NODE -1
PU 32 present=1 apicid=21 on PKG 0 CORE 10 DIE -1 NODE -1
PU 33 present=1 apicid=23 on PKG 0 CORE 11 DIE -1 NODE -1
PU 34 present=1 apicid=25 on PKG 0 CORE 12 DIE -1 NODE -1
PU 35 present=1 apicid=27 on PKG 0 CORE 13 DIE -1 NODE -1
PU 36 present=1 apicid=33 on PKG 1 CORE 0 DIE -1 NODE -1
PU 37 present=1 apicid=35 on PKG 1 CORE 1 DIE -1 NODE -1
PU 38 present=1 apicid=37 on PKG 1 CORE 2 DIE -1 NODE -1
PU 39 present=1 apicid=39 on PKG 1 CORE 3 DIE -1 NODE -1
PU 40 present=1 apicid=41 on PKG 1 CORE 4 DIE -1 NODE -1
PU 41 present=1 apicid=43 on PKG 1 CORE 5 DIE -1 NODE -1
PU 42 present=1 apicid=49 on PKG 1 CORE 8 DIE -1 NODE -1
PU 43 present=1 apicid=51 on PKG 1 CORE 9 DIE -1 NODE -1
PU 44 present=1 apicid=53 on PKG 1 CORE 10 DIE -1 NODE -1
PU 45 present=1 apicid=55 on PKG 1 CORE 11 DIE -1 NODE -1
PU 46 present=1 apicid=57 on PKG 1 CORE 12 DIE -1 NODE -1
PU 47 present=1 apicid=59 on PKG 1 CORE 13 DIE -1 NODE -1

CPU phase discovery in component no_os...

Fixup root sets

Propagate sets

Removing unauthorized sets from all sets

Ok, finished tweaking, now connect
PCI phase discovery...
PCI phase discovery in component linux...
hwloc verbose debug enabled, may be disabled with HWLOC_DEBUG_VERBOSE=0 in the environment.

PCI hierarchy:
0000:00:00.0 Device [8086:6f00 (8086:0000) rev=00 class=0600]

Adding new PCI hostbridge 0000:00
  new PCI hostbridge covers 0000:[00-08]
Adding new PCI hostbridge 0000:7f
  new PCI hostbridge covers 0000:[7f-7f]
Adding new PCI hostbridge 0000:80
  new PCI hostbridge covers 0000:[80-82]
Adding new PCI hostbridge 0000:ff
  new PCI hostbridge covers 0000:[ff-ff]
Looking for parent of PCI busid 0000:00:00.0
  will attach PCI bus to cpuset 0x0000000f,0xff000fff
Adding PCI locality Package P#0 for bus 0000:[00:08]
Looking for parent of PCI busid 0000:7f:08.0
  will attach PCI bus to cpuset 0x0000ffff,0xffffffff
Adding PCI locality Machine P#0 for bus 0000:[7f:7f]
Looking for parent of PCI busid 0000:80:02.0
  will attach PCI bus to cpuset 0x0000fff0,0x00fff000
Adding PCI locality Package P#1 for bus 0000:[80:82]
Looking for parent of PCI busid 0000:ff:08.0
  will attach PCI bus to cpuset 0x0000ffff,0xffffffff
Adding PCI locality Machine P#0 for bus 0000:[ff:ff]
IO phase discovery...
IO phase discovery in component linux...
pcidisc looking for bus id 0000:01:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:01:00.0 below Package P#0
  found busid 0000:01:00.0
pcidisc looking for bus id 0000:00:1f.2
  found pci locality for 0000:[00:08]
  looking for bus 0000:00:1f.2 below Package P#0
  found busid 0000:00:1f.2
pcidisc looking for bus id 0000:00:11.4
  found pci locality for 0000:[00:08]
  looking for bus 0000:00:11.4 below Package P#0
  found busid 0000:00:11.4
pcidisc looking for bus id 0000:08:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:08:00.0 below Package P#0
  found busid 0000:08:00.0
pcidisc looking for bus id 0000:00:1f.2
  found pci locality for 0000:[00:08]
  looking for bus 0000:00:1f.2 below Package P#0
  found busid 0000:00:1f.2
pcidisc looking for bus id 0000:00:1f.2
  found pci locality for 0000:[00:08]
  looking for bus 0000:00:1f.2 below Package P#0
  found busid 0000:00:1f.2
pcidisc looking for bus id 0000:00:11.4
  found pci locality for 0000:[00:08]
  looking for bus 0000:00:11.4 below Package P#0
  found busid 0000:00:11.4
pcidisc looking for bus id 0000:06:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:06:00.0 below Package P#0
  found busid 0000:06:00.0
pcidisc looking for bus id 0000:07:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:07:00.0 below Package P#0
  found busid 0000:07:00.0
pcidisc looking for bus id 0000:03:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:03:00.0 below Package P#0
  found busid 0000:03:00.0
pcidisc looking for bus id 0000:03:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:03:00.0 below Package P#0
  found busid 0000:03:00.0
IO phase discovery in component opencl...
hwloc verbose debug enabled, may be disabled with HWLOC_DEBUG_VERBOSE=0 in the environment.
2 OpenCL platforms
This is opencl0d0
This is opencl1d0
pcidisc looking for bus id 0000:03:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:03:00.0 below Package P#0
  found busid 0000:03:00.0
IO phase discovery in component cuda...
pcidisc looking for bus id 0000:03:00.0
  found pci locality for 0000:[00:08]
  looking for bus 0000:03:00.0 below Package P#0
  found busid 0000:03:00.0
IO phase discovery in component gl...

the process is freeze in the same point

->make check -C hwloc

 └───╼  make check -C hwloc
make: se entra en el directorio '/tmp/makepkg/sl1-hwloc/src/build/hwloc'
make  hwloc_fake.la
make[1]: se entra en el directorio '/tmp/makepkg/sl1-hwloc/src/build/hwloc'
make[1]: 'hwloc_fake.la' está actualizado.
make[1]: se sale del directorio '/tmp/makepkg/sl1-hwloc/src/build/hwloc'
make: se sale del directorio '/tmp/makepkg/sl1-hwloc/src/build/hwloc'

the rest of the command output the same conterts like test-fake-plugin.sh.log, and the process freeze

if help. my environment is KDE plasma 5 in Wayland (nvidia drivers 510.47.03) over GBM. CUDA is 11.6 (I pass 'CUDA_VERSION=11.6` to the configure process)

greetings

@bgoglin
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bgoglin commented Feb 4, 2022

I wonder if this is related to make check and this fake plugin. Did you try running lstopo as requested in the github issue template?
It seems like it's stuck in the GL component, I have no idea if it has been tested on wayland. If lstopo doesn't work, try setting HWLOC_COMPONENTS=-gl in the environment. If it makes lstopo work, then the problem is in the GL backend.

@sl1pkn07
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sl1pkn07 commented Feb 4, 2022

the hwloc provided in arch (by binary package (https://archlinux.org/packages/extra/x86_64/hwloc/) but is builded without cuda/nvidia/things support. for that i what build my own package with more options enabled

lstopo from arch works ok

Screenshot_20220204_161409

but fails when try to build myself (in the check step).

if force the installation, and run my own build, this fail on show the lstopo window, but run again when pass HWLOC_COMPONENTS=-gl like you say

Screenshot_20220204_161924

glxgears, eglgears_{x11,wayland) and vkcube (similar to glxgears, but for Vukan) works, so in not a instalation problem

greetings

@bgoglin
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bgoglin commented Feb 4, 2022

I don't have any wayland/NVIDIA machine to debug unfortunately. If you want to debug on your side, you should add some printf inside hwloc/topology-gl.c before and after each XNVCtrl function call. I guess one of them is hanging.

@bgoglin bgoglin changed the title hwloc 2.7.0 fails unittest in test-fake-plugin GL backend hangs, wayland related? Feb 5, 2022
@bgoglin bgoglin mentioned this issue Sep 22, 2023
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@bgoglin
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bgoglin commented Jan 23, 2024

Hello. If you still have this issue, can you check whether something is listening on a port between 6000 and 6009 on this Linux? We've seen another hang that was caused by tensorflow listening on 6006 and hwloc's call to XOpenDisplay() timeouting because of that.

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