Synch up OMI and MCA frequencies

There is an intrinsic link between ATTR_FREQ_MCA_MHZ and
ATTR_FREQ_OMI_MHZ and ATTR_MC_PLL_BUCKET.
-ATTR_MC_PLL_BUCKET will be read-only, platforms will return the
 value based on ATTR_FREQ_OMI_MHZ.
-ATTR_FREQ_MCA_MHZ will be read-only (again), platforms will return
 the value based on ATTR_FREQ_OMI_MHZ.
-ATTR_FREQ_OMI_MHZ will be writeable, defaulted by mrw/config file,
 written by mss_freq_system.
-OMI_PLL_FREQ_LIST was be expanded to include the value of
 ATTR_FREQ_MCA_MHZ. Platforms will use ATTR_FREQ_OMI_MHZ (and VCO)
 as the key into OMI_PLL_FREQ_LIST to determine the value of
 ATTR_MC_PLL_BUCKET and ATTR_FREQ_MCA_MHZ

Change-Id: I17681b8b1ff8ad6b195fc741e20e48ac60ce1c99
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76877
Tested-by: FSP CI Jenkins <[email protected]>
Tested-by: Jenkins Server <[email protected]>
Dev-Ready: Steven B. Janssen <[email protected]>
Tested-by: HWSV CI <[email protected]>
Reviewed-by: Benjamin Gass <[email protected]>
Tested-by: PPE CI <[email protected]>
Reviewed-by: Louis Stermole <[email protected]>
Tested-by: Hostboot CI <[email protected]>
Reviewed-by: Jennifer A. Stofer <[email protected]>

import/chips/p9/common/include/p9_frequency_buckets.H

@@ -68,22 +68,25 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] =
 // OMI bucket descriptor
 struct OmiBucketDescriptor_t
 {
-    uint32_t freq; // Frequency in MHz
-    uint32_t vco;  // VCO selector
+    uint32_t omifreq; // OMI Frequency in MHz
+    uint32_t vco;     // VCO selector
+
+    uint32_t mcafreq; // MCA Frequency in MHz
 };
 
 //MC PLL frequency in MHz for Axone
 // index is bucket number
 // OMI -> ATTR_FREQ_OMI_MHZ
 // VCO -> ATTR_OMI_PLL_VCO
+// MCA -> ATTR_FREQ_MCA_MHZ
 const OmiBucketDescriptor_t OMI_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] =
 {
-    //  OMI    VCO       Data rate   MCA_FREQ
-    { 19200, 0 }, // ->DDR4-2400   1200
-    { 21330, 0 }, // ->DDR4-2667   1333
-    { 23460, 0 }, // ->DDR4-2933   1466
-    { 23460, 1 }, // ->DDR4-2933   1466
-    { 25600, 1 }  // ->DDR4-3200   1600
+    //  OMI    VCO   MCA          Data rate
+    { 19200,   0,    1200 }, // ->DDR4-2400
+    { 21330,   0,    1333 }, // ->DDR4-2667
+    { 23460,   0,    1466 }, // ->DDR4-2933
+    { 23460,   1,    1466 }, // ->DDR4-2933
+    { 25600,   1,    1600 }  // ->DDR4-3200
 };
 
 // constant definining number of OBUS PLL frequency options ('buckets')