PGPE: Fix Voltage Delay Math

- fix attribute consumption in busy-wait implementation Key_Cronus_Test=PM_REGRESS Change-Id: Ifc38fb147fd6c202154b5c3d930c638e1f110583 CQ: SW465588 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77667 Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <[email protected]> Tested-by: Jenkins Server <[email protected]> Tested-by: Cronus HW CI <[email protected]> Tested-by: FSP CI Jenkins <[email protected]> Reviewed-by: Gregory S. Still <[email protected]> Reviewed-by: Jennifer A Stofer <[email protected]>
open-power · Jun 6, 2019 · cade833 · cade833
1 parent ff534ad
commit cade833
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Showing 4 changed files with 16 additions and 15 deletions.
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
@@ -72,8 +72,8 @@ const uint8_t G_vdm_threshold_table[13] =
 
 //Globals and externs
 GlobalPstateParmBlock* G_gppb;//Global pointer to GlobalPstateParmBlock
-uint32_t G_ext_vrm_inc_rate_mult_usperus;
-uint32_t G_ext_vrm_dec_rate_mult_usperus;
+uint32_t G_ext_vrm_inc_rate_mult_usperv;
+uint32_t G_ext_vrm_dec_rate_mult_usperv;
 extern PgpeHeader_t* G_pgpe_header_data;
 
 //
@@ -94,11 +94,11 @@ void p9_pgpe_gppb_init()
     G_gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
 
     //PK_TRACE_INF("INIT: DPLL0Value=0x%x", G_gppb->dpll_pstate0_value);
-    //External VRM increasing rate in us/uv
-    G_ext_vrm_inc_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_inc_uv_per_us;
+    //External VRM increasing rate in us/v
+    G_ext_vrm_inc_rate_mult_usperv = (1000 * 1000) / G_gppb->ext_vrm_transition_rate_inc_uv_per_us;
 
-    //External VRM decreasing rate in us/uv
-    G_ext_vrm_dec_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_dec_uv_per_us;
+    //External VRM decreasing rate in us/v
+    G_ext_vrm_dec_rate_mult_usperv = (1000 * 1000) / G_gppb->ext_vrm_transition_rate_dec_uv_per_us;
 }
 
 //

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -49,8 +49,8 @@
 extern TraceData_t G_pgpe_optrace_data;
 extern PgpeHeader_t* G_pgpe_header_data;
 extern GlobalPstateParmBlock* G_gppb;
-extern uint32_t G_ext_vrm_inc_rate_mult_usperus;
-extern uint32_t G_ext_vrm_dec_rate_mult_usperus;
+extern uint32_t G_ext_vrm_inc_rate_mult_usperv;
+extern uint32_t G_ext_vrm_dec_rate_mult_usperv;
 extern PgpePstateRecord G_pgpe_pstate_record;
 extern void p9_pgpe_ipc_ack_sgpe_ctrl_stop_updt(ipc_msg_t* msg, void* arg);
 extern void p9_pgpe_ipc_ack_sgpe_suspend_stop(ipc_msg_t* msg, void* arg);
@@ -2065,7 +2065,7 @@ void p9_pgpe_pstate_updt_ext_volt()
         //to keep the math simple(use shift instead of multiply) we approximate
         //1us as (1024/32)=32 OTBR ticks
         delay_ticks = ((G_pgpe_pstate_record.extVrmCurr - G_pgpe_pstate_record.extVrmNext) *
-                       G_ext_vrm_dec_rate_mult_usperus) << 5;
+                       G_ext_vrm_dec_rate_mult_usperv) >> 5;
     }
     //Increasing
     else if (G_pgpe_pstate_record.extVrmNext > G_pgpe_pstate_record.extVrmCurr)
@@ -2074,7 +2074,7 @@ void p9_pgpe_pstate_updt_ext_volt()
         //to keep the math simple(use shift instead of multiply) we approximate
         //1us as (1024/32)=32 OTBR ticks
         delay_ticks  = ((G_pgpe_pstate_record.extVrmNext - G_pgpe_pstate_record.extVrmCurr) *
-                        G_ext_vrm_inc_rate_mult_usperus) << 5;
+                        G_ext_vrm_inc_rate_mult_usperv) >> 5;
     }
 
 #endif
@@ -2118,7 +2118,7 @@ void p9_pgpe_pstate_updt_ext_volt()
     if(G_pgpe_pstate_record.biasSyspExtVrmNext == p9_pgpe_gppb_intp_vdd_from_ps(G_pgpe_pstate_record.psNext.fields.glb,
             VPD_PT_SET_BIASED_SYSP))
     {
-        delay_ticks = G_gppb->ext_vrm_stabilization_time_us << 5;
+        delay_ticks = G_gppb->ext_vrm_stabilization_time_us >> 5;
 
         //Read TimebaseStart
         tbStart = in32(OCB_OTBR);

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
@@ -126,6 +126,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                     (G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_WOF_CTRL].pending_processing == 0))
                 {
                     out32(G_OCB_OCCFLG_CLR, BIT32(PGPE_PM_RESET_SUPPRESS));
+                    PK_TRACE_INF("ACT_TH: PM_RESET_SUPP=0");
                 }
             }
 
@@ -291,7 +292,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
             //Check if IPC should be opened again
             if (restore_irq == 1)
             {
-                PK_TRACE_DBG("ACT_TH: IRQ Restore");
+                PK_TRACE_INF("ACT_TH: IRQ Restore");
                 restore_irq = 0;
                 pk_irq_vec_restore(&ctx);
             }

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
@@ -1034,7 +1034,7 @@ inline void p9_pgpe_process_wof_vfrt()
 //
 inline void p9_pgpe_process_set_pmcr_req()
 {
-    PK_TRACE_DBG("PTH: Set PMCR Enter");
+    PK_TRACE_INF("PTH: Set PMCR Enter");
 
     uint32_t q, c, bad_rc = 0;
     ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SET_PMCR_REQ].cmd;
@@ -1092,7 +1092,7 @@ inline void p9_pgpe_process_set_pmcr_req()
     }
     else
     {
-        PK_TRACE_DBG("PTH: Upd coresPSReq");
+        PK_TRACE_INF("PTH: Upd coresPSReq");
 
         for (q = 0; q < MAX_QUADS; q++)
         {
@@ -1129,7 +1129,7 @@ inline void p9_pgpe_process_set_pmcr_req()
         PGPE_OPTIONAL_TRACE_AND_PANIC(PGPE_OCC_IPC_ACK_BAD_RC);
     }
 
-    PK_TRACE_DBG("PTH: Set PMCR Exit");
+    PK_TRACE_INF("PTH: Set PMCR Exit");
 }
 
 //