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Add new path in EEPROM device op to allow reading from new EECACHE
Recently a new EECACHE section was introduced to Hostboot. This section gets populated with a copy of every PRIMARY_VPD eeprom (someday could contain other eeprom roles also) during host_discover_targets. This commit add support to allow users to select where they want to perform their EEPROM device operation. If they pass CACHE to the deviceOp macro then a read will come from the pnor cache, writes will write to pnor cache and then also write to the eeprom HW. If HARDWARE is passed in then reads and writes will be directly done on the eeprom hardware. If AUTOSELECT is passed the code will check our cache to see if we have a copy of the eeprom in question, if we have a copy we will go the CACHE path, if no copy exists we will go the HARDWARE path. Along with this change some reorganization was done w/ the eeprom related files. RTC: 196805 Change-Id: If2c4e5d3e338a1a10780740c1a019eb4af003b73 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70822 Reviewed-by: Matt Derksen <[email protected]> Tested-by: Jenkins Server <[email protected]> Tested-by: Jenkins OP Build CI <[email protected]> Tested-by: FSP CI Jenkins <[email protected]> Reviewed-by: Roland Veloz <[email protected]> Tested-by: Jenkins OP HW <[email protected]> Reviewed-by: Daniel M. Crowell <[email protected]>
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Original file line number | Diff line number | Diff line change |
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@@ -1,11 +1,12 @@ | ||
set DJVPD_READ_FROM_HW | ||
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# You can enabled MVPD read from HW but adds time to IPL | ||
#set MVPD_READ_FROM_HW | ||
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#skip enabling checkstop analysis until OCC is ready in simics | ||
unset IPLTIME_CHECKSTOP_ANALYSIS | ||
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#Try to keep a list of things this does | ||
# - skipping setting voltages in istep 8.12, nothing on other side of AVSbus | ||
# in simics currently. | ||
set AXONE_BRING_UP | ||
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set SUPPORT_EEPROM_CACHING | ||
set SUPPORT_EEPROM_CACHING | ||
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