From a7bf0135fb18c462f5bdca06ee614c956891b1db Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Wed, 17 Aug 2016 08:29:44 -0500 Subject: [PATCH] Implement MRW attributes; dram_clks, db_util, 2n_mode ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL ATTR_MSS_MRW_DRAM_2N_MODE TSYS_ADR, TSYS_DATA moved the MT VPD GPO, RLO, WLO moved to the MT VPD Update hb defaults Update unit test to catch the 2N mode MRW changes Change-Id: I3d998c70d30df978062ce923096ba741d597782e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28383 Dev-Ready: Brian R. Silver Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Matt K. Light Reviewed-by: Louis Stermole Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell Reviewed-by: ANDRE A. MARIN Reviewed-by: JACOB L. HARVEY Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69778 Reviewed-by: Sachin Gupta Tested-by: Sachin Gupta --- .../xml/attribute_info/memory_mcs_attributes.xml | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 744146426..56b052541 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -2120,21 +2120,6 @@ vmem_regulator_max_dimm_count - - ATTR_MSS_DATABUS_UTIL - TARGET_TYPE_MCS - - - - DRAM data bus utilization percent to use to determine cfg_nm_n_per_port - - - uint8 - - 2 - databus_util - - ATTR_MSS_OCC_THROTTLED_N_CMDS TARGET_TYPE_MCS