From 8407734678772c17d3fc0fc8a5223bab1f1e5625 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 18 Mar 2024 18:54:01 +0100 Subject: [PATCH 1/3] Added possibility to make lec between v2 versions. Updated headers date and moved to Solderpad 2.1 Signed-off-by: Pascal Gouedo --- scripts/slec/README.md | 18 ++++++ scripts/slec/cadence/lec.tcl | 43 ++++++++++----- scripts/slec/run.sh | 100 +++++++++++++++++++++++++++------- scripts/slec/synopsys/lec.tcl | 47 +++++++++++++--- 4 files changed, 168 insertions(+), 40 deletions(-) diff --git a/scripts/slec/README.md b/scripts/slec/README.md index ff5311322..6249563cc 100644 --- a/scripts/slec/README.md +++ b/scripts/slec/README.md @@ -59,3 +59,21 @@ From a bash shell using LEC, please execute: setenv GOLDEN_RTL YOUR_GOLDEN_CORE_RTL_PATH ``` +### Additional improvements for v2 + +To be able to make LEC checks between v2 versions, the scripts have been augmented with additional optional switches: +* for RTL version : -v v1 or v2 +* for PULP instructions selection : -x 0 or 1 +* for FPU instructions selection : -f 0 or 1 +* for ZFINX selection : -z 0 or 1 + +When those options are not used, present behavior is happenning, meaning verifying local RTL files with `cv32e40p_v1.0.0` tag. +When v2 option is selected, `cv32e40p_top` is used as a top module, including both `cv32e40p_core` and `CVFPU`. +CAUTION : Right now dev branch is cloned as a golden reference when v2 version is used. It will have to be changed to `cv32e40p_v2.0.0` tag after CV32E40Pv2 RTL freeze. + +From a bash shell using LEC, please execute: + +``` +./run.sh -t synopsys -p lec -v v2 -x 1 -f 1 +``` + diff --git a/scripts/slec/cadence/lec.tcl b/scripts/slec/cadence/lec.tcl index 3cc8bea7b..7acbfd3a5 100644 --- a/scripts/slec/cadence/lec.tcl +++ b/scripts/slec/cadence/lec.tcl @@ -1,33 +1,48 @@ -// Copyright 2021 OpenHW Group +// Copyright 2024 OpenHW Group and Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. // You may obtain a copy of the License at // -// https://solderpad.org/licenses/ +// https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + set summary_log $::env(summary_log) set top_module $::env(top_module) +set version $::env(version) +set pulp_cfg $::env(pulp_cfg) +set fpu_cfg $::env(fpu_cfg) +set zfinx_cfg $::env(zfinx_cfg) + +if {"$version" == "v1"} { + set golden_parameter_list "-parameter PULP_XPULP 0 -parameter FPU 0 -parameter PULP_ZFINX 0" +} else { + set golden_parameter_list "-parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg" +} -read_design -SV -replace -noelaborate -golden -File ./golden.src +read_design -SV09 -replace -noelaborate -golden -File ./golden.src -elaborate_design -golden +elaborate_design -golden -root $top_module $golden_parameter_list -read_design -SV -replace -noelaborate -revised -File ./revised.src +read_design -SV09 -replace -noelaborate -revised -File ./revised.src -elaborate_design -revised +elaborate_design -revised -root $top_module -parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg report_design_data -add_ignored_outputs apu_req_o -Both -add_ignored_outputs apu_operands_o* -Both -add_ignored_outputs apu_op_o* -Both -add_ignored_outputs apu_flags_o* -Both +if {"$top_module" == "cv32e40p_core"} { + add_ignored_outputs apu_req_o -Both + add_ignored_outputs apu_operands_o* -Both + add_ignored_outputs apu_op_o* -Both + add_ignored_outputs apu_flags_o* -Both +} write_hier_compare_dofile hier_compare_r2r.do -constraint -replace diff --git a/scripts/slec/run.sh b/scripts/slec/run.sh index 064154815..23a51bab5 100755 --- a/scripts/slec/run.sh +++ b/scripts/slec/run.sh @@ -1,21 +1,25 @@ #!/bin/bash -# Copyright 2023 OpenHW Group +# Copyright 2024 OpenHW Group and Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. # You may obtain a copy of the License at # -# https://solderpad.org/licenses/ +# https://solderpad.org/licenses/SHL-2.1/ # -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an “AS IS” BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. usage() { # Function: Print a help message. - echo "Usage: $0 [ -t {cadence,synopsys,siemens} -p {sec,lec} ]" 1>&2 + echo "Usage: $0 -t {cadence,synopsys,siemens} -p {sec,lec} [-v {v1,v2}] [-x {0,1}] [-f {0,1}] [-z {0,1}]]" 1>&2 + echo "For v2 : if f or z is 1 then p must be 1" 1>&2 + echo " if z is 1 then f must be 1" 1>&2 } exit_abnormal() { # Function: Exit with error. @@ -32,7 +36,12 @@ print_log() { echo "[LOG] $1" } -while getopts "t:p:" flag +VERSION=v1 +PULP_CFG=0 +FPU_CFG=0 +ZFINX_CFG=0 + +while getopts "t:p:v:x:f:z:" flag do case "${flag}" in t) @@ -41,6 +50,18 @@ do p) target_process=${OPTARG} ;; + v) + VERSION=${OPTARG} + ;; + x) + PULP_CFG=${OPTARG} + ;; + f) + FPU_CFG=${OPTARG} + ;; + z) + ZFINX_CFG=${OPTARG} + ;; :) exit_abnormal ;; @@ -61,25 +82,63 @@ if [[ "${target_process}" != "sec" && "${target_process}" != "lec" ]]; then exit_abnormal fi +if [[ "${VERSION}" != "v1" && "${VERSION}" != "v2" ]]; then + exit_abnormal +elif [[ "${VERSION}" == "v1" && ("${PULP_CFG}" != "0" || "${FPU_CFG}" != "0" || "${ZFINX_CFG}" != "0") ]]; then + exit_abnormal +fi + +if [[ "${PULP_CFG}" != 0 && "${PULP_CFG}" != 1 ]]; then + exit_abnormal +fi + +if [[ "${FPU_CFG}" != 0 && "${FPU_CFG}" != 1 ]]; then + exit_abnormal +fi + +if [[ "${ZFINX_CFG}" != 0 && "${ZFINX_CFG}" != 1 ]]; then + exit_abnormal +fi + +if [[ (("${PULP_CFG}" == 0 && ("${FPU_CFG}" == 1 || "${ZFINX_CFG}" == 1)) || ("${PULP_CFG}" == 1 && "${FPU_CFG}" == 0 && "${ZFINX_CFG}" == 1)) ]]; then + exit_abnormal +fi + +if [[ "${VERSION}" == "v1" ]]; then + REF_BRANCH=cv32e40p_v1.0.0 + TOP_MODULE=cv32e40p_core +else + REF_BRANCH=dev + TOP_MODULE=cv32e40p_top +fi + +export top_module=${TOP_MODULE} +export version=${VERSION} +export pulp_cfg=${PULP_CFG} +export fpu_cfg=${FPU_CFG} +export zfinx_cfg=${ZFINX_CFG} + if [ -z "${REF_REPO}" ]; then print_log "Empty REF_REPO env variable" REF_REPO=https://github.com/openhwgroup/cv32e40p.git REF_FOLDER=ref_design - REF_BRANCH=cv32e40p_v1.0.0 print_log " * Setting REF_REPO ${REF_REPO}" print_log " * Setting REF_FOLDER ${REF_FOLDER}" print_log " * Setting REF_BRANCH ${REF_BRANCH}" + print_log " * Setting TOP_MODULE ${TOP_MODULE}" fi RTL_FOLDER=$(readlink -f ../..) -FLIST=cv32e40p_manifest.flist +if [[ "${PULP_CFG}" == 0 && "${ZFINX_CFG}" == 0 ]]; then + FLIST=cv32e40p_manifest.flist +else + FLIST=cv32e40p_fpu_manifest.flist +fi if [[ -z "${TOP_MODULE}" ]]; then print_log "Empty TOP_MODULE env variable" - TOP_MODULE=cv32e40p_core print_log " * Setting TOP_MODULE ${TOP_MODULE}" - export top_module=${TOP_MODULE} fi if [ ! -d ./reports/ ]; then @@ -88,11 +147,10 @@ fi if [[ -z "${GOLDEN_RTL}" ]]; then print_log "The env variable GOLDEN_RTL is empty." - if [ ! -d "./${REF_FOLDER}" ]; then - print_log " * Cloning Golden Design...." - git clone $REF_REPO --single-branch -b $REF_BRANCH $REF_FOLDER; - git -C ${REF_FOLDER} checkout $REF_COMMIT - fi + \rm -rf "./${REF_FOLDER}" + print_log " * Cloning Golden Design...." + git clone $REF_REPO --single-branch -b $REF_BRANCH $REF_FOLDER; + git -C ${REF_FOLDER} checkout $REF_COMMIT export GOLDEN_RTL=$(pwd)/${REF_FOLDER}/rtl else print_log "${target_process^^}: Using ${GOLDEN_RTL} as reference design" @@ -104,9 +162,13 @@ REVISED_FLIST=$(pwd)/revised.src GOLDEN_DIR=$(readlink -f ./${REF_FOLDER}/) GOLDEN_FLIST=$(pwd)/golden.src -var_golden_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "wrapper") print $0 }' ${GOLDEN_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${GOLDEN_DIR}"'/rtl/|') +var_golden_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "tb_wrapper" && $0 !~ "cv32e40p_wrapper") print $0 }' ${GOLDEN_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${GOLDEN_DIR}"'/rtl/|') -var_revised_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "wrapper" && $0 !~ "_top") print $0 }' ${REVISED_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${REVISED_DIR}"'/rtl/|') +if [[ "${VERSION}" == "v1" ]]; then + var_revised_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "tb_wrapper" && $0 !~ "cv32e40p_wrapper" && $0 !~ "top") print $0 }' ${REVISED_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${REVISED_DIR}"'/rtl/|') +else + var_revised_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "tb_wrapper") print $0 }' ${REVISED_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${REVISED_DIR}"'/rtl/|') +fi print_log "Generating GOLDEN flist in path: ${GOLDEN_FLIST}" echo $var_golden_rtl > ${GOLDEN_FLIST} diff --git a/scripts/slec/synopsys/lec.tcl b/scripts/slec/synopsys/lec.tcl index 5d8f9130d..b8683fce5 100644 --- a/scripts/slec/synopsys/lec.tcl +++ b/scripts/slec/synopsys/lec.tcl @@ -1,26 +1,59 @@ +# Copyright 2024 OpenHW Group and Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an “AS IS” BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + set synopsys_auto_setup true set summary_log $::env(summary_log) set top_module $::env(top_module) +set version $::env(version) +set pulp_cfg $::env(pulp_cfg) +set fpu_cfg $::env(fpu_cfg) +set zfinx_cfg $::env(zfinx_cfg) + +set top_impl_name cv32e40p_core_COREV_PULP${pulp_cfg}_FPU${fpu_cfg}_ZFINX${zfinx_cfg} + +if {"$version" == "v1"} { + set golden_parameter_list "PULP_XPULP = 0, FPU = 0, PULP_ZFINX = 0" + set top_ref_name cv32e40p_core_PULP_XPULP0_FPU0_PULP_ZFINX0 +} else { + set golden_parameter_list "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg" + set top_ref_name $top_impl_name +} read_sverilog -container r -libname WORK -12 -f golden.src -set_top r:/WORK/$top_module +set_top r:/WORK/$top_module -parameter $golden_parameter_list read_sverilog -container i -libname WORK -12 -f revised.src -set_top i:/WORK/$top_module +set_top i:/WORK/$top_module -parameter "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg" match > $summary_log.match.rpt if {"$top_module" == "cv32e40p_core"} { - set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_req_o - set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_operands_o* - set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_op_o* - set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_flags_o* + set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_req_o + set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_operands_o* + set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_op_o* + set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_flags_o* + set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_req_o + set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_operands_o* + set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_op_o* + set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_flags_o* } verify > $summary_log report_aborted_points > $summary_log.aborted_points.rpt report_failing_points > $summary_log.failing_points.rpt -analyze_points -failing >> $summary_log exit From 0d56c5673f485ac1549f580af6a6d3d3ce4b5a67 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 21 Mar 2024 14:45:43 +0100 Subject: [PATCH 2/3] Corrected mis-leading variable name. Signed-off-by: Pascal Gouedo --- scripts/slec/synopsys/lec.tcl | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/scripts/slec/synopsys/lec.tcl b/scripts/slec/synopsys/lec.tcl index b8683fce5..e4365fc20 100644 --- a/scripts/slec/synopsys/lec.tcl +++ b/scripts/slec/synopsys/lec.tcl @@ -22,14 +22,14 @@ set pulp_cfg $::env(pulp_cfg) set fpu_cfg $::env(fpu_cfg) set zfinx_cfg $::env(zfinx_cfg) -set top_impl_name cv32e40p_core_COREV_PULP${pulp_cfg}_FPU${fpu_cfg}_ZFINX${zfinx_cfg} +set core_impl_name cv32e40p_core_COREV_PULP${pulp_cfg}_FPU${fpu_cfg}_ZFINX${zfinx_cfg} if {"$version" == "v1"} { set golden_parameter_list "PULP_XPULP = 0, FPU = 0, PULP_ZFINX = 0" - set top_ref_name cv32e40p_core_PULP_XPULP0_FPU0_PULP_ZFINX0 + set core_ref_name cv32e40p_core_PULP_XPULP0_FPU0_PULP_ZFINX0 } else { set golden_parameter_list "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg" - set top_ref_name $top_impl_name + set core_ref_name $core_impl_name } read_sverilog -container r -libname WORK -12 -f golden.src @@ -41,14 +41,14 @@ set_top i:/WORK/$top_module -parameter "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, match > $summary_log.match.rpt if {"$top_module" == "cv32e40p_core"} { - set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_req_o - set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_operands_o* - set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_op_o* - set_dont_verify_point -type port r:/WORK/$top_ref_name/apu_flags_o* - set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_req_o - set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_operands_o* - set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_op_o* - set_dont_verify_point -type port i:/WORK/$top_impl_name/apu_flags_o* + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_req_o + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_operands_o* + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_op_o* + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_flags_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_req_o + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_operands_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_op_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_flags_o* } verify > $summary_log From 3654122e07e8a30a6c062e897a04d3184de8dc82 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 21 Mar 2024 14:47:59 +0100 Subject: [PATCH 3/3] Updated gitignore Signed-off-by: Pascal Gouedo --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 66eb251ac..582002c7b 100644 --- a/.gitignore +++ b/.gitignore @@ -24,3 +24,4 @@ revised.src cadence_conformal synopsys_formality questa_autocheck +slec/reports