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[BUG] User Mode Counters Not Implemented. #166

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emgens opened this issue Oct 17, 2023 · 2 comments · May be fixed by #167
Open

[BUG] User Mode Counters Not Implemented. #166

emgens opened this issue Oct 17, 2023 · 2 comments · May be fixed by #167
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@szbieg

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@emgens
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emgens commented Oct 17, 2023

Bug Description

The CV32E20 Specification lists the following CSR's as implemented:

0xc00 cycle // unprivileged mode cycle, lower 32b
0xc02 instret // unprivileged mode instret, lower 32b
0xc80 cycleh // unprivileged mode cycle, upper 32b
0xc82 instreth // unprivileged mode instret, upper 32b

Attempting to read any of these CSR's in machine mode causes an illegal instruction exception. (User mode access has not yet been tested.) This is consistent with Ibex and CV32E40 handling of unimplemented CSR's.

If the desire is to implement these CSR's then functionality needs to be added to properly return data. If that is not desired, then the documentation should be updated to remove them.
@szbieg szbieg self-assigned this Oct 25, 2023
@LeeHoff
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LeeHoff commented Oct 25, 2023 •
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Are these CSRs supposed to be able to be read in machine mode? I see that the riscv-privilege spec has them as URO privilege in table 2.2. This lead me to believe that these registers are User mode Read Only. Although I don't see a definition of URO in the spec.

@emgens
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emgens commented Oct 25, 2023

From page 5 of the riscv-privilege spec:
"Note that although CSRs and instructions are associated with one privilege level, they are also accessible at all higher privilege levels."
So these registers should be readable in machine mode.

@emgens emgens linked a pull request Oct 25, 2023 that will close this issue
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@szbieg szbieg linked a pull request Nov 28, 2023 that will close this issue
[rtl] CSR cleanup #167
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[rtl] CSR cleanup NXP/openhwgroup-cve2
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@LeeHoff @szbieg @emgens