RVV：My two simd_vpu seem to be ineffective

[AlutionXian]

CPU:O3
ISA:Riscv(Rvv)
config: src/cpu/o3/FuncUnitConfig.py :count of SIMD_Unit =2

I wrote a code to do the multiplication, and the loop part looks like this:

I successfully compiled it and ran it in SE mode with this command:

But I found that "count of SIMD_Unit =2 or 1", the number of cycles is the same.
I don't know what the problem is, whether there is a wrong configuration in my GEM5 or a problem in my code?

Thanks for taking the time to read this.

[qqli579]

What is N? It is possible that N is too small and did not fill all the execution units of the vector. Another possibility is that the issue width of the vector instruction is 1. You can open O3PipeView to check the pipeline

[AlutionXian]

@qqli579 thank you for your reply ! N = 32768, i also tried N=131072,problem still persists.
I checked the trace.out generated after running it, and the vector instructions part is as follows. I think "0x10702@main +1450.0 0x10702@main+1450.1" seems to mean that instructions are being parallel.

In addition, I checked some width settings in "baseO3CPU.py","fetchwidth = Param.Unsigned(8,"Fetch width")" and so on. The width settings have not been modified and are all default.
Am I wrong in my understanding? Looking forward to hearing from you.

[qqli579]

Why is there a vmv2r_v instruction? You can put the first line of code, which is the definition of variables, inside the for loop and see the result

[AlutionXian]

@qqli579 Thank you for your suggestion！After I put the variable definition in the first line of the for loop, it showed an error of redeclaration . I dont understand about vmv2r_v, does its appearance represent any problem? Additionally, I made some attempts and the issue of 2vup being ineffective still persists.Some people say that multiple concurrent instructions need to be arranged in a for loop, and I am confused about how to implement this. Did I achieve it in my previous code?Looking forward to your reply.