Support of RISC-V Packed SIMD Instructions

[tirumalnaidu]

I’ve been following the gem5 Bootcamp 2022, and in one of the tutorials, there's an example of adding a packed SIMD instruction to the RISC-V ISA. I wanted to check if support for this instruction extension has already been added into Gem5. I wasn't able to find any relevant information in the GitHub issues or pull requests.