Heterogeneous Memory Config in Full System Mode (x86-spec-cpu2017-benchmarks.py) #1608
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LujhCoconut
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I don't have the exact solution, but I'm almost certain the memory is connected to the board in the cache_hierarchy files, generally in incorporate_cache(). Hope this helps! |
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The previous
fs.py
(configs/deprecated/example/fs.py
) has been deprecated in gem5.In this file, modifying the memory configuration can be done almost as easily as in SE mode.
I’m not very clear on the reasons for deprecating this file. I choose to use the Full System mode according to the latest tutorial.
Here is the tutorial : https://github.com/gem5/gem5-resources/blob/stable/src/spec-2017/README.md
I followed this step and executed it successfully, although it was very slow.
Now I want to configure heterogeneous memory in this configuration file, but it seems I don't know where to start.
First, in this basic configuration file
x86-spec-cpu2017-benchmarks.py
, the memory settings consist only of the following code:I attempted to delve into the Python files related to the board (
x86_board.py
) to explore how the memory is connected to the board. Unfortunately, I couldn't find where the memory is connected to any bus inx86_board.py
or in its parent classesabstract_system_board.py
andabstract_board.py
.If different memories could be properly interleaved and connected to the system bus like in SE mode, it would be easy to complete the configuration of heterogeneous memory.
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