Full System (FS) AMP simulation

[TheSSDGuy]

Dear all,

I would like to kindly ask if it is possible to create a FS platform able to simulate a full AMP system. The idea is to have two or more cores running their own program where each program has its own bootloader and linkerscript. The platform would have, one private local memory (ram) per each core and a segmented-unified rom memory where the programs are stored. I know that it is possible simulate these cases in SE mode, but the whole thing here is to get it work in FS mode so that the final system and the programs executed by the cores are much more adherent to what is done by real hw.
Any suggestions?

Many thanks in advance

[TheSSDGuy]

Dear all, after a lot of trials I came to this solution:

import m5
from m5.objects import *

system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

system.mem_mode = 'timing'

# Create the system and set the memory system
system.cluster_0 = System()
system.cluster_0.clk_domain = SrcClockDomain()
system.cluster_0.clk_domain.clock = '1GHz'
system.cluster_0.clk_domain.voltage_domain = VoltageDomain()

system.cluster_1 = System()
system.cluster_1.clk_domain = SrcClockDomain()
system.cluster_1.clk_domain.clock = '1GHz'
system.cluster_1.clk_domain.voltage_domain = VoltageDomain()

# Set the memory mode (timing)
system.cluster_0.mem_mode = 'timing'
system.cluster_1.mem_mode = 'timing'

# Define the memory map ranges
system.cluster_0.mem_ranges = [
    AddrRange(0x80000000, size='512kB'),  # ROM 0 at 0x80000000, 512KB
    AddrRange(0x80100000, size='512kB')   # RAM 0 at 0x80080000, 512KB
]

system.cluster_1.mem_ranges = [
    AddrRange(0x80080000, size='512kB'),  # ROM 1 at 0x80000000, 512KB
    AddrRange(0x80180000, size='512kB')   # RAM 1 at 0x80100000, 512KB
]

system.mem_ranges = [
    AddrRange(0x90000000, size='1MB')  # Shared memory region
]

# Create the CPUs (RISC-V) and set the ISA
system.cluster_0.cpu = RiscvTimingSimpleCPU()
system.cluster_0.cpu.ArchISA.riscv_type = "RV32"
system.cluster_0.cpu.createInterruptController()

system.cluster_1.cpu = RiscvTimingSimpleCPU()
system.cluster_1.cpu.ArchISA.riscv_type = "RV32"
system.cluster_1.cpu.createInterruptController()

# Set up a platform object for the system
system.cluster_0.platform = HiFiveBase()
system.cluster_1.platform = HiFiveBase()

# Add the RTC
system.cluster_0.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
system.cluster_1.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))

# Add the clint
system.cluster_0.platform.clint = Clint(pio_addr=0x2000000)
system.cluster_0.platform.clint.int_pin = system.cluster_0.platform.rtc.int_pin
system.cluster_0.platform.clint.num_threads = 1  # Set number of threads to match CPU count

system.cluster_1.platform.clint = Clint(pio_addr=0x2000000)
system.cluster_1.platform.clint.int_pin = system.cluster_1.platform.rtc.int_pin
system.cluster_1.platform.clint.num_threads = 1  # Set number of threads to match CPU count

# Connect a dummy plic. This basically doesn't handle any interrupts
system.cluster_0.platform.plic = Plic(pio_addr=0xC000000)
system.cluster_0.platform.plic.n_src = 0

system.cluster_1.platform.plic = Plic(pio_addr=0xC000000)
system.cluster_1.platform.plic.n_src = 0

# Setup the UART (PL011 for example)
system.cluster_0.uart = Uart8250(pio_addr=0x10000000, platform=system.cluster_0.platform)
system.cluster_1.uart = Uart8250(pio_addr=0x10001000, platform=system.cluster_1.platform)

# Set up memory bus
system.cluster_0.membus = SystemXBar()
system.cluster_1.membus = SystemXBar()

# Connect each CPU to membus
system.cluster_0.cpu.icache_port = system.cluster_0.membus.cpu_side_ports
system.cluster_0.cpu.dcache_port = system.cluster_0.membus.cpu_side_ports
system.cluster_1.cpu.icache_port = system.cluster_1.membus.cpu_side_ports
system.cluster_1.cpu.dcache_port = system.cluster_1.membus.cpu_side_ports

# Create ROM (using a simple memory device)
system.cluster_0.rom = SimpleMemory()
system.cluster_0.rom.range = system.cluster_0.mem_ranges[0]  # ROM at 0x80000000
system.cluster_0.rom.port = system.cluster_0.membus.mem_side_ports

# Create RAM (also using a simple memory device)
system.cluster_0.ram = SimpleMemory()
system.cluster_0.ram.range = system.cluster_0.mem_ranges[1]  # RAM at 0x80080000
system.cluster_0.ram.port = system.cluster_0.membus.mem_side_ports

# Create ROM (using a simple memory device)
system.cluster_1.rom = SimpleMemory()
system.cluster_1.rom.range = system.cluster_1.mem_ranges[0]  # ROM at 0x80000000
system.cluster_1.rom.port = system.cluster_1.membus.mem_side_ports

# Create RAM (also using a simple memory device)
system.cluster_1.ram = SimpleMemory()
system.cluster_1.ram.range = system.cluster_1.mem_ranges[1]  # RAM at 0x80080000
system.cluster_1.ram.port = system.cluster_1.membus.mem_side_ports

system.membus = SystemXBar()

# Create shared memory (accessible by both cores)
system.shared_memory = SimpleMemory()
system.shared_memory.range = system.mem_ranges[0]
system.shared_memory.port = system.membus.mem_side_ports

# Connect shared memory to both membuses
system.cluster_0.membus.mem_side_ports = system.membus.cpu_side_ports
system.cluster_1.membus.mem_side_ports = system.membus.cpu_side_ports
system.system_port = system.membus.cpu_side_ports

# Connect devices to the system's bus
system.cluster_0.uart.pio = system.cluster_0.membus.mem_side_ports
system.cluster_0.platform.clint.pio = system.cluster_0.membus.mem_side_ports  # Connect the CLINT to the membus
system.cluster_0.platform.plic.pio = system.cluster_0.membus.mem_side_ports  # Connect the PLIC to the membus
system.cluster_0.system_port = system.cluster_0.membus.cpu_side_ports

system.cluster_1.uart.pio = system.cluster_1.membus.mem_side_ports
system.cluster_1.platform.clint.pio = system.cluster_1.membus.mem_side_ports  # Connect the CLINT to the membus
system.cluster_1.platform.plic.pio = system.cluster_1.membus.mem_side_ports  # Connect the PLIC to the membus
system.cluster_1.system_port = system.cluster_1.membus.cpu_side_ports


# Load the binary using a Process object for each CPU
binary_cluster0 = 'bin_core0.axf'  # Path to your RISC-V binary
binary_cluster1 = 'bin_core1.axf'  # Path to your RISC-V binary

system.cluster_0.workload = RiscvBareMetal()
system.cluster_0.workload.bootloader = binary_cluster0
system.cluster_0.cpu.createThreads()

system.cluster_1.workload = RiscvBareMetal()
system.cluster_1.workload.bootloader = binary_cluster1
system.cluster_1.cpu.createThreads()

# Create a Terminal to simulate serial input/output with UART
system.cluster_0.term = Terminal()
system.cluster_0.uart.device = system.cluster_0.term

system.cluster_1.term = Terminal()
system.cluster_1.uart.device = system.cluster_1.term

# Set up the simulation root
root = Root(full_system=True, system=system)

# Instantiate the simulation
m5.instantiate()

# Run the simulation
print("Beginning simulation")
exit_event = m5.simulate()

m5.stats.dump()
m5.stats.reset()
print(f"Exited @ tick {m5.curTick()} because {exit_event.getCause()}")

Both cores can execute their program independently and both clusters have their own independent memory map.
Now I'm trying to get access to the shared memory at 0x90000000 but as soon as one of the cores tries to get access to that memory I'm getting this error:

gem5.opt: src/base/statistics.hh:1054: gem5::statistics::VectorBase<Derived, Stor>::Proxy gem5::statistics::VectorBase<Derived, Stor>::operator[](gem5::statistics::off_type) [with Derived = gem5::statistics::Vector; Stor = gem5::statistics::StatStor; Proxy = gem5::statistics::ScalarProxy<gem5::statistics::Vector>; gem5::statistics::off_type = unsigned int]: Assertion `index < size()' failed.

do you have any idea why this happens?
thanks in advance.

attached I'm sending also the resulting graph

[robhau]

Hi,

did you solve your problem?

My guess is that the stats of the base class of SimpleMemory are the problems. The vectors of MemStats are as large as the number of requestors in the system.

gem5/src/mem/abstract_mem.cc

Lines 148 to 247 in b1a44b8

	void
	AbstractMemory::MemStats::regStats()
	{
	using namespace statistics;
	statistics::Group::regStats();
	System *sys = mem.system();
	assert(sys);
	const auto max_requestors = sys->maxRequestors();
	bytesRead
	.init(max_requestors)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bytesRead.subname(i, sys->getRequestorName(i));
	}
	bytesInstRead
	.init(max_requestors)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bytesInstRead.subname(i, sys->getRequestorName(i));
	}
	bytesWritten
	.init(max_requestors)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bytesWritten.subname(i, sys->getRequestorName(i));
	}
	numReads
	.init(max_requestors)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	numReads.subname(i, sys->getRequestorName(i));
	}
	numWrites
	.init(max_requestors)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	numWrites.subname(i, sys->getRequestorName(i));
	}
	numOther
	.init(max_requestors)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	numOther.subname(i, sys->getRequestorName(i));
	}
	bwRead
	.precision(0)
	.prereq(bytesRead)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bwRead.subname(i, sys->getRequestorName(i));
	}
	bwInstRead
	.precision(0)
	.prereq(bytesInstRead)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bwInstRead.subname(i, sys->getRequestorName(i));
	}
	bwWrite
	.precision(0)
	.prereq(bytesWritten)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bwWrite.subname(i, sys->getRequestorName(i));
	}
	bwTotal
	.precision(0)
	.prereq(bwTotal)
	.flags(total | nozero | nonan)
	;
	for (int i = 0; i < max_requestors; i++) {
	bwTotal.subname(i, sys->getRequestorName(i));
	}
	bwRead = bytesRead / simSeconds;
	bwInstRead = bytesInstRead / simSeconds;
	bwWrite = bytesWritten / simSeconds;
	bwTotal = (bytesRead + bytesWritten) / simSeconds;
	}

Since your CPUs is in a subsystem, this might be a problem. You could simply check if my theory is true by printing out max_requestors and end every requestor name (sys->getRequestorName(RequestorID requestor_id)).