From 338d4c1e8df55363a57ac3e936ffc6ce86e7e016 Mon Sep 17 00:00:00 2001 From: Massimiliano Giacometti Date: Sun, 24 Mar 2024 14:46:48 +0100 Subject: [PATCH] license --- vendor/planv/ace/README.md | 3 +++ vendor/planv/ace/src/ccu_fsm.sv | 4 ++++ vendor/planv_ace.lock.hjson | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/vendor/planv/ace/README.md b/vendor/planv/ace/README.md index 404217b0c6..e66e6876e0 100644 --- a/vendor/planv/ace/README.md +++ b/vendor/planv/ace/README.md @@ -8,3 +8,6 @@ This repository provides modules to implement cache coherence SoC's. |------------------------------------------------------|--------------------------------------------------------------------------------------------------------------|--------------------------------| | [`ace_ccu_top`](src/ace_ccu_top.sv) | ACE interconnector, broadcasts snooping messages to the cache controllers and AXI transactions to the slave | [Doc](doc/ace_ccu_top.md) | +## License + +The ACE repository is released under Solderpad v0.51 (SHL-0.51) see [LICENSE](LICENSE) \ No newline at end of file diff --git a/vendor/planv/ace/src/ccu_fsm.sv b/vendor/planv/ace/src/ccu_fsm.sv index 1150178d91..f1cfe879eb 100644 --- a/vendor/planv/ace/src/ccu_fsm.sv +++ b/vendor/planv/ace/src/ccu_fsm.sv @@ -1,3 +1,7 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + `include "ace/assign.svh" `include "ace/typedef.svh" diff --git a/vendor/planv_ace.lock.hjson b/vendor/planv_ace.lock.hjson index 032d25cb6f..81204fb7db 100644 --- a/vendor/planv_ace.lock.hjson +++ b/vendor/planv_ace.lock.hjson @@ -9,6 +9,6 @@ upstream: { url: https://github.com/planvtech/ace.git - rev: d80ae1727aae2ebf280a99c273ddde0fcac3df62 + rev: f919f5cabf41961321bf37327ab4eb726dfdbd0c } }