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Generic Register Interface

This repository contains a simple register interface definition as well as protocol adapters from APB, AXI-Lite, and AXI to said interface. Furthermore, it allows to generate a uniform register interface.

Read Timing

Read Timing

Write Timing

Write Timing

Register File Generator

We re-use lowrisc's register file generator to generate arbitrary configuration registers from an hjson description. See the the tool's description for further usage details.

We use the bender import tool (>v0.26.0) to get the sources and apply our custom patches on top.

curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- 0.26.0
./bender import --refetch

to re-vendor.