Bump chipyard to build circt from source (#1)

* Bump testchipip for improved TLSerdesser * Remove bringup vcu118 * Bump firechip * Bump testchipip * Bump testchipip * Make symmetric test clearer * Bump testchipip * doc: Update FireSim docs * Enabling JTAG Debuging in VCU118 FPGA * Fix invalid escape sequences In Python 3.12, these show up as SyntaxWarning messages. * Add coherent chiplet config * bump to verilator v5.022 * Add LLCChiplet to CI * Bump testchipip * Bump firesim * [cd] Bump CIRCT from firtool-1.61.0 to firtool-1.66.0 This is an automated commit generated by the `circt/update-circt` GitHub Action. (cherry picked from commit dc02e40) * Bump FireMarshal * Bump FireMarshal * Bump Gemmini to dev * Bump for CIRCT | Fix style * Use statically linked CIRCT * Bump testchipip * Bump FireMarshal * Add script to build circt-from-source - from submodule * Add --build-circt flag to build-setup * Build CIRCT in release mode * Don't checkout CIRCT with init-submods.sh * Always checkout CIRCT/LLVM shallow * Set CIRCT/llvm branch * Add old TLSerdes * Fix build-setup.sh typo Co-authored-by: Abraham Gonzalez <[email protected]> * Fix build-circt-from-source * feat: Add HPU * Add MultiRoCC config for HPU * Update to new HPU module name * Add system bus width * misc: Bump HPU into v0.2.0 * feat: Add HPU SoC config for FireSim * feat: Replace FireSim repo with our fork * fix: Create config soft link for build-setup * misc: Bump firesim * feat: Bump HPU for FireSim support --------- Co-authored-by: Jerry Zhao <[email protected]> Co-authored-by: Sungkeun Kim <[email protected]> Co-authored-by: Jerry Zhao <[email protected]> Co-authored-by: Tynan McAuley <[email protected]> Co-authored-by: Vighnesh Iyer <[email protected]> Co-authored-by: Vighnesh Iyer <[email protected]> Co-authored-by: bartender <[email protected]> Co-authored-by: abejgonzalez <[email protected]> Co-authored-by: Allen Pan <[email protected]>
riscv-hdc · Mar 4, 2024 · 7994f86 · 7994f86
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diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
@@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -59,6 +59,7 @@ mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_S
 mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
 mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
+mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"

diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
@@ -122,6 +122,10 @@ case $1 in
         make -C $LOCAL_CHIPYARD_DIR/tests
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
         ;;
+    chipyard-llcchiplet)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;

diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
@@ -731,6 +731,29 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-symmetric"
 
+  chipyard-llcchiplet-run-tests:
+    name: chipyard-llcchiplet-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-llcchiplet"
+
   chipyard-sha3-run-tests:
     name: chipyard-sha3-run-tests
     needs: prepare-chipyard-accels
@@ -1095,6 +1118,7 @@ jobs:
             chipyard-manyperipherals-run-tests,
             chipyard-tethered-run-tests,
             chipyard-symmetric-run-tests,
+            chipyard-llcchiplet-run-tests,
             chipyard-sha3-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,

diff --git a/.gitmodules b/.gitmodules
@@ -148,6 +148,9 @@
 [submodule "generators/rocket-chip-inclusive-cache"]
 	path = generators/rocket-chip-inclusive-cache
 	url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
+[submodule "tools/circt"]
+	path = tools/circt
+	url = https://github.com/llvm/circt.git
 [submodule "generators/hpu"]
 	path = generators/hpu
 	url = https://github.com/allpan3/Hyper.git
diff --git a/common.mk b/common.mk
@@ -193,7 +193,7 @@ SFC_MFC_TARGETS = \
 	$(GEN_COLLATERAL_DIR)
 
 SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
-MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
+MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
 
 # DOC include start: FirrtlCompiler
 # There are two possible cases for this step. In the first case, SFC

diff --git a/conda-reqs/chipyard-base.yaml b/conda-reqs/chipyard-base.yaml
@@ -31,5 +31,5 @@ dependencies:
     - sbt
     - openjdk=20
     - dtc
-    - verilator==5.020
+    - verilator==5.022
     - conda-lock=1.4
diff --git a/conda-reqs/circt.json b/conda-reqs/circt.json
@@ -1,3 +1,3 @@
 {
-  "version": "firtool-1.61.0"
+  "version": "firtool-1.66.0"
 }