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Adding Zilsd and Zcmlsd extension #250

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Adding Zilsd and Zcmlsd extension #250

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6 changes: 6 additions & 0 deletions arg_lut.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -98,3 +98,9 @@
"c_rs2", 6, 2
"c_sreg1", 9, 7
"c_sreg2", 4, 2
"rd_p_e", 4, 3
"rs2_p_e", 4, 3
"rd_n0_e", 11, 8
"c_rs2_e", 6, 3
"rd_e", 11, 8
"rs2_e", 24, 21
7 changes: 7 additions & 0 deletions constants.py
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Original file line number Diff line number Diff line change
Expand Up @@ -116,6 +116,13 @@
latex_mapping['c_uimm10sp_s'] = 'uimm[5:4$\\vert$9:6]'
latex_mapping['c_uimm9sp_s'] = 'uimm[5:3$\\vert$8:6]'

latex_mapping['rd_p_e'] = "rd\\,$'$, even values only"
latex_mapping['rs2_p_e'] = "rs2\\,$'$, even values only"
latex_mapping['rd_n0_e'] = 'rd$\\neq$0, even values only'
latex_mapping['c_rs2_e'] = 'rs2, even values only'
latex_mapping['rd_e'] = 'rd, even values only'
latex_mapping['rs2_e'] = 'rs2, even values only'

# created a dummy instruction-dictionary like dictionary for all the instruction
# types so that the same logic can be used to create their tables
latex_inst_type = {}
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10 changes: 10 additions & 0 deletions unratified/rv32_zcmlsd
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@@ -0,0 +1,10 @@
# Compressed load/store pair for RV32

# quadrant 0
$pseudo_op rv32_c_f::c.flw c.ld rd_p_e rs1_p c_uimm8lo c_uimm8hi 2..0=0 15..13=3
$pseudo_op rv32_c_f::c.fsw c.sd rs1_p rs2_p_e c_uimm8hi c_uimm8lo 2..0=0 15..13=7

#quadrant 2
$pseudo_op rv32_c_f::c.flwsp c.ldsp rd_n0_e c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 7=0
$pseudo_op rv32_c_f::c.fswsp c.sdsp c_rs2_e c_uimm9sp_s 2..0=2 15..13=7

4 changes: 4 additions & 0 deletions unratified/rv32_zilsd
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Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
# Load/store pair for RV32

ld rd_e rs1 imm12 14..12=3 7..2=0x00 1..0=3
sd imm12hi rs1 rs2_e imm12lo 20=0 14..12=3 6..2=0x08 1..0=3