Add more SIMD intrinsics

rust-lang · Sep 6, 2024 · 62f44d7 · 62f44d7
1 parent cb0b519
commit 62f44d7
Showing 1 changed file with 45 additions and 0 deletions.
diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs
@@ -418,6 +418,27 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
                 new_args.push(old_args.swap_remove(0));
                 args = new_args.into();
             }
+            "__builtin_ia32_addph512_mask_round"
+            | "__builtin_ia32_subph512_mask_round"
+            | "__builtin_ia32_mulph512_mask_round"
+            | "__builtin_ia32_divph512_mask_round" => {
+                let mut new_args = args.to_vec();
+                let last_arg = new_args.pop().expect("last arg");
+
+                let arg3_type = gcc_func.get_param_type(2);
+                let vector_type = arg3_type.dyncast_vector().expect("vector type");
+                let zero = builder.context.new_rvalue_zero(vector_type.get_element_type());
+                let num_units = vector_type.get_num_units();
+                let first_arg =
+                    builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]);
+                new_args.push(first_arg);
+
+                let arg4_type = gcc_func.get_param_type(3);
+                let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
+                new_args.push(minus_one);
+                new_args.push(last_arg);
+                args = new_args.into();
+            }
             _ => (),
         }
     } else {
@@ -1094,6 +1115,23 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.avx512.mask.load.q.256" => "__builtin_ia32_movdqa64load256_mask",
         "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask_round",
         "llvm.x86.avx512fp16.vcomi.sh" => "__builtin_ia32_cmpsh_mask_round",
+        "llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512_mask_round",
+        "llvm.x86.avx512fp16.sub.ph.512" => "__builtin_ia32_subph512_mask_round",
+        "llvm.x86.avx512fp16.mul.ph.512" => "__builtin_ia32_mulph512_mask_round",
+        "llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512_mask_round",
+        "llvm.x86.avx512fp16.mask.vfmul.cph.512" => "__builtin_ia32_vfmulcph512_mask_round",
+        "llvm.x86.avx512fp16.mask.vfmul.csh" => "__builtin_ia32_vfmulcsh_mask_round",
+        "llvm.x86.avx512fp16.mask.vfcmul.cph.512" => "__builtin_ia32_vfcmulcph512_mask_round",
+        "llvm.x86.avx512fp16.mask.vfcmul.csh" => "__builtin_ia32_vfcmulcsh_mask_round",
+        "llvm.x86.avx512fp16.mask.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_mask3_round",
+        "llvm.x86.avx512fp16.maskz.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_maskz_round",
+        "llvm.x86.avx512fp16.mask.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_mask3_round",
+        "llvm.x86.avx512fp16.maskz.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_maskz_round",
+        "llvm.x86.avx512fp16.mask.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_mask3_round",
+        "llvm.x86.avx512fp16.maskz.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_maskz_round",
+        "llvm.x86.avx512fp16.mask.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_mask_round",
+        "llvm.x86.avx512fp16.maskz.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_maskz_round",
+
         // TODO: support the tile builtins:
         "llvm.x86.ldtilecfg" => "__builtin_trap",
         "llvm.x86.sttilecfg" => "__builtin_trap",
@@ -1103,6 +1141,13 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.tileloaddt164" => "__builtin_trap",
         "llvm.x86.tilezero" => "__builtin_trap",
         "llvm.x86.tdpbf16ps" => "__builtin_trap",
+        "llvm.x86.tdpbssd" => "__builtin_trap",
+        "llvm.x86.tdpbsud" => "__builtin_trap",
+        "llvm.x86.tdpbusd" => "__builtin_trap",
+        "llvm.x86.tdpbuud" => "__builtin_trap",
+        "llvm.x86.tdpfp16ps" => "__builtin_trap",
+        "llvm.x86.tcmmimfp16ps" => "__builtin_trap",
+        "llvm.x86.tcmmrlfp16ps" => "__builtin_trap",
 
         // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
         _ => include!("archs.rs"),