forked from klauspost/reedsolomon
-
Notifications
You must be signed in to change notification settings - Fork 0
/
galois_gen_amd64.s
20243 lines (19257 loc) · 414 KB
/
galois_gen_amd64.s
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Code generated by command: go run gen.go -out galois_gen_amd64.s -stubs galois_gen_amd64.go. DO NOT EDIT.
// +build !appengine
// +build !noasm
// +build !nogen
// +build gc
// func mulAvxTwo_1x1(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x1(SB), $0-88
// Loading all tables to registers
// Destination kept in GP registers
// Full registers estimated 6 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x1_end
VMOVDQU (CX), Y0
VMOVDQU 32(CX), Y1
MOVQ in_base+24(FP), CX
MOVQ (CX), CX
MOVQ out_base+48(FP), DX
MOVQ (DX), DX
MOVQ start+72(FP), BX
// Add start offset to output
ADDQ BX, DX
// Add start offset to input
ADDQ BX, CX
MOVQ $0x0000000f, BX
MOVQ BX, X3
VPBROADCASTB X3, Y3
mulAvxTwo_1x1_loop:
// Clear 1 outputs
VPXOR Y2, Y2, Y2
// Load and process 32 bytes from input 0 to 1 outputs
VMOVDQU (CX), Y4
ADDQ $0x20, CX
VPSRLQ $0x04, Y4, Y5
VPAND Y3, Y4, Y4
VPAND Y3, Y5, Y5
VPSHUFB Y4, Y0, Y4
VPSHUFB Y5, Y1, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y2, Y2
// Store 1 outputs
VMOVDQU Y2, (DX)
ADDQ $0x20, DX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x1_loop
VZEROUPPER
mulAvxTwo_1x1_end:
RET
// func mulAvxTwo_1x2(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x2(SB), $0-88
// Loading all tables to registers
// Destination kept in GP registers
// Full registers estimated 11 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x2_end
VMOVDQU (CX), Y0
VMOVDQU 32(CX), Y1
VMOVDQU 64(CX), Y2
VMOVDQU 96(CX), Y3
MOVQ in_base+24(FP), CX
MOVQ (CX), CX
MOVQ out_base+48(FP), DX
MOVQ (DX), BX
MOVQ 24(DX), DX
MOVQ start+72(FP), BP
// Add start offset to output
ADDQ BP, BX
ADDQ BP, DX
// Add start offset to input
ADDQ BP, CX
MOVQ $0x0000000f, BP
MOVQ BP, X6
VPBROADCASTB X6, Y6
mulAvxTwo_1x2_loop:
// Clear 2 outputs
VPXOR Y4, Y4, Y4
VPXOR Y5, Y5, Y5
// Load and process 32 bytes from input 0 to 2 outputs
VMOVDQU (CX), Y9
ADDQ $0x20, CX
VPSRLQ $0x04, Y9, Y10
VPAND Y6, Y9, Y9
VPAND Y6, Y10, Y10
VPSHUFB Y9, Y0, Y7
VPSHUFB Y10, Y1, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y4, Y4
VPSHUFB Y9, Y2, Y7
VPSHUFB Y10, Y3, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y5, Y5
// Store 2 outputs
VMOVDQU Y4, (BX)
ADDQ $0x20, BX
VMOVDQU Y5, (DX)
ADDQ $0x20, DX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x2_loop
VZEROUPPER
mulAvxTwo_1x2_end:
RET
// func mulAvxTwo_1x3(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x3(SB), $0-88
// Loading all tables to registers
// Destination kept in GP registers
// Full registers estimated 14 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x3_end
VMOVDQU (CX), Y0
VMOVDQU 32(CX), Y1
VMOVDQU 64(CX), Y2
VMOVDQU 96(CX), Y3
VMOVDQU 128(CX), Y4
VMOVDQU 160(CX), Y5
MOVQ in_base+24(FP), CX
MOVQ (CX), CX
MOVQ out_base+48(FP), DX
MOVQ (DX), BX
MOVQ 24(DX), BP
MOVQ 48(DX), DX
MOVQ start+72(FP), SI
// Add start offset to output
ADDQ SI, BX
ADDQ SI, BP
ADDQ SI, DX
// Add start offset to input
ADDQ SI, CX
MOVQ $0x0000000f, SI
MOVQ SI, X9
VPBROADCASTB X9, Y9
mulAvxTwo_1x3_loop:
// Clear 3 outputs
VPXOR Y6, Y6, Y6
VPXOR Y7, Y7, Y7
VPXOR Y8, Y8, Y8
// Load and process 32 bytes from input 0 to 3 outputs
VMOVDQU (CX), Y12
ADDQ $0x20, CX
VPSRLQ $0x04, Y12, Y13
VPAND Y9, Y12, Y12
VPAND Y9, Y13, Y13
VPSHUFB Y12, Y0, Y10
VPSHUFB Y13, Y1, Y11
VPXOR Y10, Y11, Y10
VPXOR Y10, Y6, Y6
VPSHUFB Y12, Y2, Y10
VPSHUFB Y13, Y3, Y11
VPXOR Y10, Y11, Y10
VPXOR Y10, Y7, Y7
VPSHUFB Y12, Y4, Y10
VPSHUFB Y13, Y5, Y11
VPXOR Y10, Y11, Y10
VPXOR Y10, Y8, Y8
// Store 3 outputs
VMOVDQU Y6, (BX)
ADDQ $0x20, BX
VMOVDQU Y7, (BP)
ADDQ $0x20, BP
VMOVDQU Y8, (DX)
ADDQ $0x20, DX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x3_loop
VZEROUPPER
mulAvxTwo_1x3_end:
RET
// func mulAvxTwo_1x4(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x4(SB), $0-88
// Loading no tables to registers
// Destination kept in GP registers
// Full registers estimated 17 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x4_end
MOVQ in_base+24(FP), DX
MOVQ (DX), DX
MOVQ out_base+48(FP), BX
MOVQ (BX), BP
MOVQ 24(BX), SI
MOVQ 48(BX), DI
MOVQ 72(BX), BX
MOVQ start+72(FP), R8
// Add start offset to output
ADDQ R8, BP
ADDQ R8, SI
ADDQ R8, DI
ADDQ R8, BX
// Add start offset to input
ADDQ R8, DX
MOVQ $0x0000000f, R8
MOVQ R8, X4
VPBROADCASTB X4, Y4
mulAvxTwo_1x4_loop:
// Clear 4 outputs
VPXOR Y0, Y0, Y0
VPXOR Y1, Y1, Y1
VPXOR Y2, Y2, Y2
VPXOR Y3, Y3, Y3
// Load and process 32 bytes from input 0 to 4 outputs
VMOVDQU (DX), Y7
ADDQ $0x20, DX
VPSRLQ $0x04, Y7, Y8
VPAND Y4, Y7, Y7
VPAND Y4, Y8, Y8
VMOVDQU (CX), Y5
VMOVDQU 32(CX), Y6
VPSHUFB Y7, Y5, Y5
VPSHUFB Y8, Y6, Y6
VPXOR Y5, Y6, Y5
VPXOR Y5, Y0, Y0
VMOVDQU 64(CX), Y5
VMOVDQU 96(CX), Y6
VPSHUFB Y7, Y5, Y5
VPSHUFB Y8, Y6, Y6
VPXOR Y5, Y6, Y5
VPXOR Y5, Y1, Y1
VMOVDQU 128(CX), Y5
VMOVDQU 160(CX), Y6
VPSHUFB Y7, Y5, Y5
VPSHUFB Y8, Y6, Y6
VPXOR Y5, Y6, Y5
VPXOR Y5, Y2, Y2
VMOVDQU 192(CX), Y5
VMOVDQU 224(CX), Y6
VPSHUFB Y7, Y5, Y5
VPSHUFB Y8, Y6, Y6
VPXOR Y5, Y6, Y5
VPXOR Y5, Y3, Y3
// Store 4 outputs
VMOVDQU Y0, (BP)
ADDQ $0x20, BP
VMOVDQU Y1, (SI)
ADDQ $0x20, SI
VMOVDQU Y2, (DI)
ADDQ $0x20, DI
VMOVDQU Y3, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x4_loop
VZEROUPPER
mulAvxTwo_1x4_end:
RET
// func mulAvxTwo_1x5(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x5(SB), $0-88
// Loading no tables to registers
// Destination kept in GP registers
// Full registers estimated 20 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x5_end
MOVQ in_base+24(FP), DX
MOVQ (DX), DX
MOVQ out_base+48(FP), BX
MOVQ (BX), BP
MOVQ 24(BX), SI
MOVQ 48(BX), DI
MOVQ 72(BX), R8
MOVQ 96(BX), BX
MOVQ start+72(FP), R9
// Add start offset to output
ADDQ R9, BP
ADDQ R9, SI
ADDQ R9, DI
ADDQ R9, R8
ADDQ R9, BX
// Add start offset to input
ADDQ R9, DX
MOVQ $0x0000000f, R9
MOVQ R9, X5
VPBROADCASTB X5, Y5
mulAvxTwo_1x5_loop:
// Clear 5 outputs
VPXOR Y0, Y0, Y0
VPXOR Y1, Y1, Y1
VPXOR Y2, Y2, Y2
VPXOR Y3, Y3, Y3
VPXOR Y4, Y4, Y4
// Load and process 32 bytes from input 0 to 5 outputs
VMOVDQU (DX), Y8
ADDQ $0x20, DX
VPSRLQ $0x04, Y8, Y9
VPAND Y5, Y8, Y8
VPAND Y5, Y9, Y9
VMOVDQU (CX), Y6
VMOVDQU 32(CX), Y7
VPSHUFB Y8, Y6, Y6
VPSHUFB Y9, Y7, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y0, Y0
VMOVDQU 64(CX), Y6
VMOVDQU 96(CX), Y7
VPSHUFB Y8, Y6, Y6
VPSHUFB Y9, Y7, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y1, Y1
VMOVDQU 128(CX), Y6
VMOVDQU 160(CX), Y7
VPSHUFB Y8, Y6, Y6
VPSHUFB Y9, Y7, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y2, Y2
VMOVDQU 192(CX), Y6
VMOVDQU 224(CX), Y7
VPSHUFB Y8, Y6, Y6
VPSHUFB Y9, Y7, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y3, Y3
VMOVDQU 256(CX), Y6
VMOVDQU 288(CX), Y7
VPSHUFB Y8, Y6, Y6
VPSHUFB Y9, Y7, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y4, Y4
// Store 5 outputs
VMOVDQU Y0, (BP)
ADDQ $0x20, BP
VMOVDQU Y1, (SI)
ADDQ $0x20, SI
VMOVDQU Y2, (DI)
ADDQ $0x20, DI
VMOVDQU Y3, (R8)
ADDQ $0x20, R8
VMOVDQU Y4, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x5_loop
VZEROUPPER
mulAvxTwo_1x5_end:
RET
// func mulAvxTwo_1x6(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x6(SB), $0-88
// Loading no tables to registers
// Destination kept in GP registers
// Full registers estimated 23 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x6_end
MOVQ in_base+24(FP), DX
MOVQ (DX), DX
MOVQ out_base+48(FP), BX
MOVQ (BX), BP
MOVQ 24(BX), SI
MOVQ 48(BX), DI
MOVQ 72(BX), R8
MOVQ 96(BX), R9
MOVQ 120(BX), BX
MOVQ start+72(FP), R10
// Add start offset to output
ADDQ R10, BP
ADDQ R10, SI
ADDQ R10, DI
ADDQ R10, R8
ADDQ R10, R9
ADDQ R10, BX
// Add start offset to input
ADDQ R10, DX
MOVQ $0x0000000f, R10
MOVQ R10, X6
VPBROADCASTB X6, Y6
mulAvxTwo_1x6_loop:
// Clear 6 outputs
VPXOR Y0, Y0, Y0
VPXOR Y1, Y1, Y1
VPXOR Y2, Y2, Y2
VPXOR Y3, Y3, Y3
VPXOR Y4, Y4, Y4
VPXOR Y5, Y5, Y5
// Load and process 32 bytes from input 0 to 6 outputs
VMOVDQU (DX), Y9
ADDQ $0x20, DX
VPSRLQ $0x04, Y9, Y10
VPAND Y6, Y9, Y9
VPAND Y6, Y10, Y10
VMOVDQU (CX), Y7
VMOVDQU 32(CX), Y8
VPSHUFB Y9, Y7, Y7
VPSHUFB Y10, Y8, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y0, Y0
VMOVDQU 64(CX), Y7
VMOVDQU 96(CX), Y8
VPSHUFB Y9, Y7, Y7
VPSHUFB Y10, Y8, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y1, Y1
VMOVDQU 128(CX), Y7
VMOVDQU 160(CX), Y8
VPSHUFB Y9, Y7, Y7
VPSHUFB Y10, Y8, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y2, Y2
VMOVDQU 192(CX), Y7
VMOVDQU 224(CX), Y8
VPSHUFB Y9, Y7, Y7
VPSHUFB Y10, Y8, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y3, Y3
VMOVDQU 256(CX), Y7
VMOVDQU 288(CX), Y8
VPSHUFB Y9, Y7, Y7
VPSHUFB Y10, Y8, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y4, Y4
VMOVDQU 320(CX), Y7
VMOVDQU 352(CX), Y8
VPSHUFB Y9, Y7, Y7
VPSHUFB Y10, Y8, Y8
VPXOR Y7, Y8, Y7
VPXOR Y7, Y5, Y5
// Store 6 outputs
VMOVDQU Y0, (BP)
ADDQ $0x20, BP
VMOVDQU Y1, (SI)
ADDQ $0x20, SI
VMOVDQU Y2, (DI)
ADDQ $0x20, DI
VMOVDQU Y3, (R8)
ADDQ $0x20, R8
VMOVDQU Y4, (R9)
ADDQ $0x20, R9
VMOVDQU Y5, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x6_loop
VZEROUPPER
mulAvxTwo_1x6_end:
RET
// func mulAvxTwo_1x7(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x7(SB), $0-88
// Loading no tables to registers
// Destination kept in GP registers
// Full registers estimated 26 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x7_end
MOVQ in_base+24(FP), DX
MOVQ (DX), DX
MOVQ out_base+48(FP), BX
MOVQ (BX), BP
MOVQ 24(BX), SI
MOVQ 48(BX), DI
MOVQ 72(BX), R8
MOVQ 96(BX), R9
MOVQ 120(BX), R10
MOVQ 144(BX), BX
MOVQ start+72(FP), R11
// Add start offset to output
ADDQ R11, BP
ADDQ R11, SI
ADDQ R11, DI
ADDQ R11, R8
ADDQ R11, R9
ADDQ R11, R10
ADDQ R11, BX
// Add start offset to input
ADDQ R11, DX
MOVQ $0x0000000f, R11
MOVQ R11, X7
VPBROADCASTB X7, Y7
mulAvxTwo_1x7_loop:
// Clear 7 outputs
VPXOR Y0, Y0, Y0
VPXOR Y1, Y1, Y1
VPXOR Y2, Y2, Y2
VPXOR Y3, Y3, Y3
VPXOR Y4, Y4, Y4
VPXOR Y5, Y5, Y5
VPXOR Y6, Y6, Y6
// Load and process 32 bytes from input 0 to 7 outputs
VMOVDQU (DX), Y10
ADDQ $0x20, DX
VPSRLQ $0x04, Y10, Y11
VPAND Y7, Y10, Y10
VPAND Y7, Y11, Y11
VMOVDQU (CX), Y8
VMOVDQU 32(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y0, Y0
VMOVDQU 64(CX), Y8
VMOVDQU 96(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y1, Y1
VMOVDQU 128(CX), Y8
VMOVDQU 160(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y2, Y2
VMOVDQU 192(CX), Y8
VMOVDQU 224(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y3, Y3
VMOVDQU 256(CX), Y8
VMOVDQU 288(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y4, Y4
VMOVDQU 320(CX), Y8
VMOVDQU 352(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y5, Y5
VMOVDQU 384(CX), Y8
VMOVDQU 416(CX), Y9
VPSHUFB Y10, Y8, Y8
VPSHUFB Y11, Y9, Y9
VPXOR Y8, Y9, Y8
VPXOR Y8, Y6, Y6
// Store 7 outputs
VMOVDQU Y0, (BP)
ADDQ $0x20, BP
VMOVDQU Y1, (SI)
ADDQ $0x20, SI
VMOVDQU Y2, (DI)
ADDQ $0x20, DI
VMOVDQU Y3, (R8)
ADDQ $0x20, R8
VMOVDQU Y4, (R9)
ADDQ $0x20, R9
VMOVDQU Y5, (R10)
ADDQ $0x20, R10
VMOVDQU Y6, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x7_loop
VZEROUPPER
mulAvxTwo_1x7_end:
RET
// func mulAvxTwo_1x8(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_1x8(SB), $0-88
// Loading no tables to registers
// Destination kept in GP registers
// Full registers estimated 29 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_1x8_end
MOVQ in_base+24(FP), DX
MOVQ (DX), DX
MOVQ out_base+48(FP), BX
MOVQ (BX), BP
MOVQ 24(BX), SI
MOVQ 48(BX), DI
MOVQ 72(BX), R8
MOVQ 96(BX), R9
MOVQ 120(BX), R10
MOVQ 144(BX), R11
MOVQ 168(BX), BX
MOVQ start+72(FP), R12
// Add start offset to output
ADDQ R12, BP
ADDQ R12, SI
ADDQ R12, DI
ADDQ R12, R8
ADDQ R12, R9
ADDQ R12, R10
ADDQ R12, R11
ADDQ R12, BX
// Add start offset to input
ADDQ R12, DX
MOVQ $0x0000000f, R12
MOVQ R12, X8
VPBROADCASTB X8, Y8
mulAvxTwo_1x8_loop:
// Clear 8 outputs
VPXOR Y0, Y0, Y0
VPXOR Y1, Y1, Y1
VPXOR Y2, Y2, Y2
VPXOR Y3, Y3, Y3
VPXOR Y4, Y4, Y4
VPXOR Y5, Y5, Y5
VPXOR Y6, Y6, Y6
VPXOR Y7, Y7, Y7
// Load and process 32 bytes from input 0 to 8 outputs
VMOVDQU (DX), Y11
ADDQ $0x20, DX
VPSRLQ $0x04, Y11, Y12
VPAND Y8, Y11, Y11
VPAND Y8, Y12, Y12
VMOVDQU (CX), Y9
VMOVDQU 32(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y0, Y0
VMOVDQU 64(CX), Y9
VMOVDQU 96(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y1, Y1
VMOVDQU 128(CX), Y9
VMOVDQU 160(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y2, Y2
VMOVDQU 192(CX), Y9
VMOVDQU 224(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y3, Y3
VMOVDQU 256(CX), Y9
VMOVDQU 288(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y4, Y4
VMOVDQU 320(CX), Y9
VMOVDQU 352(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y5, Y5
VMOVDQU 384(CX), Y9
VMOVDQU 416(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y6, Y6
VMOVDQU 448(CX), Y9
VMOVDQU 480(CX), Y10
VPSHUFB Y11, Y9, Y9
VPSHUFB Y12, Y10, Y10
VPXOR Y9, Y10, Y9
VPXOR Y9, Y7, Y7
// Store 8 outputs
VMOVDQU Y0, (BP)
ADDQ $0x20, BP
VMOVDQU Y1, (SI)
ADDQ $0x20, SI
VMOVDQU Y2, (DI)
ADDQ $0x20, DI
VMOVDQU Y3, (R8)
ADDQ $0x20, R8
VMOVDQU Y4, (R9)
ADDQ $0x20, R9
VMOVDQU Y5, (R10)
ADDQ $0x20, R10
VMOVDQU Y6, (R11)
ADDQ $0x20, R11
VMOVDQU Y7, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_1x8_loop
VZEROUPPER
mulAvxTwo_1x8_end:
RET
// func mulAvxTwo_2x1(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_2x1(SB), $0-88
// Loading all tables to registers
// Destination kept in GP registers
// Full registers estimated 8 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_2x1_end
VMOVDQU (CX), Y0
VMOVDQU 32(CX), Y1
VMOVDQU 64(CX), Y2
VMOVDQU 96(CX), Y3
MOVQ in_base+24(FP), CX
MOVQ (CX), DX
MOVQ 24(CX), CX
MOVQ out_base+48(FP), BX
MOVQ (BX), BX
MOVQ start+72(FP), BP
// Add start offset to output
ADDQ BP, BX
// Add start offset to input
ADDQ BP, DX
ADDQ BP, CX
MOVQ $0x0000000f, BP
MOVQ BP, X5
VPBROADCASTB X5, Y5
mulAvxTwo_2x1_loop:
// Clear 1 outputs
VPXOR Y4, Y4, Y4
// Load and process 32 bytes from input 0 to 1 outputs
VMOVDQU (DX), Y6
ADDQ $0x20, DX
VPSRLQ $0x04, Y6, Y7
VPAND Y5, Y6, Y6
VPAND Y5, Y7, Y7
VPSHUFB Y6, Y0, Y6
VPSHUFB Y7, Y1, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y4, Y4
// Load and process 32 bytes from input 1 to 1 outputs
VMOVDQU (CX), Y6
ADDQ $0x20, CX
VPSRLQ $0x04, Y6, Y7
VPAND Y5, Y6, Y6
VPAND Y5, Y7, Y7
VPSHUFB Y6, Y2, Y6
VPSHUFB Y7, Y3, Y7
VPXOR Y6, Y7, Y6
VPXOR Y6, Y4, Y4
// Store 1 outputs
VMOVDQU Y4, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_2x1_loop
VZEROUPPER
mulAvxTwo_2x1_end:
RET
// func mulAvxTwo_2x2(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_2x2(SB), $0-88
// Loading all tables to registers
// Destination kept in GP registers
// Full registers estimated 15 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_2x2_end
VMOVDQU (CX), Y0
VMOVDQU 32(CX), Y1
VMOVDQU 64(CX), Y2
VMOVDQU 96(CX), Y3
VMOVDQU 128(CX), Y4
VMOVDQU 160(CX), Y5
VMOVDQU 192(CX), Y6
VMOVDQU 224(CX), Y7
MOVQ in_base+24(FP), CX
MOVQ (CX), DX
MOVQ 24(CX), CX
MOVQ out_base+48(FP), BX
MOVQ (BX), BP
MOVQ 24(BX), BX
MOVQ start+72(FP), SI
// Add start offset to output
ADDQ SI, BP
ADDQ SI, BX
// Add start offset to input
ADDQ SI, DX
ADDQ SI, CX
MOVQ $0x0000000f, SI
MOVQ SI, X10
VPBROADCASTB X10, Y10
mulAvxTwo_2x2_loop:
// Clear 2 outputs
VPXOR Y8, Y8, Y8
VPXOR Y9, Y9, Y9
// Load and process 32 bytes from input 0 to 2 outputs
VMOVDQU (DX), Y13
ADDQ $0x20, DX
VPSRLQ $0x04, Y13, Y14
VPAND Y10, Y13, Y13
VPAND Y10, Y14, Y14
VPSHUFB Y13, Y0, Y11
VPSHUFB Y14, Y1, Y12
VPXOR Y11, Y12, Y11
VPXOR Y11, Y8, Y8
VPSHUFB Y13, Y2, Y11
VPSHUFB Y14, Y3, Y12
VPXOR Y11, Y12, Y11
VPXOR Y11, Y9, Y9
// Load and process 32 bytes from input 1 to 2 outputs
VMOVDQU (CX), Y13
ADDQ $0x20, CX
VPSRLQ $0x04, Y13, Y14
VPAND Y10, Y13, Y13
VPAND Y10, Y14, Y14
VPSHUFB Y13, Y4, Y11
VPSHUFB Y14, Y5, Y12
VPXOR Y11, Y12, Y11
VPXOR Y11, Y8, Y8
VPSHUFB Y13, Y6, Y11
VPSHUFB Y14, Y7, Y12
VPXOR Y11, Y12, Y11
VPXOR Y11, Y9, Y9
// Store 2 outputs
VMOVDQU Y8, (BP)
ADDQ $0x20, BP
VMOVDQU Y9, (BX)
ADDQ $0x20, BX
// Prepare for next loop
DECQ AX
JNZ mulAvxTwo_2x2_loop
VZEROUPPER
mulAvxTwo_2x2_end:
RET
// func mulAvxTwo_2x3(matrix []byte, in [][]byte, out [][]byte, start int, n int)
// Requires: AVX, AVX2, SSE2
TEXT ·mulAvxTwo_2x3(SB), $0-88
// Loading no tables to registers
// Destination kept in GP registers
// Full registers estimated 20 YMM used
MOVQ n+80(FP), AX
MOVQ matrix_base+0(FP), CX
SHRQ $0x05, AX
TESTQ AX, AX
JZ mulAvxTwo_2x3_end
MOVQ in_base+24(FP), DX
MOVQ (DX), BX
MOVQ 24(DX), DX
MOVQ out_base+48(FP), BP
MOVQ (BP), SI
MOVQ 24(BP), DI
MOVQ 48(BP), BP
MOVQ start+72(FP), R8
// Add start offset to output
ADDQ R8, SI
ADDQ R8, DI
ADDQ R8, BP
// Add start offset to input
ADDQ R8, BX
ADDQ R8, DX
MOVQ $0x0000000f, R8
MOVQ R8, X3
VPBROADCASTB X3, Y3
mulAvxTwo_2x3_loop:
// Clear 3 outputs
VPXOR Y0, Y0, Y0
VPXOR Y1, Y1, Y1
VPXOR Y2, Y2, Y2
// Load and process 32 bytes from input 0 to 3 outputs
VMOVDQU (BX), Y6
ADDQ $0x20, BX
VPSRLQ $0x04, Y6, Y7
VPAND Y3, Y6, Y6
VPAND Y3, Y7, Y7
VMOVDQU (CX), Y4
VMOVDQU 32(CX), Y5
VPSHUFB Y6, Y4, Y4
VPSHUFB Y7, Y5, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y0, Y0
VMOVDQU 64(CX), Y4
VMOVDQU 96(CX), Y5
VPSHUFB Y6, Y4, Y4
VPSHUFB Y7, Y5, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y1, Y1
VMOVDQU 128(CX), Y4
VMOVDQU 160(CX), Y5
VPSHUFB Y6, Y4, Y4
VPSHUFB Y7, Y5, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y2, Y2
// Load and process 32 bytes from input 1 to 3 outputs
VMOVDQU (DX), Y6
ADDQ $0x20, DX
VPSRLQ $0x04, Y6, Y7
VPAND Y3, Y6, Y6
VPAND Y3, Y7, Y7
VMOVDQU 192(CX), Y4
VMOVDQU 224(CX), Y5
VPSHUFB Y6, Y4, Y4
VPSHUFB Y7, Y5, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y0, Y0
VMOVDQU 256(CX), Y4
VMOVDQU 288(CX), Y5
VPSHUFB Y6, Y4, Y4
VPSHUFB Y7, Y5, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y1, Y1
VMOVDQU 320(CX), Y4
VMOVDQU 352(CX), Y5
VPSHUFB Y6, Y4, Y4
VPSHUFB Y7, Y5, Y5
VPXOR Y4, Y5, Y4
VPXOR Y4, Y2, Y2