New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Differential pairs inversion #57

Open

jmatyas opened this issue May 29, 2023 · 0 comments

Milestone

jmatyas commented May 29, 2023

A few of the differential lines are inverted:

FPGA_CLK1
FPGA_CLK2 (already marked on schematics)
EEM LVDS1
EEM LVDS2
EEM LVDS3
EEM LVDS4
EEM LVDS5
EEM LVDS7

The following lines are marked as inverted, even though they aren't:

OUT1A
OUT1B
OUT1C

Those were found in addition to the ones reported in issue #55

kaolpr added this to the v1.1 milestone

kaolpr added bug and removed bug labels

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment