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Faulty I2C separation between P3V3_MP and P3V3 #149

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mkiepiela opened this issue Feb 18, 2022 · 1 comment
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Faulty I2C separation between P3V3_MP and P3V3 #149

mkiepiela opened this issue Feb 18, 2022 · 1 comment

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@mkiepiela
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T6-T9 NMOS transistors (driven from P12V0 - always existing) does not separate P3V3_MP and P3V3 domains when the power supply circuits onboard are off.
It causes that the I2C lines on P3V3_MP side are loaded (voltage drop) by P3V3 domain eg. when thermal shutdown occured and LM75 shutted down the supply. Then it is sometimes impossible to write to LM75 sensors and clear the over temperature condition.

Solution: drive the NMOS from another voltage, generated onboard.

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@gkasprow
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gkasprow commented Sep 9, 2022

switched to P5V5 rail.

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