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SYNC_CLK to Stabilizer ETR/CHx timer input #76
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@jordens I plan a new release of Stabilizer. Which solution would be the most promising? An LVCMOS divider /8 would be fine? |
AFAICT the best approach would be to clock a timer via its ETR. I am not entirely sure about the maximum frequency we can do this at. But there is a (async) prescaler on that input on some timer channels. The possible pins that are available without too much rejiggering seem to be: PE0 (TIM4_ETR, unused) and PA0 (TIM8_ETR, TIM2_ETR, conveniently already on the header and AFAIK unused in any mezzanine, i.e. easily repurposable).
I'd like to see that frequency counting test done. Could either you rig that up (simple CubeMX test: count 125 MHz on PA0 clocking TIM2_ETR with /8 prescaler, and drive a TIM2 output compare channel from that counter, verify the output frequency is 125MHz/8/counter reload) with an existing board? Or should I give it a try? If that works we can skip the prescaler and just need PA0 to SYNC_CLK. Prescaler phase measurement would allow timing the DDS io_update w.r.t. the SYNC_CLK phase deterministically and thus ensure deterministic latency between the Stabilizer ADC sampling and IIR loop iterations and the Pounder DDS updates. But I think we may be able to live without that. It looks a bit tricky to make that deterministic. |
If anybody can find the max frequency of the ETR prescaler or the input pin buffers, please enlighten me. |
We use PA0 for DDS_RESET on Pounder v1.0. After we checked the max input frequency on PA0, I'd suggest connecting DDS_RESET to J10:11 (PG6) and SYNC_CLK (if needed through a /8 prescaler) to J10:18 (PA0). And on Stabilizer the PA0 wire should be cleaned up to and there should probably be some termination (series or AC parallel?). |
It's easier for me to add a prescaller and bypass option than to check max STM frequency, especially if it is undocumented and may not work with other production batches. |
@jordens I cleaned the PA0, the next action is to modify the pounder, right? |
Yes |
I checked the counter input. No external prescaler needed. Just
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The changes @jordens proposed above were manually completed by me on TS 38/20 0002. In addition to the changes mentioned above, I also removed R70 (to disconnect SYNC_IN from PA0). I have run firmware and verified that the clock can be properly driven using this hardware configuration and this is sufficient for timestamping ADC samples. |
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