SYNC_CLK to Stabilizer ETR/CHx timer input

[jordens]

• I don't see how SYNC_IN is useful. Should have done thorough analysis in SYNC in #55
• We should enable SYNC_OUT to the CPU for accurate software-demodulation (required for super heterodyne quartiq/stabilizer#80)
• This needs a timer channel input with external clocking capability to be used as counter
• Counting 125 MHz may or may not be doable with the stm32h7 (but should be checked) physically.
• Potentially interesting input topologies would be: TIMx_CHx or maybe better TIMx_ETR+internal asynchronous ETPS prescaler (/4 or /8)?
• From what I can tell it's not possible with the HRTIM. It would need to be a general purpose or advanced timer. Maybe HRTIM_EEVx though?
• If 125 MHz is too fast for a timer, the alternatives are (a) a discrete prescaler or (b) using one of the the reference clock outputs from Pounder (10 MHz from SMA only then) to a timer channel counter input on Stabilizer
• If prescaler, then consider possible prescaler phase measurement and compensation (deterministic closed loop phase)
• Better to use SYNC_CLK than SYNC_OUT b/c duty cycle?

[gkasprow]

@jordens I plan a new release of Stabilizer. Which solution would be the most promising? An LVCMOS divider /8 would be fine?
Of course, I would have to change in Stabilizer design the IO pin assigned to this particular GPIO header pin. I can add such circuit to existing boards - I have one Stabilizer and one Pounder.
What do you mean by prescaler phase measurement and compensation? D you mean IC propagation delay? Why would we care about it since the STM32 input is not compensated.

[jordens]

AFAICT the best approach would be to clock a timer via its ETR. I am not entirely sure about the maximum frequency we can do this at. But there is a (async) prescaler on that input on some timer channels. The possible pins that are available without too much rejiggering seem to be: PE0 (TIM4_ETR, unused) and PA0 (TIM8_ETR, TIM2_ETR, conveniently already on the header and AFAIK unused in any mezzanine, i.e. easily repurposable).

• We should check that 125 MHz frequency counting works with this method on an ETR input with internal prescaler.
• Then I'd like to get SYNC_CLK from the DDS to an ETR input.
• I'd like a /8 prescaler that can handle 125 MHz between SYNC_CLK and ETR. That prescaler can be on Pounder and should have a population option bypass.

I'd like to see that frequency counting test done. Could either you rig that up (simple CubeMX test: count 125 MHz on PA0 clocking TIM2_ETR with /8 prescaler, and drive a TIM2 output compare channel from that counter, verify the output frequency is 125MHz/8/counter reload) with an existing board? Or should I give it a try? If that works we can skip the prescaler and just need PA0 to SYNC_CLK.

Prescaler phase measurement would allow timing the DDS io_update w.r.t. the SYNC_CLK phase deterministically and thus ensure deterministic latency between the Stabilizer ADC sampling and IIR loop iterations and the Pounder DDS updates. But I think we may be able to live without that. It looks a bit tricky to make that deterministic.

[jordens]

If anybody can find the max frequency of the ETR prescaler or the input pin buffers, please enlighten me.

[jordens]

We use PA0 for DDS_RESET on Pounder v1.0. After we checked the max input frequency on PA0, I'd suggest connecting DDS_RESET to J10:11 (PG6) and SYNC_CLK (if needed through a /8 prescaler) to J10:18 (PA0). And on Stabilizer the PA0 wire should be cleaned up to and there should probably be some termination (series or AC parallel?).

[gkasprow]

It's easier for me to add a prescaller and bypass option than to check max STM frequency, especially if it is undocumented and may not work with other production batches.

[gkasprow]

@jordens I cleaned the PA0, the next action is to modify the pounder, right?

[jordens]

Yes

[jordens]

I checked the counter input. No external prescaler needed. Just

• connect DDS_RESET to J10:11 (PG6)
• connect SYNC_CLK to J10:18 (PA0) make sure that this 125 MHz signal gets to the CPU with correct level and decent termination/matching

[ryan-summers]

The changes @jordens proposed above were manually completed by me on TS 38/20 0002. In addition to the changes mentioned above, I also removed R70 (to disconnect SYNC_IN from PA0).

I have run firmware and verified that the clock can be properly driven using this hardware configuration and this is sufficient for timestamping ADC samples.