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Sinara is an open-source (CERN OHL v1.2) hardware ecosystem designed by physicists for use in quantum science laboratories largely focused on work with trapped atomic ion qubits. Sinara is designed to work closely with the ARTIQ control software. While Sinara and ARTIQ were founded by a particular niche in the experimental physics community, users and contributors from all disciplines are invited to use and contribute to the project.

Control electronics used in many atomic physics laboratories suffers from a number of problems. Control solutions developed in-house by physicists often optimize for lab-specific needs and the publish-or-perish reality of many PIs circumstances. The result is solutions that compromise on architectural design, reproducibility, testing and documentation which translates into systems that are fragile, difficulty to reproduce in other labs and hard to maintain. It also duplicates similar infrastructural work undertaken in other laboratories. Further, the performance and feature set of commercial off the shelf hardware-software solutions is poorly matched to many labs needs (e.g. RF pulse shaping, branching latency).

To alleviate those problems, Sinara aims to be:

fully transparent design workflow
open source hardware, firmware and unit tests
simple to use and "turn-key" (we're not quite "turn-key" yet)
reproducible
flexible and modular
well tested at the hardware level
well supported by the ARTIQ control software

Sinara was developed by a collaboration including M-Labs, QUARTIQ, Warsaw University of Technology (WUT), US Army Research Laboratory (ARL), the University of Oxford, the University of Maryland, the University of Oregon, and NIST -- the list of contributors has grown beyond this core group as of 2023. The majority of the hardware was designed by WUT. The work was funded by ARL, Duke University, the University of Oxford, the University of Oregon, and the University of Freiburg -- the list of funders has grown beyond this core group as of 2023.

Currently, much of this hardware is well tested, commercially available and deployed for routine use in many AMO labs. Information about the hardware and firmware/software status of the various hardware projects making up Sinara can be found here. Options for purchasing Sinara hardware can be found here.

Overview

Following the ARTIQ model, a minimal laboratory setup consists of a core device -- typically Kasli or Kasli-SOC -- controlling multiple satellite devices in real time using the ARTIQ distributed real-time IO (DRTIO) protocol. DRTIO provides both gigabit communication links and time distribution over copper cable or optical fiber. It synchronizes all device clocks, ensuring they have deterministic phase relationships, and enables nanosecond timing resolution for input and output events across all devices in the experiment. More detailed information about communication between devices and time distribution inside Sinara can be found here.

In Sinara systems, the core device provides power, configuration (using kasli-i2c) and DRTIO to real-time peripherals. Sinara uses two main core device form factors: microTCA (uTCA) and Eurocard Extension Modules (EEM) -- as of 2023 the EEM form factor is vastly dominant.

In the case of EEM, the core device is resides in a 3U Eurocard-style rack and connects to other Sinara real-time peripherals using ribbon cables. More details about the extension module standard can be found here. Non real-time hardware is typically connected to the host PC using USB or Ethernet.
uTCA hardware interfaces with the extension modules either directly, using a VHDCI carrier, or indirectly, using a Kasli DRTIO satellite.

form factor: MicroTCA hardware

An overview of uTCA in Sinara can be found here, for more detailed information on specific topics, see the links below. The uTCA hardware is still in beta and not yet fullly supported by ARTIQ. See this page for status.

uTCA Chassis
Metlino: uTCA MCH (rack master device)
Sayma: 8 channel 2.4GSPS Smart Arbitrary Waveform Generator
Sayma analogue front-end mezzanines
uTCA misc: mainly adapters and test harnesses

form factor: EEM

Information about the Eurocard Extension Module (EEM) standard can be found here. Note that EEM was devised by the Sinara project.
To provision Sinara hardware (flash) use kasli-i2c.
To test systems built from Sinara hardware use kasli_tester.py.

Kasli family of EEM core devices

EEM extension modules

Note that not all PCBs in this section are fully debugged and supported by ARTIQ. See this page for status.

DIO_BNC: Digital IO on BNCs
DIO_SMA: Digital IO on SMAs
DIO_RJ45: LVDS IO on RJ45s
Zotino: 32-channel DAC
Sampler: 8-channel ADC
Grabber: Camera Framegrabber
Mirny: Quad Microwave Synthesiser
Urukul: Quad DDS
Clocker: Clock Buffer
Humpback: SBC baseboard with FPGA
Stabilizer: Dual channel fast servo
Banker: FPGA-based 128x GPIO with adapters
Fastino: Fast 32-channel DAC

Sinara support hardware

Other supporting hardware, not requiring real-time control from the ARTIQ master:

Booster: RF Power Amplifier
Thermostat: Temp Controller

Sinara adapters and breakout hardware

Project structure and development

Development discussions take place on two forums: the GitHub issue trackers for well-defined actionable items; and the web forum for more vague questions, general brainstorming, new hardware proposals, discussions about funding, and so forth.

Two main CAD tool used for PCB design within Sinara is Altium Designer. Altium Designer is preferred for more complex designs, such as the uTCA and EEM hardware. Kicad is also used for simple designs, like adapters, in particular, those intended to be modifiable by the users (physicists).

A list of future hardware ideas can be found here.