From ab70e6615ab72f4d5ca1679224753f000bcf2792 Mon Sep 17 00:00:00 2001 From: Junchao-Mellanox <57339448+Junchao-Mellanox@users.noreply.github.com> Date: Thu, 10 Aug 2023 13:47:50 +0800 Subject: [PATCH 1/2] Add new SSD type support (#390) * Add new SSD type support * Fix review comment --------- Co-authored-by: Prince George <45705344+prgeor@users.noreply.github.com> --- sonic_platform_base/sonic_ssd/ssd_generic.py | 20 +++- tests/ssd_generic_test.py | 116 +++++++++++++++++++ 2 files changed, 135 insertions(+), 1 deletion(-) diff --git a/sonic_platform_base/sonic_ssd/ssd_generic.py b/sonic_platform_base/sonic_ssd/ssd_generic.py index 1541d31f3..2fc5903b0 100644 --- a/sonic_platform_base/sonic_ssd/ssd_generic.py +++ b/sonic_platform_base/sonic_ssd/ssd_generic.py @@ -23,6 +23,8 @@ # Set Vendor Specific IDs INNODISK_HEALTH_ID = 169 INNODISK_TEMPERATURE_ID = 194 +SWISSBIT_HEALTH_ID = 248 +SWISSBIT_TEMPERATURE_ID = 194 class SsdUtil(SsdBase): """ @@ -42,7 +44,8 @@ def __init__(self, diskdev): "InnoDisk" : { "utility" : INNODISK, "parser" : self.parse_innodisk_info }, "M.2" : { "utility" : INNODISK, "parser" : self.parse_innodisk_info }, "StorFly" : { "utility" : VIRTIUM, "parser" : self.parse_virtium_info }, - "Virtium" : { "utility" : VIRTIUM, "parser" : self.parse_virtium_info } + "Virtium" : { "utility" : VIRTIUM, "parser" : self.parse_virtium_info }, + "Swissbit" : { "utility" : SMARTCTL, "parser" : self.parse_swissbit_info }, } self.dev = diskdev @@ -78,6 +81,8 @@ def _parse_vendor(self): return model_short elif self.model.startswith('VSF'): return 'Virtium' + elif self.model.startswith('SFS'): + return 'Swissbit' else: return None @@ -154,6 +159,19 @@ def parse_virtium_info(self): except ValueError: pass + def parse_swissbit_info(self): + if self.ssd_info: + health_raw = self.parse_id_number(SWISSBIT_HEALTH_ID) + if health_raw == NOT_AVAILABLE: + self.health = NOT_AVAILABLE + else: + self.health = health_raw.split()[-1] + temp_raw = self.parse_id_number(SWISSBIT_TEMPERATURE_ID) + if temp_raw == NOT_AVAILABLE: + self.temperature = NOT_AVAILABLE + else: + self.temperature = temp_raw.split()[-3] + def fetch_vendor_ssd_info(self, diskdev, model): self.vendor_ssd_info = self._execute_shell(self.vendor_ssd_utility[model]["utility"].format(diskdev)) diff --git a/tests/ssd_generic_test.py b/tests/ssd_generic_test.py index 889205e11..26fc0cd25 100644 --- a/tests/ssd_generic_test.py +++ b/tests/ssd_generic_test.py @@ -532,6 +532,112 @@ ID Attribute High Raw Low Raw Value Worst Threshold """ +output_swissbit_vendor = """ +smartctl 7.2 2020-12-30 r5155 [x86_64-linux-5.10.0-23-2-amd64] (local build) +Copyright (C) 2002-20, Bruce Allen, Christian Franke, www.smartmontools.org + +=== START OF INFORMATION SECTION === +Device Model: SFSA160GM2AK2TO-I-8C-22K-STD +Serial Number: 00006022750795000010 +Firmware Version: SBR15004 +User Capacity: 160,041,885,696 bytes [160 GB] +Sector Size: 512 bytes logical/physical +Rotation Rate: Solid State Device +Form Factor: 2.5 inches +TRIM Command: Available, deterministic, zeroed +Device is: Not in smartctl database [for details use: -P showall] +ATA Version is: ACS-3 (minor revision not indicated) +SATA Version is: SATA 3.2, 6.0 Gb/s (current: 6.0 Gb/s) +Local Time is: Wed Aug 2 08:24:31 2023 UTC +SMART support is: Available - device has SMART capability. +SMART support is: Enabled + +=== START OF READ SMART DATA SECTION === +SMART overall-health self-assessment test result: PASSED + +General SMART Values: +Offline data collection status: (0x00) Offline data collection activity + was never started. + Auto Offline Data Collection: Disabled. +Self-test execution status: ( 0) The previous self-test routine completed + without error or no self-test has ever + been run. +Total time to complete Offline +data collection: ( 0) seconds. +Offline data collection +capabilities: (0x53) SMART execute Offline immediate. + Auto Offline data collection on/off support. + Suspend Offline collection upon new + command. + No Offline surface scan supported. + Self-test supported. + No Conveyance Self-test supported. + Selective Self-test supported. +SMART capabilities: (0x0003) Saves SMART data before entering + power-saving mode. + Supports SMART auto save timer. +Error logging capability: (0x01) Error logging supported. + General Purpose Logging supported. +Short self-test routine +recommended polling time: ( 2) minutes. +Extended self-test routine +recommended polling time: ( 15) minutes. +SCT capabilities: (0x0031) SCT Status supported. + SCT Feature Control supported. + SCT Data Table supported. + +SMART Attributes Data Structure revision number: 1 +Vendor Specific SMART Attributes with Thresholds: +ID# ATTRIBUTE_NAME FLAG VALUE WORST THRESH TYPE UPDATED WHEN_FAILED RAW_VALUE + 1 Raw_Read_Error_Rate 0x000b 100 100 000 Pre-fail Always - 0 + 5 Reallocated_Sector_Ct 0x0013 100 100 000 Pre-fail Always - 0 + 9 Power_On_Hours 0x0012 100 100 000 Old_age Always - 825 + 12 Power_Cycle_Count 0x0012 100 100 000 Old_age Always - 447 + 16 Unknown_Attribute 0x0112 100 100 001 Old_age Always - 4 + 17 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 30000 +160 Unknown_Attribute 0x0002 100 100 000 Old_age Always - 0 +161 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 15401195 +163 Unknown_Attribute 0x0003 100 100 000 Pre-fail Always - 33 +164 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 6506 +165 Unknown_Attribute 0x0002 100 100 000 Old_age Always - 38 +166 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 1 +167 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 4 +168 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 30000 +169 Unknown_Attribute 0x0003 100 100 000 Pre-fail Always - 421 +193 Unknown_SSD_Attribute 0x0012 100 100 000 Old_age Always - 0 +194 Temperature_Celsius 0x0023 100 100 000 Pre-fail Always - 25 (Min/Max 22/45) +195 Hardware_ECC_Recovered 0x0012 100 100 000 Old_age Always - 0 +196 Reallocated_Event_Count 0x0012 000 000 000 Old_age Always - 0 +198 Offline_Uncorrectable 0x0012 100 100 000 Old_age Always - 0 +199 UDMA_CRC_Error_Count 0x000b 100 100 000 Pre-fail Always - 0 +215 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 4275 +231 Unknown_SSD_Attribute 0x1913 100 100 025 Pre-fail Always - 100 +235 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 1302467136 +237 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 0 +241 Total_LBAs_Written 0x0012 100 100 000 Old_age Always - 1186450104 +242 Total_LBAs_Read 0x0012 100 100 000 Old_age Always - 2257141451 +243 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 0 +244 Unknown_Attribute 0x0012 100 100 000 Old_age Always - 0 +248 Unknown_Attribute 0x0112 100 100 001 Old_age Always - 100 + +SMART Error Log Version: 1 +No Errors Logged + +SMART Self-test log structure revision number 1 +No self-tests have been logged. [To run self-tests, use: smartctl -t] + +SMART Selective self-test log data structure revision number 1 + SPAN MIN_LBA MAX_LBA CURRENT_TEST_STATUS + 1 0 0 Not_testing + 2 0 0 Not_testing + 3 0 0 Not_testing + 4 0 0 Not_testing + 5 0 0 Not_testing +Selective self-test flags (0x0): + After scanning selected spans, do NOT read-scan remainder of disk. +If Selective self-test is pending on power-up, resume after 0 minute delay. +""" + class TestSsdGeneric: @mock.patch('sonic_platform_base.sonic_ssd.ssd_generic.SsdUtil._execute_shell', mock.MagicMock(return_value=output_nvme_ssd)) def test_nvme_ssd(self): @@ -631,3 +737,13 @@ def test_virtium_ssd(self, mock_exec): mock_exec.side_effect = [output_virtium_generic, output_virtium_invalid_remain_life] virtium_ssd = SsdUtil('/dev/sda') assert virtium_ssd.get_health() == "N/A" + + @mock.patch('sonic_platform_base.sonic_ssd.ssd_generic.SsdUtil._execute_shell') + def test_swissbit_ssd(self, mock_exec): + mock_exec.return_value = output_swissbit_vendor + swissbit_ssd = SsdUtil('/dev/sda') + assert swissbit_ssd.get_health() == '100' + assert swissbit_ssd.get_model() == 'SFSA160GM2AK2TO-I-8C-22K-STD' + assert swissbit_ssd.get_firmware() == "SBR15004" + assert swissbit_ssd.get_temperature() == '25' + assert swissbit_ssd.get_serial() == "00006022750795000010" From ae7049cd0ac917c7f19f82fa3a5fb1fc231eefbb Mon Sep 17 00:00:00 2001 From: Anoop Kamath <115578705+AnoopKamath@users.noreply.github.com> Date: Fri, 11 Aug 2023 12:52:54 -0700 Subject: [PATCH 2/2] Apply custom Si settings via CMIS: SONiC xcvrd platform common changes (#384) Co-authored-by: Prince George <45705344+prgeor@users.noreply.github.com> --- .../sonic_xcvr/api/public/cmis.py | 322 +++++++++++++++++- .../sonic_xcvr/fields/consts.py | 97 ++++++ .../sonic_xcvr/mem_maps/public/cmis.py | 134 ++++++++ tests/sonic_xcvr/test_cmis.py | 116 ++++++- 4 files changed, 657 insertions(+), 12 deletions(-) diff --git a/sonic_platform_base/sonic_xcvr/api/public/cmis.py b/sonic_platform_base/sonic_xcvr/api/public/cmis.py index 36657ddd7..a677f32ff 100644 --- a/sonic_platform_base/sonic_xcvr/api/public/cmis.py +++ b/sonic_platform_base/sonic_xcvr/api/public/cmis.py @@ -31,6 +31,12 @@ def __init__(self, xcvr_eeprom): self.vdm = CmisVdmApi(xcvr_eeprom) if not self.is_flat_memory() else None self.cdb = CmisCdbApi(xcvr_eeprom) if not self.is_flat_memory() else None + def get_manufacturer(self): + ''' + This function returns the manufacturer of the module + ''' + return self.xcvr_eeprom.read(consts.VENDOR_NAME_FIELD) + def get_model(self): ''' This function returns the part number of the module @@ -2069,7 +2075,7 @@ def get_application(self, lane): return (appl & 0xf) - def set_application(self, channel, appl_code): + def set_application(self, channel, appl_code, ec=0): """ Update the selected application code to the specified lanes on the host side @@ -2092,11 +2098,323 @@ def set_application(self, channel, appl_code): lane_first = lane addr = "{}_{}_{}".format(consts.STAGED_CTRL_APSEL_FIELD, 0, lane + 1) data = (appl_code << 4) | (lane_first << 1) + #set EC bit + data|= ec self.xcvr_eeprom.write(addr, data) - # Apply DataPathInit + def scs_apply_datapath_init(self, channel): + ''' + This function applies DataPathInit + ''' return self.xcvr_eeprom.write("%s_%d" % (consts.STAGED_CTRL_APPLY_DPINIT_FIELD, 0), channel) + def get_rx_output_amp_max_val(self): + ''' + This function returns the supported RX output amp val + ''' + rx_amp_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_LEVEL_SUPPORT) + if rx_amp_max_val is None: + return None + return rx_amp_max_val + + def get_rx_output_eq_pre_max_val(self): + ''' + This function returns the supported RX output eq pre cursor val + ''' + rx_pre_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_PRE_CURSOR_MAX) + if rx_pre_max_val is None: + return None + return rx_pre_max_val + + def get_rx_output_eq_post_max_val(self): + ''' + This function returns the supported RX output eq post cursor val + ''' + rx_post_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_POST_CURSOR_MAX) + if rx_post_max_val is None: + return None + return rx_post_max_val + + def get_tx_input_eq_max_val(self): + ''' + This function returns the supported TX input eq val + ''' + tx_input_max_val = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_MAX) + if tx_input_max_val is None: + return None + return tx_input_max_val + + def get_tx_cdr_supported(self): + ''' + This function returns the supported TX CDR field + ''' + tx_cdr_support = self.xcvr_eeprom.read(consts.TX_CDR_SUPPORT_FIELD) + if not tx_cdr_support or tx_cdr_support is None: + return False + return tx_cdr_support + + def get_rx_cdr_supported(self): + ''' + This function returns the supported RX CDR field + ''' + rx_cdr_support = self.xcvr_eeprom.read(consts.RX_CDR_SUPPORT_FIELD) + if not rx_cdr_support or rx_cdr_support is None: + return False + return rx_cdr_support + + def get_tx_input_eq_fixed_supported(self): + ''' + This function returns the supported TX input eq field + ''' + tx_fixed_support = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD) + if not tx_fixed_support or tx_fixed_support is None: + return False + return tx_fixed_support + + def get_tx_input_adaptive_eq_supported(self): + ''' + This function returns the supported TX input adaptive eq field + ''' + tx_adaptive_support = self.xcvr_eeprom.read(consts.TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD) + if not tx_adaptive_support or tx_adaptive_support is None: + return False + return tx_adaptive_support + + def get_tx_input_recall_buf1_supported(self): + ''' + This function returns the supported TX input recall buf1 field + ''' + tx_recall_buf1_support = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_RECALL_BUF1_SUPPORT_FIELD) + if not tx_recall_buf1_support or tx_recall_buf1_support is None: + return False + return tx_recall_buf1_support + + def get_tx_input_recall_buf2_supported(self): + ''' + This function returns the supported TX input recall buf2 field + ''' + tx_recall_buf2_support = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_RECALL_BUF2_SUPPORT_FIELD) + if not tx_recall_buf2_support or tx_recall_buf2_support is None: + return False + return tx_recall_buf2_support + + def get_rx_ouput_amp_ctrl_supported(self): + ''' + This function returns the supported RX output amp control field + ''' + rx_amp_support = self.xcvr_eeprom.read(consts.RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD) + if not rx_amp_support or rx_amp_support is None: + return False + return rx_amp_support + + def get_rx_output_eq_pre_ctrl_supported(self): + ''' + This function returns the supported RX output eq pre control field + ''' + rx_pre_support = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_PRE_CTRL_SUPPORT_FIELD) + if not rx_pre_support or rx_pre_support is None: + return False + return rx_pre_support + + def get_rx_output_eq_post_ctrl_supported(self): + ''' + This function returns the supported RX output eq post control field + ''' + rx_post_support = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_POST_CTRL_SUPPORT_FIELD) + if not rx_post_support or rx_post_support is None: + return False + return rx_post_support + + def scs_lane_write(self, si_param, host_lanes_mask, si_settings_dict): + ''' + This function sets each lane val based on SI param + ''' + for lane in range(self.NUM_CHANNELS): + if ((1 << lane) & host_lanes_mask) == 0: + continue + lane = lane+1 + si_param_lane = "{}{}".format(si_param, lane) + si_param_lane_val = si_settings_dict[si_param_lane] + if si_param_lane_val is None: + return False + if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val): + return False + return True + + def stage_output_eq_pre_cursor_target_rx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies RX output eq pre cursor settings + ''' + rx_pre_max_val = self.get_rx_output_eq_pre_max_val() + if rx_pre_max_val is None: + return False + for lane in range(self.NUM_CHANNELS): + if ((1 << lane) & host_lanes_mask) == 0: + continue + lane = lane+1 + si_param_lane = "{}{}".format(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX, lane) + si_param_lane_val = si_settings_dict[si_param_lane] + if si_param_lane_val is None or si_param_lane_val > rx_pre_max_val: + return False + if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val): + return False + return True + + def stage_output_eq_post_cursor_target_rx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies RX output eq post cursor settings + ''' + rx_post_max_val = self.get_rx_output_eq_post_max_val() + if rx_post_max_val is None: + return False + for lane in range(self.NUM_CHANNELS): + if ((1 << lane) & host_lanes_mask) == 0: + continue + lane = lane+1 + si_param_lane = "{}{}".format(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX, lane) + si_param_lane_val = si_settings_dict[si_param_lane] + if si_param_lane_val is None or si_param_lane_val > rx_post_max_val: + return False + if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val): + return False + return True + + def stage_output_amp_target_rx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies RX output amp settings + ''' + rx_amp_max_val = self.get_rx_output_amp_max_val() + if rx_amp_max_val is None: + return False + for lane in range(self.NUM_CHANNELS): + if ((1 << lane) & host_lanes_mask) == 0: + continue + lane = lane+1 + si_param_lane = "{}{}".format(consts.OUTPUT_AMPLITUDE_TARGET_RX, lane) + si_param_lane_val = si_settings_dict[si_param_lane] + if si_param_lane_val is None or si_param_lane_val > rx_amp_max_val: + return False + if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val): + return False + return True + + def stage_fixed_input_target_tx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies fixed TX input si settings + ''' + tx_fixed_input = self.get_tx_input_eq_max_val() + if tx_fixed_input is None: + return False + for lane in range(self.NUM_CHANNELS): + if ((1 << lane) & host_lanes_mask) == 0: + continue + lane = lane+1 + si_param_lane = "{}{}".format(consts.FIXED_INPUT_EQ_TARGET_TX, lane) + si_param_lane_val = si_settings_dict[si_param_lane] + if si_param_lane_val is None or si_param_lane_val > tx_fixed_input: + return False + if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val): + return False + return True + + def stage_adaptive_input_eq_recall_tx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies adaptive TX input recall si settings. + ''' + if si_settings_dict is None: + return False + return self.scs_lane_write(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX, host_lanes_mask, si_settings_dict) + + def stage_adaptive_input_eq_enable_tx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies adaptive TX input enable si settings + ''' + if si_settings_dict is None: + return False + return self.scs_lane_write(consts.ADAPTIVE_INPUT_EQ_ENABLE_TX, host_lanes_mask, si_settings_dict) + + def stage_cdr_tx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies TX CDR si settings + ''' + if si_settings_dict is None: + return False + return self.scs_lane_write(consts.CDR_ENABLE_TX, host_lanes_mask, si_settings_dict) + + def stage_cdr_rx(self, host_lanes_mask, si_settings_dict): + ''' + This function applies RX CDR si settings + ''' + if si_settings_dict is None: + return False + return self.scs_lane_write(consts.CDR_ENABLE_RX, host_lanes_mask, si_settings_dict) + + def stage_rx_si_settings(self, host_lanes_mask, si_settings_dict): + for si_param in si_settings_dict: + if si_param == consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX: + if self.get_rx_output_eq_pre_ctrl_supported(): + if not self.stage_output_eq_pre_cursor_target_rx(host_lanes_mask, si_settings_dict[si_param]): + return False + elif si_param == consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX: + if self.get_rx_output_eq_post_ctrl_supported(): + if not self.stage_output_eq_post_cursor_target_rx(host_lanes_mask, si_settings_dict[si_param]): + return False + elif si_param == consts.OUTPUT_AMPLITUDE_TARGET_RX: + if self.get_rx_ouput_amp_ctrl_supported(): + if not self.stage_output_amp_target_rx(host_lanes_mask, si_settings_dict[si_param]): + return False + elif si_param == consts.CDR_ENABLE_RX: + if self.get_rx_cdr_supported(): + if not self.stage_cdr_rx(host_lanes_mask, si_settings_dict[si_param]): + return False + else: + return False + + return True + + def stage_tx_si_settings(self, host_lanes_mask, si_settings_dict): + for si_param in si_settings_dict: + if si_param == consts.FIXED_INPUT_EQ_TARGET_TX: + if self.get_tx_input_eq_fixed_supported(): + if not self.stage_fixed_input_target_tx(host_lanes_mask, si_settings_dict[si_param]): + return False + elif si_param == consts.ADAPTIVE_INPUT_EQ_RECALLED_TX: + if self.get_tx_input_recall_buf1_supported() or self.get_tx_input_recall_buf2_supported(): + if not self.stage_adaptive_input_eq_recall_tx(host_lanes_mask, si_settings_dict[si_param]): + return False + elif si_param == consts.ADAPTIVE_INPUT_EQ_ENABLE_TX: + if self.get_tx_input_adaptive_eq_supported(): + if not self.stage_adaptive_input_eq_enable_tx(host_lanes_mask, si_settings_dict[si_param]): + return False + elif si_param == consts.CDR_ENABLE_TX: + if self.get_tx_cdr_supported(): + if not self.stage_cdr_tx(host_lanes_mask, si_settings_dict[si_param]): + return False + else: + return False + + return True + + def stage_custom_si_settings(self, host_lanes_mask, optics_si_dict): + # Create TX/RX specific si_dict + rx_si_settings = {} + tx_si_settings = {} + for si_param in optics_si_dict: + if si_param.endswith("Tx"): + tx_si_settings[si_param] = optics_si_dict[si_param] + elif si_param.endswith("Rx"): + rx_si_settings[si_param] = optics_si_dict[si_param] + + # stage RX si settings + if not self.stage_rx_si_settings(host_lanes_mask, rx_si_settings): + return False + + # stage TX si settings + if not self.stage_tx_si_settings(host_lanes_mask, tx_si_settings): + return False + + return True + def get_error_description(self): dp_state = self.get_datapath_state() conf_state = self.get_config_datapath_hostlane_status() diff --git a/sonic_platform_base/sonic_xcvr/fields/consts.py b/sonic_platform_base/sonic_xcvr/fields/consts.py index c638f19b6..e9e250a32 100644 --- a/sonic_platform_base/sonic_xcvr/fields/consts.py +++ b/sonic_platform_base/sonic_xcvr/fields/consts.py @@ -299,6 +299,103 @@ STAGED_CTRL_APPLY_IMMEDIATE_FIELD = "Staged Control Set Apply Immediate" STAGED_CTRL_APSEL_FIELD = "Staged Control Set ApSel" +STAGED_CTRL0_TX_RX_CTRL_FIELD = "Staged Control TX RX Control" + +TX_INPUT_EQ_MAX = "TXInputEqMax" +RX_OUTPUT_LEVEL_SUPPORT = "RX Output Level Supported" +RX_OUTPUT_LEVEL_0_SUPPORTED = "RXOutputLevel0Supported" +RX_OUTPUT_LEVEL_1_SUPPORTED = "RXOutputLevel1Supported" +RX_OUTPUT_LEVEL_2_SUPPORTED = "RXOutputLevel2Supported" +RX_OUTPUT_LEVEL_3_SUPPORTED = "RXOutputLevel3Supported" +RX_OUTPUT_EQ_PRE_CURSOR_MAX = "RXOutputEqPreCursorMax" +RX_OUTPUT_EQ_POST_CURSOR_MAX = "RXOutputEqPostCursorMax" + +SIGNAL_INTEGRITY_CTRL_ADVT_FIELD = "Signal Integrity Control Advertisement" +TX_SI_CTRL_ADVT = "TX SI Control Advertisement" +TX_CDR_SUPPORT_FIELD = "TXCDRSupported" +TX_CDR_BYPASS_CTRL_FIELD = "TXCDRBypassSupported" +TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD = "TXInputEqFixedManualSupported" +TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD = "TXInputAdaptiveEqSupported" +TX_INPUT_EQ_FREEZE_SUPPORT_FIELD = "TXInputEqFreezeSupported" +TX_INPUT_EQ_RECALL_BUF1_SUPPORT_FIELD = "TXInputEqRecallBuf1Supported" +TX_INPUT_EQ_RECALL_BUF2_SUPPORT_FIELD = "TXInputEqRecallBuf2Supported" +TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD = "TXInputEqRecallBufSupported" +RX_SI_CTRL_ADVT = "RX SI Control Advertisement" +RX_CDR_SUPPORT_FIELD = "RxCDRSupported" +RX_CDR_BYPASS_CTRL_FIELD = "RXCDRBypassSupported" +RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD = "RXOutputAmpSupported" +RX_OUTPUT_EQ_PRE_CTRL_SUPPORT_FIELD = "RXOutputEQPreSupported" +RX_OUTPUT_EQ_POST_CTRL_SUPPORT_FIELD = "RXOutputEQPostSupported" +RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD = "RXOutputEQSupported" + +ACTIVE_CTRL_FIELD = "Active Control Set" +ADAPTIVE_INPUT_EQ_ENABLE_TX = "AdaptiveInputEqEnableTx" +ADAPTIVE_INPUT_EQ_RECALLED_TX = "AdaptiveInputEqRecalledTx" +ADAPTIVE_INPUT_EQ_RECALLED_TX1_4 = "AdaptiveInputEqRecalledTx1_4" +ADAPTIVE_INPUT_EQ_RECALLED_TX1 = "AdaptiveInputEqRecalledTx1" +ADAPTIVE_INPUT_EQ_RECALLED_TX2 = "AdaptiveInputEqRecalledTx2" +ADAPTIVE_INPUT_EQ_RECALLED_TX3 = "AdaptiveInputEqRecalledTx3" +ADAPTIVE_INPUT_EQ_RECALLED_TX4 = "AdaptiveInputEqRecalledTx4" +ADAPTIVE_INPUT_EQ_RECALLED_TX5_8 = "AdaptiveInputEqRecalledTx5_8" +ADAPTIVE_INPUT_EQ_RECALLED_TX5 = "AdaptiveInputEqRecalledTx5" +ADAPTIVE_INPUT_EQ_RECALLED_TX6 = "AdaptiveInputEqRecalledTx6" +ADAPTIVE_INPUT_EQ_RECALLED_TX7 = "AdaptiveInputEqRecalledTx7" +ADAPTIVE_INPUT_EQ_RECALLED_TX8 = "AdaptiveInputEqRecalledTx8" +FIXED_INPUT_EQ_TARGET_TX = "FixedInputEqTargetTx" +FIXED_INPUT_EQ_TARGET_TX1_2 = "FixedInputEqTargetTx1_2" +FIXED_INPUT_EQ_TARGET_TX1 = "FixedInputEqTargetTx1" +FIXED_INPUT_EQ_TARGET_TX2 = "FixedInputEqTargetTx2" +FIXED_INPUT_EQ_TARGET_TX3_4 = "FixedInputEqTargetTx3_4" +FIXED_INPUT_EQ_TARGET_TX3 = "FixedInputEqTargetTx3" +FIXED_INPUT_EQ_TARGET_TX4 = "FixedInputEqTargetTx4" +FIXED_INPUT_EQ_TARGET_TX5_6 = "FixedInputEqTargetTx5_6" +FIXED_INPUT_EQ_TARGET_TX5 = "FixedInputEqTargetTx5" +FIXED_INPUT_EQ_TARGET_TX6 = "FixedInputEqTargetTx6" +FIXED_INPUT_EQ_TARGET_TX7_8 = "FixedInputEqTargetTx7_8" +FIXED_INPUT_EQ_TARGET_TX7 = "FixedInputEqTargetTx7" +FIXED_INPUT_EQ_TARGET_TX8 = "FixedInputEqTargetTx8" +CDR_ENABLE_TX = "CDREnableTx" +CDR_ENABLE_RX = "CDREnableRx" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX = "OutputEqPreCursorTargetRx" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX1_2 = "OutputEqPreCursorTargetRx1_2" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX1 = "OutputEqPreCursorTargetRx1" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX2 = "OutputEqPreCursorTargetRx2" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX3_4 = "OutputEqPreCursorTargetRx3_4" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX3 = "OutputEqPreCursorTargetRx3" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX4 = "OutputEqPreCursorTargetRx4" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX5_6 = "OutputEqPreCursorTargetRx5_6" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX5 = "OutputEqPreCursorTargetRx5" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX6 = "OutputEqPreCursorTargetRx6" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX7_8 = "OutputEqPreCursorTargetRx7_8" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX7 = "OutputEqPreCursorTargetRx7" +OUTPUT_EQ_PRE_CURSOR_TARGET_RX8 = "OutputEqPreCursorTargetRx8" +OUTPUT_EQ_POST_CURSOR_TARGET_RX = "OutputEqPostCursorTargetRx" +OUTPUT_EQ_POST_CURSOR_TARGET_RX1_2 = "OutputEqPostCursorTargetRx1_2" +OUTPUT_EQ_POST_CURSOR_TARGET_RX1 = "OutputEqPostCursorTargetRx1" +OUTPUT_EQ_POST_CURSOR_TARGET_RX2 = "OutputEqPostCursorTargetRx2" +OUTPUT_EQ_POST_CURSOR_TARGET_RX3_4 = "OutputEqPostCursorTargetRx3_4" +OUTPUT_EQ_POST_CURSOR_TARGET_RX3 = "OutputEqPostCursorTargetRx3" +OUTPUT_EQ_POST_CURSOR_TARGET_RX4 = "OutputEqPostCursorTargetRx4" +OUTPUT_EQ_POST_CURSOR_TARGET_RX5_6 = "OutputEqPostCursorTargetRx5_6" +OUTPUT_EQ_POST_CURSOR_TARGET_RX5 = "OutputEqPostCursorTargetRx5" +OUTPUT_EQ_POST_CURSOR_TARGET_RX6 = "OutputEqPostCursorTargetRx6" +OUTPUT_EQ_POST_CURSOR_TARGET_RX7_8 = "OutputEqPostCursorTargetRx7_8" +OUTPUT_EQ_POST_CURSOR_TARGET_RX7 = "OutputEqPostCursorTargetRx7" +OUTPUT_EQ_POST_CURSOR_TARGET_RX8 = "OutputEqPostCursorTargetRx8" +OUTPUT_AMPLITUDE_TARGET_RX = "OutputAmplitudeTargetRx" +OUTPUT_AMPLITUDE_TARGET_RX1_2 = "OutputAmplitudeTargetRx1_2" +OUTPUT_AMPLITUDE_TARGET_RX1 = "OutputAmplitudeTargetRx1" +OUTPUT_AMPLITUDE_TARGET_RX2 = "OutputAmplitudeTargetRx2" +OUTPUT_AMPLITUDE_TARGET_RX3_4 = "OutputAmplitudeTargetRx3_4" +OUTPUT_AMPLITUDE_TARGET_RX3 = "OutputAmplitudeTargetRx3" +OUTPUT_AMPLITUDE_TARGET_RX4 = "OutputAmplitudeTargetRx4" +OUTPUT_AMPLITUDE_TARGET_RX5_6 = "OutputAmplitudeTargetRx5_6" +OUTPUT_AMPLITUDE_TARGET_RX5 = "OutputAmplitudeTargetRx5" +OUTPUT_AMPLITUDE_TARGET_RX6 = "OutputAmplitudeTargetRx6" +OUTPUT_AMPLITUDE_TARGET_RX7_8 = "OutputAmplitudeTargetRx7_8" +OUTPUT_AMPLITUDE_TARGET_RX7 = "OutputAmplitudeTargetRx7" +OUTPUT_AMPLITUDE_TARGET_RX8 = "OutputAmplitudeTargetRx8" + # C-CMIS # Module configuration support fields diff --git a/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py b/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py index 512ed0776..140faeafd 100644 --- a/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py +++ b/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py @@ -11,6 +11,7 @@ HexRegField, NumberRegField, RegBitField, + RegBitsField, RegGroupField, StringRegField, ) @@ -195,6 +196,21 @@ def __init__(self, codes): NumberRegField(consts.PAGE_SUPPORT_ADVT_FIELD, self.getaddr(0x1, 142), RegBitField(consts.VDM_SUPPORTED, 6), ), + NumberRegField(consts.TX_INPUT_EQ_MAX, self.getaddr(0x1, 153), + *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4)) + ), + NumberRegField(consts.RX_OUTPUT_LEVEL_SUPPORT, self.getaddr(0x1, 153), + RegBitField(consts.RX_OUTPUT_LEVEL_0_SUPPORTED, 4), + RegBitField(consts.RX_OUTPUT_LEVEL_1_SUPPORTED, 5), + RegBitField(consts.RX_OUTPUT_LEVEL_2_SUPPORTED, 6), + RegBitField(consts.RX_OUTPUT_LEVEL_3_SUPPORTED, 7), + ), + NumberRegField(consts.RX_OUTPUT_EQ_PRE_CURSOR_MAX, self.getaddr(0x1, 154), + *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4)) + ), + NumberRegField(consts.RX_OUTPUT_EQ_POST_CURSOR_MAX, self.getaddr(0x1, 154), + *(RegBitField("Bit%d" % (bit), bit) for bit in range (4 , 8)) + ), NumberRegField(consts.CTRLS_ADVT_FIELD, self.getaddr(0x1, 155), RegBitField(consts.TX_DISABLE_SUPPORT_FIELD, 1), size=2, format="