From 45831071e063390a209bc12b336fa315119b877f Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Thu, 25 Jul 2019 09:38:37 +0200 Subject: [PATCH 1/4] Updating submodules. * edid-decode changed from 15df4ae to 42f5fa4 * 42f5fa4 - edid-decode: add comment w.r.t. JOC * a479a24 - edid-decode: parse additional flags in the DD+ Short Audio Descriptor * litedram changed from 67de3ce to 6c53996 * 6c53996 - core/refresher: reduce refresh period by one cycle * afb6d0a - core/refresher: reduce RefreshGenerator start delay by 1 cycle * b543286 - test/test_refresh: add Refresher test * 7daf355 - test/test_bist: remove vcd generation (only useful for debug) * b4125fa - test/test_refresh: add RefreshTimer test * 9584c2f - test: remove use of rand_wait, rename rand_level to random * 0eef5d4 - test: add test_refresh with simple RefreshGenerator test * 9348800 - test: rename test_timing_controllers to test_timing * 8cf561d - test/test_timing_controllers: add simple tFAWController tests * 3ae666d - test/test_timing_controllers: add simple tXXDController tests * 394a49a - test: add test_timing_controllers with tXXDController test * 6e3f769 - core: move timing controllers to common * 54cdc7f - test: -x on tests * 2ecb053 - frontend/ecc: move generic part of ECC to LiteX * 8646b2e - test/test_adaption: use same DUT for up/down converter tests * 9f9fed0 - test: merge test_downconverter/test_upconverter in a single test_adaptation file * fc41751 - frontend/dma: simplify rsv_level expose * 88835de - Merge pull request #86 from sergachev/master |\ | * f145287 - dma: expose reservation level in the reader |/ * f018c9e - add CONTRIBUTORS file and add copyright header to all files. * 18dda2d - phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits * 690e4f8 - README: fix ECP5 frequency ratio * liteeth changed from 2424e62 to ad187d3 * ad187d3 - add CONTRIBUTORS file and add copyright header to all files * fd6d6c3 - mac: update imports * a170acd - change MAC location (next to phy/core/frontend), keep import retro-compatibility * 789dadd - liteeth/software: remove libwip/libuip examples. * litepcie changed from de6cd01 to 71c9a3a * 71c9a3a - core/tlp: rewrite controller (simplify, always enable reordering) * 619f5c5 - add CONTRIBUTORS file and copyright header to all files. * litesata changed from 6fe4cce to db5d2f7 * db5d2f7 - add CONTRIBUTORS and copyright header to all files. * litescope changed from 2474ce9 to 9e3b9d8 * 9e3b9d8 - add CONTRIBUTORS file and add copyright header to all files. * 66956cb - Merge pull request #13 from keesj/arty_fast_scope * 144bd06 - Add an example of sampling at 800Mhz using a serdes on arty. * 7f4dc39 - Add functionality to flatten values that are sampled using a serdes. * liteusb changed from 0a9110f to 7457a29 * 7457a29 - README: deprecate, indicate new code location * litex changed from 113f7f40 to e637aa65 * e637aa65 - Merge pull request #222 from antmicro/bump_vexriscv |\ | * 932475a2 - cpu/vexriscv: bump submodule |/ * bc7ab637 - bios/sdram: fix compilation warning * a7895e49 - test/test_axi: remove use of rand_wait, rename rand_level to random * 1cfb36e1 - soc_core: round memory regions size/length to next power of 2 (if not already a power of 2) * 556d2c7c - Merge pull request #221 from antmicro/bump_vexriscv |\ | * 3e89c564 - cpu/vexriscv: bump submodule |/ * e673fce4 - bios/boot: fix default EMULATOR_RAM_BASE * 0acacbaa - cores/clock: cleanup * edf8aa8c - cores/clock: add initial iCE40 support * 6d543358 - cores/spi_flash/add_clk_primitive: return if clk primitive is not needed * 462d12ba - bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET * fc12961e - soc_core: fix cpu_variant definition * af61688d - bios/boot: fix booting rework * 4b686dbd - soc_core: fix cpu_variant config (we don't want the extension) * 7d9cf1d2 - Merge pull request #216 from antmicro/booting_vexriscv_linux |\ | * 8335f13f - bios/boot: rework netboot/flashboot for VexRiscv in linux variant | * a19bdd0e - soc_core: generate extra string-based config defines | * 005c0776 - soc_core: include information about cpu variant in csv and headers * | 95cfd0b9 - cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) * | bfdcf4b2 - platforms/versa_ecp5: add spiflash pads * | 41eb21b3 - soc_core: optimize mem_decoder * | 0eff65bb - cores/up5ksram: optimize bus.adr decoding * | bb99c468 - cores/up5kspram: simplify and add support for all width/depth configurations * | eaf84b85 - cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional * | ea619e3a - cores/spi: rename add_control paramter to add_csr * | ec411a6a - soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs * | bca42f74 - Merge pull request #219 from flammit/fix-ecp5-pll |\ \ | |/ |/| | * c6c74391 - soc: cores: fix name of EHXPLLL output clock in ECP5PLL |/ * d3aaaf5e - cores/spi: fix/simplify loopback * 59fda8da - README: update banner * 769d15d4 - cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test * ee8fec10 - soc/cores: add ECC (Error Correcting Code) * 7dbddb3a - platforms/tinyfpga_bx: add serial extension * 831a1916 - README: add a few links to papers/presentations/tutorials * 95796c5b - Merge pull request #218 from railnova/zynq |\ | * dcf55ad4 - [fix] Slave interface HP0 clk name * | 08772fc0 - Merge pull request #217 from sergachev/master |\ \ | |/ |/| | * dacec6aa - spi: change CSR to CSRStorage |/ * be280bed - soc_zynq: use zynq fabric reset as sys reset * 220f4375 - soc_zynq: add missing axi hp0 clock * 9c8c0371 - soc_zynq: move axi gp0 clock connection to add_gp0 method * b0192e5f - soc_core: use fixed 16MB CSR address space * 68a50317 - soc_sdram: limit main_ram to 512MB for now * ccbf1418 - compiler-rt: update to new location, fixes #209 * 21a5aaa4 - soc_core: declare csr address size when registering csr, fixes #212 * 41b6fbde - soc_cores: fix typos * bff081a8 - Merge pull request #214 from gsomlo/gls-alignment-fixup |\ | * e42f33ed - soc_core: additional csr_alignment follow-up fixes |/ * f4770219 - soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs * 927b7c13 - soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) * 96f45bbd - software/libbase/id: update code (length is now fixed to 256) * 282ae963 - cores: add simple PWM (Pulse Width Modulation) module * 77e7f9b3 - core/spi: make cs_n optional (sometimes managed externally) * e726ad80 - cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) * 4c18c991 - cores: add ICAP core (tested with reconfiguration commands) * 6b82f23c - cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. * ada70e8c - soc/cores/spi: remove too complicated and does not seem reliable in all cases. * 7cd5c0f3 - cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging * d29b8419 - cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) * 3f6bd266 - cores/gpio: remove Blinker * 359b8fe4 - Merge pull request #210 from DurandA/master |\ | * 68eeba91 - Add verilog submodule from CPU cores to manifest |/ * 4ee9c53f - csr: add assert to ensure CSR size < busword (thanks tweakoz) * 0116b2b7 - soc_core: update default RocketChip mem_map * 9d170b09 - soc_core: rearrange default mem_map * 05b667bb - bios/main: fix #ifdefs for fw command * 37687579 - libnet/tftp: fix compilation warning * 9f3c8a9b - bios/main: fix spiflash compilation warnings * 2da59b29 - soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) * b8d45af5 - targets: use new prefered way to add wishbone slave * 7618b845 - soc_core: use new way to add wisbone slave (now prefered) * 740629ba - soc_core: remove 256MB mem_map limitation * b65968c3 - soc/core: remove #!/usr/bin/env python3 * f49d0fe6 - Merge pull request #206 from gsomlo/gls-tftp-spinner |\ | * 5a42dbf3 - BIOS: TFTP: ASCII spinner progress indicator (cosmetic) |/ * d5177d72 - Merge pull request #204 from antmicro/write_to_flash |\ | * 2ee194b2 - bios: add fw (flash write) command * | cef23690 - core/spi_flash: re-integrate bitbang write support |/ * 5cc4c334 - README: remove LiteUSB (deprecated) * dc03b7fa - boards: community supported boards are now located at https://github.com/litex-hub/litex-boards * 0af017e6 - liteeth: update mac imports (olds still works, but that's now the prefered way) * ecf999b8 - soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB * e667d5ae - README: update Intro * 8f6e66ca - make sure #!/usr/bin/env python3 is before copyright header * c7f36ab0 - test: add copyright header * daa4307d - add CONTRIBUTORS file and add copyright header to all files * 361f9d0d - bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) * d8ac9362 - Convert top level comment to a docstring. * 45632c66 - Merge pull request #202 from xobs/add-up5kspram |\ | * 7656f54d - soc: cores: add up5kspram module |/ * 73dbffe8 - cores/frequency_meter: allow passing clk to be measured as a parameter * 408d3f1f - Merge pull request #201 from gsomlo/gls-fix-initmem |\ | * ab827d21 - tools/litex_sim: fix default endianness for mem_init |/ * f47b4902 - Merge pull request #200 from gsomlo/gls-rocket-variants |\ | * f75863fc - cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants |/ * c0df9e08 - cpu/rocket: update submodule * 87118d50 - integration/soc_core: move cpu_variant checks/formating to cpu * f6b67a6d - cpu/vexriscv: add "linux+no-dsp" variant * 95b1b454 - cpu/vexriscv: update * e46d287b - targets/ulx3s: use CAS latency of 3 to be compatible with production boards * litex-renode changed from bd1d0a0 to a57aa47 * a57aa47 - Merge pull request #8 from antmicro/newest_litex_fixes |\ | * aebbe7f - Rework obtaining system clock frequency. | * bd77b6c - Do not generate `csr` memory region. |/ * 0d3b303 - Merge pull request #7 from antmicro/support_more_peripherals * 406eafb - Fix generation of SPI flash peripheral. * ab22e8f - Change VexRiscv configuration. * f799d28 - Generate `cpu` (CPU timer) peripheral. * c2bea62 - Allow to set custom interrupts. * 66a4add - Allow to override the peripheral name. * 409b696 - Generate `cas` (Control And Status) peripheral. * ae3bee6 - Generate `ethphy` peripheral. * migen changed from 0.6.dev-283-g562c046 to 0.6.dev-289-g5585912 * 5585912 - cdc: avoid race between data and request in BusSynchronizer * f4979a2 - cdc: add BlindTransfer (from artiq.rtio.cdc) * dd4ed5d - lattice/diamond: remove source/toolchain_path * b0d9a18 - fix ISE build * caab414 - build: remove tool version detection and sourcing of vendor script * 5c5486b - xilinx: work around Vivado locale bug. Closes #183 Full submodule status -- 42f5fa4ed99b669da4b4169a42eca7dbf5a293c7 edid-decode (remotes/origin/HEAD) 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master) 6c53996a7042050def908882b36e92585b6ef138 litedram (remotes/origin/HEAD) ad187d35f2b967eb152adcc9f1998a914e5bb53a liteeth (heads/master) 71c9a3a2eeaae8c4c44ffae14fb5417b94319206 litepcie (remotes/origin/HEAD) db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master) 9e3b9d84ce6d0e895d0ac275df78ccbd0e0e0ab2 litescope (heads/master) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master) e637aa657b7c1163c7c21c4b972f4aa947406272 litex (remotes/origin/HEAD) a57aa47ff6863f08d75d33fb5545ea489817ac0d litex-renode (remotes/origin/HEAD) 558591288dd08302cb8830310ba6975757b58c72 migen (0.6.dev-289-g5585912) --- third_party/edid-decode | 2 +- third_party/litedram | 2 +- third_party/liteeth | 2 +- third_party/litepcie | 2 +- third_party/litesata | 2 +- third_party/litescope | 2 +- third_party/liteusb | 2 +- third_party/litex | 2 +- third_party/litex-renode | 2 +- third_party/migen | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/third_party/edid-decode b/third_party/edid-decode index 15df4aebf..42f5fa4ed 160000 --- a/third_party/edid-decode +++ b/third_party/edid-decode @@ -1 +1 @@ -Subproject commit 15df4aebf06da579241c58949493b866139d0e2b +Subproject commit 42f5fa4ed99b669da4b4169a42eca7dbf5a293c7 diff --git a/third_party/litedram b/third_party/litedram index 67de3cee1..6c53996a7 160000 --- a/third_party/litedram +++ b/third_party/litedram @@ -1 +1 @@ -Subproject commit 67de3cee14b13beabc90804e3b62c66e028fd951 +Subproject commit 6c53996a7042050def908882b36e92585b6ef138 diff --git a/third_party/liteeth b/third_party/liteeth index 2424e62bf..ad187d35f 160000 --- a/third_party/liteeth +++ b/third_party/liteeth @@ -1 +1 @@ -Subproject commit 2424e62bf9637c2623b627a56aca7a3f90349e92 +Subproject commit ad187d35f2b967eb152adcc9f1998a914e5bb53a diff --git a/third_party/litepcie b/third_party/litepcie index de6cd01d3..71c9a3a2e 160000 --- a/third_party/litepcie +++ b/third_party/litepcie @@ -1 +1 @@ -Subproject commit de6cd01d3f158387337bf4f47fd5a351ec2c3267 +Subproject commit 71c9a3a2eeaae8c4c44ffae14fb5417b94319206 diff --git a/third_party/litesata b/third_party/litesata index 6fe4cceaa..db5d2f788 160000 --- a/third_party/litesata +++ b/third_party/litesata @@ -1 +1 @@ -Subproject commit 6fe4cceaab77d6a117fa539f461b3ae9ca7e668e +Subproject commit db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 diff --git a/third_party/litescope b/third_party/litescope index 2474ce9db..9e3b9d84c 160000 --- a/third_party/litescope +++ b/third_party/litescope @@ -1 +1 @@ -Subproject commit 2474ce9db23e4d06bff4bbeacf0051efa3042f37 +Subproject commit 9e3b9d84ce6d0e895d0ac275df78ccbd0e0e0ab2 diff --git a/third_party/liteusb b/third_party/liteusb index 0a9110f90..7457a29b1 160000 --- a/third_party/liteusb +++ b/third_party/liteusb @@ -1 +1 @@ -Subproject commit 0a9110f901182a1233cc4e64b6e39175f6784621 +Subproject commit 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 diff --git a/third_party/litex b/third_party/litex index 113f7f408..e637aa657 160000 --- a/third_party/litex +++ b/third_party/litex @@ -1 +1 @@ -Subproject commit 113f7f408e7c95150011c55ca473f45befb7f9bb +Subproject commit e637aa657b7c1163c7c21c4b972f4aa947406272 diff --git a/third_party/litex-renode b/third_party/litex-renode index bd1d0a04b..a57aa47ff 160000 --- a/third_party/litex-renode +++ b/third_party/litex-renode @@ -1 +1 @@ -Subproject commit bd1d0a04bb0543ac19e8ebd035c6d25598f2f543 +Subproject commit a57aa47ff6863f08d75d33fb5545ea489817ac0d diff --git a/third_party/migen b/third_party/migen index 562c04664..558591288 160000 --- a/third_party/migen +++ b/third_party/migen @@ -1 +1 @@ -Subproject commit 562c0466443f859d6cf0c87a0bb50db094d27cf4 +Subproject commit 558591288dd08302cb8830310ba6975757b58c72 From 8015c66b665ee2c891cc9fba40f9d65923033d07 Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Wed, 24 Jul 2019 18:36:03 +0200 Subject: [PATCH 2/4] arty/base: change SoCSDRAM memory map This reverts the map to the state before the commit 9d170b0 in LiteX, as the new one does not work with VexRiscv in linux variant. --- targets/arty/base.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/targets/arty/base.py b/targets/arty/base.py index 100025b80..ea9aa6b62 100755 --- a/targets/arty/base.py +++ b/targets/arty/base.py @@ -112,6 +112,13 @@ class BaseSoC(SoCSDRAM): ) csr_map_update(SoCSDRAM.csr_map, csr_peripherals) + SoCSDRAM.mem_map = { + "rom": 0x00000000, # (default shadow @0x80000000) + "sram": 0x10000000, # (default shadow @0x90000000) + "main_ram": 0x40000000, # (default shadow @0xc0000000) + "csr": 0x60000000, # (default shadow @0xe0000000) + } + mem_map = { "spiflash": 0x20000000, # (default shadow @0xa0000000) } From a806ea546a4aa98e100fbf28e9e4a0133a44b83b Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Thu, 25 Jul 2019 09:55:51 +0200 Subject: [PATCH 3/4] firmware: use CONFIG_CLOCK_FREQUENCY instead of SYSTEM_CLOCK_FREQUENCY SYSTEM_CLOCK_FREQUENCY is removed from LiteX in 927b7c1, as it was a duplicate of CONFIG_CLOCK_FREQUENCY. --- firmware/bist.c | 6 +++--- firmware/ci.c | 4 ++-- firmware/encoder.c | 4 ++-- firmware/ethernet.c | 4 ++-- firmware/hdmi_in0.c | 6 +++--- firmware/heartbeat.c | 2 +- firmware/oled.c | 2 +- firmware/pattern.c | 2 +- firmware/uip/clock-arch.c | 2 +- firmware/uptime.c | 2 +- 10 files changed, 17 insertions(+), 17 deletions(-) diff --git a/firmware/bist.c b/firmware/bist.c index 500d07774..c0a50d4ba 100644 --- a/firmware/bist.c +++ b/firmware/bist.c @@ -19,7 +19,7 @@ static void busy_wait(unsigned int ds) { timer0_en_write(0); timer0_reload_write(0); - timer0_load_write(SYSTEM_CLOCK_FREQUENCY/10*ds); + timer0_load_write(CONFIG_CLOCK_FREQUENCY/10*ds); timer0_en_write(1); timer0_update_value_write(1); while(timer0_value_read()) timer0_update_value_write(1); @@ -44,7 +44,7 @@ void bist_test(void) { timer0_update_value_write(1); ticks = timer0_value_read(); ticks = 0xffffffff - ticks; - speed = SYSTEM_CLOCK_FREQUENCY/ticks; + speed = CONFIG_CLOCK_FREQUENCY/ticks; speed = test_size*speed/1000000; speed = 8*speed; printf(" / %u Mbps\n", speed); @@ -66,7 +66,7 @@ void bist_test(void) { timer0_update_value_write(1); ticks = timer0_value_read(); ticks = 0xffffffff - ticks; - speed = SYSTEM_CLOCK_FREQUENCY/ticks; + speed = CONFIG_CLOCK_FREQUENCY/ticks; speed = test_size*speed/1000000; speed = 8*speed; printf(" / %u Mbps\n", speed); diff --git a/firmware/ci.c b/firmware/ci.c index fe13545b5..4a48a46ba 100644 --- a/firmware/ci.c +++ b/firmware/ci.c @@ -582,7 +582,7 @@ static void status_service(void) { static int last_event; - if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) { + if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) { if(status_enabled) { status_print(); wputchar('\n'); @@ -1008,7 +1008,7 @@ static void debug_ddr(void) sdram_controller_bandwidth_update_write(1); nr = sdram_controller_bandwidth_nreads_read(); nw = sdram_controller_bandwidth_nwrites_read(); - f = SYSTEM_CLOCK_FREQUENCY; + f = CONFIG_CLOCK_FREQUENCY; burstbits = (2*DFII_NPHASES) << DFII_PIX_DATA_SIZE; rdb = (nr*f >> (24 - log2(burstbits)))/1000000ULL; wrb = (nw*f >> (24 - log2(burstbits)))/1000000ULL; diff --git a/firmware/encoder.c b/firmware/encoder.c index 1460f85ca..25cde1f17 100644 --- a/firmware/encoder.c +++ b/firmware/encoder.c @@ -178,7 +178,7 @@ void encoder_service(void) { static int can_start; if(encoder_enabled) { - if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY/encoder_target_fps)) + if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY/encoder_target_fps)) can_start = 1; if(can_start & encoder_done()) { encoder_init(encoder_quality); @@ -191,7 +191,7 @@ void encoder_service(void) { encoder_reader_v_width_write(processor_v_active); encoder_reader_start_write(1); } - if(elapsed(&last_fps_event, SYSTEM_CLOCK_FREQUENCY)) { + if(elapsed(&last_fps_event, CONFIG_CLOCK_FREQUENCY)) { encoder_fps = frame_cnt; frame_cnt = 0; } diff --git a/firmware/ethernet.c b/firmware/ethernet.c index 08501e65f..3953195fb 100644 --- a/firmware/ethernet.c +++ b/firmware/ethernet.c @@ -31,8 +31,8 @@ void ethernet_init(const unsigned char * mac_addr, const unsigned char *ip_addr) liteethmac_init(); /* uip periods */ - uip_periodic_period = SYSTEM_CLOCK_FREQUENCY/100; /* 10 ms */ - uip_arp_period = SYSTEM_CLOCK_FREQUENCY/10; /* 100 ms */ + uip_periodic_period = CONFIG_CLOCK_FREQUENCY/100; /* 10 ms */ + uip_arp_period = CONFIG_CLOCK_FREQUENCY/10; /* 100 ms */ /* init uip */ process_init(); diff --git a/firmware/hdmi_in0.c b/firmware/hdmi_in0.c index 7d3fb8d08..ba2d34468 100644 --- a/firmware/hdmi_in0.c +++ b/firmware/hdmi_in0.c @@ -204,7 +204,7 @@ static int wait_idelays(void) while(hdmi_in0_data0_cap_dly_busy_read() || hdmi_in0_data1_cap_dly_busy_read() || hdmi_in0_data2_cap_dly_busy_read()) { - if(elapsed(&ev, SYSTEM_CLOCK_FREQUENCY >> 6) == 0) { + if(elapsed(&ev, CONFIG_CLOCK_FREQUENCY >> 6) == 0) { wprintf("dvisampler0: IDELAY busy timeout (%hhx %hhx %hhx)\n", hdmi_in0_data0_cap_dly_busy_read(), hdmi_in0_data1_cap_dly_busy_read(), @@ -402,7 +402,7 @@ static int hdmi_in0_clocking_locked_filtered(void) lock_status = 1; break; case 1: - if(elapsed(&lock_start_time, SYSTEM_CLOCK_FREQUENCY/4)) + if(elapsed(&lock_start_time, CONFIG_CLOCK_FREQUENCY/4)) lock_status = 2; break; case 2: @@ -432,7 +432,7 @@ void hdmi_in0_service(int freq) } else { if(hdmi_in0_locked) { if(hdmi_in0_clocking_locked_filtered()) { - if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY/2)) { + if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY/2)) { hdmi_in0_adjust_phase(); if(hdmi_in0_debug) hdmi_in0_print_status(); diff --git a/firmware/heartbeat.c b/firmware/heartbeat.c index abaecff0a..a5e78d167 100644 --- a/firmware/heartbeat.c +++ b/firmware/heartbeat.c @@ -30,7 +30,7 @@ void hb_service(fb_ptrdiff_t fb_offset) if (heartbeat_status==1) { hb_fill(color_v, fb_offset); - if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY/FILL_RATE)) { + if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY/FILL_RATE)) { counter = counter + 1; if(counter > FILL_RATE/(HEARTBEAT_FREQUENCY*2)) { color_v = !color_v; diff --git a/firmware/oled.c b/firmware/oled.c index 58a3fe1ea..76e27d363 100644 --- a/firmware/oled.c +++ b/firmware/oled.c @@ -42,7 +42,7 @@ static void busy_wait(unsigned int ds) { timer0_en_write(0); timer0_reload_write(0); - timer0_load_write(SYSTEM_CLOCK_FREQUENCY/100*ds); + timer0_load_write(CONFIG_CLOCK_FREQUENCY/100*ds); timer0_en_write(1); timer0_update_value_write(1); while(timer0_value_read()) timer0_update_value_write(1); diff --git a/firmware/pattern.c b/firmware/pattern.c index b9b3104d6..087991f05 100644 --- a/firmware/pattern.c +++ b/firmware/pattern.c @@ -260,7 +260,7 @@ void pattern_service(void) static int last_event; static char buffer[16]; - if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) { + if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) { sprintf(buffer, "Uptime: %s", uptime_str()); pattern_draw_text(1, 1, buffer); } diff --git a/firmware/uip/clock-arch.c b/firmware/uip/clock-arch.c index 394e5a50a..52ac66621 100644 --- a/firmware/uip/clock-arch.c +++ b/firmware/uip/clock-arch.c @@ -21,7 +21,7 @@ clock_time_t clock_time(void) unsigned int prescaler; clock_time_t ticks; - freq = SYSTEM_CLOCK_FREQUENCY; + freq = CONFIG_CLOCK_FREQUENCY; prescaler = freq/CLOCK_CONF_SECOND; timer0_update_value_write(1); ticks = (0xffffffff - timer0_value_read())/prescaler; diff --git a/firmware/uptime.c b/firmware/uptime.c index e12378d6e..319810dfc 100644 --- a/firmware/uptime.c +++ b/firmware/uptime.c @@ -13,7 +13,7 @@ void uptime_service(void) { static int last_event; - if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) { + if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) { uptime_seconds++; } } From 8a0263f8c8020ef7eedde7d5f49d3e81cc9bf406 Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Thu, 25 Jul 2019 09:57:27 +0200 Subject: [PATCH 4/4] submodules: remove libusb submodule The content of this repo has been merged to LiteX. Now it contains only a README file. --- Makefile | 2 +- scripts/settings.sh | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile b/Makefile index b985f3f0d..63821d9b3 100644 --- a/Makefile +++ b/Makefile @@ -241,7 +241,7 @@ image-flash-py: image # This is indicated by a "git submodule status" that does not start with # a space (" "). # -LITEX_SUBMODULES=migen litex litedram liteeth litepcie litesata litescope liteusb litevideo +LITEX_SUBMODULES=migen litex litedram liteeth litepcie litesata litescope litevideo litex-submodules: $(addsuffix /.git,$(addprefix third_party/,$(LITEX_SUBMODULES))) @if git submodule status --recursive | grep "^[^ ]" >/dev/null; then \ echo ""; \ diff --git a/scripts/settings.sh b/scripts/settings.sh index 4a11ab0f4..4740fab15 100644 --- a/scripts/settings.sh +++ b/scripts/settings.sh @@ -31,6 +31,5 @@ LITE_REPOS=" litepcie litesata litescope - liteusb litevideo "