Yosys synthesis

[donnie-j]

Here is a patch that will allow the boot loader to synthesize with Yosys. All of the changes are simple, and allow the RTL to pass Yosys rather strict syntax (parameter, assignment) and topology checking (IO cell usage).

I have not yet tested the bitstream. The results of synthesis are:
=== TinyFPGA_B ===

Number of wires: 454
Number of wire bits: 1102
Number of public wires: 174
Number of public wire bits: 569
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 706
SB_CARRY 95
SB_DFF 54
SB_DFFE 76
SB_DFFESR 70
SB_DFFESS 46
SB_DFFSR 14
SB_DFFSS 2
SB_LUT4 346
SB_PLL40_CORE 1
SB_RAM40_4K 1
SB_WARMBOOT 1

index 31e8268..3db16f0 100644
--- a/bootloader/verilog/TinyFPGA_B.v
+++ b/bootloader/verilog/TinyFPGA_B.v
@@ -2,27 +2,27 @@ module TinyFPGA_B (
   inout pin1_usb_dp,
   inout pin2_usb_dn,
   input pin3_clk_16mhz,
-  inout pin4,
-  inout pin5,
-  inout pin6,
-  inout pin7,
-  inout pin8,
-  inout pin9,
-  inout pin10,
-  inout pin11,
-  inout pin12,
-  inout pin13,
-  inout pin14_sdo,
-  inout pin15_sdi,
-  inout pin16_sck,
-  inout pin17_ss,
-  inout pin18,
-  inout pin19,
-  inout pin20,
-  inout pin21,
-  inout pin22,
-  inout pin23,
-  inout pin24
+  input pin4,
+  input pin5,
+  input pin6,
+  input pin7,
+  input pin8,
+  input pin9,
+  input pin10,
+  input pin11,
+  output pin12,
+  input pin13,
+  output pin14_sdo,
+  input pin15_sdi,
+  output pin16_sck,
+  output pin17_ss,
+  input pin18,
+  input pin19,
+  input pin20,
+  input pin21,
+  input pin22,
+  input pin23,
+  input pin24
 );
   wire clk_48mhz;
 
@@ -46,7 +46,7 @@ module TinyFPGA_B (
     .PLLOUTGLOBAL(),
     .EXTFEEDBACK(),
     .DYNAMICDELAY(),
-    .RESETB(1),
+    .RESETB(1'b1),
     .BYPASS(1'b0),
     .LATCHINPUTVALUE(),
     .LOCK(),
@@ -127,8 +127,8 @@ module TinyFPGA_B (
   wire reset;
 
   SB_WARMBOOT warmboot_inst (
-    .S1(0),
-    .S0(1),
+    .S1(1'b0),
+    .S0(1'b1),
     .BOOT(host_presence_timeout || boot_to_user_design)
   );
 
@@ -253,23 +253,6 @@ module TinyFPGA_B (
     end
   end
 
-
-  assign pin4 =  1'bz;
-  assign pin5 =  1'bz;
-  assign pin6 =  1'bz;
-  assign pin7 =  1'bz;
-  assign pin10 = 1'bz;
-  assign pin11 = 1'bz;
   assign pin12 = 1'b0;
-  assign pin13 = 1'bz;
-  assign pin18 = 1'bz;
-  assign pin19 = 1'bz;
-  assign pin20 = 1'bz;
-  assign pin21 = 1'bz;
-  assign pin22 = 1'bz;
-  assign pin23 = 1'bz;
-  assign pin24 = 1'bz;
-  assign pin8 =  1'bz;
-  assign pin9 =  1'bz;
 
 endmodule
diff --git a/bootloader/verilog/usb_fs_pe.v b/bootloader/verilog/usb_fs_pe.v
index 56becb0..eabc1cb 100644
--- a/bootloader/verilog/usb_fs_pe.v
+++ b/bootloader/verilog/usb_fs_pe.v
@@ -1,6 +1,6 @@
 module usb_fs_pe #(
-  NUM_OUT_EPS = 1,
-  NUM_IN_EPS = 1
+  parameter NUM_OUT_EPS = 1,
+  parameter NUM_IN_EPS = 1
 ) (
   input clk,
   input [6:0] dev_addr,```

[tinyfpga]

Hmm... those synthesis results are too small. Using Synplify Pro the design consumes 2 BRAMS, 458 DFFs, and 1300 LUTs. I wonder if some parts are getting optimized away somehow.

[Rogdham]

I belive this issue can be closed since there is a working template for project icestorm in the icestorm_template directory.

[donnie-j]

No, the template is the easy part. The problem is synthesis of the bootloader RTL results in a bitstream with incorrect logic, evidenced by impossibly small utilisation.

[Rogdham]

Oh, my bad, I wasn't getting that you were tring to synthetise the bootloader! Sorry for the noise 😯