diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 4cca3c8b50..c85f5c9976 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -194,21 +194,7 @@ class WithCospikeBridge extends ComposeHarnessBinder({
       bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
       has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
     )
-    ports.map {
-      p => p.traces.zipWithIndex.map(t => CospikeBridge(
-        t._1,
-        t._2,
-        cfg.isa,
-        cfg.vlen,
-        cfg.priv,
-        cfg.pmpregions,
-        cfg.mem0_base,
-        cfg.mem0_size,
-        cfg.nharts,
-        cfg.bootrom,
-        cfg.has_dtm
-      ))
-    }
+    ports.map { p => p.traces.zipWithIndex.map(t => CospikeBridge(t._1, t._2, cfg)) }
   }
 })