diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index ccb26c7def..40de41270d 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -35,7 +35,7 @@ class WithArtyTweaks extends Config(
 
 class TinyRocketArtyConfig extends Config(
   new WithArtyTweaks ++
-  new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
+  new freechips.rocketchip.rocket.WithNBreakpoints(2) ++
   new chipyard.TinyRocketConfig
 )
 // DOC include end: AbstractArty and Rocket
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 5b766107b1..d4d09b2cd9 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -8,7 +8,6 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
 import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
 import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
-import freechips.rocketchip.tile.{XLen}
 
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index afcbf7d47e..eaa72deece 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -8,7 +8,6 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
 import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
 import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
-import freechips.rocketchip.tile.{XLen}
 
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
diff --git a/generators/boom b/generators/boom
index 6a3ad0a1d9..6b5523a4c3 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 6a3ad0a1d9ae659aba5aea78978ef1a7cb5dd163
+Subproject commit 6b5523a4c3cf1cfd8fedbe9be96a318bc1bf6c60
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index e435d7aaf8..511576009f 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -17,6 +17,8 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
 case class SpikeCoreParams() extends CoreParams {
+  val xLen = 64
+  val pgLevels = 5
   val useVM = true
   val useHypervisor = false
   val useSupervisor = true
@@ -65,6 +67,8 @@ case class SpikeCoreParams() extends CoreParams {
   val useConditionalZero = false
 
   override def vLen = 128
+  override def eLen = 64
+  override def vfLen = 64
   override def vMemDataBits = 128
 }
 
diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index 2a88ebb2a2..11e86e06e2 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -3,7 +3,7 @@ package chipyard
 import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{XLen, TileParams}
+import freechips.rocketchip.tile.{TileParams}
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
@@ -64,7 +64,7 @@ class TestSuiteHelper
   * Add generic tests (asm, bmark, regression) for all cores.
   */
   def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
-    val xlen = p(XLen)
+    val xlen = p(MaxXLen)
     tiles.find(_.tileId == 0).map { tileParams =>
       val coreParams = tileParams.core
       val vm = coreParams.useVM
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index c34492a47d..08aab4c0e3 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -16,8 +16,8 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up tiles
   //==================================
-  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                             // 1 RocketTile
+  new freechips.rocketchip.rocket.WithAsynchronousCDCs(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++                      // 1 RocketTile
 
   //==================================
   // Set up I/O
diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
index dbf3fa0a5d..da65d9d1cb 100644
--- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -35,7 +35,7 @@ class SymmetricChipletRocketConfig extends Config(
     replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
   ) ++
   new testchipip.soc.WithOffchipBus ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
@@ -71,7 +71,7 @@ class RocketCoreChipletConfig extends Config(
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // LLC-only chiplet
diff --git a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala
index 0d3197ea65..837e732eeb 100644
--- a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala
@@ -14,7 +14,7 @@ import testchipip.soc.{OBUS}
 // Note: This is what designs inheriting from AbstractConfig do by default
 class DefaultClockingRocketConfig extends Config(
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This is a more physically realistic approach, normally we can't punch out a separate
@@ -23,12 +23,12 @@ class DefaultClockingRocketConfig extends Config(
 // clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info
 class ChipLikeClockingRocketConfig extends Config(
   new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single
 // clock input pin.
 class SingleClockBroadcastRocketConfig extends Config(
   new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
index 9de616eab2..1d344ee543 100644
--- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
@@ -7,28 +7,28 @@ import org.chipsalliance.cde.config.{Config}
 // ---------------------
 
 class LargeBoomAndRocketConfig extends Config(
-  new boom.v3.common.WithNLargeBooms(1) ++                          // single-core boom
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new boom.v3.common.WithNLargeBooms(1) ++                    // single-core boom
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class DualLargeBoomAndDualRocketConfig extends Config(
-  new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores
+  new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
+  new freechips.rocketchip.rocket.WithNBigCores(2) ++  // add 2 rocket cores
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DualBoomAndSingleRocket
 class DualLargeBoomAndSingleRocketConfig extends Config(
-  new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++  // add 1 rocket core
+  new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++  // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DualBoomAndSingleRocket
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
-  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
-  new boom.v3.common.WithNLargeBooms(1) ++                    // Add 1 boom core
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNSmallCores(1) ++    // Add a small "control" core
+  new boom.v3.common.WithNLargeBooms(1) ++                 // Add 1 boom core
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++      // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/IbexConfigs.scala b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
index 6d1b6e4e6b..7d472af526 100644
--- a/generators/chipyard/src/main/scala/config/IbexConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
@@ -11,5 +11,6 @@ import org.chipsalliance.cde.config.{Config}
 // Multi-core and 32b heterogeneous configs are supported
 
 class IbexConfig extends Config(
-  new ibex.WithNIbexCores(1) ++
+  new ibex.WithNIbexCores(1) ++
+  new chipyard.config.WithInclusiveCacheWriteBytes(4) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index c1213d937f..eaae215ae9 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -10,51 +10,51 @@ import org.chipsalliance.cde.config.{Config}
 class FFTRocketConfig extends Config(
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++              // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: FFTRocketConfig
 
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDTLRocketConfig
 
 // DOC include start: GCDAXI4BlackBoxRocketConfig
 class GCDAXI4BlackBoxRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++            // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(
   new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: InitZeroRocketConfig
 
 class StreamingPassthroughRocketConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: StreamingFIRRocketConfig
 class StreamingFIRRocketConfig extends Config (
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LargeNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class ManyMMIOAcceleratorRocketConfig extends Config(
@@ -63,5 +63,5 @@ class ManyMMIOAcceleratorRocketConfig extends Config(
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
index fe99d5f13a..2162435c97 100644
--- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
@@ -8,38 +8,38 @@ import org.chipsalliance.cde.config.{Config}
 
 class SimAXIRocketConfig extends Config(
   new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class GB1MemoryRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadOnlyRocketConfig extends Config(
   new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: mbusscratchpadrocket
 
 class SbusScratchpadRocketConfig extends Config(
   new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SbusBypassRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++ // Add bypass path to access DRAM incoherently through an address alias
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class QuadChannelRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BroadcastCoherenceRocketConfig extends Config(
   new chipyard.config.WithBroadcastManager ++                 // Use broadcast-based coherence hub
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index ebd196c3ca..4bc457d938 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -101,7 +101,7 @@ class MultiNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
       routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1))
   )) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNBigCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
   new chipyard.config.AbstractConfig
@@ -180,7 +180,7 @@ class SharedNoCConfig extends Config(
         "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
         "pbus" -> 4))
   )) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNBigCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
   new chipyard.config.AbstractConfig
@@ -216,7 +216,7 @@ class SbusRingNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
   )) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNBigCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig
 )
@@ -260,7 +260,7 @@ class SbusMeshNoCConfig extends Config(
     ),
     beDivision = 4
   ), inlineNoC = true) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(12) ++
+  new freechips.rocketchip.rocket.WithNBigCores(12) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig
@@ -286,6 +286,6 @@ class QuadRocketSbusRingNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
   )) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(4) ++
+  new freechips.rocketchip.rocket.WithNBigCores(4) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index c84427ada6..0da9ef2c7d 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -10,44 +10,44 @@ import freechips.rocketchip.subsystem.{MBUS}
 class LargeSPIFlashROMRocketConfig extends Config(
   new chipyard.harness.WithSimSPIFlashModel(true) ++        // add the SPI flash model in the harness (read-only)
   new chipyard.config.WithSPIFlash ++                       // add the SPI flash controller
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SmallSPIFlashRocketConfig extends Config(
   new chipyard.harness.WithSimSPIFlashModel(false) ++       // add the SPI flash model in the harness (writeable)
   new chipyard.config.WithSPIFlash(0x100000) ++             // add the SPI flash controller (1 MiB)
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++                // drive block-device IOs with SimBlockDevice
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to peripherybus
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
   new chipyard.harness.WithBlockDeviceModel ++              // drive block-device IOs with a BlockDeviceModel
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to periphery bus
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: GPIORocketConfig
 class GPIORocketConfig extends Config(
   new chipyard.config.WithGPIO ++                           // add GPIOs to the peripherybus
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GPIORocketConfig
 
 class LoopbackNICRocketConfig extends Config(
   new chipyard.harness.WithLoopbackNIC ++                      // drive NIC IOs with loopback
   new icenet.WithIceNIC ++                                     // add an IceNIC
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MMIORocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LBWIFRocketConfig extends Config(
@@ -56,14 +56,14 @@ class LBWIFRocketConfig extends Config(
   new testchipip.soc.WithOffchipBus ++
   new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove AXI4 backing memory
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DmiRocket
 
@@ -79,7 +79,7 @@ class ManyPeripheralsRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
   new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class UARTTSIRocketConfig extends Config(
@@ -88,5 +88,5 @@ class UARTTSIRocketConfig extends Config(
   new chipyard.config.WithMemoryBusFrequency(10) ++
   new chipyard.config.WithFrontBusFrequency(10) ++
   new chipyard.config.WithPeripheryBusFrequency(10) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index a654d70fc6..6e210e0bc6 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -9,26 +9,26 @@ import org.chipsalliance.cde.config.{Config}
 // DOC include start: GemminiRocketConfig
 class GemminiRocketConfig extends Config(
   new gemmini.DefaultGemminiConfig ++                            // use Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GemminiRocketConfig
 
 class FPGemminiRocketConfig extends Config(
   new gemmini.GemminiFP32DefaultConfig ++                         // use FP32Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class LeanGemminiRocketConfig extends Config(
   new gemmini.LeanGemminiConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class LeanGemminiPrintfRocketConfig extends Config(
   new gemmini.LeanGemminiPrintfConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
@@ -39,12 +39,12 @@ class MempressRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBanks(8) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=16, capacityKB=2048) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class AES256ECBRocketConfig extends Config(
   new aes.WithAES256ECBAccel ++                                   // use Caliptra AES 256 ECB accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.WithSystemBusWidth(256) ++
   new chipyard.config.AbstractConfig)
 
@@ -55,7 +55,7 @@ class ReRoCCTestConfig extends Config(
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile2 is accum
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile1 is accum
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile0 is accum
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class ReRoCCManyGemminiConfig extends Config(
@@ -64,10 +64,10 @@ class ReRoCCManyGemminiConfig extends Config(
   new gemmini.LeanGemminiConfig ++                              // rerocc tile2 is gemmini
   new gemmini.LeanGemminiConfig ++                              // rerocc tile1 is gemmini
   new gemmini.LeanGemminiConfig ++                              // rerocc tile0 is gemmini
-  new freechips.rocketchip.subsystem.WithNBigCores(4) ++        // 4 rocket cores
+  new freechips.rocketchip.rocket.WithNBigCores(4) ++           // 4 rocket cores
   new chipyard.config.AbstractConfig)
 
 class ZstdCompressorRocketConfig extends Config(
   new compressacc.WithZstdCompressor ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index c0ee4bbad9..5bbb1810e4 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -9,11 +9,11 @@ import freechips.rocketchip.subsystem.{InCluster}
 // --------------
 
 class RocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
 class DualRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++
+  new freechips.rocketchip.rocket.WithNBigCores(2) ++
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
@@ -22,21 +22,21 @@ class TinyRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
   new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
   new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
-  new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
+  new freechips.rocketchip.rocket.With1TinyCore ++                // single tiny rocket-core
   new chipyard.config.AbstractConfig)
 
 class QuadRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithNBigCores(4) ++    // quad-core (4 RocketTiles)
+  new freechips.rocketchip.rocket.WithNBigCores(4) ++    // quad-core (4 RocketTiles)
   new chipyard.config.AbstractConfig)
 
 class Cloned64RocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithCloneRocketTiles(63, 0) ++ // copy tile0 63 more times
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++            // tile0 is a BigRocket
+  new freechips.rocketchip.rocket.WithCloneRocketTiles(63, 0) ++ // copy tile0 63 more times
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++            // tile0 is a BigRocket
   new chipyard.config.AbstractConfig)
 
 class RV32RocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithRV32 ++            // set RocketTiles to be 32-bit
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithRV32 ++            // set RocketTiles to be 32-bit
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: l1scratchpadrocket
@@ -45,8 +45,8 @@ class ScratchpadOnlyRocketConfig extends Config(
   new testchipip.soc.WithNoScratchpads ++                      // remove subsystem scratchpads, confusingly named, does not remove the L1D$ scratchpads
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // remove offchip mem port
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 DCache scratchpad as base phys mem
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithScratchpadsOnly ++       // use rocket l1 DCache scratchpad as base phys mem
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: l1scratchpadrocket
 
@@ -59,12 +59,12 @@ class MMIOScratchpadOnlyRocketConfig extends Config(
 class L1ScratchpadRocketConfig extends Config(
   new chipyard.config.WithRocketICacheScratchpad ++         // use rocket ICache scratchpad
   new chipyard.config.WithRocketDCacheScratchpad ++         // use rocket DCache scratchpad
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MulticlockRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithAsynchronousCDCs(8, 3) ++ // Add async crossings between RocketTile and uncore
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   // Frequency specifications
   new chipyard.config.WithTileFrequency(1000.0) ++        // Matches the maximum frequency of U540
   new chipyard.clocking.WithClockGroupsCombinedByName(("uncore"   , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil),
@@ -82,7 +82,7 @@ class CustomIOChipTopRocketConfig extends Config(
   new chipyard.example.WithBrokenOutUARTIO ++
   new chipyard.example.WithCustomChipTop ++
   new chipyard.example.WithCustomIOCells ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
 class PrefetchingRocketConfig extends Config(
@@ -90,13 +90,13 @@ class PrefetchingRocketConfig extends Config(
   new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++             // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2
   new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++                // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2
   new chipyard.config.WithTilePrefetchers ++                                           // add TL prefetchers between tiles and the sbus
-  new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++                           // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                               // single rocket-core
+  new freechips.rocketchip.rocket.WithL1DCacheNonblocking(2) ++                        // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++                                  // single rocket-core
   new chipyard.config.AbstractConfig)
 
 class ClusteredRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(1)) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(0)) ++
+  new freechips.rocketchip.rocket.WithNBigCores(4, location=InCluster(1)) ++
+  new freechips.rocketchip.rocket.WithNBigCores(4, location=InCluster(0)) ++
   new freechips.rocketchip.subsystem.WithCluster(1) ++
   new freechips.rocketchip.subsystem.WithCluster(0) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 2edda3ce97..f531fe0305 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -9,7 +9,6 @@ class Sodor1StageConfig extends Config(
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
   new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new chipyard.config.AbstractConfig)
@@ -19,7 +18,6 @@ class Sodor2StageConfig extends Config(
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
   new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new chipyard.config.AbstractConfig)
@@ -29,7 +27,6 @@ class Sodor3StageConfig extends Config(
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
   new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new chipyard.config.AbstractConfig)
@@ -39,7 +36,6 @@ class Sodor3StageSinglePortConfig extends Config(
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
   new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new chipyard.config.AbstractConfig)
@@ -49,7 +45,6 @@ class Sodor5StageConfig extends Config(
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
   new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new chipyard.config.AbstractConfig)
@@ -59,7 +54,6 @@ class SodorUCodeConfig extends Config(
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
   new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index dca2af0347..dd3175cbc7 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -27,7 +27,7 @@ class TutorialStarterConfig extends Config(
   // CUSTOMIZE THE CORE
   // Uncomment out one (or multiple) of the lines below, and choose
   // how many cores you want.
-  // new freechips.rocketchip.subsystem.WithNBigCores(1) ++    // Specify we want some number of Rocket cores
+  // new freechips.rocketchip.rocket.WithNBigCores(1) ++    // Specify we want some number of Rocket cores
   // new boom.v3.common.WithNSmallBooms(1) ++                     // Specify we want some number of BOOM cores
 
   // CUSTOMIZE the L2
@@ -46,7 +46,7 @@ class TutorialMMIOConfig extends Config(
   // new chipyard.example.WithGCD(useAXI4=true) ++  // Use AXI4 version
 
   // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig
 )
 
@@ -90,6 +90,6 @@ class TutorialNoCConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++
 
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++
+  new freechips.rocketchip.rocket.WithNBigCores(2) ++
   new chipyard.config.AbstractConfig
 )
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index 87229cb452..a4931220cb 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -10,7 +10,6 @@ import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, D
 import freechips.rocketchip.prci.{AsynchronousCrossing}
 import chipyard.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{XLen}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -36,7 +35,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt =
         address = address,
         size = size,
         hang = hang,
-        contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"
+        contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(MaxXLen)}.img"
       ))
 })
 
diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
index 4289928621..3aaae1771f 100644
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -18,6 +18,10 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
 })
 
+class WithInclusiveCacheWriteBytes(b: Int) extends Config((site, here, up) => {
+  case InclusiveCacheKey => up(InclusiveCacheKey).copy(writeBytes = b)
+})
+
 // Adds buffers on the interior of the inclusive LLC, to improve PD
 class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
   case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index b61b99f389..1186bcaad6 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -5,7 +5,7 @@ import chisel3._
 import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, PgLevels}
+import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
 
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
@@ -75,14 +75,6 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
   }
 })
 
-class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(rowBits = rowBits)),
-      icache = tp.tileParams.icache.map(_.copy(rowBits = rowBits))
-    ))
-  }
-})
 
 class WithRocketICacheScratchpad extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -117,22 +109,14 @@ class WithTilePrefetchers extends Config((site, here, up) => {
   }
 })
 
-// Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
-// This typically makes it easier to close timing
-class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
-      boundaryBuffers=buffers
-    ))
-  }
-})
-
 // Uses SV48 if possible, otherwise default to the Rocket Chip core default
 class WithSV48IfPossible extends Config((site, here, up) => {
-  case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
-})
-
-// Uses SV39 if possible, otherwise default to the Rocket Chip core default
-class WithSV39 extends Config((site, here, up) => {
-  case PgLevels => { require(site(XLen) == 64); 3; }
+  case TilesLocated(loc) => up(TilesLocated(loc), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core =
+      tp.tileParams.core.copy(pgLevels = 4)))
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core =
+      tp.tileParams.core.copy(pgLevels = 4)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core =
+      tp.tileParams.core.copy(pgLevels = 4)))
+  }
 })
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index f69ec864c9..bc2bb7084d 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -26,6 +26,8 @@ case class MyCoreParams(
   bhtEntries: Int = 16,
   enableToFromHostCaching: Boolean = false,
 ) extends CoreParams {
+  val xLen: Int = 32
+  val pgLevels: Int = 2
   val useVM: Boolean = true
   val useHypervisor: Boolean = false
   val useUser: Boolean = true
@@ -245,8 +247,6 @@ class WithNMyCores(n: Int = 1) extends Config((site, here, up) => {
   }
   // Configurate # of bytes in one memory / IO transaction. For RV64, one load/store instruction can transfer 8 bytes at most.
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
-  // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits.
-  case XLen => 64
   case NumTiles => up(NumTiles) + n
 })
 // DOC include end: Config fragment
diff --git a/generators/cva6 b/generators/cva6
index de4772f1d6..cafef4a4b8 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit de4772f1d66cc6d4ef42e75f34c42eb7b941c8f0
+Subproject commit cafef4a4b8722e5a18bf3ddad359926fe92a0808
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index c61c4ad948..832c9c89c3 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -22,8 +22,8 @@ import firesim.configs._
 
 class WithBootROM extends Config((site, here, up) => {
   case BootROMLocated(x) => {
-    val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
-    val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
+    val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img")
+    val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img")
 
     val bootROMPath = if (chipyardBootROM.exists()) {
       chipyardBootROM.getAbsolutePath()
@@ -198,7 +198,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
   //  Crossing specifications
   new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
   new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
-  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
+  new freechips.rocketchip.rocket.WithRationalCDCs ++   // Add rational crossings between RocketTile and uncore
   new boom.v3.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
   new WithFireSimDesignTweaks
 )
@@ -384,5 +384,5 @@ class FireSimLargeBoomSV39CospikeConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks++
-  new chipyard.config.WithSV39 ++
+  new freechips.rocketchip.rocket.WithSV39 ++
   new chipyard.LargeBoomV3Config)
diff --git a/generators/gemmini b/generators/gemmini
index f92444503f..25809f7832 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit f92444503f5561f581ff06f49174039dacf95f2e
+Subproject commit 25809f78323a729ef76fb68f3cedd8a24da2942b
diff --git a/generators/ibex b/generators/ibex
index 8a43aa70da..06b3983d36 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 8a43aa70da1c06f4d34ec8710a3d2ee7585948a5
+Subproject commit 06b3983d36105c850d2feeaf104047bd9b5c4ac6
diff --git a/generators/rerocc b/generators/rerocc
index a22dce622d..e334374491 160000
--- a/generators/rerocc
+++ b/generators/rerocc
@@ -1 +1 @@
-Subproject commit a22dce622db350e4a159ed90cf83d00782ed8187
+Subproject commit e334374491a59ff0c69be702a2f1a652ac6185a2
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index 732cbe1990..83c7e490b8 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit 732cbe1990e9ef55ba122664465b372744f2eaab
+Subproject commit 83c7e490b85216a3e74d31aa04c62b4f9e33ddc4
diff --git a/generators/rocket-chip b/generators/rocket-chip
index ea9979b1c6..93cef4edfe 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit ea9979b1c6e3cc078a6efe1f58012180753c5ec8
+Subproject commit 93cef4edfe8d940e3dbd06d90541f3c4645c11fc
diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache
index 4aab5460bd..8e157c808c 160000
--- a/generators/rocket-chip-inclusive-cache
+++ b/generators/rocket-chip-inclusive-cache
@@ -1 +1 @@
-Subproject commit 4aab5460bd569b2142eb760e4772ea8db6998dc3
+Subproject commit 8e157c808c8ba019b6fdb42232c4e6ac6b11b439
diff --git a/generators/shuttle b/generators/shuttle
index 799263c618..8bddf96ff9 160000
--- a/generators/shuttle
+++ b/generators/shuttle
@@ -1 +1 @@
-Subproject commit 799263c6180587670fe42de23f3338f1f218d87e
+Subproject commit 8bddf96ff95b7109261d4df6524ea0ebc89b0612
diff --git a/generators/testchipip b/generators/testchipip
index c27a2e4a59..0bd83bcf0b 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit c27a2e4a59163c18bd27bdb165cb01b57864d6cf
+Subproject commit 0bd83bcf0b9b82259e1e510ed755f1787c3458bc
diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
index 85fdf3372e..20d884dbc0 100644
--- a/generators/tracegen/src/main/scala/Configs.scala
+++ b/generators/tracegen/src/main/scala/Configs.scala
@@ -7,14 +7,15 @@ import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
 import freechips.rocketchip.rocket.DCacheParams
-import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
+import freechips.rocketchip.tile.{MaxHartIdBits}
 import scala.math.{max, min}
 
 class WithTraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
-  nReqs: Int = 8192
+  nReqs: Int = 8192,
+  wordBits: Int = 64
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
@@ -25,7 +26,7 @@ class WithTraceGen(
         tileParams = TraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
-          wordBits = site(XLen),
+          wordBits = wordBits,
           addrBits = 48,
           addrBag = {
             val nSets = dcp.nSets
@@ -53,7 +54,8 @@ class WithBoomV3TraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
-  nReqs: Int = 8192
+  nReqs: Int = 8192,
+  wordBits: Int = 64
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
@@ -64,7 +66,7 @@ class WithBoomV3TraceGen(
         tileParams = boom.v3.lsu.BoomTraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
-          wordBits = site(XLen),
+          wordBits = wordBits,
           addrBits = 48,
           addrBag = {
             val nSets = dcp.nSets
@@ -89,7 +91,8 @@ class WithBoomV4TraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
-  nReqs: Int = 8192
+  nReqs: Int = 8192,
+  wordBits: Int = 64
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
@@ -100,7 +103,7 @@ class WithBoomV4TraceGen(
         tileParams = boom.v4.lsu.BoomTraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
-          wordBits = site(XLen),
+          wordBits = wordBits,
           addrBits = 48,
           addrBag = {
             val nSets = dcp.nSets
@@ -125,7 +128,8 @@ class WithL2TraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
-  nReqs: Int = 8192
+  nReqs: Int = 8192,
+  wordBits: Int = 64
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
@@ -137,7 +141,7 @@ class WithL2TraceGen(
         tileParams = TraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
-          wordBits = site(XLen),
+          wordBits = wordBits,
           addrBits = 48,
           addrBag = {
             val sbp = site(SystemBusKey)
diff --git a/tools/stage-chisel3/src/main/scala/phases/AddDefaultTests.scala b/tools/stage-chisel3/src/main/scala/phases/AddDefaultTests.scala
index 01e963d19d..3434f392a1 100644
--- a/tools/stage-chisel3/src/main/scala/phases/AddDefaultTests.scala
+++ b/tools/stage-chisel3/src/main/scala/phases/AddDefaultTests.scala
@@ -13,8 +13,7 @@ import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options._
 import firrtl.options.Viewer._
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
-import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
-import freechips.rocketchip.tile.XLen
+import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem, MaxXLen}
 
 import chipyard.TestSuiteHelper
 import chipyard.TestSuitesKey
@@ -34,7 +33,7 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasChipyardSta
     // Use Xlen as a proxy for detecting if we are a processor-like target
     // The underlying test suites expect this field to be defined
     val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
-    if (p.lift(XLen).nonEmpty)
+    if (p.lift(MaxXLen).nonEmpty)
       // If a custom test suite is set up, use the custom test suite
       annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
 
diff --git a/tools/stage/src/main/scala/phases/AddDefaultTests.scala b/tools/stage/src/main/scala/phases/AddDefaultTests.scala
index e0addc401e..758131ad05 100644
--- a/tools/stage/src/main/scala/phases/AddDefaultTests.scala
+++ b/tools/stage/src/main/scala/phases/AddDefaultTests.scala
@@ -13,8 +13,7 @@ import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options._
 import firrtl.options.Viewer._
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
-import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
-import freechips.rocketchip.tile.XLen
+import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem, MaxXLen}
 
 import chipyard.TestSuiteHelper
 import chipyard.TestSuitesKey
@@ -34,7 +33,7 @@ class AddDefaultTests extends Phase with PreservesAll with HasChipyardStageUtils
     // Use Xlen as a proxy for detecting if we are a processor-like target
     // The underlying test suites expect this field to be defined
     val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
-    if (p.lift(XLen).nonEmpty)
+    if (p.lift(MaxXLen).nonEmpty)
       // If a custom test suite is set up, use the custom test suite
       annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))