diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index dd02d55e21..2dd207c978 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -462,7 +462,6 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, cfg.bootargs = nullptr; cfg.isa = isastr; cfg.priv = "MSU"; - cfg.varch = "vlen:128,elen:64"; cfg.misaligned = false; cfg.endianness = endianness_little; cfg.pmpregions = pmpregions; @@ -1076,7 +1075,7 @@ void chipyard_simif_t::loadmem(size_t base, const char* fname) { } loadmem_memif(this, tcm_base); reg_t entry; - load_elf(fname, &loadmem_memif, &entry); + load_elf(fname, &loadmem_memif, &entry, 0); } bool insn_should_fence(uint64_t bits) { diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 6811be7a45..e435d7aaf8 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -115,7 +115,7 @@ class SpikeTile( val masterNode = visibilityNode val slaveNode = TLIdentityNode() - override def isaDTS = "rv64gcv_Zfh" + override def isaDTS = "rv64imafdcv_zicsr_zifencei_zihpm_zvl128b_zve64d" // Required entry of CPU device in the device tree for interrupt purpose val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,spike", "riscv")) { diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 61f347443c..ca64fc47be 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -486,7 +486,6 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({ val tiles = chipyardSystem.totalTiles.values val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), - vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0), priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""), mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)), mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), diff --git a/generators/testchipip b/generators/testchipip index 5856bedf49..c27a2e4a59 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5856bedf495188a95934969eac19a5fd9534bb0a +Subproject commit c27a2e4a59163c18bd27bdb165cb01b57864d6cf diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index fe42d9971b..6d0daa0d23 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -142,7 +142,8 @@ echo "quit" >> $CMDS_FILE echo "spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY" > $SPIKECMD_FILE echo "Capturing state at checkpoint to spikeout" -spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY 2> $LOADARCH_FILE +echo $NHARTS > $LOADARCH_FILE +spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY 2>> $LOADARCH_FILE echo "Finding tohost/fromhost in elf file" diff --git a/sims/firesim b/sims/firesim index 62ce5cbcba..7cc90d1844 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 62ce5cbcbaf62e4fc8270b96e2abadbb9973c208 +Subproject commit 7cc90d184404006aa63ab5e9d999987faddf9ffd diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 4d8651be94..1b1a333763 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 4d8651be943ea706eb8dcb3443add2e7ccc117a6 +Subproject commit 1b1a333763eae2e74dbf38b39d9adab39c4bed7c diff --git a/toolchains/riscv-tools/riscv-spike-devices b/toolchains/riscv-tools/riscv-spike-devices index cc184f2cc1..67e123c1ca 160000 --- a/toolchains/riscv-tools/riscv-spike-devices +++ b/toolchains/riscv-tools/riscv-spike-devices @@ -1 +1 @@ -Subproject commit cc184f2cc179765bb7dcf4a82075403604a60813 +Subproject commit 67e123c1ca09533b0cde9b2cfc7b8a1f36155c46