From 4d31ccf218fb97a2601f9e42950046c5712c2cc3 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sun, 12 Feb 2023 20:36:09 -0800 Subject: [PATCH 1/4] Remove gen-collateral when rebuilding --- common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/common.mk b/common.mk index 820b6d4429..433406159c 100644 --- a/common.mk +++ b/common.mk @@ -102,6 +102,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS) + if [ -d $(OUT_DIR) ]; then rm -rf $(OUT_DIR); fi mkdir -p $(build_dir) $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ From 6cd46d3c73bb96ff36e377dcc68549fc4bbb90d5 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 13 Feb 2023 02:14:23 -0800 Subject: [PATCH 2/4] fixes --- common.mk | 1 - fpga/Makefile | 7 ++++--- sims/vcs/Makefile | 7 ++++--- sims/verilator/Makefile | 7 ++++--- vlsi/Makefile | 7 ++++--- 5 files changed, 16 insertions(+), 13 deletions(-) diff --git a/common.mk b/common.mk index 433406159c..820b6d4429 100644 --- a/common.mk +++ b/common.mk @@ -102,7 +102,6 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS) - if [ -d $(OUT_DIR) ]; then rm -rf $(OUT_DIR); fi mkdir -p $(build_dir) $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ diff --git a/fpga/Makefile b/fpga/Makefile index d037833bb2..4ae4bb0f60 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -94,10 +94,11 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v # copy files but ignore *.h files in *.f (match vcs) -$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) - cp -f $^ $(OUT_DIR) +$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR) + rm -rf $(OUT_DIR)/* + cp -f $(SIM_FILE_REQS) $(OUT_DIR) $(foreach file,\ - $^,\ + $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ ,\ echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index d407fe4f2c..3e78643dc3 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -38,10 +38,11 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) - cp -f $^ $(OUT_DIR) +$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR) + rm -rf $(OUT_DIR)/* + cp -f $(SIM_FILE_REQS) $(OUT_DIR) $(foreach file,\ - $^,\ + $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ ,\ echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 5c15973ad7..269915a943 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -66,10 +66,11 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f -$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) - cp -f $^ $(OUT_DIR) +$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR) + rm -rf $(OUT_DIR)/* + cp -f $(SIM_FILE_REQS) $(OUT_DIR) $(foreach file,\ - $^,\ + $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ echo "-FI $(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;,\ echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) diff --git a/vlsi/Makefile b/vlsi/Makefile index 228401b2c6..e699a476d7 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -108,10 +108,11 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) +$(sim_files): $(SIM_FILE_REQS) $(build_dir) + rm -rf $(build_dir)/* + cp -f $(SIM_FILE_REQS) $(build_dir) $(foreach file,\ - $^,\ + $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ ,\ echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) From 58a6e725289be76cacb31081edde75ca1d8d2a47 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 13 Feb 2023 13:24:04 -0800 Subject: [PATCH 3/4] rename OUT_DIR to GEN_COLLATERAL_DIR --- common.mk | 10 +++++----- fpga/Makefile | 8 ++++---- sims/common-sim-flags.mk | 2 +- sims/vcs/Makefile | 8 ++++---- sims/verilator/Makefile | 14 +++++++------- variables.mk | 14 +++++++------- vcs.mk | 2 +- 7 files changed, 29 insertions(+), 29 deletions(-) diff --git a/common.mk b/common.mk index 820b6d4429..dffd16c238 100644 --- a/common.mk +++ b/common.mk @@ -91,7 +91,7 @@ endif ######################################################################################### # copy over bootrom files ######################################################################################### -$(build_dir) $(OUT_DIR): +$(build_dir) $(GEN_COLLATERAL_DIR): mkdir -p $@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) @@ -172,7 +172,7 @@ endif --no-dedup \ --output-file $(SFC_FIRRTL_BASENAME) \ --output-annotation-file $(SFC_ANNO_FILE) \ - --target-dir $(OUT_DIR) \ + --target-dir $(GEN_COLLATERAL_DIR) \ --input-file $(FIRRTL_FILE) \ --annotation-file $(FINAL_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ @@ -198,7 +198,7 @@ endif --repl-seq-mem-circuit=$(MODEL) \ --annotation-file=$(SFC_ANNO_FILE) \ --split-verilog \ - -o $(OUT_DIR) \ + -o $(GEN_COLLATERAL_DIR) \ $(SFC_FIRRTL_FILE) -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler @@ -211,8 +211,8 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL --out-dut-filelist $(TOP_MODS_FILELIST) \ --out-model-filelist $(MODEL_MODS_FILELIST) \ --in-all-filelist $(MFC_FILELIST) \ - --target-dir $(OUT_DIR) - $(SED) -e 's;^;$(OUT_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) + --target-dir $(GEN_COLLATERAL_DIR) + $(SED) -e 's;^;$(GEN_COLLATERAL_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) diff --git a/fpga/Makefile b/fpga/Makefile index 4ae4bb0f60..cee60f525f 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -94,14 +94,14 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v # copy files but ignore *.h files in *.f (match vcs) -$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR) - rm -rf $(OUT_DIR)/* - cp -f $(SIM_FILE_REQS) $(OUT_DIR) +$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) + rm -rf $(GEN_COLLATERAL_DIR)/* + cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) $(foreach file,\ $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ ,\ - echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) + echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) ######################################################################################### # import other necessary rules and variables diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 3b4281c3a5..8787e60ae2 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -20,7 +20,7 @@ SIM_CXXFLAGS = \ -std=c++17 \ -I$(RISCV)/include \ -I$(dramsim_dir) \ - -I$(OUT_DIR) \ + -I$(GEN_COLLATERAL_DIR) \ $(EXTRA_SIM_CXXFLAGS) SIM_LDFLAGS = \ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 3e78643dc3..289b1b531a 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -38,14 +38,14 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR) - rm -rf $(OUT_DIR)/* - cp -f $(SIM_FILE_REQS) $(OUT_DIR) +$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) + rm -rf $(GEN_COLLATERAL_DIR)/* + cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) $(foreach file,\ $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ ,\ - echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) + echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) ######################################################################################### # import other necessary rules and variables diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 269915a943..eb0ad41dad 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -66,14 +66,14 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f -$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR) - rm -rf $(OUT_DIR)/* - cp -f $(SIM_FILE_REQS) $(OUT_DIR) +$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) + rm -rf $(GEN_COLLATERAL_DIR)/* + cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) $(foreach file,\ $(SIM_FILE_REQS),\ $(if $(filter %.h,$(file)),\ - echo "-FI $(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;,\ - echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) + echo "-FI $(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;,\ + echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) ######################################################################################### # import other necessary rules and variables @@ -144,7 +144,7 @@ CHIPYARD_VERILATOR_FLAGS := \ # options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ - if grep -qiP "module\s+(CVA6|NVDLA)" $(OUT_DIR)/*.*v; \ + if grep -qiP "module\s+(CVA6|NVDLA)" $(GEN_COLLATERAL_DIR)/*.*v; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) @@ -182,7 +182,7 @@ VERILATOR_CXXFLAGS = \ -DTEST_HARNESS=V$(VLOG_MODEL) \ -DVERILATOR \ -include $(build_dir)/$(long_name).plusArgs \ - -include $(OUT_DIR)/verilator.h + -include $(GEN_COLLATERAL_DIR)/verilator.h VERILATOR_LDFLAGS = $(SIM_LDFLAGS) diff --git a/variables.mk b/variables.mk index fab54a6a9a..2172fbe57f 100644 --- a/variables.mk +++ b/variables.mk @@ -161,18 +161,18 @@ MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf # hardcoded firtool outputs -MFC_FILELIST = $(OUT_DIR)/filelist.f -MFC_BB_MODS_FILELIST = $(OUT_DIR)/firrtl_black_box_resource_files.f -MFC_TOP_SMEMS_JSON = $(OUT_DIR)/metadata/seq_mems.json -MFC_MODEL_SMEMS_JSON = $(OUT_DIR)/metadata/tb_seq_mems.json +MFC_FILELIST = $(GEN_COLLATERAL_DIR)/filelist.f +MFC_BB_MODS_FILELIST = $(GEN_COLLATERAL_DIR)/firrtl_black_box_resource_files.f +MFC_TOP_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/seq_mems.json +MFC_MODEL_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/tb_seq_mems.json # macrocompiler smems in/output SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf -TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v +TOP_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).top.mems.v TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf -MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v +MODEL_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).model.mems.v MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir # top module files to include @@ -254,7 +254,7 @@ gen_dir=$(sim_dir)/generated-src # per-project output directory build_dir=$(gen_dir)/$(long_name) # final generated collateral per-project -OUT_DIR ?= $(build_dir)/gen-collateral +GEN_COLLATERAL_DIR ?= $(build_dir)/gen-collateral ######################################################################################### # assembly/benchmark variables diff --git a/vcs.mk b/vcs.mk index 002fd09af7..edd19f8cd6 100644 --- a/vcs.mk +++ b/vcs.mk @@ -51,7 +51,7 @@ VCS_NONCC_OPTS = \ -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ - +incdir+$(OUT_DIR) + +incdir+$(GEN_COLLATERAL_DIR) PREPROC_DEFINES = \ +define+VCS \ From 55950b61b9bc4dd7254bb5de30b070e224f89a6e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 15 Feb 2023 11:31:47 -0800 Subject: [PATCH 4/4] Move sim_files creation after FIRTOOL | Have FIRTOOL delete collateral dir --- common.mk | 8 +++++--- fpga/Makefile | 7 +++---- sims/vcs/Makefile | 7 +++---- sims/verilator/Makefile | 7 +++---- vlsi/Makefile | 7 +++---- 5 files changed, 17 insertions(+), 19 deletions(-) diff --git a/common.mk b/common.mk index dffd16c238..087335636a 100644 --- a/common.mk +++ b/common.mk @@ -91,7 +91,7 @@ endif ######################################################################################### # copy over bootrom files ######################################################################################### -$(build_dir) $(GEN_COLLATERAL_DIR): +$(build_dir): mkdir -p $@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) @@ -101,7 +101,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip # create firrtl file rule and variables ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ @@ -144,7 +144,8 @@ SFC_MFC_TARGETS = \ $(MFC_MODEL_HRCHY_JSON) \ $(MFC_MODEL_SMEMS_JSON) \ $(MFC_FILELIST) \ - $(MFC_BB_MODS_FILELIST) + $(MFC_BB_MODS_FILELIST) \ + $(GEN_COLLATERAL_DIR) SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) @@ -161,6 +162,7 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) + rm -rf $(GEN_COLLATERAL_DIR) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) diff --git a/fpga/Makefile b/fpga/Makefile index cee60f525f..20676835a2 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -94,11 +94,10 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v # copy files but ignore *.h files in *.f (match vcs) -$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) - rm -rf $(GEN_COLLATERAL_DIR)/* - cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) +$(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR) + cp -f $^ $(GEN_COLLATERAL_DIR) $(foreach file,\ - $(SIM_FILE_REQS),\ + $^,\ $(if $(filter %.h,$(file)),\ ,\ echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 289b1b531a..b26df84331 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -38,11 +38,10 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) - rm -rf $(GEN_COLLATERAL_DIR)/* - cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) +$(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR) + cp -f $^ $(GEN_COLLATERAL_DIR) $(foreach file,\ - $(SIM_FILE_REQS),\ + $^,\ $(if $(filter %.h,$(file)),\ ,\ echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index eb0ad41dad..fd171b4cb3 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -66,11 +66,10 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f -$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) - rm -rf $(GEN_COLLATERAL_DIR)/* - cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) +$(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR) + cp -f $^ $(GEN_COLLATERAL_DIR) $(foreach file,\ - $(SIM_FILE_REQS),\ + $^,\ $(if $(filter %.h,$(file)),\ echo "-FI $(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;,\ echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) diff --git a/vlsi/Makefile b/vlsi/Makefile index e699a476d7..228401b2c6 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -108,11 +108,10 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) $(build_dir) - rm -rf $(build_dir)/* - cp -f $(SIM_FILE_REQS) $(build_dir) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) + cp -f $^ $(build_dir) $(foreach file,\ - $(SIM_FILE_REQS),\ + $^,\ $(if $(filter %.h,$(file)),\ ,\ echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))