diff --git a/docs/Advanced-Concepts/Harness-Clocks.rst b/docs/Advanced-Concepts/Harness-Clocks.rst index ef2249749e..e7501cec96 100644 --- a/docs/Advanced-Concepts/Harness-Clocks.rst +++ b/docs/Advanced-Concepts/Harness-Clocks.rst @@ -18,12 +18,12 @@ for a new clock domain. This is useful for simulating systems in which modules in the harness have independent clock domains from the DUT. -Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/TestHarness.scala``. +Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/harness/TestHarness.scala``. This class is accessed in harness components by referencing the Rocket Chip parameters key ``p(HarnessClockInstantiatorKey)``. Then you can request a clock and syncronized reset at a particular frequency by invoking the ``requestClockBundle`` function. Take the following example: -.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala :language: scala :start-after: DOC include start: HarnessClockInstantiatorEx :end-before: DOC include end: HarnessClockInstantiatorEx diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 1ae95512aa..d3626a03c4 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -31,7 +31,7 @@ Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarne For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present. -.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala :language: scala :start-after: DOC include start: WithUARTAdapter :end-before: DOC include end: WithUARTAdapter diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index 2da52d24ad..890d991c67 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -115,7 +115,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped .. code-block:: shell - ./view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds + ./view_gds.py build/chipyard.harness.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. @@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc CONFIG=TinyRocketConfig - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc make lvs CONFIG=TinyRocketConfig - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 4bc8449ec5..300a22d785 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -121,7 +121,7 @@ It is recommended that you edit these variables directly in the Makefile rather The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources and (2) the mapping of memory instances in the design to SRAM macros; -all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows (due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate @@ -168,9 +168,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc tutorial=sky130-commercial - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-commercial - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 882429d7c7..6777bb7908 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -149,7 +149,7 @@ It is recommended that you edit these variables directly in the Makefile rather The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources and (2) the mapping of memory instances in the design to SRAM macros; -all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows (due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate @@ -197,7 +197,7 @@ Hammer generates a convenient script to launch these sessions .. code-block:: shell - cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + cd ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated-scripts/open_chip Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout, @@ -212,7 +212,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin .. code-block:: shell - cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + cd build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated_scripts/open_chip -h " Usage: ./generated-scripts/open_chip [-t] [openroad_db_name] @@ -245,9 +245,9 @@ To run DRC & LVS in Magic & Netgen, respectively: .. code-block:: shell make drc tutorial=sky130-openroad - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-openroad - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Note that in ``sky130-openroad.yml`` we have set the following YAML keys: diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 5e280469da..d368ec5568 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -7,8 +7,7 @@ import org.chipsalliance.cde.config.{Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import chipyard.{BuildTop, HasHarnessSignalReferences} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, BuildTop, HasHarnessSignalReferences} import chipyard.iobinders.{HasIOBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 88ea88af77..dd76589a5c 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -13,8 +13,8 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.blocks.devices.uart._ -import chipyard._ -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem} +import chipyard.harness._ import chipyard.iobinders.{HasIOBinders} class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index fa08a18477..c029861094 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.harness.{DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 94c0ba8ed7..8e0bd5bf59 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -16,9 +16,9 @@ import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} +import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey} class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer => diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index c4f4684e7f..ea6df6c3a5 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.harness.{DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index d60af21a88..50fbfeb4c6 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,8 +9,8 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} -import chipyard.harness.{OverrideHarnessBinder} +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.harness.{HasHarnessSignalReferences, OverrideHarnessBinder} /*** UART ***/ class WithUART extends OverrideHarnessBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index e46745a82d..9e7529dddb 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,7 +17,7 @@ import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} import chipyard._ import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 27689ca8dc..7008092a6d 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -13,8 +13,7 @@ import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} -import chipyard.{HasHarnessSignalReferences} -import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder, HasHarnessSignalReferences} /*** UART ***/ class WithBringupUART extends ComposeHarnessBinder({ diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index d571bc95fc..1522648a79 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.{TLTileResetCtrl} -import chipyard.{DefaultClockFrequencyKey} +import chipyard.harness.{DefaultClockFrequencyKey} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 5628064974..e51ac52523 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -8,8 +8,8 @@ class ChipLikeQuadRocketConfig extends Config( //================================== // Set up TestHarness //================================== - new chipyard.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness - // NOTE: This only simulates properly in VCS + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness + // NOTE: This only simulates properly in VCS //================================== // Set up tiles diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 7000c81c26..6080c36f63 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams} import chipyard._ import chipyard.clocking._ - +import chipyard.harness.{DefaultClockFrequencyKey} // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala index 19ec945b4f..f2ebfc3309 100644 --- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -7,6 +7,7 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.{InModuleBody} import barstools.iocell.chisel._ import chipyard._ +import chipyard.harness.{BuildTop} // A "custom" IOCell with additional I/O // The IO don't do anything here in this example diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 50b76dffdf..6151f45634 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem.{CacheBlockBytes} import freechips.rocketchip.devices.debug.{SimJTAG} import freechips.rocketchip.jtag.{JTAGIO} import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM} -import chipyard.{BuildTop} +import chipyard.harness.{BuildTop} // A "flat" TestHarness that doesn't use IOBinders // use with caution. diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala similarity index 100% rename from generators/chipyard/src/main/scala/HarnessBinders.scala rename to generators/chipyard/src/main/scala/harness/HarnessBinders.scala diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala similarity index 97% rename from generators/chipyard/src/main/scala/HarnessClocks.scala rename to generators/chipyard/src/main/scala/harness/HarnessClocks.scala index f9665e12a6..513ca38c79 100644 --- a/generators/chipyard/src/main/scala/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.harness import chisel3._ @@ -8,10 +8,9 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.prci._ -import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey} import chipyard.iobinders.HasIOBinders import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} -import chipyard.HarnessClockInstantiatorKey // HarnessClockInstantiators are classes which generate clocks that drive diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala similarity index 97% rename from generators/chipyard/src/main/scala/TestHarness.scala rename to generators/chipyard/src/main/scala/harness/TestHarness.scala index a8b18d4f2e..22bcc1670a 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.harness import chisel3._ @@ -11,6 +11,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkP import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} import chipyard.iobinders.HasIOBinders import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} +import chipyard.{ChipTop} // ------------------------------- // Chipyard Test Harness diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index b543254d1d..cd98c7fef2 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -30,7 +30,6 @@ import cva6.CVA6Tile import boom.common.{BoomTile} import barstools.iocell.chisel._ import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} -import chipyard.{HasHarnessSignalReferences} import chipyard.harness._ object MainMemoryConsts { diff --git a/variables.mk b/variables.mk index 9caaf6763b..89e66cd92d 100644 --- a/variables.mk +++ b/variables.mk @@ -70,7 +70,7 @@ ifeq ($(SUB_PROJECT),chipyard) SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= $(MODEL) - MODEL_PACKAGE ?= $(SBT_PROJECT) + MODEL_PACKAGE ?= chipyard.harness CONFIG ?= RocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT)