From 646ba4fba7ce1d2603460ceb709c4620b177897f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 18 Oct 2023 00:38:52 -0700 Subject: [PATCH 1/9] Bump testchipip --- .../src/main/scala/config/AbstractConfig.scala | 13 +++++++++---- .../src/main/scala/config/ChipConfigs.scala | 2 +- .../main/scala/config/PeripheralDeviceConfigs.scala | 3 +++ .../src/main/scala/config/RocketConfigs.scala | 1 - .../scala/config/fragments/ClockingFragments.scala | 6 ++++++ .../scala/config/fragments/SubsystemFragments.scala | 6 +++++- .../src/main/scala/example/FlatChipTop.scala | 2 +- .../src/main/scala/example/FlatTestHarness.scala | 9 +++++---- .../src/main/scala/harness/HarnessBinders.scala | 4 ++-- .../src/main/scala/iobinders/IOBinders.scala | 10 +++++----- generators/testchipip | 2 +- 11 files changed, 38 insertions(+), 20 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index a08abb6d63..06f9af3b3e 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -53,15 +53,20 @@ class AbstractConfig extends Config( // By default, punch out IOs to the Harness new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus + new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus + new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus + new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus + new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address - new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port - new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance - new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( // add a serial-tilelink interface + client = Some(testchipip.SerialTLClientParams(idBits = 4)), // serial-tilelink interface will master the FBUS, and support 4 idBits + width = 32 // serial-tilelink interface with 32 lanes + ))) ++ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index cc61794cdb..95b0149bf8 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -23,7 +23,7 @@ class ChipLikeRocketConfig extends Config( // Set up I/O //================================== new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO - new testchipip.WithSerialTLBackingMemory ++ // Configure the off-chip memory accessible over serial-tl as backing memory + new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 7ad7a1ac81..790c6a0efa 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -52,6 +52,9 @@ class MMIORocketConfig extends Config( new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( + new chipyard.config.WithOffchipBusFrequency(500) ++ + new testchipip.WithOffchipBusClient(MBUS) ++ + new testchipip.WithOffchipBus ++ new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index c45fb6f236..3a2c1b0805 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -93,7 +93,6 @@ class MulticlockRocketConfig extends Config( new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) class CustomIOChipTopRocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 2da9fbf283..c34be1bbfc 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -14,6 +14,8 @@ import freechips.rocketchip.tilelink.{HasTLBusParams} import chipyard._ import chipyard.clocking._ +import testchipip.{OffchipBusKey} + // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend // the diplomacy graph upwards into the ChipTop, where we connect it to @@ -103,6 +105,10 @@ class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) +class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) + class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 40f18d5dc7..51272e8a16 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,7 +1,7 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{DTSTimebase} // Replaces the L2 with a broadcast manager for maintaining coherence @@ -9,6 +9,10 @@ class WithBroadcastManager extends Config((site, here, up) => { case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) +class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => { + case BroadcastKey => params +}) + class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) }) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index a1a1aeaa2a..a09bb06f56 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -97,7 +97,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //========================= // Serialized TileLink //========================= - val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey)) + val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tls(0).getWrappedValue, "serial_tl", p(IOCellKey)) //========================= // JTAG/Debug diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 5b3168b3de..5f6c69f199 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -39,8 +39,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1) // Serialized TL - val sVal = p(SerialTLKey).get - val serialTLManagerParams = sVal.serialTLManagerParams.get + val sVal = p(SerialTLKey)(0) + val serialTLManagerParams = sVal.manager.get require(serialTLManagerParams.isMemoryDevice) withClockAndReset(clock, reset) { @@ -49,10 +49,11 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { dut.serial_tl_pad.clock := clock } val harnessRAM = TSIHarness.connectRAM( - lazyDut.system.serdesser.get, + p(SerialTLKey)(0), + lazyDut.system.serdessers(0), serial_bits, reset) - io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset) + io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset) } diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 8530bb3395..943215060e 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -215,13 +215,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ if (DataMirror.directionOf(port.io.clock) == Direction.Input) { port.io.clock := th.harnessBinderClock } - val ram = LazyModule(new SerialRAM(port.serdesser)(port.serdesser.p)) + val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)) Module(ram.module) ram.module.io.ser <> port.io.bits val tsi = Module(new SimTSI) tsi.io.clock := th.harnessBinderClock tsi.io.reset := th.harnessBinderReset - tsi.io.tsi <> ram.module.io.tsi + tsi.io.tsi <> ram.module.io.tsi.get val exit = tsi.io.exit val success = exit === 1.U val error = exit >= 2.U diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 773f3d3919..6c1cf8d235 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -342,10 +342,10 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { - val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) => + val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true) - (SerialTLPort(port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true) + (SerialTLPort(port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells) }).unzip (ports.toSeq, cells.flatten.toSeq) } @@ -353,11 +353,11 @@ class WithSerialTLIOCells extends OverrideIOBinder({ class WithSerialTLPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { - val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) => + val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] val port = IO(s.getWrappedValue.cloneType) port <> s.getWrappedValue - (SerialTLPort(port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil) + (SerialTLPort(port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil) }).unzip (ports.toSeq, cells.flatten.toSeq) } diff --git a/generators/testchipip b/generators/testchipip index 6436959d99..e1e1ee0288 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6436959d997d0bb578790d95078648b478ca049b +Subproject commit e1e1ee02884f457f62785c41af23406a6cf7738a From 68f7c90938644c1f9f6889a29a5e4813ab9aaeea Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 20 Oct 2023 15:42:16 -0700 Subject: [PATCH 2/9] Fix SharedNoC config --- .../src/main/scala/config/NoCConfigs.scala | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 0b6be558ae..2a5d218589 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -45,7 +45,7 @@ import scala.collection.immutable.ListMap * | SI:Core 2 | SO:system[0] | SO:system[1] | SI:Core 3 | * |(0)___________|(1)___________|(2)___________|(3)___________| * | FBus | Core 0 | Core 1 | Pbus | - * | SI:serial-tl | SI:Core 0 | SI:Core 1 | SO:pbus | + * | SI:serial_tl | SI:Core 0 | SI:Core 1 | SO:pbus | * |______________|______________|______________|______________| * * |(0)___________|(1)___________|(2)___________|(3)___________| @@ -65,7 +65,7 @@ class MultiNoCConfig extends Config( new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( - "serial-tl" -> 0), + "serial_tl" -> 0), outNodeMapping = ListMap( "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4, "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)), @@ -81,7 +81,7 @@ class MultiNoCConfig extends Config( "L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6), outNodeMapping = ListMap( "system[0]" -> 0, "system[1]" -> 3, "system[2]" -> 4 , "system[3]" -> 7, - "serdesser" -> 0)), + "serial_tl_0" -> 0)), NoCParams( topology = TerminalRouter(BidirectionalTorus1D(8)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), @@ -92,7 +92,7 @@ class MultiNoCConfig extends Config( inNodeMapping = ListMap( "Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7, "Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14, - "serial-tl" -> 0), + "serial_tl" -> 0), outNodeMapping = ListMap( "system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10, "pbus" -> 3)), @@ -133,7 +133,7 @@ class MultiNoCConfig extends Config( * Core 6 | SI | Core 6 | 16 * Core 7 | SI | Core 7 | 18 * Core 8 | SI | Core 8 | 19 - * fbus | SI | serial-tl | 9 + * fbus | SI | serial_tl | 9 * pbus | SO | pbus | 4 * L2 0 | SO | system[0] | 0 * L2 1 | SO | system[1] | 2 @@ -145,7 +145,7 @@ class MultiNoCConfig extends Config( * L2 3 | MI | Cache[3] | 6 * DRAM 0 | MO | system[0] | 3 * DRAM 1 | MO | system[1] | 5 - * extram | MO | serdesser | 9 + * extram | MO | serial_tl_0 | 9 */ // DOC include start: SharedNoCConfig class SharedNoCConfig extends Config( @@ -168,12 +168,12 @@ class SharedNoCConfig extends Config( "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6), outNodeMapping = ListMap( "system[0]" -> 3, "system[1]" -> 5, - "serdesser" -> 9)) + "serial_tl_0" -> 9)) ), true) ++ new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( - "serial-tl" -> 9, "Core 0" -> 2, + "serial_tl" -> 9, "Core 0" -> 2, "Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14, "Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19), outNodeMapping = ListMap( @@ -199,13 +199,13 @@ class SbusRingNoCConfig extends Config( "Core 5" -> 5, "Core 6" -> 6, "Core 7" -> 7, - "serial-tl" -> 8), + "serial_tl" -> 8), outNodeMapping = ListMap( "system[0]" -> 9, "system[1]" -> 10, "system[2]" -> 11, "system[3]" -> 12, - "pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node + "pbus" -> 8)), // TSI is on the pbus, so serial_tl and pbus should be on the same node NoCParams( topology = UnidirectionalTorus1D(13), channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), From d83f39573842e2077db758b150d33e9a53c394a1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 24 Oct 2023 18:42:27 -0700 Subject: [PATCH 3/9] Update firechip for new testchipip --- generators/firechip/src/main/scala/BridgeBinders.scala | 4 ++-- generators/firechip/src/main/scala/TargetConfigs.scala | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index e4169ec26e..ad643deb1f 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -69,7 +69,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ case (th: FireSim, port: SerialTLPort) => { val bits = port.io.bits port.io.clock := th.harnessBinderClock - val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty)) + val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)) Module(ram.module) ram.module.io.ser <> port.io.bits @@ -78,7 +78,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ // If FASED bridge is attached, loadmem widget is present val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx))) - TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p) + TSIBridge(th.harnessBinderClock, ram.module.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p) } }) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 6f2a02913d..49e85c273b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -129,8 +129,7 @@ class WithFireSimHighPerfClocking extends Config( // 1 GHz matches the FASED default, using some other frequency will require // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. new chipyard.config.WithMemoryBusFrequency(1000.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing + new chipyard.config.WithAsynchrousMemoryBusCrossing ) // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz @@ -192,7 +191,6 @@ class WithFireSimTestChipConfigTweaks extends Config( new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new WithFireSimDesignTweaks ) @@ -250,7 +248,10 @@ class FireSimSmallSystemConfig extends Config( new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithDefaultSerialTL ++ + new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( + client = Some(testchipip.SerialTLClientParams(idBits = 4)), + width = 32 + ))) ++ new testchipip.WithBlockDevice ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ From 228d9351f87aaf00609a267ccd19559ae3846053 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 25 Oct 2023 17:18:24 -0700 Subject: [PATCH 4/9] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index e1e1ee0288..d023a3175c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e1e1ee02884f457f62785c41af23406a6cf7738a +Subproject commit d023a3175cbdb7343cdb26aa8450e86e978c591d From 6f17292e85c10b4bc42fd1c4924e29461a7c7f48 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 26 Oct 2023 11:27:03 -0700 Subject: [PATCH 5/9] Fix removal of axi4mem for ChipLikeRocketConfig --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 95b0149bf8..b8b02dfaed 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -24,7 +24,7 @@ class ChipLikeRocketConfig extends Config( //================================== new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory - new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel //================================== From 59fd67df5735fad4d7e14fa383349a698e9049af Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 26 Oct 2023 11:27:39 -0700 Subject: [PATCH 6/9] Fix match statement --- generators/chipyard/src/main/scala/Subsystem.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index d25d4fa3f1..5d2ba60cf8 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true + case _: CanHavePeripheryTLSerial if (!p(SerialTLKey).isEmpty) => true case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true case _ => false }) { From a8766ea8fc5fd46dcff115eb08bfb283d60e37cc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 31 Oct 2023 14:25:16 -0700 Subject: [PATCH 7/9] Precisely specify bus frequencies --- fpga/src/main/scala/arty/Configs.scala | 2 ++ fpga/src/main/scala/arty100t/Configs.scala | 1 + fpga/src/main/scala/nexysvideo/Configs.scala | 3 ++- fpga/src/main/scala/vc707/Configs.scala | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 7 +++++-- generators/chipyard/src/main/scala/Subsystem.scala | 2 +- .../chipyard/src/main/scala/config/ChipConfigs.scala | 3 +++ generators/firechip/src/main/scala/TargetConfigs.scala | 9 +++++++++ 8 files changed, 24 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 3e208060c8..1bf2b64318 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -27,6 +27,8 @@ class WithArtyTweaks extends Config( new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.config.WithDTSTimebase(32000) ++ new chipyard.config.WithSystemBusFrequency(32) ++ + new chipyard.config.WithFrontBusFrequency(32) ++ + new chipyard.config.WithControlBusFrequency(32) ++ new chipyard.config.WithPeripheryBusFrequency(32) ++ new testchipip.WithNoSerialTL ) diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 4a0fb293a4..f4e25fd259 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -32,6 +32,7 @@ class WithArty100TTweaks extends Config( new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index f31e38d111..01b095fa51 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -33,6 +33,7 @@ class WithNexysVideoTweaks extends Config( new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag @@ -69,4 +70,4 @@ class TinyRocketNexysVideoConfig extends Config( new WithTinyNexysVideoTweaks ++ new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.TinyRocketConfig) - // DOC include end: WithTinyNexysVideoTweaks and Rocket \ No newline at end of file + // DOC include end: WithTinyNexysVideoTweaks and Rocket diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index b37064ac9c..1be812fa91 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -35,7 +35,7 @@ class WithSystemModifications extends Config((site, here, up) => { p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin") } case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size) - case SerialTLKey => None // remove serialized tl port + case SerialTLKey => Nil // remove serialized tl port }) class WithVC707Tweaks extends Config ( diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 3563296130..32dc3c2c0c 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -36,7 +36,7 @@ class WithSystemModifications extends Config((site, here, up) => { p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") } case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size - case SerialTLKey => None // remove serialized tl port + case SerialTLKey => Nil // remove serialized tl port }) // DOC include start: AbstractVCU118 and Rocket @@ -46,6 +46,7 @@ class WithVCU118Tweaks extends Config( new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithMemoryBusFrequency(100) ++ new chipyard.config.WithSystemBusFrequency(100) ++ + new chipyard.config.WithControlBusFrequency(100) ++ new chipyard.config.WithPeripheryBusFrequency(100) ++ new WithFPGAFrequency(100) ++ // default 100MHz freq // harness binders @@ -76,7 +77,9 @@ class BoomVCU118Config extends Config( class WithFPGAFrequency(fMHz: Double) extends Config( new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++ new chipyard.config.WithSystemBusFrequency(fMHz) ++ - new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithControlBusFrequency(fMHz) ++ + new chipyard.config.WithFrontBusFrequency(fMHz) ++ new chipyard.config.WithMemoryBusFrequency(fMHz) ) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 5d2ba60cf8..a3ba679ec1 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTLSerial if (!p(SerialTLKey).isEmpty) => true + case _: CanHavePeripheryTLSerial if (p(SerialTLKey).size != 0) => true case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true case _ => false }) { diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index b8b02dfaed..caf150aeb9 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -85,6 +85,9 @@ class ChipBringupHostConfig extends Config( new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz new chipyard.config.WithMemoryBusFrequency(75.0) ++ new chipyard.config.WithPeripheryBusFrequency(75.0) ++ + new chipyard.config.WithSystemBusFrequency(75.0) ++ + new chipyard.config.WithControlBusFrequency(75.0) ++ + new chipyard.config.WithOffchipBusFrequency(75.0) ++ // Base is the no-cores config new chipyard.NoCoresConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 49e85c273b..0ceaea1c5c 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -123,6 +123,7 @@ class WithFireSimHighPerfClocking extends Config( new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ new chipyard.config.WithSystemBusFrequency(3200.0) ++ new chipyard.config.WithFrontBusFrequency(3200.0) ++ + new chipyard.config.WithControlBusFrequency(3200.0) ++ // Optional: These three configs put the DRAM memory system in it's own clock domain. // Removing the first config will result in the FASED timing model running // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. @@ -138,8 +139,10 @@ class WithFireSimConfigTweaks extends Config( // Using some other frequency will require runnings the FASED runtime configuration generator // to generate faithful DDR3 timing values. new chipyard.config.WithSystemBusFrequency(1000.0) ++ + new chipyard.config.WithControlBusFrequency(1000.0) ++ new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ + new chipyard.config.WithFrontBusFrequency(1000.0) ++ new WithFireSimDesignTweaks ) @@ -185,6 +188,8 @@ class WithFireSimTestChipConfigTweaks extends Config( new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithFrontBusFrequency(500.0) ++ // Match the sbus and fbus frequency + new chipyard.config.WithControlBusFrequency(500.0) ++ // Match the sbus and cbus frequency new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS @@ -245,6 +250,10 @@ class FireSimSmallSystemConfig extends Config( new WithDefaultMemModel ++ new WithBootROM ++ new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + new chipyard.config.WithControlBusFrequency(3200.0) ++ + new chipyard.config.WithSystemBusFrequency(3200.0) ++ + new chipyard.config.WithFrontBusFrequency(3200.0) ++ + new chipyard.config.WithMemoryBusFrequency(3200.0) ++ new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ From 52215f3d40a0f493506d6b1e09b7d1d2af0c66bc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 31 Oct 2023 18:46:15 -0700 Subject: [PATCH 8/9] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index d023a3175c..23d6a3805f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit d023a3175cbdb7343cdb26aa8450e86e978c591d +Subproject commit 23d6a3805f8f5081a8ec8cb5a9392fde3204772c From 6bb173bd219e8cb14fd5a3f0471f0d57f9644464 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 31 Oct 2023 21:40:45 -0700 Subject: [PATCH 9/9] Fix vc707 clock freqs --- fpga/src/main/scala/vc707/Configs.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index 1be812fa91..124920d78d 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -45,6 +45,8 @@ class WithVC707Tweaks extends Config ( new chipyard.config.WithMemoryBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ + new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new WithFPGAFrequency(50) ++ // default 50MHz freq @@ -74,8 +76,11 @@ class BoomVC707Config extends Config ( ) class WithFPGAFrequency(fMHz: Double) extends Config ( - new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. - new chipyard.config.WithMemoryBusFrequency(fMHz) + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithMemoryBusFrequency(fMHz) ++ + new chipyard.config.WithSystemBusFrequency(fMHz) ++ + new chipyard.config.WithControlBusFrequency(fMHz) ++ + new chipyard.config.WithFrontBusFrequency(fMHz) ) class WithFPGAFreq25MHz extends WithFPGAFrequency(25)