From 77ee5906e258f0694e8a498670b908603d6ffa89 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 19 Oct 2023 11:19:56 -0700 Subject: [PATCH] [vlsi][ci skip] Fix INPUT_CONFS override in tutorial.mk --- vlsi/tutorial.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 6b970fcbac..92ba0a988c 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -12,6 +12,7 @@ ifeq ($(tutorial),asap7) TECH_CONF ?= example-asap7.yml DESIGN_CONFS ?= VLSI_OBJ_DIR ?= build-asap7-commercial + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) endif ifeq ($(tutorial),sky130-commercial) @@ -23,6 +24,7 @@ ifeq ($(tutorial),sky130-commercial) $(if $(filter $(VLSI_TOP),Rocket), \ example-designs/sky130-rocket.yml, ) VLSI_OBJ_DIR ?= build-sky130-commercial + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) endif ifeq ($(tutorial),sky130-openroad) @@ -36,8 +38,8 @@ ifeq ($(tutorial),sky130-openroad) $(if $(filter $(VLSI_TOP),RocketTile), \ example-designs/sky130-openroad-rockettile.yml, ) VLSI_OBJ_DIR ?= build-sky130-openroad + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. ENABLE_YOSYS_FLOW = 1 endif -INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)