diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index ac4fc0a41..8c3ed2a58 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -46,7 +46,7 @@ search () { } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index ea90bbaee..10ae41028 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -25,7 +25,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-vexiiriscv" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector chipyard-shuttleara" grouping["group-constellation"]="chipyard-constellation" @@ -54,6 +54,7 @@ mapping["chipyard-spike"]=" CONFIG=SpikeZicntrConfig EXTRA_SIM_FLAGS='+spike-ipc mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-ibex"]=" CONFIG=IbexConfig" +mapping["chipyard-vexiiriscv"]=" CONFIG=VexiiRiscvConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 250f26b03..7b4f8e870 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -160,6 +160,10 @@ case $1 in # Ibex cannot run the riscv-tests binaries for some reason # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple ;; + chipyard-vexiiriscv) + run_asm LOADMEM=1 + run_bmark LOADMEM=1 + ;; chipyard-sodor) run_asm ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 31d4900c5..bf0623008 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -558,6 +558,29 @@ jobs: group-key: "group-cores" project-key: "chipyard-ibex" + chipyard-vexiiriscv-run-tests: + name: chipyard-vexiiriscv-run-tests + needs: prepare-chipyard-cores + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v4 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-cores" + project-key: "chipyard-vexiiriscv" + chipyard-sodor-run-tests: name: chipyard-sodor-run-tests needs: prepare-chipyard-cores @@ -1188,6 +1211,7 @@ jobs: chipyard-shuttle-run-tests, chipyard-cva6-run-tests, chipyard-ibex-run-tests, + chipyard-vexiiriscv-run-tests, chipyard-sodor-run-tests, chipyard-dmiboomv3-run-tests, chipyard-dmiboomv4-run-tests, diff --git a/.gitmodules b/.gitmodules index f233483ca..94c5c7e7f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -151,3 +151,6 @@ [submodule "tools/firrtl2"] path = tools/firrtl2 url = https://github.com/ucb-bar/firrtl2.git +[submodule "generators/vexiiriscv"] + path = generators/vexiiriscv + url = https://github.com/ucb-bar/vexiiriscv-tile.git diff --git a/build.sbt b/build.sbt index 39fd7f214..f50564e64 100644 --- a/build.sbt +++ b/build.sbt @@ -158,7 +158,7 @@ lazy val chipyard = (project in file("generators/chipyard")) dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle, caliptra_aes, rerocc, - compressacc, saturn, ara, firrtl2_bridge) + compressacc, saturn, ara, firrtl2_bridge, vexiiriscv) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -233,6 +233,11 @@ lazy val ibex = (project in file("generators/ibex")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val vexiiriscv = (project in file("generators/vexiiriscv")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val sodor = (project in file("generators/riscv-sodor")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index a412c2a38..757563838 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -20,6 +20,10 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Generators/BOOM:Berkeley Out-of-Order Machine (BOOM)` for more information. +**Shuttle Core** + A superscalar in-order RISC-V core. + See :ref:`Generators/Shuttle:Shuttle RISC-V Core` for more information + **CVA6 Core** An in-order RISC-V core written in System Verilog. Previously called Ariane. See :ref:`Generators/CVA6:CVA6 Core` for more information. @@ -28,6 +32,11 @@ Processor Cores An in-order 32 bit RISC-V core written in System Verilog. See :ref:`Generators/Ibex:Ibex Core` for more information. +**VexiiRiscv Core** + A dual-issue in-order 64 bit RISC-V core implemented in SpinalHDL + See :ref:`Generators/VexiiRiscv:VexiiRiscv Core` for more information. + + Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/Generators/Shuttle.rst b/docs/Generators/Shuttle.rst index 87c8f78bc..1108743a6 100644 --- a/docs/Generators/Shuttle.rst +++ b/docs/Generators/Shuttle.rst @@ -6,3 +6,5 @@ Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base The superscalar microarchitecture presents the most advantages for 1) floating-point kernels and 2) RoCC accelerator kernels, as scalar control code can execute concurrently with floating point or RoCC instructions, maintaining high utilization of those units. Shuttle is tape-out proven, and has similar physical design complexity as Rocket. + +``ShuttleConfig`` provides a base configuration of a single-core Shuttle-based SoC. diff --git a/docs/Generators/VexiiRiscv.rst b/docs/Generators/VexiiRiscv.rst new file mode 100644 index 000000000..358f90d77 --- /dev/null +++ b/docs/Generators/VexiiRiscv.rst @@ -0,0 +1,9 @@ +VexiiRiscv Core +=================================== +`VexiiRiscv `__ is a RV64IMAFDCB in-order superscalar core implemented in `SpinalHDL `__. +VexiiRiscv is Linux-capable and achieves competitive IPC in its design class. +VexiiRiscv implements cache-coherent TileLink L1 data caches and is integrated as a selectable Tile in Chipyard. + +The example VexiiRiscv config is ``VexiiRiscvConfig``. +When building this Config, Chipyard will call VexiiRiscv's SpinalHDL RTL generator to generate the core's SystemVerilog, before integrating it as a Chisel blackbox. + diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 53a8895f4..7fd5519a1 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -29,6 +29,7 @@ so changes to the generators themselves will automatically be used when building Rocket-Chip-Generators CVA6 Ibex + VexiiRiscv fft NVDLA Sodor diff --git a/generators/chipyard/src/main/scala/config/VexiiRiscvConfigs.scala b/generators/chipyard/src/main/scala/config/VexiiRiscvConfigs.scala new file mode 100644 index 000000000..8effede25 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/VexiiRiscvConfigs.scala @@ -0,0 +1,13 @@ +package chipyard + +import chisel3._ + +import org.chipsalliance.cde.config.{Config} + +// --------------------- +// VexiiRiscv Configs +// --------------------- + +class VexiiRiscvConfig extends Config( + new vexiiriscv.WithNVexiiRiscvCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 9f15f6e72..2f07ab9c5 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -10,6 +10,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import cva6.{CVA6TileAttachParams} import sodor.common.{SodorTileAttachParams} import ibex.{IbexTileAttachParams} +import vexiiriscv.{VexiiRiscvTileAttachParams} import testchipip.cosim.{TracePortKey, TracePortParams} import barf.{TilePrefetchingMasterPortParams} @@ -106,6 +107,8 @@ class WithTilePrefetchers extends Config((site, here, up) => { master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) + case tp: VexiiRiscvTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) } diff --git a/generators/vexiiriscv b/generators/vexiiriscv new file mode 160000 index 000000000..10a351329 --- /dev/null +++ b/generators/vexiiriscv @@ -0,0 +1 @@ +Subproject commit 10a351329eb2f8b0ebf29331e0fe911fe3bb5a9b diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 4e2ed43ec..2aaa4dbc6 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -76,6 +76,7 @@ cd "$RDIR" generators/gemmini \ generators/rocket-chip \ generators/compress-acc \ + generators/vexiiriscv \ sims/firesim \ software/nvdla-workload \ software/coremark \ @@ -130,6 +131,12 @@ cd "$RDIR" # Non-recursive clone git submodule update --init generators/compress-acc + # Non-recursive clone + git submodule update --init generators/vexiiriscv + git -C generators/vexiiriscv submodule update --init VexiiRiscv + git -C generators/vexiiriscv/VexiiRiscv submodule update --init ext/SpinalHDL + git -C generators/vexiiriscv/VexiiRiscv submodule update --init ext/rvls + # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim git config --local submodule.sims/firesim.update none