From 5f511b66e77f0cace26ea5ef7738cd3567f2a379 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jul 2023 15:58:15 -0700 Subject: [PATCH] Delete all tests --- src/test/resources/TBGoldenModel.v | 843 ------------------ src/test/scala/dsptools/BaseNSpec.scala | 54 -- src/test/scala/dsptools/DspContextSpec.scala | 126 --- src/test/scala/dsptools/DspTesterSpec.scala | 70 -- src/test/scala/dsptools/LoggingSpec.scala | 70 -- .../dsptools/ShiftRegisterDelaySpec.scala | 158 ---- .../SimpleTBwGenTypeOption.scala | 451 ---------- src/test/scala/dsptools/numbers/AbsSpec.scala | 88 -- .../scala/dsptools/numbers/BaseNSpec.scala | 29 - .../dsptools/numbers/BlackBoxFloat.scala | 321 ------- .../dsptools/numbers/DspComplexSpec.scala | 72 -- .../dsptools/numbers/FixedPointSpec.scala | 231 ----- .../numbers/FixedPrecisionChangerSpec.scala | 82 -- src/test/scala/dsptools/numbers/LnSpec.scala | 41 - .../scala/dsptools/numbers/NumbersSpec.scala | 493 ---------- .../scala/dsptools/numbers/OverflowSpec.scala | 10 - .../numbers/ParameterizedOpSpec.scala | 181 ---- .../scala/dsptools/numbers/SaturateSpec.scala | 202 ----- .../dsptools/numbers/TypeclassSpec.scala | 174 ---- .../scala/examples/CaseClassBundleSpec.scala | 50 -- .../examples/ComplexMultiplierSpec.scala | 61 -- src/test/scala/examples/Demod.scala | 149 ---- .../examples/ParameterizedAdderSpec.scala | 70 -- .../ParameterizedSaturatingAdder.scala | 78 -- src/test/scala/examples/RealAdderSpec.scala | 58 -- src/test/scala/examples/SimpleAdderSpec.scala | 49 - .../scala/examples/SimpleDspModuleSpec.scala | 107 --- .../StreamingAutocorrelatorSpec.scala | 36 - src/test/scala/examples/TestVectors.scala | 162 ---- .../examples/TransposedStreamFIRSpec.scala | 70 -- 30 files changed, 4586 deletions(-) delete mode 100644 src/test/resources/TBGoldenModel.v delete mode 100644 src/test/scala/dsptools/BaseNSpec.scala delete mode 100644 src/test/scala/dsptools/DspContextSpec.scala delete mode 100644 src/test/scala/dsptools/DspTesterSpec.scala delete mode 100644 src/test/scala/dsptools/LoggingSpec.scala delete mode 100644 src/test/scala/dsptools/ShiftRegisterDelaySpec.scala delete mode 100644 src/test/scala/dsptools/VerboseDspTesterSpec/SimpleTBwGenTypeOption.scala delete mode 100644 src/test/scala/dsptools/numbers/AbsSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/BaseNSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/BlackBoxFloat.scala delete mode 100644 src/test/scala/dsptools/numbers/DspComplexSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/FixedPointSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/FixedPrecisionChangerSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/LnSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/NumbersSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/OverflowSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/ParameterizedOpSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/SaturateSpec.scala delete mode 100644 src/test/scala/dsptools/numbers/TypeclassSpec.scala delete mode 100644 src/test/scala/examples/CaseClassBundleSpec.scala delete mode 100644 src/test/scala/examples/ComplexMultiplierSpec.scala delete mode 100644 src/test/scala/examples/Demod.scala delete mode 100644 src/test/scala/examples/ParameterizedAdderSpec.scala delete mode 100644 src/test/scala/examples/ParameterizedSaturatingAdder.scala delete mode 100644 src/test/scala/examples/RealAdderSpec.scala delete mode 100644 src/test/scala/examples/SimpleAdderSpec.scala delete mode 100644 src/test/scala/examples/SimpleDspModuleSpec.scala delete mode 100644 src/test/scala/examples/StreamingAutocorrelatorSpec.scala delete mode 100644 src/test/scala/examples/TestVectors.scala delete mode 100644 src/test/scala/examples/TransposedStreamFIRSpec.scala diff --git a/src/test/resources/TBGoldenModel.v b/src/test/resources/TBGoldenModel.v deleted file mode 100644 index ec0d396b..00000000 --- a/src/test/resources/TBGoldenModel.v +++ /dev/null @@ -1,843 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Example VCS Command: $VCS_HOME/bin/vcs -debug_pp -full64 +define+UNIT_DELAY +rad +v2k +vcs+lic+wait +vc+list +vcs+initreg+random +vcs+dumpvars+out.vcd tb.v SimpleIOModule.v ... -`timescale 100ps / 10ps - -`define CLK_PERIOD 1 - -`define HALF_CLK_PERIOD 0.5 -`define RESET_TIME 5 -`define INIT_TIME 5.5 -`define expect(nodeName, nodeVal, expVal, cycle) if (nodeVal !== expVal) begin \ - $display("\t ASSERTION ON %s FAILED @ CYCLE = %d, 0x%h != EXPECTED 0x%h", \ - nodeName,cycle,nodeVal,expVal); $stop; end - -module testbench_v; - - integer cycle = 0; - - reg clock = 1; - reg reset = 1; - reg signed [7:0] io_i_vF_0 = 0; - reg signed [7:0] io_i_vF_1 = 0; - reg signed [7:0] io_i_vF_2 = 0; - reg signed [7:0] io_i_vF_3 = 0; - reg signed [7:0] io_i_vF_4 = 0; - reg signed [7:0] io_i_vF_5 = 0; - reg signed [7:0] io_i_vF_6 = 0; - reg signed [7:0] io_i_vF_7 = 0; - reg signed [7:0] io_i_vF_8 = 0; - reg signed [7:0] io_i_vF_9 = 0; - reg signed [7:0] io_i_vS_0 = 0; - reg signed [7:0] io_i_vS_1 = 0; - reg signed [7:0] io_i_vS_2 = 0; - reg signed [7:0] io_i_vS_3 = 0; - reg signed [7:0] io_i_vS_4 = 0; - reg signed [7:0] io_i_vS_5 = 0; - reg signed [7:0] io_i_vS_6 = 0; - reg signed [7:0] io_i_vS_7 = 0; - reg signed [7:0] io_i_vS_8 = 0; - reg signed [7:0] io_i_vS_9 = 0; - reg[7:0] io_i_vU_0 = 0; - reg[7:0] io_i_vU_1 = 0; - reg[7:0] io_i_vU_2 = 0; - reg[7:0] io_i_vU_3 = 0; - reg[7:0] io_i_vU_4 = 0; - reg[7:0] io_i_vU_5 = 0; - reg[7:0] io_i_vU_6 = 0; - reg[7:0] io_i_vU_7 = 0; - reg[7:0] io_i_vU_8 = 0; - reg[7:0] io_i_vU_9 = 0; - reg[15:0] io_i_long_u = 0; - reg signed [15:0] io_i_long_f = 0; - reg signed [15:0] io_i_long_s = 0; - reg signed [15:0] io_i_long_gen = 0; - reg[7:0] io_i_short_u = 0; - reg signed [7:0] io_i_short_f = 0; - reg signed [7:0] io_i_short_s = 0; - reg signed [7:0] io_i_short_gen = 0; - reg signed [7:0] io_i_cFS_imag = 0; - reg signed [7:0] io_i_cFS_real = 0; - reg signed [15:0] io_i_cGenL_imag = 0; - reg signed [15:0] io_i_cGenL_real = 0; - reg[0:0] io_i_b = 0; - wire signed [7:0] io_o_vF_0; - wire signed [7:0] io_o_vF_1; - wire signed [7:0] io_o_vF_2; - wire signed [7:0] io_o_vF_3; - wire signed [7:0] io_o_vF_4; - wire signed [7:0] io_o_vF_5; - wire signed [7:0] io_o_vF_6; - wire signed [7:0] io_o_vF_7; - wire signed [7:0] io_o_vF_8; - wire signed [7:0] io_o_vF_9; - wire signed [7:0] io_o_vS_0; - wire signed [7:0] io_o_vS_1; - wire signed [7:0] io_o_vS_2; - wire signed [7:0] io_o_vS_3; - wire signed [7:0] io_o_vS_4; - wire signed [7:0] io_o_vS_5; - wire signed [7:0] io_o_vS_6; - wire signed [7:0] io_o_vS_7; - wire signed [7:0] io_o_vS_8; - wire signed [7:0] io_o_vS_9; - wire[7:0] io_o_vU_0; - wire[7:0] io_o_vU_1; - wire[7:0] io_o_vU_2; - wire[7:0] io_o_vU_3; - wire[7:0] io_o_vU_4; - wire[7:0] io_o_vU_5; - wire[7:0] io_o_vU_6; - wire[7:0] io_o_vU_7; - wire[7:0] io_o_vU_8; - wire[7:0] io_o_vU_9; - wire[15:0] io_o_long_u; - wire signed [15:0] io_o_long_f; - wire signed [15:0] io_o_long_s; - wire signed [15:0] io_o_long_gen; - wire[7:0] io_o_short_u; - wire signed [7:0] io_o_short_f; - wire signed [7:0] io_o_short_s; - wire signed [7:0] io_o_short_gen; - wire signed [7:0] io_o_cFS_imag; - wire signed [7:0] io_o_cFS_real; - wire signed [15:0] io_o_cGenL_imag; - wire signed [15:0] io_o_cGenL_real; - wire[0:0] io_o_b; - - always #`HALF_CLK_PERIOD clock = ~clock; - - initial begin - #`RESET_TIME - forever #`CLK_PERIOD cycle = cycle + 1; - end - - SimpleIOModule SimpleIOModule( - .clock(clock), - .reset(reset), - .io_i_vF_0(io_i_vF_0), - .io_i_vF_1(io_i_vF_1), - .io_i_vF_2(io_i_vF_2), - .io_i_vF_3(io_i_vF_3), - .io_i_vF_4(io_i_vF_4), - .io_i_vF_5(io_i_vF_5), - .io_i_vF_6(io_i_vF_6), - .io_i_vF_7(io_i_vF_7), - .io_i_vF_8(io_i_vF_8), - .io_i_vF_9(io_i_vF_9), - .io_i_vS_0(io_i_vS_0), - .io_i_vS_1(io_i_vS_1), - .io_i_vS_2(io_i_vS_2), - .io_i_vS_3(io_i_vS_3), - .io_i_vS_4(io_i_vS_4), - .io_i_vS_5(io_i_vS_5), - .io_i_vS_6(io_i_vS_6), - .io_i_vS_7(io_i_vS_7), - .io_i_vS_8(io_i_vS_8), - .io_i_vS_9(io_i_vS_9), - .io_i_vU_0(io_i_vU_0), - .io_i_vU_1(io_i_vU_1), - .io_i_vU_2(io_i_vU_2), - .io_i_vU_3(io_i_vU_3), - .io_i_vU_4(io_i_vU_4), - .io_i_vU_5(io_i_vU_5), - .io_i_vU_6(io_i_vU_6), - .io_i_vU_7(io_i_vU_7), - .io_i_vU_8(io_i_vU_8), - .io_i_vU_9(io_i_vU_9), - .io_i_long_u(io_i_long_u), - .io_i_long_f(io_i_long_f), - .io_i_long_s(io_i_long_s), - .io_i_long_gen(io_i_long_gen), - .io_i_short_u(io_i_short_u), - .io_i_short_f(io_i_short_f), - .io_i_short_s(io_i_short_s), - .io_i_short_gen(io_i_short_gen), - .io_i_cFS_imag(io_i_cFS_imag), - .io_i_cFS_real(io_i_cFS_real), - .io_i_cGenL_imag(io_i_cGenL_imag), - .io_i_cGenL_real(io_i_cGenL_real), - .io_i_b(io_i_b), - .io_o_vF_0(io_o_vF_0), - .io_o_vF_1(io_o_vF_1), - .io_o_vF_2(io_o_vF_2), - .io_o_vF_3(io_o_vF_3), - .io_o_vF_4(io_o_vF_4), - .io_o_vF_5(io_o_vF_5), - .io_o_vF_6(io_o_vF_6), - .io_o_vF_7(io_o_vF_7), - .io_o_vF_8(io_o_vF_8), - .io_o_vF_9(io_o_vF_9), - .io_o_vS_0(io_o_vS_0), - .io_o_vS_1(io_o_vS_1), - .io_o_vS_2(io_o_vS_2), - .io_o_vS_3(io_o_vS_3), - .io_o_vS_4(io_o_vS_4), - .io_o_vS_5(io_o_vS_5), - .io_o_vS_6(io_o_vS_6), - .io_o_vS_7(io_o_vS_7), - .io_o_vS_8(io_o_vS_8), - .io_o_vS_9(io_o_vS_9), - .io_o_vU_0(io_o_vU_0), - .io_o_vU_1(io_o_vU_1), - .io_o_vU_2(io_o_vU_2), - .io_o_vU_3(io_o_vU_3), - .io_o_vU_4(io_o_vU_4), - .io_o_vU_5(io_o_vU_5), - .io_o_vU_6(io_o_vU_6), - .io_o_vU_7(io_o_vU_7), - .io_o_vU_8(io_o_vU_8), - .io_o_vU_9(io_o_vU_9), - .io_o_long_u(io_o_long_u), - .io_o_long_f(io_o_long_f), - .io_o_long_s(io_o_long_s), - .io_o_long_gen(io_o_long_gen), - .io_o_short_u(io_o_short_u), - .io_o_short_f(io_o_short_f), - .io_o_short_s(io_o_short_s), - .io_o_short_gen(io_o_short_gen), - .io_o_cFS_imag(io_o_cFS_imag), - .io_o_cFS_real(io_o_cFS_real), - .io_o_cGenL_imag(io_o_cGenL_imag), - .io_o_cGenL_real(io_o_cGenL_real), - .io_o_b(io_o_b)); - - initial begin - #`INIT_TIME reset = 0; - io_i_short_u = 2'd3; - io_i_short_f = -53; - io_i_short_s = -3; - io_i_short_gen = -53; - io_i_long_u = 2'd3; - io_i_long_f = -845; - io_i_long_s = -3; - io_i_long_gen = -845; - io_i_b = 1'd1; - io_i_cGenL_real = -845; - io_i_cGenL_imag = 10'd845; - io_i_cFS_real = -53; - io_i_cFS_imag = 6'd53; - #(1*`CLK_PERIOD) io_i_short_u = 2'd2; - io_i_short_f = -35; - io_i_short_s = -2; - io_i_short_gen = -35; - io_i_long_u = 2'd2; - io_i_long_f = -563; - io_i_long_s = -2; - io_i_long_gen = -563; - io_i_b = 1'd1; - io_i_cGenL_real = -563; - io_i_cGenL_imag = 10'd563; - io_i_cFS_real = -35; - io_i_cFS_imag = 6'd35; - `expect("io_o_short_u",io_o_short_u,3,cycle) - `expect("io_o_short_u",io_o_short_u,3,cycle) - `expect("io_o_short_f",io_o_short_f,-53,cycle) - `expect("io_o_short_f",io_o_short_f,-53,cycle) - `expect("io_o_short_s",io_o_short_s,-3,cycle) - `expect("io_o_short_s",io_o_short_s,-3,cycle) - `expect("io_o_short_gen",io_o_short_gen,-53,cycle) - `expect("io_o_short_gen",io_o_short_gen,-53,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-845,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,845,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-845,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,845,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-53,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,53,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-53,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,53,cycle) - `expect("io_o_long_u",io_o_long_u,3,cycle) - `expect("io_o_long_u",io_o_long_u,3,cycle) - `expect("io_o_long_f",io_o_long_f,-848,cycle) - `expect("io_o_long_f",io_o_long_f,-848,cycle) - `expect("io_o_long_s",io_o_long_s,-3,cycle) - `expect("io_o_long_s",io_o_long_s,-3,cycle) - `expect("io_o_long_gen",io_o_long_gen,-848,cycle) - `expect("io_o_long_gen",io_o_long_gen,-848,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 1'd1; - io_i_short_f = -18; - io_i_short_s = -1; - io_i_short_gen = -18; - io_i_long_u = 1'd1; - io_i_long_f = -282; - io_i_long_s = -1; - io_i_long_gen = -282; - io_i_b = 1'd1; - io_i_cGenL_real = -282; - io_i_cGenL_imag = 9'd282; - io_i_cFS_real = -18; - io_i_cFS_imag = 5'd18; - `expect("io_o_short_u",io_o_short_u,2,cycle) - `expect("io_o_short_u",io_o_short_u,2,cycle) - `expect("io_o_short_f",io_o_short_f,-36,cycle) - `expect("io_o_short_f",io_o_short_f,-36,cycle) - `expect("io_o_short_s",io_o_short_s,-2,cycle) - `expect("io_o_short_s",io_o_short_s,-2,cycle) - `expect("io_o_short_gen",io_o_short_gen,-36,cycle) - `expect("io_o_short_gen",io_o_short_gen,-36,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-563,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,563,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-563,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,563,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-35,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,35,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-35,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,35,cycle) - `expect("io_o_long_u",io_o_long_u,2,cycle) - `expect("io_o_long_u",io_o_long_u,2,cycle) - `expect("io_o_long_f",io_o_long_f,-560,cycle) - `expect("io_o_long_f",io_o_long_f,-560,cycle) - `expect("io_o_long_s",io_o_long_s,-2,cycle) - `expect("io_o_long_s",io_o_long_s,-2,cycle) - `expect("io_o_long_gen",io_o_long_gen,-560,cycle) - `expect("io_o_long_gen",io_o_long_gen,-560,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 1'd1; - io_i_short_f = -9; - io_i_short_s = -1; - io_i_short_gen = -9; - io_i_long_u = 1'd1; - io_i_long_f = -141; - io_i_long_s = -1; - io_i_long_gen = -141; - io_i_b = 1'd1; - io_i_cGenL_real = -141; - io_i_cGenL_imag = 8'd141; - io_i_cFS_real = -9; - io_i_cFS_imag = 4'd9; - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_f",io_o_short_f,-18,cycle) - `expect("io_o_short_f",io_o_short_f,-18,cycle) - `expect("io_o_short_s",io_o_short_s,-1,cycle) - `expect("io_o_short_s",io_o_short_s,-1,cycle) - `expect("io_o_short_gen",io_o_short_gen,-18,cycle) - `expect("io_o_short_gen",io_o_short_gen,-18,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-282,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,282,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-282,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,282,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-18,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,18,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-18,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,18,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_f",io_o_long_f,-288,cycle) - `expect("io_o_long_f",io_o_long_f,-288,cycle) - `expect("io_o_long_s",io_o_long_s,-1,cycle) - `expect("io_o_long_s",io_o_long_s,-1,cycle) - `expect("io_o_long_gen",io_o_long_gen,-288,cycle) - `expect("io_o_long_gen",io_o_long_gen,-288,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 1'd0; - io_i_short_f = -6; - io_i_short_s = 1'd0; - io_i_short_gen = -6; - io_i_long_u = 1'd0; - io_i_long_f = -102; - io_i_long_s = 1'd0; - io_i_long_gen = -102; - io_i_b = 1'd1; - io_i_cGenL_real = -102; - io_i_cGenL_imag = 7'd102; - io_i_cFS_real = -6; - io_i_cFS_imag = 3'd6; - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_f",io_o_short_f,-9,cycle) - `expect("io_o_short_f",io_o_short_f,-9,cycle) - `expect("io_o_short_s",io_o_short_s,-1,cycle) - `expect("io_o_short_s",io_o_short_s,-1,cycle) - `expect("io_o_short_gen",io_o_short_gen,-9,cycle) - `expect("io_o_short_gen",io_o_short_gen,-9,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-141,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,141,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-141,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,141,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-9,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,9,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-9,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,9,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_f",io_o_long_f,-144,cycle) - `expect("io_o_long_f",io_o_long_f,-144,cycle) - `expect("io_o_long_s",io_o_long_s,-1,cycle) - `expect("io_o_long_s",io_o_long_s,-1,cycle) - `expect("io_o_long_gen",io_o_long_gen,-144,cycle) - `expect("io_o_long_gen",io_o_long_gen,-144,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 1'd0; - io_i_short_f = 3'd6; - io_i_short_s = 1'd0; - io_i_short_gen = 3'd6; - io_i_long_u = 1'd0; - io_i_long_f = 7'd102; - io_i_long_s = 1'd0; - io_i_long_gen = 7'd102; - io_i_b = 1'd1; - io_i_cGenL_real = 7'd102; - io_i_cGenL_imag = -102; - io_i_cFS_real = 3'd6; - io_i_cFS_imag = -6; - `expect("io_o_short_u",io_o_short_u,0,cycle) - `expect("io_o_short_u",io_o_short_u,0,cycle) - `expect("io_o_short_f",io_o_short_f,-7,cycle) - `expect("io_o_short_f",io_o_short_f,-7,cycle) - `expect("io_o_short_s",io_o_short_s,0,cycle) - `expect("io_o_short_s",io_o_short_s,0,cycle) - `expect("io_o_short_gen",io_o_short_gen,-7,cycle) - `expect("io_o_short_gen",io_o_short_gen,-7,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-102,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,102,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,-102,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,102,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-6,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,6,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,-6,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,6,cycle) - `expect("io_o_long_u",io_o_long_u,0,cycle) - `expect("io_o_long_u",io_o_long_u,0,cycle) - `expect("io_o_long_f",io_o_long_f,-96,cycle) - `expect("io_o_long_f",io_o_long_f,-96,cycle) - `expect("io_o_long_s",io_o_long_s,0,cycle) - `expect("io_o_long_s",io_o_long_s,0,cycle) - `expect("io_o_long_gen",io_o_long_gen,-96,cycle) - `expect("io_o_long_gen",io_o_long_gen,-96,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 1'd1; - io_i_short_f = 4'd9; - io_i_short_s = 1'd1; - io_i_short_gen = 4'd9; - io_i_long_u = 1'd1; - io_i_long_f = 8'd141; - io_i_long_s = 1'd1; - io_i_long_gen = 8'd141; - io_i_b = 1'd1; - io_i_cGenL_real = 8'd141; - io_i_cGenL_imag = -141; - io_i_cFS_real = 4'd9; - io_i_cFS_imag = -9; - `expect("io_o_short_u",io_o_short_u,0,cycle) - `expect("io_o_short_u",io_o_short_u,0,cycle) - `expect("io_o_short_f",io_o_short_f,6,cycle) - `expect("io_o_short_f",io_o_short_f,6,cycle) - `expect("io_o_short_s",io_o_short_s,0,cycle) - `expect("io_o_short_s",io_o_short_s,0,cycle) - `expect("io_o_short_gen",io_o_short_gen,6,cycle) - `expect("io_o_short_gen",io_o_short_gen,6,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,102,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-102,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,102,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-102,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,6,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-6,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,6,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-6,cycle) - `expect("io_o_long_u",io_o_long_u,0,cycle) - `expect("io_o_long_u",io_o_long_u,0,cycle) - `expect("io_o_long_f",io_o_long_f,96,cycle) - `expect("io_o_long_f",io_o_long_f,96,cycle) - `expect("io_o_long_s",io_o_long_s,0,cycle) - `expect("io_o_long_s",io_o_long_s,0,cycle) - `expect("io_o_long_gen",io_o_long_gen,96,cycle) - `expect("io_o_long_gen",io_o_long_gen,96,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 1'd1; - io_i_short_f = 5'd18; - io_i_short_s = 1'd1; - io_i_short_gen = 5'd18; - io_i_long_u = 1'd1; - io_i_long_f = 9'd282; - io_i_long_s = 1'd1; - io_i_long_gen = 9'd282; - io_i_b = 1'd1; - io_i_cGenL_real = 9'd282; - io_i_cGenL_imag = -282; - io_i_cFS_real = 5'd18; - io_i_cFS_imag = -18; - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_f",io_o_short_f,8,cycle) - `expect("io_o_short_f",io_o_short_f,8,cycle) - `expect("io_o_short_s",io_o_short_s,1,cycle) - `expect("io_o_short_s",io_o_short_s,1,cycle) - `expect("io_o_short_gen",io_o_short_gen,8,cycle) - `expect("io_o_short_gen",io_o_short_gen,8,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,141,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-141,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,141,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-141,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,9,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-9,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,9,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-9,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_f",io_o_long_f,144,cycle) - `expect("io_o_long_f",io_o_long_f,144,cycle) - `expect("io_o_long_s",io_o_long_s,1,cycle) - `expect("io_o_long_s",io_o_long_s,1,cycle) - `expect("io_o_long_gen",io_o_long_gen,144,cycle) - `expect("io_o_long_gen",io_o_long_gen,144,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 2'd2; - io_i_short_f = 6'd35; - io_i_short_s = 2'd2; - io_i_short_gen = 6'd35; - io_i_long_u = 2'd2; - io_i_long_f = 10'd563; - io_i_long_s = 2'd2; - io_i_long_gen = 10'd563; - io_i_b = 1'd1; - io_i_cGenL_real = 10'd563; - io_i_cGenL_imag = -563; - io_i_cFS_real = 6'd35; - io_i_cFS_imag = -35; - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_u",io_o_short_u,1,cycle) - `expect("io_o_short_f",io_o_short_f,17,cycle) - `expect("io_o_short_f",io_o_short_f,17,cycle) - `expect("io_o_short_s",io_o_short_s,1,cycle) - `expect("io_o_short_s",io_o_short_s,1,cycle) - `expect("io_o_short_gen",io_o_short_gen,17,cycle) - `expect("io_o_short_gen",io_o_short_gen,17,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,282,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-282,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,282,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-282,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,18,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-18,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,18,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-18,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_u",io_o_long_u,1,cycle) - `expect("io_o_long_f",io_o_long_f,288,cycle) - `expect("io_o_long_f",io_o_long_f,288,cycle) - `expect("io_o_long_s",io_o_long_s,1,cycle) - `expect("io_o_long_s",io_o_long_s,1,cycle) - `expect("io_o_long_gen",io_o_long_gen,288,cycle) - `expect("io_o_long_gen",io_o_long_gen,288,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 2'd3; - io_i_short_f = 6'd53; - io_i_short_s = 2'd3; - io_i_short_gen = 6'd53; - io_i_long_u = 2'd3; - io_i_long_f = 10'd845; - io_i_long_s = 2'd3; - io_i_long_gen = 10'd845; - io_i_b = 1'd1; - io_i_cGenL_real = 10'd845; - io_i_cGenL_imag = -845; - io_i_cFS_real = 6'd53; - io_i_cFS_imag = -53; - `expect("io_o_short_u",io_o_short_u,2,cycle) - `expect("io_o_short_u",io_o_short_u,2,cycle) - `expect("io_o_short_f",io_o_short_f,35,cycle) - `expect("io_o_short_f",io_o_short_f,35,cycle) - `expect("io_o_short_s",io_o_short_s,2,cycle) - `expect("io_o_short_s",io_o_short_s,2,cycle) - `expect("io_o_short_gen",io_o_short_gen,35,cycle) - `expect("io_o_short_gen",io_o_short_gen,35,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,563,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-563,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,563,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-563,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,35,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-35,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,35,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-35,cycle) - `expect("io_o_long_u",io_o_long_u,2,cycle) - `expect("io_o_long_u",io_o_long_u,2,cycle) - `expect("io_o_long_f",io_o_long_f,560,cycle) - `expect("io_o_long_f",io_o_long_f,560,cycle) - `expect("io_o_long_s",io_o_long_s,2,cycle) - `expect("io_o_long_s",io_o_long_s,2,cycle) - `expect("io_o_long_gen",io_o_long_gen,560,cycle) - `expect("io_o_long_gen",io_o_long_gen,560,cycle) - #(1*`CLK_PERIOD) io_i_short_u = 2'd3; - io_i_short_f = -53; - io_i_short_s = -3; - io_i_short_gen = -53; - io_i_long_u = 2'd3; - io_i_long_f = -845; - io_i_long_s = -3; - io_i_long_gen = -845; - io_i_b = 1'd1; - io_i_cGenL_real = -845; - io_i_cGenL_imag = 10'd845; - io_i_cFS_real = -53; - io_i_cFS_imag = 6'd53; - `expect("io_o_short_u",io_o_short_u,3,cycle) - `expect("io_o_short_u",io_o_short_u,3,cycle) - `expect("io_o_short_f",io_o_short_f,52,cycle) - `expect("io_o_short_f",io_o_short_f,52,cycle) - `expect("io_o_short_s",io_o_short_s,3,cycle) - `expect("io_o_short_s",io_o_short_s,3,cycle) - `expect("io_o_short_gen",io_o_short_gen,52,cycle) - `expect("io_o_short_gen",io_o_short_gen,52,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_b",io_o_b,1,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,845,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-845,cycle) - `expect("io_o_cGenL_real",io_o_cGenL_real,845,cycle) - `expect("io_o_cGenL_imag",io_o_cGenL_imag,-845,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,53,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-53,cycle) - `expect("io_o_cFS_real",io_o_cFS_real,53,cycle) - `expect("io_o_cFS_imag",io_o_cFS_imag,-53,cycle) - `expect("io_o_long_u",io_o_long_u,3,cycle) - `expect("io_o_long_u",io_o_long_u,3,cycle) - `expect("io_o_long_f",io_o_long_f,848,cycle) - `expect("io_o_long_f",io_o_long_f,848,cycle) - `expect("io_o_long_s",io_o_long_s,3,cycle) - `expect("io_o_long_s",io_o_long_s,3,cycle) - `expect("io_o_long_gen",io_o_long_gen,848,cycle) - `expect("io_o_long_gen",io_o_long_gen,848,cycle) - #(1*`CLK_PERIOD) io_i_vU_0 = 2'd3; - io_i_vS_0 = -3; - io_i_vF_0 = -53; - io_i_vU_1 = 2'd2; - io_i_vS_1 = -2; - io_i_vF_1 = -35; - io_i_vU_2 = 1'd1; - io_i_vS_2 = -1; - io_i_vF_2 = -18; - io_i_vU_3 = 1'd1; - io_i_vS_3 = -1; - io_i_vF_3 = -9; - io_i_vU_4 = 1'd0; - io_i_vS_4 = 1'd0; - io_i_vF_4 = -6; - io_i_vU_5 = 1'd0; - io_i_vS_5 = 1'd0; - io_i_vF_5 = 3'd6; - io_i_vU_6 = 1'd1; - io_i_vS_6 = 1'd1; - io_i_vF_6 = 4'd9; - io_i_vU_7 = 1'd1; - io_i_vS_7 = 1'd1; - io_i_vF_7 = 5'd18; - io_i_vU_8 = 2'd2; - io_i_vS_8 = 2'd2; - io_i_vF_8 = 6'd35; - io_i_vU_9 = 2'd3; - io_i_vS_9 = 2'd3; - io_i_vF_9 = 6'd53; - #(5*`CLK_PERIOD) io_i_vU_0 = 2'd3; - io_i_vS_0 = 2'd3; - io_i_vF_0 = 6'd53; - `expect("io_o_vU_0",io_o_vU_0,3,cycle) - `expect("io_o_vU_0",io_o_vU_0,3,cycle) - `expect("io_o_vS_0",io_o_vS_0,-3,cycle) - `expect("io_o_vS_0",io_o_vS_0,-3,cycle) - `expect("io_o_vF_0",io_o_vF_0,-53,cycle) - `expect("io_o_vF_0",io_o_vF_0,-53,cycle) - io_i_vU_1 = 2'd2; - io_i_vS_1 = 2'd2; - io_i_vF_1 = 6'd35; - `expect("io_o_vU_1",io_o_vU_1,2,cycle) - `expect("io_o_vU_1",io_o_vU_1,2,cycle) - `expect("io_o_vS_1",io_o_vS_1,-2,cycle) - `expect("io_o_vS_1",io_o_vS_1,-2,cycle) - `expect("io_o_vF_1",io_o_vF_1,-35,cycle) - `expect("io_o_vF_1",io_o_vF_1,-35,cycle) - io_i_vU_2 = 1'd1; - io_i_vS_2 = 1'd1; - io_i_vF_2 = 5'd18; - `expect("io_o_vU_2",io_o_vU_2,1,cycle) - `expect("io_o_vU_2",io_o_vU_2,1,cycle) - `expect("io_o_vS_2",io_o_vS_2,-1,cycle) - `expect("io_o_vS_2",io_o_vS_2,-1,cycle) - `expect("io_o_vF_2",io_o_vF_2,-18,cycle) - `expect("io_o_vF_2",io_o_vF_2,-18,cycle) - io_i_vU_3 = 1'd1; - io_i_vS_3 = 1'd1; - io_i_vF_3 = 4'd9; - `expect("io_o_vU_3",io_o_vU_3,1,cycle) - `expect("io_o_vU_3",io_o_vU_3,1,cycle) - `expect("io_o_vS_3",io_o_vS_3,-1,cycle) - `expect("io_o_vS_3",io_o_vS_3,-1,cycle) - `expect("io_o_vF_3",io_o_vF_3,-9,cycle) - `expect("io_o_vF_3",io_o_vF_3,-9,cycle) - io_i_vU_4 = 1'd0; - io_i_vS_4 = 1'd0; - io_i_vF_4 = 3'd6; - `expect("io_o_vU_4",io_o_vU_4,0,cycle) - `expect("io_o_vU_4",io_o_vU_4,0,cycle) - `expect("io_o_vS_4",io_o_vS_4,0,cycle) - `expect("io_o_vS_4",io_o_vS_4,0,cycle) - `expect("io_o_vF_4",io_o_vF_4,-6,cycle) - `expect("io_o_vF_4",io_o_vF_4,-6,cycle) - io_i_vU_5 = 1'd0; - io_i_vS_5 = 1'd0; - io_i_vF_5 = -6; - `expect("io_o_vU_5",io_o_vU_5,0,cycle) - `expect("io_o_vU_5",io_o_vU_5,0,cycle) - `expect("io_o_vS_5",io_o_vS_5,0,cycle) - `expect("io_o_vS_5",io_o_vS_5,0,cycle) - `expect("io_o_vF_5",io_o_vF_5,6,cycle) - `expect("io_o_vF_5",io_o_vF_5,6,cycle) - io_i_vU_6 = 1'd1; - io_i_vS_6 = -1; - io_i_vF_6 = -9; - `expect("io_o_vU_6",io_o_vU_6,1,cycle) - `expect("io_o_vU_6",io_o_vU_6,1,cycle) - `expect("io_o_vS_6",io_o_vS_6,1,cycle) - `expect("io_o_vS_6",io_o_vS_6,1,cycle) - `expect("io_o_vF_6",io_o_vF_6,9,cycle) - `expect("io_o_vF_6",io_o_vF_6,9,cycle) - io_i_vU_7 = 1'd1; - io_i_vS_7 = -1; - io_i_vF_7 = -18; - `expect("io_o_vU_7",io_o_vU_7,1,cycle) - `expect("io_o_vU_7",io_o_vU_7,1,cycle) - `expect("io_o_vS_7",io_o_vS_7,1,cycle) - `expect("io_o_vS_7",io_o_vS_7,1,cycle) - `expect("io_o_vF_7",io_o_vF_7,18,cycle) - `expect("io_o_vF_7",io_o_vF_7,18,cycle) - io_i_vU_8 = 2'd2; - io_i_vS_8 = -2; - io_i_vF_8 = -35; - `expect("io_o_vU_8",io_o_vU_8,2,cycle) - `expect("io_o_vU_8",io_o_vU_8,2,cycle) - `expect("io_o_vS_8",io_o_vS_8,2,cycle) - `expect("io_o_vS_8",io_o_vS_8,2,cycle) - `expect("io_o_vF_8",io_o_vF_8,35,cycle) - `expect("io_o_vF_8",io_o_vF_8,35,cycle) - io_i_vU_9 = 2'd3; - io_i_vS_9 = -3; - io_i_vF_9 = -53; - `expect("io_o_vU_9",io_o_vU_9,3,cycle) - `expect("io_o_vU_9",io_o_vU_9,3,cycle) - `expect("io_o_vS_9",io_o_vS_9,3,cycle) - `expect("io_o_vS_9",io_o_vS_9,3,cycle) - `expect("io_o_vF_9",io_o_vF_9,53,cycle) - `expect("io_o_vF_9",io_o_vF_9,53,cycle) - #(5*`CLK_PERIOD) io_i_vU_0 = 1'd0; - io_i_vS_0 = 1'd0; - io_i_vF_0 = 1'd0; - `expect("io_o_vU_0",io_o_vU_0,3,cycle) - `expect("io_o_vU_0",io_o_vU_0,3,cycle) - `expect("io_o_vS_0",io_o_vS_0,3,cycle) - `expect("io_o_vS_0",io_o_vS_0,3,cycle) - `expect("io_o_vF_0",io_o_vF_0,53,cycle) - `expect("io_o_vF_0",io_o_vF_0,53,cycle) - io_i_vU_1 = 1'd0; - io_i_vS_1 = 1'd0; - io_i_vF_1 = 1'd0; - `expect("io_o_vU_1",io_o_vU_1,2,cycle) - `expect("io_o_vU_1",io_o_vU_1,2,cycle) - `expect("io_o_vS_1",io_o_vS_1,2,cycle) - `expect("io_o_vS_1",io_o_vS_1,2,cycle) - `expect("io_o_vF_1",io_o_vF_1,35,cycle) - `expect("io_o_vF_1",io_o_vF_1,35,cycle) - io_i_vU_2 = 1'd0; - io_i_vS_2 = 1'd0; - io_i_vF_2 = 1'd0; - `expect("io_o_vU_2",io_o_vU_2,1,cycle) - `expect("io_o_vU_2",io_o_vU_2,1,cycle) - `expect("io_o_vS_2",io_o_vS_2,1,cycle) - `expect("io_o_vS_2",io_o_vS_2,1,cycle) - `expect("io_o_vF_2",io_o_vF_2,18,cycle) - `expect("io_o_vF_2",io_o_vF_2,18,cycle) - io_i_vU_3 = 1'd0; - io_i_vS_3 = 1'd0; - io_i_vF_3 = 1'd0; - `expect("io_o_vU_3",io_o_vU_3,1,cycle) - `expect("io_o_vU_3",io_o_vU_3,1,cycle) - `expect("io_o_vS_3",io_o_vS_3,1,cycle) - `expect("io_o_vS_3",io_o_vS_3,1,cycle) - `expect("io_o_vF_3",io_o_vF_3,9,cycle) - `expect("io_o_vF_3",io_o_vF_3,9,cycle) - io_i_vU_4 = 1'd0; - io_i_vS_4 = 1'd0; - io_i_vF_4 = 1'd0; - `expect("io_o_vU_4",io_o_vU_4,0,cycle) - `expect("io_o_vU_4",io_o_vU_4,0,cycle) - `expect("io_o_vS_4",io_o_vS_4,0,cycle) - `expect("io_o_vS_4",io_o_vS_4,0,cycle) - `expect("io_o_vF_4",io_o_vF_4,6,cycle) - `expect("io_o_vF_4",io_o_vF_4,6,cycle) - io_i_vU_5 = 1'd0; - io_i_vS_5 = 1'd0; - io_i_vF_5 = 1'd0; - `expect("io_o_vU_5",io_o_vU_5,0,cycle) - `expect("io_o_vU_5",io_o_vU_5,0,cycle) - `expect("io_o_vS_5",io_o_vS_5,0,cycle) - `expect("io_o_vS_5",io_o_vS_5,0,cycle) - `expect("io_o_vF_5",io_o_vF_5,-6,cycle) - `expect("io_o_vF_5",io_o_vF_5,-6,cycle) - io_i_vU_6 = 1'd0; - io_i_vS_6 = 1'd0; - io_i_vF_6 = 1'd0; - `expect("io_o_vU_6",io_o_vU_6,1,cycle) - `expect("io_o_vU_6",io_o_vU_6,1,cycle) - `expect("io_o_vS_6",io_o_vS_6,-1,cycle) - `expect("io_o_vS_6",io_o_vS_6,-1,cycle) - `expect("io_o_vF_6",io_o_vF_6,-9,cycle) - `expect("io_o_vF_6",io_o_vF_6,-9,cycle) - io_i_vU_7 = 1'd0; - io_i_vS_7 = 1'd0; - io_i_vF_7 = 1'd0; - `expect("io_o_vU_7",io_o_vU_7,1,cycle) - `expect("io_o_vU_7",io_o_vU_7,1,cycle) - `expect("io_o_vS_7",io_o_vS_7,-1,cycle) - `expect("io_o_vS_7",io_o_vS_7,-1,cycle) - `expect("io_o_vF_7",io_o_vF_7,-18,cycle) - `expect("io_o_vF_7",io_o_vF_7,-18,cycle) - io_i_vU_8 = 1'd0; - io_i_vS_8 = 1'd0; - io_i_vF_8 = 1'd0; - `expect("io_o_vU_8",io_o_vU_8,2,cycle) - `expect("io_o_vU_8",io_o_vU_8,2,cycle) - `expect("io_o_vS_8",io_o_vS_8,-2,cycle) - `expect("io_o_vS_8",io_o_vS_8,-2,cycle) - `expect("io_o_vF_8",io_o_vF_8,-35,cycle) - `expect("io_o_vF_8",io_o_vF_8,-35,cycle) - io_i_vU_9 = 1'd0; - io_i_vS_9 = 1'd0; - io_i_vF_9 = 1'd0; - `expect("io_o_vU_9",io_o_vU_9,3,cycle) - `expect("io_o_vU_9",io_o_vU_9,3,cycle) - `expect("io_o_vS_9",io_o_vS_9,-3,cycle) - `expect("io_o_vS_9",io_o_vS_9,-3,cycle) - `expect("io_o_vF_9",io_o_vF_9,-53,cycle) - `expect("io_o_vF_9",io_o_vF_9,-53,cycle) - `expect("io_o_vU_0",io_o_vU_0,3,cycle) - `expect("io_o_vU_1",io_o_vU_1,2,cycle) - `expect("io_o_vU_2",io_o_vU_2,1,cycle) - `expect("io_o_vU_3",io_o_vU_3,1,cycle) - `expect("io_o_vU_4",io_o_vU_4,0,cycle) - `expect("io_o_vU_5",io_o_vU_5,0,cycle) - `expect("io_o_vU_6",io_o_vU_6,1,cycle) - `expect("io_o_vU_7",io_o_vU_7,1,cycle) - `expect("io_o_vU_8",io_o_vU_8,2,cycle) - `expect("io_o_vU_9",io_o_vU_9,3,cycle) - `expect("io_o_vS_0",io_o_vS_0,3,cycle) - `expect("io_o_vS_1",io_o_vS_1,2,cycle) - `expect("io_o_vS_2",io_o_vS_2,1,cycle) - `expect("io_o_vS_3",io_o_vS_3,1,cycle) - `expect("io_o_vS_4",io_o_vS_4,0,cycle) - `expect("io_o_vS_5",io_o_vS_5,0,cycle) - `expect("io_o_vS_6",io_o_vS_6,-1,cycle) - `expect("io_o_vS_7",io_o_vS_7,-1,cycle) - `expect("io_o_vS_8",io_o_vS_8,-2,cycle) - `expect("io_o_vS_9",io_o_vS_9,-3,cycle) - - #`CLK_PERIOD $display("\t **Ran through all test vectors**"); $finish; - - end -endmodule \ No newline at end of file diff --git a/src/test/scala/dsptools/BaseNSpec.scala b/src/test/scala/dsptools/BaseNSpec.scala deleted file mode 100644 index 516f7aaf..00000000 --- a/src/test/scala/dsptools/BaseNSpec.scala +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -/* -package dsptools - -import chisel3._ - - - -//scalastyle:off magic.number - -class BaseNCircuit extends Module { - val thing = Reg(BaseN(Seq.fill(5)(UInt(4.W)), rad = 3)) - val io = IO(new Bundle { - val inc = Input(UInt(3.W)) - val out = Output(thing.cloneType) - }) - val increment = BaseN(Seq.fill(5)(UInt(4.W)), rad = 3) - - increment := io.inc - - - thing := thing + increment - io.out := thing -} - -class BaseNCircuitTester(c: BaseNCircuit) extends DspTester(c) { - for(_ <- 0 to 7) { - poke(c.io.inc, 1) - step(1) - println(f"current value ${peek(c.io.out.underlying.asUInt())}%04x") //scalastyle:off regex - } -} - -class BaseNSpec extends AnyFreeSpec with Matchers { - "baseN tester increments" ignore { - chisel3.iotesters.Driver(() => new BaseNCircuit) { c => - new BaseNCircuitTester(c) - } should be(true) - } - - "BaseN utilities have a number of capabilities" - { - "create a list of ints from an int based on a radix" ignore { - BaseN.toIntList(0, 5) should be (List(0)) - BaseN.toIntList(1, 5) should be (List(1)) - BaseN.toIntList(6, 5) should be (List(1, 1)) - } - "create a compute length of list" ignore { - BaseN.numDigits(0, 5) should be (1) - BaseN.toIntList(1, 5) should be (1) - BaseN.toIntList(6, 5) should be (2) - } - } -} -*/ diff --git a/src/test/scala/dsptools/DspContextSpec.scala b/src/test/scala/dsptools/DspContextSpec.scala deleted file mode 100644 index e15b2df0..00000000 --- a/src/test/scala/dsptools/DspContextSpec.scala +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools - -import chisel3._ -import dsptools.numbers._ - - - -import scala.collection.parallel.CollectionConverters.RangeIsParallelizable - -class DspContextSpec extends AnyFreeSpec with Matchers { - "Context handling should be unobtrusive and convenient" - { - "There should be a default available at all times" in { - DspContext.current.binaryPoint should be (DspContext.defaultBinaryPoint) - } - - "it can be very to override for simple alterations" in { - DspContext.current.binaryPoint should be (DspContext.defaultBinaryPoint) - - DspContext.withBinaryPoint(-22) { - DspContext.current.binaryPoint.get should be (-22) - } - - DspContext.current.binaryPoint should be (DspContext.defaultBinaryPoint) - } - - "it should be easy to override when using multiples" in { - DspContext.current.binaryPoint should be (DspContext.defaultBinaryPoint) - DspContext.current.overflowType should be (DspContext.defaultOverflowType) - - DspContext.alter(DspContext.current.copy(binaryPoint = Some(77), overflowType = Saturate)) { - DspContext.current.binaryPoint.get should be (77) - DspContext.current.overflowType should be (Saturate) - } - - DspContext.current.binaryPoint should be (DspContext.defaultBinaryPoint) - DspContext.current.overflowType should be (DspContext.defaultOverflowType) - } - - "it should work multi-threaded and return values of block" ignore { - DspContext.current.numBits should be (DspContext.defaultNumBits) - - val points = (1 to 100).par.map { n => - DspContext.withNumBits(n) { - DspContext.current.numBits.get should be (n) - n * n - } - } - - val zipped = points.zipWithIndex - zipped.foreach { - case (p: Int, i: Int) => p should be (math.pow(i + 1, 2)) - } - - DspContext.current.numBits should be (DspContext.defaultNumBits) - } - } - - "Test proper nesting of DspContext over module instantiation" in { - dsptools.Driver.execute( - () => new ContextNestingTop(UInt(4.W), UInt(5.W)), - Array("--backend-name", "firrtl") - ) { c => - new ContextNestingTester(c) - } should be(true) } -} - -class ContextNestingTester(c: ContextNestingTop[UInt]) extends DspTester(c) { - poke(c.io.in1, 15.0) - poke(c.io.in2, 2.0) - - expect(c.io.mod1Default, 1.0) - expect(c.io.mod1Wrap, 1.0) - expect(c.io.mod1Grow, 17.0) - expect(c.io.mod2Default, 17.0) - expect(c.io.mod2Wrap, 1.0) - expect(c.io.mod2Grow, 17.0) -} - -class ContextNestingBottom[T <: Data : Ring](gen1: T, gen2: T) extends Module { - val io = IO( new Bundle { - val in1 = Input(gen1) - val in2 = Input(gen1) - val outDefault = Output(gen2) - val outWrap = Output(gen2) - val outGrow = Output(gen2) - }) - - DspContext.withOverflowType(Wrap) { - io.outWrap := io.in1 context_+ io.in2 - } - DspContext.withOverflowType(Grow) { - io.outGrow := io.in1 context_+ io.in2 - } - - io.outDefault := io.in1 context_+ io.in2 -} - -class ContextNestingTop[T <: Data : Ring](gen1: T, gen2: T) extends Module { - val io = IO( new Bundle { - val in1 = Input(gen1) - val in2 = Input(gen1) - val mod1Default = Output(gen2) - val mod1Wrap = Output(gen2) - val mod1Grow = Output(gen2) - val mod2Default = Output(gen2) - val mod2Wrap = Output(gen2) - val mod2Grow = Output(gen2) - }) - - private val mod1 = DspContext.withOverflowType(Wrap) { Module(new ContextNestingBottom(gen1, gen2)) } - private val mod2 = DspContext.withOverflowType(Grow) { Module(new ContextNestingBottom(gen1, gen2)) } - - mod1.io.in1 := io.in1 - mod1.io.in2 := io.in2 - mod2.io.in1 := io.in1 - mod2.io.in2 := io.in2 - - io.mod1Default := mod1.io.outDefault - io.mod1Wrap := mod1.io.outWrap - io.mod1Grow := mod1.io.outGrow - io.mod2Default := mod2.io.outDefault - io.mod2Wrap := mod2.io.outWrap - io.mod2Grow := mod2.io.outGrow -} diff --git a/src/test/scala/dsptools/DspTesterSpec.scala b/src/test/scala/dsptools/DspTesterSpec.scala deleted file mode 100644 index 7793977d..00000000 --- a/src/test/scala/dsptools/DspTesterSpec.scala +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools - -import DspTesterUtilities._ - - -import scala.math.{pow, abs} - -class DspTesterSpec { - -} - -class DspTesterUtilitiesSpec extends AnyFlatSpec with Matchers { - - behavior of "Tester Converters" - - it should "convert positive and negative doubles to their BigInt, fixed point equivalents" in { - - def check_conversion(value: Double, totalWidth: Int, fractionalWidth: Int, verbose: Boolean = false): Unit = { - if (verbose) { println(s"value = $value\ntotal width = $totalWidth\nfractional width = $fractionalWidth") } - var bi = signedToBigIntUnsigned(value, totalWidth, fractionalWidth) - if (verbose) { println(s"result = $bi") } - // check sign, flip if necessary - if (totalWidth > 0 && bi.testBit(totalWidth-1)) { - bi = -1 * ((bi ^ ((BigInt(1) << totalWidth) - 1)) + 1) - } - val bid = bi.toDouble / (BigInt(1) << fractionalWidth).toDouble - if (verbose) { println(s"back to double = $bid") } - val comp = scala.math.abs(bid-value) - if (verbose) { println(s"comp = $comp") } - val ref = scala.math.pow(2, -fractionalWidth) - if (verbose) { println(s"ref = $ref") } - require(abs(bid-value) < pow(2, -fractionalWidth)) - } - - // integers - var width = 14 - for (i <- -pow(2,width-1).toInt until pow(2,width-1).toInt) { - check_conversion(i, width, 0) - } - - // big integers - width = 40 - for (i <- -pow(2,width-1).toInt to pow(2,width-1).toInt by pow(2, 20).toInt) { - check_conversion(i, width, 0) - } - - // total > fractional - width = 19 - var fract = 8 - for (i <- BigDecimal(-pow(2,width-fract-1)) to pow(2,width-fract-1)-1 by 1.0/fract*0.9) { - check_conversion(i.toDouble, width, fract) - } - - // total < fractional - width = 11 - fract = 17 - for (i <- BigDecimal(-pow(2,width-fract-1)) to pow(2,width-fract-1)-1 by 1.0/fract*0.9) { - check_conversion(i.toDouble, width, fract) - } - - } - - it should "fail to convert doubles to BigInts when not enough space is supplied" in { - intercept[IllegalArgumentException] { signedToBigIntUnsigned(2.0, 4, 2) } - intercept[IllegalArgumentException] { signedToBigIntUnsigned(-2.25, 4, 2) } - } - -} diff --git a/src/test/scala/dsptools/LoggingSpec.scala b/src/test/scala/dsptools/LoggingSpec.scala deleted file mode 100644 index 414a586b..00000000 --- a/src/test/scala/dsptools/LoggingSpec.scala +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools - -import chisel3._ -import logger.{LazyLogging, LogLevel, Logger} - - - -class DutWithLogging extends Module with LazyLogging { - val io = IO(new Bundle {}) - - logger.error("error level message") - logger.warn("warn level message") - logger.info("info level message") - logger.debug("debug level message") - logger.trace("trace level message") -} - -class DutWithLoggingTester(c: DutWithLogging) extends DspTester(c) - -class LoggingSpec extends AnyFreeSpec with Matchers { - "logging can be emitted during hardware generation" - { - "level defaults to warn" in { - Logger.makeScope() { - val captor = new Logger.OutputCaptor - Logger.setOutput(captor.printStream) - - dsptools.Driver.execute(() => new DutWithLogging, Array.empty[String]) { c => - new DutWithLoggingTester(c) - } - captor.getOutputAsString should include("error level message") - captor.getOutputAsString should include("warn level message") - captor.getOutputAsString should not include ("info level message") - captor.getOutputAsString should not include ("debug level message") - captor.getOutputAsString should not include ("trace level message") - } - } - "logging level can be set via command line args" in { - Logger.makeScope() { - val captor = new Logger.OutputCaptor - Logger.setOutput(captor.printStream) - - dsptools.Driver.execute(() => new DutWithLogging, Array("--log-level", "info")) { c => - new DutWithLoggingTester(c) - } - captor.getOutputAsString should include("error level message") - captor.getOutputAsString should include ("warn level message") - captor.getOutputAsString should include ("info level message") - captor.getOutputAsString should not include ("debug level message") - captor.getOutputAsString should not include ("trace level message") - } - } - "logging level can be set for a specific package" in { - Logger.makeScope() { - val captor = new Logger.OutputCaptor - Logger.setOutput(captor.printStream) - - dsptools.Driver.execute(() => new DutWithLogging, Array("--class-log-level", "dsptools:warn")) { c => - new DutWithLoggingTester(c) - } - captor.getOutputAsString should include("error level message") - captor.getOutputAsString should include ("warn level message") - captor.getOutputAsString should not include ("info level message") - captor.getOutputAsString should not include ("debug level message") - captor.getOutputAsString should not include ("trace level message") - } - } - } -} diff --git a/src/test/scala/dsptools/ShiftRegisterDelaySpec.scala b/src/test/scala/dsptools/ShiftRegisterDelaySpec.scala deleted file mode 100644 index 053bb6ae..00000000 --- a/src/test/scala/dsptools/ShiftRegisterDelaySpec.scala +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools - -import chisel3._ -import chisel3.experimental.FixedPoint -import dsptools.numbers._ - - - -import scala.collection.mutable - -//TODO: DspReal truncate, ceil -//TODO: FixedPoint ceil -//TODO: For truncate and ceil, compare delay between Fixed and Real - -//scalastyle:off magic.number regex - -class AbsCircuitWithDelays[T <: Data : Signed](gen: T, val delays: Int) extends Module { - val io = IO(new Bundle { - val in = Input(gen) - val outContextAbs = Output(gen) - }) - - DspContext.withNumAddPipes(delays) { - val con = io.in.context_abs() - printf("io.in %d con %d\n", io.in.asUInt, con.asUInt) - io.outContextAbs := con - } -} - -class CeilTruncateCircuitWithDelays(val delays: Int) extends Module { - val io = IO(new Bundle { - val inFixed = Input(FixedPoint(12.W, 4.BP)) - val inReal = Input(DspReal()) - val outFixedCeil = Output(FixedPoint(12.W, 4.BP)) - val outRealCeil = Output(DspReal()) - val outFixedTruncate = Output(FixedPoint(12.W, 4.BP)) - val outRealTruncate = Output(DspReal()) - }) - - DspContext.withNumAddPipes(delays) { - io.outFixedCeil := io.inFixed.ceil() - io.outRealCeil := io.inReal.context_ceil() - io.outFixedTruncate := io.inFixed.truncate() - io.outRealTruncate := io.inReal.truncate() - } -} -class CircuitWithDelaysTester[T <: Data : Signed](c: AbsCircuitWithDelays[T]) extends DspTester(c) { - private val delaySize = c.delays - - def oneTest(): Unit = { - def values: Seq[Double] = (BigDecimal(-delaySize) to delaySize.toDouble by 1.0).map(_.toDouble) - val inQueue = new mutable.Queue[Double] ++ values - val outQueue = new mutable.Queue[Double] ++ Seq.fill(delaySize-1)(0.0) ++ values.map(_.abs) - - while(inQueue.nonEmpty) { - val inValue = inQueue.dequeue() - poke(c.io.in, inValue) - step(1) - val expectedValue = outQueue.dequeue() - expect(c.io.outContextAbs, expectedValue) - } - while(outQueue.nonEmpty) { - val expectedValue = outQueue.dequeue() - step(1) - expect(c.io.outContextAbs, expectedValue) - } - } - - updatableDspVerbose.withValue(false) { - reset() - poke(c.io.in, 0.0) - step(10) - oneTest() - } -} - -class CeilTruncateTester(c: CeilTruncateCircuitWithDelays) extends DspTester(c) { - private val delaySize = c.delays - - def oneTest( - inFixedIo: FixedPoint, outFixedIo: FixedPoint, - inRealIo: DspReal, outRealIo: DspReal, - delaySize: Int): Unit = { - def values: Seq[Double] = (BigDecimal(-delaySize) to delaySize.toDouble by 1.0).map(_.toDouble) - val inQueue = new mutable.Queue[Double] ++ values - val outQueue = new mutable.Queue[Double] ++ Seq.fill(delaySize)(0.0) ++ values.map(_.ceil) - - while(inQueue.nonEmpty) { - val inValue = inQueue.dequeue() - poke(inFixedIo, inValue) - poke(inRealIo, inValue) - val expectedValue = outQueue.dequeue() - expect(outFixedIo, expectedValue) - expect(outRealIo, expectedValue) - step(1) - } - while(outQueue.nonEmpty) { - val expectedValue = outQueue.dequeue() - expect(outFixedIo, expectedValue) - expect(outRealIo, expectedValue) - step(1) - } - } - - updatableDspVerbose.withValue(false) { - poke(c.io.inFixed, 0.0) - poke(c.io.inReal, 0.0) - reset() - step(10) - oneTest(c.io.inFixed, c.io.outFixedCeil, c.io.inReal, c.io.outRealCeil, delaySize) - } -} - -class ShiftRegisterDelaySpec extends AnyFreeSpec with Matchers { - "ceil delay should be consistent between dsp real and fixed point" in { - dsptools.Driver.execute( - () => new CeilTruncateCircuitWithDelays(2), - Array("--backend-name", "firrtl") - ) { c => - new CeilTruncateTester(c) - } should be(true) - } - "abs delays should be consistent across both sides of underlying mux" - { - - def sGen: SInt = SInt(16.W) - def fGen: FixedPoint = FixedPoint(16.W, 8.BP) - def rGen: DspReal = DspReal() - - "when used with SInt" in { - dsptools.Driver.execute( - () => new AbsCircuitWithDelays(sGen, 3), - Array("--backend-name", "verilator") - ) { c => - new CircuitWithDelaysTester(c) - } should be(true) - } - - "when used with FixedPoint" in { - dsptools.Driver.execute( - () => new AbsCircuitWithDelays(fGen, 3), - Array("--backend-name", "verilator") - ) { c => - new CircuitWithDelaysTester(c) - } should be(true) - } - - "when used with DspReal" in { - dsptools.Driver.execute( - () => new AbsCircuitWithDelays(rGen, 8), - Array("--backend-name", "verilator") - ) { c => - new CircuitWithDelaysTester(c) - } should be(true) - } - } -} diff --git a/src/test/scala/dsptools/VerboseDspTesterSpec/SimpleTBwGenTypeOption.scala b/src/test/scala/dsptools/VerboseDspTesterSpec/SimpleTBwGenTypeOption.scala deleted file mode 100644 index 8e69a3ca..00000000 --- a/src/test/scala/dsptools/VerboseDspTesterSpec/SimpleTBwGenTypeOption.scala +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package SimpleTB - -import chisel3._ -import chisel3.util._ -import chisel3.internal.firrtl.{Width, BinaryPoint} -import chisel3.experimental.FixedPoint -import breeze.math.Complex -import dsptools.{DspTester, DspTesterOptionsManager, DspTesterOptions} -import dsptools.numbers._ - - -import chisel3.iotesters.TesterOptions - -trait EasyPeekPoke { - - self: DspTester[_] => - - def feed(d: Data, value: Double) = { - d match { - case b: Bool => poke(b, if (value == 0.0) false else true) - case u: UInt => poke(u, math.abs(value.round).toInt) - case r => poke(r, value) - } - } - def feed(d: DspComplex[_], value: Complex) = poke(d, value) - - // TB Debug only [otherwise, just use expect for any *real* tb!] - def checkP(d: Data, value: Double) { - peek(d) - // SInts are perfect in this case b/c they're just passed through (no loss of precision) - d match { - case _: SInt | _: UInt | _: Bool => fixTolLSBs.withValue(0) { check(d, value) } - case _ => check(d, value) - } - } - - def checkP(d: DspComplex[_], value: Complex) = { - peek(d) - d.real match { - case _: SInt | _: UInt | _: Bool => fixTolLSBs.withValue(0) { - check(d, value) - } - case _ => check(d, value) - } - } - - // TODO: Add runtime tolerance change here as a shortcut? - def check(d: Data, value: Double) { - d match { - case b: Bool => expect(b, if (value == 0.0) false else true) - case u: UInt => expect(u, math.abs(value.round).toInt) - case f: FixedPoint => { - expect(f, value) - require(f.binaryPoint.get > 0, "Fixed points used in this test have >0 fractional bits!") - } - case r => expect(r, value) - } - } - def check(d: DspComplex[_], value: Complex) = expect(d, value) -} - -case class TestParams( - val smallW: Int = 8, - val bigW: Int = 16, - val smallBP: Int = 4, - val bigBP: Int = 8, - val posLit: Double = 3.3, - val negLit: Double = -3.3, - val lutVals: Seq[Double] = Seq(-3.3, -2.2, -1.1, -0.55, -0.4, 0.4, 0.55, 1.1, 2.2, 3.3)) { - - val genLongF = FixedPoint(bigW.W, bigBP.BP) - val genShortF = FixedPoint(smallW.W, smallBP.BP) - val genLongS = SInt(bigW.W) - val genShortS = SInt(smallW.W) - val genR = DspReal() - val vecLen = lutVals.length - -} - -class DataTypeBundle[R <: Data:Real](genType: R, dataWidth: Width, binaryPoint: BinaryPoint) extends Bundle { - val gen = genType.cloneType - val s = SInt(dataWidth) - val f = FixedPoint(dataWidth, binaryPoint) - val u = UInt(dataWidth) -} - -class Interface[R <: Data:Real](genShort: R, genLong: R, includeR: Boolean, p: TestParams) extends Bundle { - - val smallW = p.smallW.W - val bigW = p.bigW.W - val smallBP = p.smallBP.BP - val bigBP = p.bigBP.BP - val vecLen = p.vecLen - - val r = if (includeR) Some(DspReal()) else None - val RP = if (includeR) Some(DspReal()) else None - val RN = if (includeR) Some(DspReal()) else None - val b = Bool() - val cGenL = DspComplex(genLong) - val cFS = DspComplex(FixedPoint(smallW, smallBP)) - val cR = if (includeR) Some(DspComplex(DspReal())) else None - - val short = new DataTypeBundle(genShort, smallW, smallBP) - val long = new DataTypeBundle(genLong, bigW, bigBP) - - val vU = Vec(vecLen, UInt(smallW)) - val vS = Vec(vecLen, SInt(smallW)) - val vF = Vec(vecLen, FixedPoint(smallW, smallBP)) -} - -class SimpleIOModule[R <: Data:Real](genShort: R, genLong: R, val includeR: Boolean, val p: TestParams) - extends Module { - - val io = IO(new Bundle { - val i = Input(new Interface(genShort, genLong, includeR, p)) - val o = Output(new Interface(genShort, genLong, includeR, p)) }) - - // Crossed sizes on purpose (to make sure Fixed point was interpreted correctly) - io.o.long <> RegNext(io.i.short) - io.o.short <> RegNext(io.i.long) - - if (includeR) io.o.r.get := RegNext(io.i.r.get) - io.o.b := RegNext(io.i.b) - io.o.cGenL := RegNext(io.i.cGenL) - io.o.cFS := RegNext(io.i.cFS) - if (includeR) io.o.cR.get := RegNext(io.i.cR.get) - - io.o.vU := RegNext(io.i.vU) - io.o.vS := RegNext(io.i.vS) - io.o.vF := RegNext(io.i.vF) - - if (includeR) { - io.o.RP.get := DspReal(0) - io.o.RN.get := DspReal(0) - } -} - -class SimpleLitModule[R <: Data:Real](genShort: R, genLong: R, val includeR: Boolean, val p: TestParams) - extends Module { - - val posLit = p.posLit - val negLit = p.negLit - val lutVals = p.lutVals - val bp = p.smallBP - - val io = IO(new Bundle { - val i = Input(new Interface(genShort, genLong, includeR, p)) - val o = Output(new Interface(genShort, genLong, includeR, p)) }) - - val litRP = if (includeR) Some(DspReal(posLit)) else None - val litRN = if (includeR) Some(DspReal(negLit)) else None - - val pos = new Bundle { - val litG = genShort.fromDouble(posLit) - val litS = posLit.round.toInt.S - val litF = posLit.F(bp.BP) - } - - val neg = new Bundle { - val litG = genShort.fromDouble(negLit) - val litS = negLit.round.toInt.S - val litF = negLit.F(bp.BP) - } - - val litB = true.B - val litU = posLit.round.toInt.U - val litC = DspComplex(posLit.F(bp.BP), negLit.F(bp.BP)) - - val lutGenSeq = lutVals map {x => genShort.fromDoubleWithFixedWidth(x)} - val lutSSeq = lutVals map (_.round.toInt.S(p.smallW.W)) - - val lutGen = VecInit(lutGenSeq) - val lutS = VecInit(lutSSeq) - - io.o.vU := RegNext(io.i.vU) - io.o.vS := RegNext(io.i.vS) - io.o.vF := RegNext(io.i.vF) - io.o.long := io.i.long - io.o.short := io.i.short - io.o.b := io.i.b - io.o.cGenL := io.i.cGenL - io.o.cFS := io.i.cFS - io.o.short.gen := lutGen(io.i.short.u) - io.o.short.s := lutS(io.i.short.u) - if (includeR) { - io.o.RP.get := litRP.get - io.o.RN.get := litRN.get - io.o.r.get := io.i.r.get - io.o.cR.get := io.i.cR.get - } -} - -class PassIOTester[R <: Data:Real](c: SimpleIOModule[R]) extends DspTester(c) with EasyPeekPoke { - - val lutVals = c.p.lutVals - val io = c.io - - // SInts auto rounded; UInts auto absolute valued + rounded - (lutVals :+ lutVals.head).zipWithIndex foreach { case (value, i) => { - (io.i.short.elements.unzip._2 ++ io.i.long.elements.unzip._2) foreach { a => feed(a, value) } - val complexVal = Complex(value, -value) - if (c.includeR) feed(io.i.r.get, value) - feed(io.i.b, value) - feed(io.i.cGenL, complexVal) - feed(io.i.cFS, complexVal) - if (c.includeR) feed(io.i.cR.get, complexVal) - if (i != 0) { - val prevVal = lutVals(i-1) - val prevComplexVal = Complex(prevVal, -prevVal) - io.o.short.elements.unzip._2 foreach { a => checkP(a, prevVal) } - if (c.includeR) checkP(io.o.r.get, prevVal) - checkP(io.o.b, prevVal) - checkP(io.o.cGenL, prevComplexVal) - checkP(io.o.cFS, prevComplexVal) - if (c.includeR) checkP(io.o.cR.get, prevComplexVal) - // Since long outputs come from short inputs, the tolerance must match that of smallBP - fixTolLSBs.withValue(c.p.bigBP - c.p.smallBP + fixTolLSBs.value) { - io.o.long.elements.unzip._2 foreach { a => checkP(a, prevVal) } - } - } - step(1) - }} - - lutVals.zipWithIndex foreach { case (value, i) => { - feed(io.i.vU(i), value) - feed(io.i.vS(i), value) - feed(io.i.vF(i), value) - }} - - step(5) - lutVals.reverse.zipWithIndex foreach { case (value, i) => { - feed(io.i.vU(i), value) - feed(io.i.vS(i), value) - feed(io.i.vF(i), value) - checkP(io.o.vU(i), lutVals(i)) - checkP(io.o.vS(i), lutVals(i)) - checkP(io.o.vF(i), lutVals(i)) - }} - - step(5) - lutVals.reverse.zipWithIndex foreach { case (value, i) => { - feed(io.i.vU(i), 0) - feed(io.i.vS(i), 0) - feed(io.i.vF(i), 0) - checkP(io.o.vU(i), value) - checkP(io.o.vS(i), value) - checkP(io.o.vF(i), value) - }} - - peek(io.o.vU) - peek(io.o.vS) - -} - -class PassLitTester[R <: Data:Real](c: SimpleLitModule[R]) extends DspTester(c) with EasyPeekPoke { - - val posLit = c.posLit - val negLit = c.negLit - val lutVals = c.lutVals - - if (c.includeR) { - checkP(c.io.o.RP.get, posLit) - checkP(c.io.o.RN.get, negLit) - } - - // expect properly rounds doubles to ints for SInt - c.pos.elements foreach { case (s, d) => checkP(d, posLit) } - c.neg.elements foreach { case (s, d) => checkP(d, negLit) } - - checkP(c.litB, 1) - checkP(c.litU, posLit) - - checkP(c.litC, Complex(posLit, negLit)) - - // peek(c.lutS) doesn't work -- can't peek elements of Vec[Lit] - // expect auto rounds SInts - c.lutSSeq.zipWithIndex foreach { case (x, i) => checkP(x, lutVals(i)) } - c.lutGenSeq.zipWithIndex foreach { case (x, i) => checkP(x, lutVals(i)) } - - c.lutVals.zipWithIndex foreach { case (x, i) => { - poke(c.io.i.short.u, i) - checkP(c.io.o.short.gen, x) - - // How to change expect tolerance (for Lits; SInts should match exactly) - // expect automatically rounds when data is SInt (whereas expect doesn't) - fixTolLSBs.withValue(0) { - checkP(c.io.o.short.s, x) - } - - }} - - peek(c.lutGenSeq(0)) - peek(c.lutSSeq(0)) -} - -class FailLitTester[R <: Data:Real](c: SimpleLitModule[R]) extends DspTester(c) { - - val posLit = c.posLit - val negLit = c.negLit - val lutVals = c.lutVals - - c.pos.elements foreach { case (s, d) => { - d match { - case f: FixedPoint => expect(f, posLit) - case _ => } } } - - c.neg.elements foreach { case (s, d) => { - d match { - case f: FixedPoint => expect(f, negLit) - case _ => } } } - - expect(c.litC, Complex(posLit, negLit)) - - c.lutGenSeq.zipWithIndex foreach { case (x, i) => { - expect(x, lutVals(i)) }} - - c.lutVals.zipWithIndex foreach { case (x, i) => { - poke(c.io.i.short.u, i) - expect(c.io.o.short.gen, x) - }} - -} - -object TestSetup { - val p = TestParams() - - val testerOptionsGlobal = TesterOptions( - isVerbose = false, - displayBase = 16, - backendName = "verilator", - isGenVerilog = true) - - val optionsPass = new DspTesterOptionsManager { - dspTesterOptions = DspTesterOptions( - fixTolLSBs = 1, - genVerilogTb = false, - isVerbose = false) - testerOptions = testerOptionsGlobal - } - - val optionsFail = new DspTesterOptionsManager { - dspTesterOptions = optionsPass.dspTesterOptions.copy(fixTolLSBs = 0) - testerOptions = testerOptionsGlobal - } - - val optionsPassTB = new DspTesterOptionsManager { - dspTesterOptions = optionsPass.dspTesterOptions.copy(genVerilogTb = true) - testerOptions = testerOptionsGlobal - } - -} - -class SimpleTBSpec extends AnyFlatSpec with Matchers { - - val p = TestSetup.p - val optionsPass = TestSetup.optionsPass - val optionsPassTB = TestSetup.optionsPassTB - val optionsFail = TestSetup.optionsFail - - // Note: Verilator simulation is silly. Concurrent testing gets confused when things are in the same directory. - - behavior of "simple module lits" - - ignore should "properly read lits with gen = sint (reals rounded) and expect tolerance set to 1 bit" in { - val opt = new DspTesterOptionsManager { - dspTesterOptions = optionsPass.dspTesterOptions - testerOptions = optionsPass.testerOptions -// commonOptions = optionsPass.commonOptions.copy(targetDirName = "test_run_dir/lit_sint") - } - dsptools.Driver.execute(() => new SimpleLitModule(p.genShortS, p.genLongS, includeR = true, p), opt) { c => - new PassLitTester(c) - } should be (true) - } - - ignore should "properly read lits with gen = fixed and expect tolerance set to 1 bit " + - "(even with finite fractional bits)" in { - val opt = new DspTesterOptionsManager { - dspTesterOptions = optionsPass.dspTesterOptions - testerOptions = optionsPass.testerOptions -// commonOptions = optionsPass.commonOptions.copy(targetDirName = "test_run_dir/lit_fix") - } - dsptools.Driver.execute(() => new SimpleLitModule(p.genShortF, p.genLongF, includeR = true, p), opt) { c => - new PassLitTester(c) - } should be (true) - } - - ignore should "*fail* to read all lits with gen = fixed when expect tolerance is set to 0 bits " + - "(due to not having enough fractional bits to represent #s)" in { - val opt = new DspTesterOptionsManager { - dspTesterOptions = optionsFail.dspTesterOptions - testerOptions = optionsFail.testerOptions -// commonOptions = optionsFail.commonOptions.copy(targetDirName = "test_run_dir/lit_fix") - } - dsptools.Driver.execute(() => new SimpleLitModule(p.genShortF, p.genLongF, includeR = true, p), opt) { c => - new FailLitTester(c) - } should be (false) - } - - behavior of "simple module registered io" - - it should "properly poke/peek io delayed 1 cycle with gen = sint (reals rounded) " + - "and expect tolerance set to 1 bit" in { - val opt = new DspTesterOptionsManager { - dspTesterOptions = optionsPass.dspTesterOptions - testerOptions = optionsPass.testerOptions -// commonOptions = optionsPass.commonOptions.copy(targetDirName = "test_run_dir/io_sint") - } - dsptools.Driver.execute(() => new SimpleIOModule(p.genShortS, p.genLongS, includeR = true, p), opt) { c => - new PassIOTester(c) - } should be (true) - } - - it should "properly poke/peek io delayed 1 cycle with gen = fixed and expect tolerance set to 1 bit" in { - val opt = new DspTesterOptionsManager { - dspTesterOptions = optionsPass.dspTesterOptions - testerOptions = optionsPass.testerOptions -// commonOptions = optionsPass.commonOptions.copy(targetDirName = "test_run_dir/io_fix") - } - dsptools.Driver.execute(() => new SimpleIOModule(p.genShortF, p.genLongF, includeR = true, p), opt) { c => - new PassIOTester(c) - } should be (true) - } - - it should "properly poke/peek io delayed 1 cycle with gen = fixed + print TB (no reals)" in { - this.synchronized { - val opt = new DspTesterOptionsManager { - dspTesterOptions = optionsPassTB.dspTesterOptions - testerOptions = optionsPassTB.testerOptions - commonOptions = optionsPassTB.commonOptions.copy(targetDirName = "test_run_dir/io_fix_tb") - } - var tbFileLoc: String = "" - dsptools.Driver.execute(() => new SimpleIOModule(p.genShortF, p.genLongF, includeR = false, p), - opt) { c => { - val tester = new PassIOTester(c) - tbFileLoc = tester.tbFileName - tester - } } should be (true) - println(s"The file is here: ${tbFileLoc}") - val tbTxt = scala.io.Source.fromFile(tbFileLoc).getLines - // This is a lot easier in Scala 2.12.x - val resourceGoldenModel = getClass.getResourceAsStream("/TBGoldenModel.v") - val TbGoldenModelTxt = scala.io.Source.fromInputStream(resourceGoldenModel).getLines - TbGoldenModelTxt.zip(tbTxt) foreach { case (expected, in) => - expected should be (in) - } - } - } - -} diff --git a/src/test/scala/dsptools/numbers/AbsSpec.scala b/src/test/scala/dsptools/numbers/AbsSpec.scala deleted file mode 100644 index acfa8ec4..00000000 --- a/src/test/scala/dsptools/numbers/AbsSpec.scala +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import chisel3.experimental._ -import dsptools.{DspContext, DspTester, Grow, Wrap} - - - -class AbsSpec extends AnyFreeSpec with Matchers { - "absolute value should work for all types" - { - "abs should be obvious when not at extreme negative" - { - "but returns a negative number for extreme value at max negative for SInt and FixedPoint" - { - "with interpreter" in { - dsptools.Driver.execute(() => new DoesAbs(UInt(4.W), SInt(4.W), FixedPoint(5.W, 2.BP))) { c => - new DoesAbsTester(c) - } should be(true) - } - "and with verilator" in { - dsptools.Driver.execute(() => new DoesAbs(UInt(4.W), SInt(4.W), FixedPoint(5.W, 2.BP)), - Array("--backend-name", "verilator")) { c => - new DoesAbsTester(c) - } should be(true) - } - } - } - } - -} - -class DoesAbsTester(c: DoesAbs[UInt, SInt, FixedPoint]) extends DspTester(c) { - for(i <- BigDecimal(0.0) to 15.0 by 1.0) { - poke(c.io.uIn, i) - expect(c.io.uAbsGrow, i) - expect(c.io.uAbsWrap, i) - step(1) - } - for(i <- BigDecimal(-7.0) to 7.0 by 1.0) { - poke(c.io.sIn, i) - expect(c.io.sAbsGrow, i.abs) - expect(c.io.sAbsWrap, i.abs) - step(1) - } - poke(c.io.sIn, -8.0) - expect(c.io.sAbsGrow, 8.0) - expect(c.io.sAbsWrap, -8.0) - - val increment = 0.25 - - for(i <- BigDecimal(-3.75) to 3.75 by increment) { - poke(c.io.fIn, i) - expect(c.io.fAbsGrow, i.abs) - expect(c.io.fAbsWrap, i.abs) - step(1) - } - poke(c.io.fIn, -4.0) - expect(c.io.fAbsGrow, 4.0) - expect(c.io.fAbsWrap, -4.0) -} - -class DoesAbs[TU <: Data: Signed : Ring, TS <: Data : Signed : Ring, TF <: Data : Signed : Ring] - (uGen: TU, sGen: TS, fGen: TF) - extends Module { - val io = IO(new Bundle { - val uIn = Input(uGen) - val sIn = Input(sGen) - val fIn = Input(fGen) - - val uAbsGrow = Output(uGen) - val uAbsWrap = Output(uGen) - - val sAbsGrow = Output(SInt(5.W)) - val sAbsWrap = Output(SInt(4.W)) - - val fAbsGrow = Output(FixedPoint(6.W, 2.BP)) - val fAbsWrap = Output(FixedPoint(5.W, 2.BP)) - }) - - io.uAbsGrow := DspContext.withOverflowType(Grow) { io.uIn.context_abs() } - io.uAbsWrap := DspContext.withOverflowType(Wrap) { io.uIn.context_abs() } - - io.sAbsGrow := DspContext.withOverflowType(Grow) { io.sIn.context_abs() } - io.sAbsWrap := DspContext.withOverflowType(Wrap) { io.sIn.context_abs() } - - io.fAbsGrow := DspContext.withOverflowType(Grow) { io.fIn.context_abs() } - io.fAbsWrap := DspContext.withOverflowType(Wrap) { io.fIn.context_abs() } -} diff --git a/src/test/scala/dsptools/numbers/BaseNSpec.scala b/src/test/scala/dsptools/numbers/BaseNSpec.scala deleted file mode 100644 index 5ba232f5..00000000 --- a/src/test/scala/dsptools/numbers/BaseNSpec.scala +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import dsptools.numbers.representations.BaseN - - - -class BaseNSpec extends AnyFlatSpec with Matchers { - behavior of "BaseN" - it should "properly convert a decimal into BaseN" in { - // n in decimal, rad = radix, res = expected representation in base rad - case class BaseNTest(n: Int, rad: Int, res: Seq[Int]) - - // Most significant digit first (matched against WolframAlpha) - val tests = Seq( - BaseNTest(27, 4, Seq(1, 2, 3)), - BaseNTest(17, 3, Seq(1, 2, 2)), - BaseNTest(37, 5, Seq(1, 2, 2)) - ) - tests foreach { case BaseNTest(n, rad, res) => - require(BaseN.toDigitSeqMSDFirst(n, rad) == res, s"Base $rad conversion should work!") - val paddedBaseN = BaseN.toDigitSeqMSDFirst(n, rad, 500) - require(paddedBaseN == (Seq.fill(paddedBaseN.length - res.length)(0) ++ res), - s"Padded base $rad conversion should work!") - } - } -} - diff --git a/src/test/scala/dsptools/numbers/BlackBoxFloat.scala b/src/test/scala/dsptools/numbers/BlackBoxFloat.scala deleted file mode 100644 index 4e55b5e4..00000000 --- a/src/test/scala/dsptools/numbers/BlackBoxFloat.scala +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import chisel3.iotesters.{ChiselFlatSpec, PeekPokeTester, TesterOptionsManager} -import chisel3.testers.BasicTester -import chisel3.util._ -import dsptools.DspTester - -//scalastyle:off magic.number regex - -class BlackBoxFloatTester extends BasicTester { - val (cnt, _) = Counter(true.B, 10) - val accum = RegInit(DspReal(0)) - - private val addOut = accum + DspReal(1.0) - private val mulOut = addOut * DspReal(2.0) - - accum := addOut - - printf("cnt: %x accum: %x add: %x mult: %x\n", - cnt, accum.toDoubleBits(), addOut.toDoubleBits(), mulOut.toDoubleBits()) - - when (cnt === 0.U) { - assert(addOut === DspReal(1)) - assert(mulOut === DspReal(2)) - } .elsewhen (cnt === 1.U) { - assert(addOut === DspReal(2)) - assert(mulOut === DspReal(4)) - } .elsewhen (cnt === 2.U) { - assert(addOut === DspReal(3)) - assert(mulOut === DspReal(6)) - } .elsewhen (cnt === 3.U) { - assert(addOut === DspReal(4)) - assert(mulOut === DspReal(8)) - } - - when (cnt >= 3.U) { - // for unknown reasons, stop needs to be invoked multiple times - stop() - } -} - -class BlackBoxFloatAdder extends Module { - val io = IO(new Bundle { - val a = Input(DspReal()) - val b = Input(DspReal()) - val c = Output(DspReal()) - val d = Output(DspReal()) - val e = Output(DspReal()) - }) - - io.c := io.a + io.b - io.d := io.a + io.a - io.e := io.b + io.b -} - -class BlackBoxFloatAdderTester(c: BlackBoxFloatAdder) extends DspTester(c) { - poke(c.io.a, 2.1) - poke(c.io.b, 3.0) - - expect(c.io.c, 5.1, "reals should add") - expect(c.io.d, 4.2, "reals should add") - expect(c.io.e, 6.0, "reals should add") -} - -object FloatOpCodes { - val Add = 0 - val Subtract = 1 - val Multiply = 2 - val Divide = 3 - val Ln = 4 - val Log10 = 5 - val Exp = 6 - val Sqrt = 7 - val Pow = 8 - val Floor = 9 - val Ceil = 10 - val Sin = 11 - val Cos = 12 - val Tan = 13 - val ASin = 14 - val ACos = 15 - val ATan = 16 - val ATan2 = 17 - val Hypot = 18 - val Sinh = 19 - val Cosh = 20 - val Tanh = 21 - val ASinh = 22 - val ACosh = 23 - val ATanh = 24 - val GreaterThan = 25 - val GreaterThanOrEqual = 26 - val LessThan = 27 - val LessThanOrEqual = 28 -} - -class FloatOps extends Module { - val io = IO(new Bundle { - val in1 = Input(DspReal()) - val in2 = Input(DspReal()) - val opsel = Input(UInt(64.W)) - val out = Output(DspReal()) - val boolOut = Output(Bool()) - }) - - io.boolOut := false.B - io.out := DspReal(0) -} - -class FloatOpsWithTrig extends FloatOps { - import FloatOpCodes._ - - switch (io.opsel) { - is(Add.U) { io.out := io.in1 + io.in2 } - is(Subtract.U) { io.out := io.in1 - io.in2 } - is(Multiply.U) { io.out := io.in1 * io.in2 } - is(Divide.U) { io.out := io.in1 / io.in2 } - is(Ln.U) { io.out := io.in1.ln() } - is(Log10.U) { io.out := io.in1.log10() } - is(Exp.U) { io.out := io.in1.exp() } - is(Sqrt.U) { io.out := io.in1.sqrt() } - is(Pow.U) { io.out := io.in1.pow(io.in2) } - is(FloatOpCodes.Floor.U) { io.out := io.in1.floor() } - is(Ceil.U) { io.out := io.in1.ceil() } - - is(GreaterThan.U) { io.boolOut := io.in1 > io.in2 } - is(GreaterThanOrEqual.U) { io.boolOut := io.in1 >= io.in2 } - - is(Sin.U) { io.out := io.in1.sin() } - is(Cos.U) { io.out := io.in1.cos() } - is(Tan.U) { io.out := io.in1.tan() } - is(ASin.U) { io.out := io.in1.asin() } - is(ACos.U) { io.out := io.in1.acos() } - is(ATan.U) { io.out := io.in1.atan() } - is(ATan2.U) { io.out := io.in1.atan2(io.in2) } - is(Hypot.U) { io.out := io.in1.hypot(io.in2) } - is(Sinh.U) { io.out := io.in1.sinh() } - is(Cosh.U) { io.out := io.in1.cosh() } - is(Tanh.U) { io.out := io.in1.tanh() } - is(ASinh.U) { io.out := io.in1.asinh() } - is(ACosh.U) { io.out := io.in1.acosh() } - is(ATanh.U) { io.out := io.in1.atanh() } - - } -} - -class FloatOpsWithoutTrig extends FloatOps { - import FloatOpCodes._ - switch (io.opsel) { - is(Add.U) { io.out := io.in1 + io.in2 } - is(Subtract.U) { io.out := io.in1 - io.in2 } - is(Multiply.U) { io.out := io.in1 * io.in2 } - is(Divide.U) { io.out := io.in1 / io.in2 } - is(Ln.U) { io.out := io.in1.ln() } - is(Log10.U) { io.out := io.in1.log10() } - is(Exp.U) { io.out := io.in1.exp() } - is(Sqrt.U) { io.out := io.in1.sqrt() } - is(Pow.U) { io.out := io.in1.pow(io.in2) } - is(FloatOpCodes.Floor.U) { io.out := io.in1.floor() } - is(Ceil.U) { io.out := io.in1.ceil() } - is(GreaterThan.U) { io.boolOut := io.in1 > io.in2 } - is(GreaterThanOrEqual.U) { io.boolOut := io.in1 >= io.in2 } - } -} - -class FloatOpTester[T <: FloatOps](c: T, testTrigFuncs: Boolean = true) extends DspTester(c) { - import FloatOpCodes._ - val a = 3.4 - val b = 7.1 - // scala doesn't have inverse hyperbolic functions, hardcode them - val asinh_a = 1.9378792776645006 - val acosh_a = 1.8945590126722978042798892652 - poke(c.io.in1, a) - poke(c.io.in2, b) - - poke(c.io.opsel, Add) - expect(c.io.out, a + b, "reals should add") - poke(c.io.opsel, Subtract) - expect(c.io.out, a - b, "reals should subtract") - poke(c.io.opsel, Multiply) - expect(c.io.out, a * b, "reals should multiply") - poke(c.io.opsel, Divide) - expect(c.io.out, a / b, "reals should divide") - poke(c.io.opsel, Ln) - expect(c.io.out, math.log(a), "log should work on reals") - poke(c.io.opsel, Log10) - expect(c.io.out, math.log10(a), "log10 should work on reals") - poke(c.io.opsel, Exp) - expect(c.io.out, math.exp(a), "exp should work on reals") - poke(c.io.opsel, Sqrt) - expect(c.io.out, math.sqrt(a), "sqrt should work on reals") - poke(c.io.opsel, Pow) - expect(c.io.out, math.pow(a, b), "reals should pow") - poke(c.io.opsel, FloatOpCodes.Floor) - expect(c.io.out, math.floor(a), "floor should work on reals") - poke(c.io.opsel, Ceil) - expect(c.io.out, math.ceil(a), "ceil should work on reals") - - if(testTrigFuncs) { - poke(c.io.opsel, Sin) - expect(c.io.out, math.sin(a), "sin should work on reals") - poke(c.io.opsel, Cos) - expect(c.io.out, math.cos(a), "cos should work on reals") - poke(c.io.opsel, Tan) - expect(c.io.out, math.tan(a), "tan should work on reals") - - val arcArg = 0.5 - poke(c.io.in1, arcArg) - poke(c.io.opsel, ASin) - expect(c.io.out, math.asin(arcArg), "asin should work on reals") - poke(c.io.opsel, ACos) - expect(c.io.out, math.acos(arcArg), "acos should work on reals") - - poke(c.io.in1, a) - poke(c.io.opsel, ATan) - expect(c.io.out, math.atan(a), "atan should work on reals") - poke(c.io.opsel, ATan2) - expect(c.io.out, math.atan2(a, b), "atan2 should work on reals") - poke(c.io.opsel, Hypot) - expect(c.io.out, math.hypot(a, b), "hypot should work on reals") - poke(c.io.opsel, Sinh) - expect(c.io.out, math.sinh(a), "sinh should work on reals") - poke(c.io.opsel, Cosh) - expect(c.io.out, math.cosh(a), "cosh should work on reals") - poke(c.io.opsel, Tanh) - expect(c.io.out, math.tanh(a), "tanh should work on reals") - poke(c.io.opsel, ASinh) - expect(c.io.out, asinh_a, "asinh should work on reals") - poke(c.io.opsel, ACosh) - expect(c.io.out, acosh_a, "acosh should work on reals") - poke(c.io.opsel, ATanh) - // not defined - // dspExpect(c.io.out, math.atanh(a), "atanh should work on reals") - } - - for { - x <- (BigDecimal(-1.0) to 1.0 by 1.0).map(_.toDouble) - y <- (BigDecimal(-1.0) to 1.0 by 1.0).map(_.toDouble) - } { - poke(c.io.in1, x) - poke(c.io.in2, y) - poke(c.io.opsel, GreaterThan) - expect(c.io.boolOut, x > y, s"$x > $y should be ${x > y}") - step(1) - } - -} - -class BlackBoxFloatSpec extends ChiselFlatSpec { - "A BlackBoxed FP block" should "work" in { - assertTesterPasses({ new BlackBoxFloatTester } - , Seq( - "/BBFAdd.v", - "/BBFMultiply.v", - "/BBFEquals.v" - ) - ) - } - - "basic addition" should "work with reals through black boxes" in { - val optionsManager = new TesterOptionsManager { - interpreterOptions = interpreterOptions.copy( - blackBoxFactories = interpreterOptions.blackBoxFactories :+ new DspRealFactory) -// testerOptions = testerOptions.copy(backendName = "verilator") - } - - dsptools.Driver.execute(() => new BlackBoxFloatAdder, optionsManager) { c => - new BlackBoxFloatAdderTester(c) - } should be(true) - } - - "float ops" should "work with interpreter" in { - val optionsManager = new TesterOptionsManager { - interpreterOptions = interpreterOptions.copy( - blackBoxFactories = interpreterOptions.blackBoxFactories :+ new DspRealFactory) - } - - dsptools.Driver.execute(() => new FloatOpsWithTrig, optionsManager) { c => - new FloatOpTester(c) - } should be(true) - } - - "float ops" should "work with verilator" in { - val optionsManager = new TesterOptionsManager { - testerOptions = testerOptions.copy(backendName = "verilator") - } - - dsptools.Driver.execute(() => new FloatOpsWithoutTrig, optionsManager) { c => - new FloatOpTester(c, testTrigFuncs = false) - } should be(true) - } - - "greater than" should "work with negatives" in { - val optionsManager = new TesterOptionsManager { - interpreterOptions = interpreterOptions.copy( - blackBoxFactories = interpreterOptions.blackBoxFactories :+ new DspRealFactory) - } - - dsptools.Driver.execute(() => new NegCircuit, optionsManager) { c => - new NegCircuitTester(c) - } should be(true) - } -} - -class NegCircuit extends Module { - val io = IO(new Bundle { - val in1 = Input(DspReal()) - val in2 = Input(DspReal()) - val out = Output(Bool()) - }) - io.out := io.in1 > io.in2 -} - -class NegCircuitTester(c: NegCircuit) extends DspTester(c) { - poke(c.io.in1, -1.0) - poke(c.io.in2, -2.0) - expect(c.io.out, true) -} diff --git a/src/test/scala/dsptools/numbers/DspComplexSpec.scala b/src/test/scala/dsptools/numbers/DspComplexSpec.scala deleted file mode 100644 index 7eb40b35..00000000 --- a/src/test/scala/dsptools/numbers/DspComplexSpec.scala +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package testing.dsptools.numbers - -import chisel3._ -import chisel3.iotesters.ChiselPropSpec -import chisel3.testers.BasicTester -import dsptools.numbers._ - -//scalastyle:off magic.number -class DspComplexExamples extends Module { - val io = IO(new Bundle { - val in = Input(DspComplex(SInt(5.W), SInt(5.W))) - val outJ = Output(DspComplex(SInt(5.W), SInt(5.W))) - val inByJ = Output(DspComplex(SInt(5.W), SInt(5.W))) - val inByJShortcut = Output(DspComplex(SInt(5.W), SInt(5.W))) - }) - - io.outJ := DspComplex.j[SInt] - io.inByJ := io.in * DspComplex.j[SInt] - io.inByJShortcut := io.in.mulj() -} - -class DspComplexExamplesTester extends BasicTester { - val dut = Module(new DspComplexExamples) - - dut.io.in.real := 7.S - dut.io.in.imag := (-4).S - - printf(s"inByJ.real: %d\n", dut.io.inByJ.real) - printf(s"inByJ.imag: %d\n", dut.io.inByJ.imag) - - printf(s"inByJShortcut.real: %d\n", dut.io.inByJShortcut.real) - printf(s"inByJShortcut.imag: %d\n", dut.io.inByJShortcut.imag) - - assert(dut.io.outJ.real === 0.S) - assert(dut.io.outJ.imag === 1.S) - - assert(dut.io.inByJ.real === 4.S) - assert(dut.io.inByJ.imag === 7.S) - - assert(dut.io.inByJShortcut.real === 4.S) - assert(dut.io.inByJShortcut.imag === 7.S) - - stop() -} - -class SIntTester extends BasicTester { - val x = 10.S - - val xcopy = Wire(x.cloneType) - xcopy := x - - assert( x === xcopy ) - - val y = DspComplex((-4).S, (-1).S) - - assert ( y.real === (-4).S) - assert (y.imag === (-1).S) - - stop() -} - -class DspComplexExamplesSpec extends ChiselPropSpec { - property("using j with complex numbers should work") { - assertTesterPasses { new DspComplexExamplesTester} - } - - property("assigning Wire(SInt) should work") { - assertTesterPasses { new SIntTester } - } -} diff --git a/src/test/scala/dsptools/numbers/FixedPointSpec.scala b/src/test/scala/dsptools/numbers/FixedPointSpec.scala deleted file mode 100644 index d65e2eb9..00000000 --- a/src/test/scala/dsptools/numbers/FixedPointSpec.scala +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -//scalastyle:off magic.number - -import chisel3._ -import chisel3.experimental._ -import chisel3.iotesters.ChiselPropSpec -import chisel3.testers.BasicTester -import dsptools.DspTester -import dsptools.numbers.implicits._ - - - -class FixedRing1(val width: Int, val binaryPoint: Int) extends Module { - val io = IO(new Bundle { - val in = Input(FixedPoint(width.W, binaryPoint.BP)) - val floor = Output(FixedPoint(width.W, binaryPoint.BP)) - val ceil = Output(FixedPoint(width.W, binaryPoint.BP)) - val isWhole = Output(Bool()) - val round = Output(FixedPoint(width.W, binaryPoint.BP)) - val real = Output(DspReal()) - }) - - io.floor := io.in.floor() - io.ceil := io.in.ceil() - io.isWhole := io.in.isWhole() - io.round := io.in.round() - io.real := DspReal(0) -} - -class FixedRing1Tester(c: FixedRing1) extends DspTester(c) { - val increment: Double = if(c.binaryPoint == 0) 1.0 else 1.0 / (1 << c.binaryPoint) - updatableDspVerbose.withValue(false) { - for(i <- (BigDecimal(-2.0) to 3.0 by increment).map(_.toDouble)) { - poke(c.io.in, i) - - expect(c.io.floor, breeze.numerics.floor(i), s"floor of $i should be ${breeze.numerics.floor(i)}") - expect(c.io.ceil, breeze.numerics.ceil(i), s"ceil of $i should be ${breeze.numerics.ceil(i)}") - expect(c.io.isWhole, breeze.numerics.floor(i) == i , s"isWhole of $i should be ${breeze.numerics.floor(i) == i}") - expect(c.io.round, breeze.numerics.round(i), s"round of $i should be ${breeze.numerics.round(i)}") - step(1) - } - } -} - -/** - * Shift the inValue right and left, statically and dynamically. - * @note shiftRight has a constraint that shift amount must be less than width of inValue - * @param width width of shift target - * @param binaryPoint the binary point of the shift target - * @param fixedShiftSize how much to shift the target - */ -class FixedPointShifter(val width: Int, val binaryPoint: Int, val fixedShiftSize: Int) extends Module { - val dynamicShifterWidth = 3 - - val io = IO(new Bundle { - val inValue = Input(FixedPoint(width.W, binaryPoint.BP)) - val dynamicShiftValue = Input(UInt(dynamicShifterWidth.W)) - val shiftRightResult: Option[FixedPoint] = if(fixedShiftSize < width) { - Some(Output(FixedPoint((width - fixedShiftSize).W, binaryPoint.BP))) - } - else { - None - } - val shiftLeftResult = Output(FixedPoint((width + fixedShiftSize).W, binaryPoint.BP)) - val dynamicShiftRightResult = Output(FixedPoint(width.W, binaryPoint.BP)) - val dynamicShiftLeftResult = Output(FixedPoint((width + (1 << dynamicShifterWidth) - 1).W, binaryPoint.BP)) - }) - - io.shiftLeftResult := io.inValue << fixedShiftSize - io.shiftRightResult.foreach { out => - out := io.inValue >> fixedShiftSize - } - io.dynamicShiftLeftResult := io.inValue << io.dynamicShiftValue - io.dynamicShiftRightResult := io.inValue >> io.dynamicShiftValue -} - -object FixedPointShifter extends App { - iotesters.Driver.executeFirrtlRepl(Array(), () => new FixedPointShifter(8, 4, 3)) -} - -class FixedPointShiftTester(c: FixedPointShifter) extends DspTester(c) { - val increment: Double = 1.0 / (1 << c.binaryPoint) - - def expectedValue(value: Double, left: Boolean, shift: Int): Double = { - val factor = 1 << c.binaryPoint - val x = value * factor - val y = x.toInt - val z = if(left) y << shift else y >> shift - val w = z.toDouble / factor - w - } - - def truncate(value: Double): Double = { - val factor = 1 << c.binaryPoint - val x = value * factor - val y = x.toInt.toDouble - val z = y / factor - z - } - updatableDspVerbose.withValue(false) { - - poke(c.io.dynamicShiftValue, 0) - - val (minSIntValue, maxSIntValue) = firrtl_interpreter.extremaOfSIntOfWidth(c.width) - - val minValue = minSIntValue.toDouble * increment - val maxValue = maxSIntValue.toDouble * increment - - for(value <- (BigDecimal(minValue) to maxValue by increment).map(_.toDouble)) { - poke(c.io.inValue, value) - expect(c.io.shiftLeftResult, expectedValue(value, left = true, c.fixedShiftSize), - s"shift left ${c.fixedShiftSize} of $value should be ${expectedValue(value, left = true, c.fixedShiftSize)}") - c.io.shiftRightResult.foreach { sro => - expect(sro, expectedValue(value, left = false, c.fixedShiftSize), - s"shift right ${c.fixedShiftSize} of $value should be ${expectedValue(value, left = false, c.fixedShiftSize)}") - } - - step(1) - - for(dynamicShiftValue <- 0 until c.width) { - poke(c.io.dynamicShiftValue, dynamicShiftValue) - step(1) - expect(c.io.dynamicShiftLeftResult, expectedValue(value, left = true, dynamicShiftValue), - s"dynamic shift left $dynamicShiftValue of $value should " + - s"be ${expectedValue(value, left = true, dynamicShiftValue)}") - expect(c.io.dynamicShiftRightResult, expectedValue(value, left = false, dynamicShiftValue), - s"dynamic shift right $dynamicShiftValue of $value should" + - s"be ${expectedValue(value, left = false, dynamicShiftValue)}") - } - } - - } -} - -class BrokenShifter(n: Int) extends Module { - val io = IO(new Bundle { - val i = Input(FixedPoint(8.W, 4.BP)) - val o = Output(FixedPoint(8.W, 4.BP)) - val si = Input(SInt(8.W)) - val so = Output(SInt(8.W)) - }) - io.o := io.i >> n - io.so := io.si >> n -} - -class BrokenShifterTester(c: BrokenShifter) extends DspTester(c) { - updatableDspVerbose.withValue(false) { - poke(c.io.i, 1.5) - peek(c.io.o) - poke(c.io.si, 6) - peek(c.io.so) - } -} - -class FixedPointSpec extends AnyFreeSpec with Matchers { - "FixedPoint numbers should work properly for the following mathematical type functions" - { -// for (backendName <- Seq("verilator")) { - for (backendName <- Seq("firrtl", "verilator")) { - s"The ring family run with the $backendName simulator" - { - for (binaryPoint <- 0 to 4 by 2) { - s"should work, with binaryPoint $binaryPoint" in { - dsptools.Driver.execute( - () => new FixedRing1(16, binaryPoint = binaryPoint), - Array( - "--backend-name", backendName, - "--target-dir", s"test_run_dir/fixed-point-ring-tests-$binaryPoint.BP" - ) - ) { c => - new FixedRing1Tester(c) - } should be(true) - } - } - } - - s"The shift family when run with the $backendName simulator" - { - val defaultWidth = 8 - for { - binaryPoint <- Set(0, 1, 1) ++ - (defaultWidth - 1 to defaultWidth + 1) ++ - (defaultWidth * 2 - 1 to defaultWidth * 2 + 1) - fixedShiftSize <- Set(0, 1, 2) ++ (defaultWidth - 1 to defaultWidth + 1) - } { - s"should work with binary point $binaryPoint, with shift $fixedShiftSize " in { - dsptools.Driver.execute( - () => new FixedPointShifter(width = 8, binaryPoint = binaryPoint, fixedShiftSize = fixedShiftSize), - Array( - "--backend-name", backendName, - "--target-dir", s"test_run_dir/shift-test-$fixedShiftSize-$binaryPoint.BP" - ) - ) { c => - new FixedPointShiftTester(c) - } should be(true) - } - } - } - - //TODO: This error does not seem to be caught at this time. Firrtl issue #450 - s"shifting by too big a number causes error with $backendName" ignore { - for(shiftSize <- 8 to 10) { - dsptools.Driver.execute( - () => new BrokenShifter(n = shiftSize), - Array( - "--backend-name", backendName, - "--target-dir", s"test_run_dir/broken-shifter-$shiftSize" - ) - ) { c => - new BrokenShifterTester(c) - } should be(true) - } - } - - } - } -} - -class FixedPointChiselSpec extends ChiselPropSpec { - property("asReal shold work") { - assertTesterPasses { new BasicTester { - val x = FixedPoint.fromDouble(13.5, 16.W, 4.BP) - - val y = x.asReal - - chisel3.assert(y === DspReal(13.5)) - - stop() - }} - } -} diff --git a/src/test/scala/dsptools/numbers/FixedPrecisionChangerSpec.scala b/src/test/scala/dsptools/numbers/FixedPrecisionChangerSpec.scala deleted file mode 100644 index 7e226799..00000000 --- a/src/test/scala/dsptools/numbers/FixedPrecisionChangerSpec.scala +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import chisel3.experimental.FixedPoint -import dsptools.DspTester - - - -//scalastyle:off magic.number - -class FixedPrecisionChanger(inWidth: Int, inBinaryPoint: Int, outWidth: Int, outBinaryPoint: Int) extends Module { - val io = IO(new Bundle { - val in = Input(FixedPoint(inWidth.W, inBinaryPoint.BP)) - val out = Output(FixedPoint(outWidth.W, outBinaryPoint.BP)) - }) - - val reg = Reg(FixedPoint()) - reg := io.in - io.out := reg -} - -class FixedPointTruncatorTester(c: FixedPrecisionChanger, inValue: Double, outValue: Double) extends DspTester(c) { - poke(c.io.in, inValue) - step(1) - expect(c.io.out, outValue, s"got ${peek(c.io.out)} should have $outValue") -} - -class RemoveMantissa(inWidth: Int, inBinaryPoint: Int, outWidth: Int, outBinaryPoint: Int) extends Module { - val io = IO(new Bundle { - val in = Input(FixedPoint(inWidth.W, inBinaryPoint.BP)) - val out = Output(FixedPoint(outWidth.W, 0.BP)) - }) - - val reg = Reg(FixedPoint()) - reg := io.in - io.out := reg//.setBinaryPoint(0) -} - -class RemoveMantissaTester(c: RemoveMantissa, inValue: Double, outValue: Double) extends DspTester(c) { - poke(c.io.in, inValue) - step(1) - expect(c.io.out, outValue, s"got ${peek(c.io.out)} should have $outValue") -} - -class FixedPrecisionChangerSpec extends AnyFreeSpec with Matchers { - "assignment of numbers with differing binary points seems to work as I would expect" - { - "here we assign to a F8.1 from a F8.3" in { - dsptools.Driver.execute(() => new FixedPrecisionChanger(8, 3, 8, 1)) { c => - new FixedPointTruncatorTester(c, 6.875, 6.5) - } should be (true) - } - "here we assign to a F8.1 from a F8.1" - { - "conversion to fixed point with less precision than poked value rounds up to 7, IS THIS RIGHT?" in { - dsptools.Driver.execute(() => new FixedPrecisionChanger(8, 1, 8, 1)) { c => - new FixedPointTruncatorTester(c, 6.875, 7.0) - } should be(true) - } - } - "here we assign to a F10.6 from a F10.3" in { - dsptools.Driver.execute(() => new FixedPrecisionChanger(10, 3, 10, 6)) { c => - new FixedPointTruncatorTester(c, 6.875, 6.875) - } should be (true) - } - "let's try 1/3 just for fun with a big mantissa" - { - "oops, this works because I built in a fudge factor for double comparison, how should this be done" in { - dsptools.Driver.execute(() => new FixedPrecisionChanger(64, 58, 64, 16)) { c => - new FixedPointTruncatorTester(c, 1.0 / 3.0, 0.3333282470703125) - } should be(true) - } - } - } - - "removing mantissa can be done" - { - "by using the setBinaryPoint Method" in { - dsptools.Driver.execute(() => new RemoveMantissa(12, 4, 8, 0)) { c => - new RemoveMantissaTester(c, 3.75, 3.0) - } should be(true) - } - } -} diff --git a/src/test/scala/dsptools/numbers/LnSpec.scala b/src/test/scala/dsptools/numbers/LnSpec.scala deleted file mode 100644 index 8e1cb0ad..00000000 --- a/src/test/scala/dsptools/numbers/LnSpec.scala +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import chisel3.util._ -import chisel3.testers.BasicTester -import chisel3.iotesters.{ChiselFlatSpec, PeekPokeTester, TesterOptionsManager} -import dsptools.{DspTester, ReplOptionsManager} - - - -class LnModule extends Module { - val io = IO(new Bundle { - val num = Input(DspReal()) - val ln = Output(DspReal()) - }) - - io.ln := io.num.ln() -} - -class LnTester(c: LnModule) extends DspTester(c) { - poke(c.io.num,11.0) - private val x = peek(c.io.ln) - println(s"poked 1.0 got $x expected ${math.log(11.0)}") - -} -class LnSpec extends AnyFreeSpec { - "ln should work" in { - dsptools.Driver.execute(() => new LnModule) { c => - new LnTester(c) - } - } -} - -object LnTester extends App { - val manager = new ReplOptionsManager - if(manager.parse(args)) { - dsptools.Driver.executeFirrtlRepl(() => new LnModule, manager) - } -} diff --git a/src/test/scala/dsptools/numbers/NumbersSpec.scala b/src/test/scala/dsptools/numbers/NumbersSpec.scala deleted file mode 100644 index 82c6ac64..00000000 --- a/src/test/scala/dsptools/numbers/NumbersSpec.scala +++ /dev/null @@ -1,493 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import dsptools._ -import chisel3.experimental.FixedPoint -import dsptools.numbers.implicits._ - - - -/** - * This will attempt to follow the dsptools.numbers.README.md file as close as possible. - */ -//scalastyle:off magic.number -class NumbersSpec extends AnyFreeSpec with Matchers { - def f(w: Int, b: Int): FixedPoint = FixedPoint(w.W, b.BP) - def u(w: Int): UInt = UInt(w.W) - def s(w: Int): SInt = SInt(w.W) - - "dsptools provides extensive tools for implementing well behaved mathematical operations" - { - "the behavior of operators and methods can be controlled with the DspContext object" - { - "overflow type controls how a * b, a.trimBinary(n) and a.div2(n) should round results" - { - "Overflow type tests for UInt" in { - dsptools.Driver.execute( - () => new OverflowTypeCircuit(u(4), u(5), u(5)), - Array("--backend-name", "firrtl") - ) { c => - new OverflowTypeCircuitTester(c, - // in1, in2, addWrap, addGrow, subWrap, subGrow - (15, 1, 0, 16, 14, 0), - (14, 2, 0, 16, 12, 0), - (1, 2, 3, 3, 15, 0) - ) - } should be(true) - dsptools.Driver.execute( - () => new OverflowTypeCircuit(u(4), u(5), u(5)), - Array("--backend-name", "verilator") - ) { c => - new OverflowTypeCircuitTester(c, - // in1, in2, addWrap, addGrow, subWrap, subGrow - (15, 1, 0, 16, 14, 0), - (14, 2, 0, 16, 12, 0), - (1, 2, 3, 3, 15, 0) - ) - } should be(true) - } - "UInt subtract with overflow type Grow not supported" ignore { - val expectedMessage = "OverflowType Grow is not supported for UInt subtraction" - val exception = intercept[Exception] { - dsptools.Driver.execute(() => new BadUIntSubtractWithGrow2(u(4))) { c => - new NumbersEmptyTester(c) - } - } - exception match { - case e: DspException => e.getMessage should be(expectedMessage) - case e: Exception => exception.getCause should be(new DspException(expectedMessage)) - } - } - "UInt subtract with overflow type Grow not supported cannot be detected without evidence that io is ring" in { - dsptools.Driver.execute(() => new ShouldBeBadUIntSubtractWithGrow) { c => - new NumbersEmptyTester(c) - } should be(true) - } - "Overflow type tests for SInt" in { - dsptools.Driver.execute( - () => new OverflowTypeCircuit(s(4), s(5), s(5)), - Array("--backend-name", "firrtl") - ) { c => - new OverflowTypeCircuitTester(c, - // in1, in2, addWrap, addGrow, subWrap, subGrow - (7, 2, -7, 9, 5, 5), - (-8, 2, -6, -6, 6, -10), - (-8, -2, 6, -10, -6, -6) - ) - - } should be(true) - dsptools.Driver.execute( - () => new OverflowTypeCircuit(s(4), s(5), s(5)), - Array("--backend-name", "verilator") - ) { c => - new OverflowTypeCircuitTester(c, - // in1, in2, addWrap, addGrow, subWrap, subGrow - (7, 2, -7, 9, 5, 5), - (-8, 2, -6, -6, 6, -10), - (-8, -2, 6, -10, -6, -6) - ) - - } should be(true) - } - "Overflow type tests for FixedPoint" in { - dsptools.Driver.execute( - () => new OverflowTypeCircuit(f(4, 2), f(5, 2), f(8, 3)), - Array("--backend-name", "firrtl") - ) { c => - new OverflowTypeCircuitTester(c, - // in1, in2, addWrap, addGrow, subWrap, subGrow - (1.75, 0.5, -1.75, 2.25, 1.25, 1.25), - (-1.75, 0.5, -1.25, -1.25, 1.75, -2.25), - (-1.75, -0.5, 1.75, -2.25, -1.25, -1.25) - ) - - } should be(true) - dsptools.Driver.execute( - () => new OverflowTypeCircuit(f(4, 2), f(5, 2), f(8, 3)), - Array("--backend-name", "verilator") - ) { c => - new OverflowTypeCircuitTester(c, - // in1, in2, addWrap, addGrow, subWrap, subGrow - (1.75, 0.5, -1.75, 2.25, 1.25, 1.25), - (-1.75, 0.5, -1.25, -1.25, 1.75, -2.25), - (-1.75, -0.5, 1.75, -2.25, -1.25, -1.25) - ) - - } should be(true) - } - } - "trim type controls how a * b, a.trimBinary(n) and a.div2(n) should round results" - { - "Trim type tests for multiplication" in { - dsptools.Driver.execute( - () => new TrimTypeMultiplyCircuit(f(6, 2), f(8, 4), f(12, 5)), - Array("--backend-name", "firrtl") - ) { c => - new TrimTypeMultiplyCircuitTester(c, - // a, b, mulF, mulC, mulRTZ, mulRTI, mulRHD, mulRHUp, mulRHTZ, mulRHTI, mulRHTE, mulRHTO, mulNoTrim - (1.5, 1.25, 1.75, 2.0, 1.75, 2.0, 1.75, 2.0, 1.75, 2.0, 2.0, 1.75, 1.875), - (1.25, 1.25, 1.5, 1.75, 1.5, 1.75, 1.5, 1.5, 1.5, 1.5, 1.5, 1.5, 1.5625), - (0.75, 1.5, 1.0, 1.25, 1.0, 1.25, 1.0, 1.25, 1.0, 1.25, 1.0, 1.25, 1.125), - (1.25, 0.75, 0.75, 1.0, 0.75, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 0.9375), - (-1.5, 1.25, -2.0, -1.75, -1.75, -2.0, -2.0, -1.75, -1.75, -2.0, -2.0, -1.75, -1.875), - (-1.25, 1.25, -1.75, -1.5, -1.5, -1.75, -1.5, -1.5, -1.5, -1.5, -1.5, -1.5, -1.5625), - (-0.75, 1.5, -1.25, -1.0, -1.0, -1.25, -1.25, -1.0, -1.0, -1.25, -1.0, -1.25, -1.125), - (-1.25, 0.75, -1.0, -0.75, -0.75, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -0.9375) - ) - } should be(true) - } - "Trim type tests for division" in { - dsptools.Driver.execute( - () => new TrimTypeDiv2Circuit(f(6, 2), f(8, 4), f(12, 5)), - Array("--backend-name", "firrtl") - ) { c => - new TrimTypeDiv2CircuitTester(c, - // a, divF, divC, divRTZ, divRTI, divRHD, divRHUp, divRHTZ, divRHTI, divRHTE, divRHTO, divNoTrim - (1.5, 0.25, 0.5, 0.25, 0.5, 0.25, 0.5, 0.25, 0.5, 0.5, 0.25, 0.375), - (1.25, 0.25, 0.5, 0.25, 0.5, 0.25, 0.25, 0.25, 0.25, 0.25, 0.25, 0.3125), - (0.75, 0.0, 0.25, 0.0, 0.25, 0.25, 0.25, 0.25, 0.25, 0.25, 0.25, 0.1875), - (0.5, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.125), - (-1.5, -0.5, -0.25, -0.25, -0.5, -0.5, -0.25, -0.25, -0.5, -0.5, -0.25, -0.375), - (-1.25, -0.5, -0.25, -0.25, -0.5, -0.25, -0.25, -0.25, -0.25, -0.25, -0.25, -0.3125), - (-0.75, -0.25, -0.0, -0.0, -0.25, -0.25, -0.25, -0.25, -0.25, -0.25, -0.25, -0.1875), - (-0.5, -0.25, -0.0, -0.0, -0.25, -0.25, -0.0, -0.0, -0.25, -0.0, -0.25, -0.125) - ) - } should be(true) - } - } - } - "Test for BinaryRepresentation section of Numbers Spec" in { - def f(w: Int, b: Int): FixedPoint = FixedPoint(w.W, b.BP) - dsptools.Driver.execute( - () => new BinaryRepr(u(8), s(8), f(10, 2)), - Array("--backend-name", "verilator") - ) { c => - new BinaryReprTester(c) - } should be(true) - } - } -} - -class TrimTypeMultiplyCircuit[T <: Data : Ring](gen1: T, gen2: T, gen3: T) extends Module{ - val io = IO(new Bundle { - val a = Input(gen1) - val b = Input(gen1) - val multiplyFloor = Output(gen2) - val multiplyCeiling = Output(gen2) - val multiplyRoundTowardsZero = Output(gen2) - val multiplyRoundTowardsInfinity = Output(gen2) - val multiplyRoundHalfDown = Output(gen2) - val multiplyRoundHalfUp = Output(gen2) - val multiplyRoundHalfTowardsZero = Output(gen2) - val multiplyRound = Output(gen2) - val multiplyConvergent = Output(gen2) - val multiplyRoundHalfToOdd = Output(gen2) - val multiplyNoTrim = Output(gen3) - }) - - DspContext.withBinaryPointGrowth(0){ - val regMultiplyFloor = RegNext(DspContext.withTrimType(Floor) { - io.a context_* io.b - }) - val regMultiplyCeiling = RegNext(DspContext.withTrimType(Ceiling) { - io.a context_* io.b - }) - val regMultiplyRoundTowardsZero = RegNext(DspContext.withTrimType(RoundTowardsZero) { - io.a context_* io.b - }) - val regMultiplyRoundTowardsInfinity = RegNext(DspContext.withTrimType(RoundTowardsInfinity) { - io.a context_* io.b - }) - val regMultiplyRoundHalfDown = RegNext(DspContext.withTrimType(RoundHalfDown) { - io.a context_* io.b - }) - val regMultiplyRoundHalfUp = RegNext(DspContext.withTrimType(RoundHalfUp) { - io.a context_* io.b - }) - val regMultiplyRoundHalfTowardsZero = RegNext(DspContext.withTrimType(RoundHalfTowardsZero) { - io.a context_* io.b - }) - val regMultiplyRound = RegNext(DspContext.withTrimType(Round) { - io.a context_* io.b - }) - val regMultiplyConvergent = RegNext(DspContext.withTrimType(Convergent) { - io.a context_* io.b - }) - val regMultiplyRoundHalfToOdd = RegNext(DspContext.withTrimType(RoundHalfToOdd) { - io.a context_* io.b - }) - val regMultiplyNoTrim = RegNext(DspContext.withTrimType(NoTrim) { - io.a context_* io.b - }) - - io.multiplyFloor := regMultiplyFloor - io.multiplyCeiling := regMultiplyCeiling - io.multiplyRoundTowardsZero := regMultiplyRoundTowardsZero - io.multiplyRoundTowardsInfinity := regMultiplyRoundTowardsInfinity - io.multiplyRoundHalfDown := regMultiplyRoundHalfDown - io.multiplyRoundHalfUp := regMultiplyRoundHalfUp - io.multiplyRoundHalfTowardsZero := regMultiplyRoundHalfTowardsZero - io.multiplyRound := regMultiplyRound - io.multiplyConvergent := regMultiplyConvergent - io.multiplyRoundHalfToOdd := regMultiplyRoundHalfToOdd - io.multiplyNoTrim := regMultiplyNoTrim - } -} - -class TrimTypeDiv2Circuit[T <: Data : Ring : BinaryRepresentation](gen1: T, gen2: T, gen3: T) extends Module{ - val io = IO(new Bundle { - val a = Input(gen1) - val div2Floor = Output(gen2) - val div2Ceiling = Output(gen2) - val div2RoundTowardsZero = Output(gen2) - val div2RoundTowardsInfinity = Output(gen2) - val div2RoundHalfDown = Output(gen2) - val div2RoundHalfUp = Output(gen2) - val div2RoundHalfTowardsZero = Output(gen2) - val div2Round = Output(gen2) - val div2Convergent = Output(gen2) - val div2RoundHalfToOdd = Output(gen2) - val div2NoTrim = Output(gen3) - }) - - val d = 2 - DspContext.withBinaryPointGrowth(0){ - val regDiv2Floor = RegNext(DspContext.withTrimType(RoundDown) { - io.a.div2(d) - }) - val regDiv2Ceiling = RegNext(DspContext.withTrimType(RoundUp) { - io.a.div2(d) - }) - val regDiv2RoundTowardsZero = RegNext(DspContext.withTrimType(RoundTowardsZero) { - io.a.div2(d) - }) - val regDiv2RoundTowardsInfinity = RegNext(DspContext.withTrimType(RoundTowardsInfinity) { - io.a.div2(d) - }) - val regDiv2RoundHalfDown = RegNext(DspContext.withTrimType(RoundHalfDown) { - io.a.div2(d) - }) - val regDiv2RoundHalfUp = RegNext(DspContext.withTrimType(RoundHalfUp) { - io.a.div2(d) - }) - val regDiv2RoundHalfTowardsZero = RegNext(DspContext.withTrimType(RoundHalfTowardsZero) { - io.a.div2(d) - }) - val regDiv2Round = RegNext(DspContext.withTrimType(RoundHalfTowardsInfinity) { - io.a.div2(d) - }) - val regDiv2Convergent = RegNext(DspContext.withTrimType(RoundHalfToEven) { - io.a.div2(d) - }) - val regDiv2RoundHalfToOdd = RegNext(DspContext.withTrimType(RoundHalfToOdd) { - io.a.div2(d) - }) - val regDiv2NoTrim = RegNext(DspContext.withTrimType(NoTrim) { - io.a.div2(d) - }) - - io.div2Floor := regDiv2Floor - io.div2Ceiling := regDiv2Ceiling - io.div2RoundTowardsZero := regDiv2RoundTowardsZero - io.div2RoundTowardsInfinity := regDiv2RoundTowardsInfinity - io.div2RoundHalfDown := regDiv2RoundHalfDown - io.div2RoundHalfTowardsZero := regDiv2RoundHalfTowardsZero - io.div2Round := regDiv2Round - io.div2Convergent := regDiv2Convergent - io.div2RoundHalfUp := regDiv2RoundHalfUp - io.div2RoundHalfToOdd := regDiv2RoundHalfToOdd - io.div2NoTrim := regDiv2NoTrim - } -} - -class TrimTypeMultiplyCircuitTester[T <: Data : Ring] -( - c: TrimTypeMultiplyCircuit[T], - testVectors: (Double, Double, Double, Double, Double, Double, Double, Double, Double, Double, Double, Double, Double)* -) extends DspTester(c) { - for((a, b, m1, m2, m3, m4, m5, m6, m7, m8, m9, m10, m11) <- testVectors) { - poke(c.io.a, a) - poke(c.io.b, b) - - step(1) - - expect(c.io.multiplyFloor, m1) - expect(c.io.multiplyCeiling, m2) - expect(c.io.multiplyRoundTowardsZero, m3) - expect(c.io.multiplyRoundTowardsInfinity, m4) - expect(c.io.multiplyRoundHalfDown, m5) - expect(c.io.multiplyRoundHalfUp, m6) - expect(c.io.multiplyRoundHalfTowardsZero, m7) - expect(c.io.multiplyRound, m8) - expect(c.io.multiplyConvergent, m9) - expect(c.io.multiplyRoundHalfToOdd, m10) - expect(c.io.multiplyNoTrim, m11) - } -} - -class TrimTypeDiv2CircuitTester[T <: Data : Ring : BinaryRepresentation] -( - c: TrimTypeDiv2Circuit[T], - testVectors: (Double, Double, Double, Double, Double, Double, Double, Double, Double, Double, Double, Double)* -) extends DspTester(c) { - for((a, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11) <- testVectors) { - poke(c.io.a, a) - - step(1) - - expect(c.io.div2Floor, d1) - expect(c.io.div2Ceiling, d2) - expect(c.io.div2RoundTowardsZero, d3) - expect(c.io.div2RoundTowardsInfinity, d4) - expect(c.io.div2RoundHalfDown, d5) - expect(c.io.div2RoundHalfUp, d6) - expect(c.io.div2RoundHalfTowardsZero, d7) - expect(c.io.div2Round, d8) - expect(c.io.div2Convergent, d9) - expect(c.io.div2RoundHalfToOdd, d10) - expect(c.io.div2NoTrim, d11) - } -} - -class OverflowTypeCircuitTester[T <: Data : Ring, U <: Data : Ring] -( - c: OverflowTypeCircuit[T, U], - testVectors: (Double, Double, Double, Double, Double, Double)* -) extends DspTester(c) { - for((a, b, e1, e2, e3, e4) <- testVectors) { - poke(c.io.a, a) - poke(c.io.b, b) - - step(1) - - expect(c.io.addWrap, e1) - expect(c.io.addGrow, e2) - expect(c.io.subWrap, e3) - expect(c.io.subGrow, e4) - } -} - -class OverflowTypeCircuit[T <: Data : Ring, U <: Data : Ring] -(gen1: T, gen2: T, gen3: U) extends Module { - val io = IO(new Bundle { - val a = Input(gen1) - val b = Input(gen1) - val addWrap = Output(gen2) - val addGrow = Output(gen2) - val subWrap = Output(gen3) - val subGrow = Output(gen3) - }) - - val regAddWrap = RegNext(DspContext.withOverflowType(Wrap) { io.a context_+ io.b }) - val regAddGrow = RegNext(DspContext.withOverflowType(Grow) { io.a context_+ io.b }) - - val regSubWrap = RegNext(DspContext.withOverflowType(Wrap) { io.a context_- io.b }) - val regSubGrow = RegNext(if (io.a.isInstanceOf[UInt]) 0.U else DspContext.withOverflowType(Grow) { io.a context_- io.b }) -// val regSubGrow = RegNext(DspContext.withOverflowType(Grow) { io.a context_- io.b }) - - io.addWrap := regAddWrap - io.addGrow := regAddGrow - io.subWrap := regSubWrap - io.subGrow := regSubGrow -} - -class NumbersEmptyTester[T <: Module](c: T) extends DspTester(c) - -class ShouldBeBadUIntSubtractWithGrow extends Module { - val io = IO(new Bundle { - val a = Input(UInt(4.W)) - val b = Input(UInt(4.W)) - val o = Output(UInt(4.W)) - }) - val r = RegNext(DspContext.withOverflowType(Grow) { io.a - io.b }) - io.o := r -} - -class BadUIntSubtractWithGrow2[T <: Data : Ring](gen: T) extends Module { - val io = IO(new Bundle { - val a = Input(gen) - val b = Input(gen) - val o = Output(gen) - }) - val r = RegNext(DspContext.withOverflowType(Grow) { io.a context_- io.b }) - io.o := r -} - -class BinaryReprTester(c: BinaryRepr[UInt, SInt, FixedPoint]) extends DspTester(c) { - poke(c.io.uIn, 0) - expect(c.io.uOut, 0.0) - - poke(c.io.sIn, 0) - expect(c.io.sOut, 0.0) - - poke(c.io.fIn, 0.0) - expect(c.io.fOut, 0.0) - - step(1) - - poke(c.io.sIn, 1) - expect(c.io.sOut, 0.0) - - poke(c.io.fIn, 1.0) - expect(c.io.fOut, 0.0) - - step(1) - - poke(c.io.sIn, -1) - expect(c.io.sOut, 1.0) - - poke(c.io.fIn, -1.0) - expect(c.io.fOut, 1.0) - - step(1) - - poke(c.io.uIn, 3) - expect(c.io.uDiv2, 0.0) - - poke(c.io.sIn, 3) - expect(c.io.sDiv2, 0.0) - - poke(c.io.fIn, 3.5) - expect(c.io.fOut, 0.0) - - step(1) - poke(c.io.uIn, 48) - expect(c.io.uDiv2, 12.0) - - poke(c.io.sIn, 32) - expect(c.io.sDiv2,8.0) - - poke(c.io.fIn, 14.0) - expect(c.io.fDiv2, 3.5) -} - -class BinaryRepr[TU <: Data : RealBits, TS <: Data : RealBits, TF <: Data : RealBits] -(uGen: TU, sGen: TS, fGen: TF) - extends Module { - val io = IO(new Bundle { - val uIn = Input(uGen) - val sIn = Input(sGen) - val fIn = Input(fGen) - val uOut = Output(UInt(1.W)) - val sOut = Output(UInt(1.W)) - val fOut = Output(UInt(1.W)) - - val uDiv2 = Output(uGen) - val sDiv2 = Output(sGen) - val fDiv2 = Output(fGen) - - val uMul2 = Output(UInt((uGen.getWidth * 2).W)) - val sMul2 = Output(SInt((sGen.getWidth * 2).W)) - val fMul2 = Output(FixedPoint(20.W, 2.BP)) - }) - - io.uOut := io.uIn.signBit() - io.sOut := io.sIn.signBit() - io.fOut := io.fIn.signBit() - - io.uDiv2 := io.uIn.div2(2) - io.sDiv2 := io.sIn.div2(2) - io.fDiv2 := io.fIn.div2(2) - - io.uMul2 := io.uIn.mul2(2) - io.sMul2 := io.sIn.mul2(2) - io.fMul2 := io.fIn.mul2(2) -} diff --git a/src/test/scala/dsptools/numbers/OverflowSpec.scala b/src/test/scala/dsptools/numbers/OverflowSpec.scala deleted file mode 100644 index 1cc6f296..00000000 --- a/src/test/scala/dsptools/numbers/OverflowSpec.scala +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - - - - -class OverflowSpec extends AnyFreeSpec with Matchers { - -} diff --git a/src/test/scala/dsptools/numbers/ParameterizedOpSpec.scala b/src/test/scala/dsptools/numbers/ParameterizedOpSpec.scala deleted file mode 100644 index 953e40b6..00000000 --- a/src/test/scala/dsptools/numbers/ParameterizedOpSpec.scala +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import breeze.math.Complex -import chisel3._ -import chisel3.experimental.FixedPoint -import chisel3.iotesters.TesterOptionsManager -import dsptools.DspTester - - -import dsptools.numbers._ -import dsptools._ - -//scalastyle:off magic.number - -class ParameterizedNumberOperation[T <: Data:Ring]( - inputGenerator:() => T, - outputGenerator:() => T, - val op: String = "+" - ) extends Module { - val io = IO(new Bundle { - val a1: T = Input(inputGenerator().cloneType) - val a2: T = Input(inputGenerator().cloneType) - val c: T = Output(outputGenerator().cloneType) - }) - - val register1 = Reg(outputGenerator().cloneType) - - register1 := { - op match { - case "+" => io.a1 + io.a2 - case "-" => io.a1 - io.a2 - case "*" => DspContext.withTrimType(NoTrim) { io.a1 * io.a2 } -// case "/" => io.a1 / io.a2 - case _ => throw new Exception(s"Bad operator $op passed to ParameterizedNumberOperation") - } - } - - io.c := register1 -} - -class ParameterizedOpTester[T<:Data:Ring](c: ParameterizedNumberOperation[T]) extends DspTester(c) { - for { - i <- BigDecimal(0.0) to 1.0 by 0.25 - j <- BigDecimal(0.0) to 4.0 by 0.5 - } { - val expected = c.op match { - case "+" => i + j - case "-" => i - j - case "*" => i * j - case _ => i + j - } - updatableDspVerbose.withValue(false) { - poke(c.io.a1, i) - poke(c.io.a2, j) - step(1) - - val result = peek(c.io.c) - - expect(c.io.c, expected, s"$i ${c.op} $j => $result, should have been $expected") - } - } -} - -class ParameterizedOpSpecification extends AnyFreeSpec with Matchers { - """ - The ParameterizedNumericOperation demonstrates a Module that can be instantiated to - handle different numeric types and different numerical operations - """ - - { - def realGenerator(): DspReal = new DspReal - def fixedInGenerator(): FixedPoint = FixedPoint(16.W, 8.BP) - def fixedOutGenerator(): FixedPoint = FixedPoint(48.W, 8.BP) - - "This instance will process Real numbers with the basic mathematical operations" - { - Seq("+", "-", "*").foreach { operation => - s"operation $operation should work for all inputs" in { - dsptools.Driver.execute( - () => new ParameterizedNumberOperation(realGenerator, realGenerator, operation) - ) { c => - new ParameterizedOpTester(c) - } should be(true) - } - } - } - "This instance will process Fixed point numbers with the basic mathematical operations" - { - Seq("+", "-", "*").foreach { operation => - s"operation $operation should work for all inputs" in { - dsptools.Driver.execute(() => new ParameterizedNumberOperation(fixedInGenerator, - fixedOutGenerator, - operation) - ) { c => - new ParameterizedOpTester(c) - } should be(true) - } - } - } - } -} - -class ComplexOpTester[T<:DspComplex[_]](c: ParameterizedNumberOperation[T]) extends DspTester(c) { - for { - i <- (BigDecimal(-1.0) to 1.0 by 0.25).map(_.toDouble) - j <- (BigDecimal(-4.0) to 4.0 by 0.5).map(_.toDouble) - } { - val c1 = Complex(i, j) - val c2 = Complex(j, i) - - val expected = c.op match { - case "+" => c1 + c2 - case "-" => c1 - c2 - case "*" => c1 * c2 - case _ => c1 + c2 - } - updatableDspVerbose.withValue(false) { - poke(c.io.a1, c1) - poke(c.io.a2, c2) - step(1) - - val result = peek(c.io.c) - - expect(c.io.c, expected, s"$i ${c.op} $j => $result, should have been $expected") - } - } -} - -class ComplexOpSpecification extends AnyFreeSpec with Matchers { - """ - The ParameterizedNumericOperation demonstrates a Module that can be instantiated to - handle different numeric types and different numerical operations - """ - { - def complexFixedGenerator(): DspComplex[FixedPoint] = { - DspComplex( - FixedPoint(16.W, 2.BP), - FixedPoint(16.W, 2.BP)) - } - def complexFixedOutputGenerator(): DspComplex[FixedPoint] = { - DspComplex( - FixedPoint(48.W, 4.BP), - FixedPoint(48.W, 4.BP)) - } - def complexRealGenerator(): DspComplex[DspReal] = { - DspComplex( - DspReal(1.0), - DspReal(1.0)) - } - -// "Run Repl for complexReal" in { -// dsptools.Driver.executeFirrtlRepl( -// () => new ParameterizedNumberOperation(complexRealGenerator, complexRealGenerator, "+") -// ) -// } -// - "This instance will process DspComplex[Real] numbers with the basic mathematical operations" - { - Seq("+", "-", "*").foreach { operation => - s"operation $operation should work for all inputs" in { - dsptools.Driver.execute( - () => new ParameterizedNumberOperation(complexRealGenerator, - complexRealGenerator, - operation) - ) { c => - new ComplexOpTester(c) - } should be(true) - } - } - } - "This instance will process DspComplex[FixedPoint] numbers with the basic mathematical operations" - { - Seq("+", "-", "*").foreach { operation => - s"operation $operation should work for all inputs" in { - dsptools.Driver.execute(() => new ParameterizedNumberOperation(complexFixedGenerator, - complexFixedOutputGenerator, - operation) - ) { c => - new ComplexOpTester(c) - } should be(true) - } - } - } - } -} diff --git a/src/test/scala/dsptools/numbers/SaturateSpec.scala b/src/test/scala/dsptools/numbers/SaturateSpec.scala deleted file mode 100644 index f0812e8a..00000000 --- a/src/test/scala/dsptools/numbers/SaturateSpec.scala +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import chisel3.experimental.FixedPoint -import chisel3.iotesters._ -import dsptools.numbers.rounding.Saturate - - - - -class SaturateUIntMod(val add: Boolean) extends Module { - val a = IO(Input(UInt(8.W))) - val b = IO(Input(UInt(8.W))) - val c = IO(Output(UInt())) - - // use wires so we don't know the width in the frontend - val aWire = Wire(UInt()) - val bWire = Wire(UInt()) - - aWire := a - bWire := b - - require(!aWire.isWidthKnown) - require(!bWire.isWidthKnown) - - c := (if (add) { - Saturate.addUInt(aWire, bWire) - } else { - Saturate.subUInt(aWire, bWire) - }) -} - -class SaturateUIntTester(dut: SaturateUIntMod) extends PeekPokeTester(dut) { - for (i <- 0 until 255) { - poke(dut.a, i) - for (j <- 0 until 255) { - poke(dut.b, j) - if (dut.add) { - if (i + j < 255) { - expect(dut.c, i + j) - } else { - expect(dut.c, 255) - } - } else { - if (i >= j) { - expect(dut.c, i - j) - } else { - expect(dut.c, 0) - } - } - } - } -} - -class SaturateSIntMod(val add: Boolean) extends Module { - val a = IO(Input(SInt(8.W))) - val b = IO(Input(SInt(8.W))) - val c = IO(Output(SInt())) - - // use wires so we don't know the width in the frontend - val aWire = Wire(SInt()) - val bWire = Wire(SInt()) - - aWire := a - bWire := b - - require(!aWire.isWidthKnown) - require(!bWire.isWidthKnown) - - c := (if (add) { - Saturate.addSInt(aWire, bWire) - } else { - Saturate.subSInt(aWire, bWire) - }) -} - -class SaturateSIntTester(dut: SaturateSIntMod) extends PeekPokeTester(dut) { - for (i <- -128 until 127) { - poke(dut.a, i) - for (j <- -128 until 127) { - poke(dut.b, j) - val expRes = if (dut.add) { - i + j - } else { - i - j - } - if (expRes > 127) { - expect(dut.c, 127) - } else if (expRes < -128) { - expect(dut.c, -128) - } else { - expect(dut.c, expRes) - } - } - } -} - -class SaturateFixedPointMod(val add: Boolean, val aBP: Int = 0, val bBP: Int = 0) extends Module { - val cBP = aBP max bBP - val a = IO(Input(FixedPoint(8.W, aBP.BP))) - val b = IO(Input(FixedPoint(8.W, bBP.BP))) - val c = IO(Output(FixedPoint(16.W, cBP.BP))) - - // use wires so we don't know the width in the frontend - val aWire = Wire(FixedPoint()) - val bWire = Wire(FixedPoint()) - - aWire := a - bWire := b - - require(!aWire.isWidthKnown) - require(!bWire.isWidthKnown) - - c := (if (add) { - Saturate.addFixedPoint(aWire, bWire) - } else { - Saturate.subFixedPoint(aWire, bWire) - }) -} - -class SaturateFixedPointTester(dut: SaturateFixedPointMod) extends PeekPokeTester(dut) { - import math.pow - val aBP = dut.aBP - val bBP = dut.bBP - val cBP = dut.cBP - - val max = 127 * pow(2.0, -cBP) - val min = -128 * pow(2.0, -cBP) - - val astep = pow(2.0, -aBP) - val bstep = pow(2.0, -bBP) - for (i <- (BigDecimal(-128 * astep) until 128 * astep by astep).map(_.toDouble)) { - pokeFixedPoint(dut.a, i) - for (j <- (BigDecimal(-128 * bstep) until 128 * bstep by bstep).map(_.toDouble)) { - pokeFixedPoint(dut.b, j) - val expRes = if (dut.add) { - i + j - } else { - i - j - } - if (expRes > max) { - // expectFixedPoint(dut.c, max, "max") - } else if (expRes < min) { - // expectFixedPoint(dut.c, min, "min") - } else { - // expectFixedPoint(dut.c, expRes, "middle") - } - } - } -} - -class SaturateSpec extends AnyFlatSpec with Matchers { - - behavior of "Saturating add" - - it should "work with UInt" in { - chisel3.iotesters.Driver.execute(Array[String](), () => new SaturateUIntMod(true)) { - c => new SaturateUIntTester(c) - } should be (true) - } - it should "work with SInt" in { - chisel3.iotesters.Driver.execute(Array[String](), () => new SaturateSIntMod(true)) { - c => new SaturateSIntTester(c) - } should be (true) - } - it should "work with FixedPoint" in { - for (aBP <- 0 until 8) { - for (bBP <- 0 until 8) { - chisel3.iotesters.Driver.execute(Array[String](), () => new SaturateFixedPointMod(true, aBP, bBP)) { - c => new SaturateFixedPointTester(c) - } should be (true) - } - } - } - - behavior of "Saturating sub" - - it should "work with UInt" in { - chisel3.iotesters.Driver.execute(Array[String](), () => new SaturateUIntMod(false)) { - c => new SaturateUIntTester(c) - } should be (true) - } - it should "work with SInt" in { - chisel3.iotesters.Driver.execute(Array[String](), () => new SaturateSIntMod(false)) { - c => new SaturateSIntTester(c) - } should be (true) - } - // for now, fixed point won't work because width inference and FixedPoint - // lowering happen from High -> Mid. Without finer-grained scheduling, we - // can't insert our pass after width inference but below FixedPoint lowering. - it should "work with FixedPoint" ignore { - for (aBP <- 0 until 8) { - for (bBP <- 0 until 8) { - chisel3.iotesters.Driver.execute(Array[String](), () => new SaturateFixedPointMod(false, aBP, bBP)) { - c => new SaturateFixedPointTester(c) - } should be (true) - } - } - } -} diff --git a/src/test/scala/dsptools/numbers/TypeclassSpec.scala b/src/test/scala/dsptools/numbers/TypeclassSpec.scala deleted file mode 100644 index dc3ab0f0..00000000 --- a/src/test/scala/dsptools/numbers/TypeclassSpec.scala +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package dsptools.numbers - -import chisel3._ -import chisel3.experimental.FixedPoint -import chisel3.iotesters._ -import dsptools._ -import dsptools.numbers._ - - - -/* - * These tests mostly exist to ensure that expressions of the form - * Typeclass[T].function() - * compile. Issue #17 talks about how this wasn't working for some - * typeclasses - */ - - -class FuncModule[T <: Data](gen: T, func: T=>T) extends Module { - val io = IO(new Bundle { - val in = Input(gen.cloneType) - val out = Output(gen.cloneType) - }) - io.out := func(io.in) -} - -object RingFunc { - def apply[T<:Data:Ring](in: T): T = { - val zero = Ring[T].zero - val one = Ring[T].one - Ring[T].times(one, Ring[T].plus(in, zero)) - } -} -class RingModule[T <: Data : Ring](gen: T) extends FuncModule(gen, {in: T => RingFunc(in)}) - -object EqFunc { - def apply[T <: Data : Eq : Ring](in: T): T = Mux(Eq[T].eqv(in, Ring[T].zero), Ring[T].one, in) -} -class EqModule[T <: Data : Eq : Ring](gen: T) extends FuncModule(gen, {in: T => EqFunc(in)}) - -object IntegerFunc { - def apply[T <: Data : Integer](in: T): T = - Integer[T].round(in) + IsIntegral[T].mod(in, in) -} -class IntegerModule[T <: Data : Integer](gen: T) extends FuncModule(gen, {in: T => IntegerFunc(in)}) - -object OrderFunc { - def apply[T <: Data : Order](in: T): T = - Order[T].min(in, in) -} -class OrderModule[T <: Data : Order](gen: T) extends FuncModule(gen, {in: T => OrderFunc(in)}) - -object PartialOrderFunc { - def apply[T <: Data : PartialOrder](in: T): T = - Mux(PartialOrder[T].partialCompare(in, in).bits.eq, in, in) -} -class PartialOrderModule[T <: Data : PartialOrder : Ring](gen: T) extends FuncModule( - gen, {in: T => PartialOrderFunc(in)}) - -class SignedModule[T <: Data : Signed](gen: T) extends FuncModule( - gen, {in: T => Mux(Signed[T].sign(in).neg, Signed[T].abs(in), Mux(Signed[T].sign(in).zero, in, in)) } -) - -class BinaryRepresentationModule[T <: Data : BinaryRepresentation](gen: T) extends FuncModule( - gen, {in : T => (((in << 2) >> 1) << 3.U) >> 2.U} -) - -trait FuncTester[T <: Data, V] { - def dut: FuncModule[T] - def testInputs: Seq[V] - def testOutputs: Seq[V] - - def myPoke(port: T, value: V): Unit - def myExpect(port: T, value: V): Unit - - testInputs.zip(testOutputs).foreach { case(in, out) => - myPoke(dut.io.in, in) - myExpect(dut.io.out, out) - } -} - -class SIntFuncTester[T <: FuncModule[SInt]](dut: T, val testInputs: Seq[Int], val testOutputs: Seq[Int]) -extends PeekPokeTester(dut) with FuncTester[SInt, Int] { - def myPoke(port: SInt, value: Int) = poke(port, value) - def myExpect(port: SInt, value: Int) = expect(port, value) -} - -class FixedPointFuncTester[T <: FuncModule[FixedPoint]](dut: T, val testInputs: Seq[Double], val testOutputs: Seq[Double]) -extends DspTester(dut) with FuncTester[FixedPoint, Double] { - def myPoke(port: FixedPoint, value: Double) = poke(port, value) - def myExpect(port: FixedPoint, value: Double) = expect(port, value) -} - -class DspRealFuncTester[T <: FuncModule[DspReal]](dut: T, val testInputs: Seq[Double], val testOutputs: Seq[Double]) -extends DspTester(dut) with FuncTester[DspReal, Double] { - def myPoke(port: DspReal, value: Double) = poke(port, value) - def myExpect(port: DspReal, value: Double) = expect(port, value) -} - -class TypeclassSpec extends AnyFreeSpec with Matchers { - "Ring[T].func() should work" in { - dsptools.Driver.execute( () => new RingModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - dsptools.Driver.execute( () => new RingModule(FixedPoint(10.W, 4.BP)) ) { c => - new FixedPointFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - dsptools.Driver.execute( () => new RingModule(DspReal()) ) { c => - new DspRealFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - } - "Eq[T].func() should work" in { - dsptools.Driver.execute( () => new EqModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, 0), Seq(2, 1)) - } should be (true) - dsptools.Driver.execute( () => new EqModule(FixedPoint(10.W, 4.BP)) ) { c => - new FixedPointFuncTester(c, Seq(2, 0), Seq(2, 1)) - } should be (true) - dsptools.Driver.execute( () => new EqModule(DspReal()) ) { c => - new DspRealFuncTester(c, Seq(2, 0), Seq(2, 1)) - } should be (true) - } - "Integer[T].func() should work" in { - dsptools.Driver.execute( () => new IntegerModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - } - "Order[T].func() should work" in { - dsptools.Driver.execute( () => new OrderModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - dsptools.Driver.execute( () => new OrderModule(FixedPoint(10.W, 4.BP)) ) { c => - new FixedPointFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - dsptools.Driver.execute( () => new OrderModule(DspReal()) ) { c => - new DspRealFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - } - "PartialOrder[T].func() should work" in { - dsptools.Driver.execute( () => new PartialOrderModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - dsptools.Driver.execute( () => new PartialOrderModule(FixedPoint(10.W, 4.BP)) ) { c => - new FixedPointFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - dsptools.Driver.execute( () => new PartialOrderModule(DspReal()) ) { c => - new DspRealFuncTester(c, Seq(2, -3), Seq(2, -3)) - } should be (true) - } - "Signed[T].func() should work" in { - dsptools.Driver.execute( () => new SignedModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, -3), Seq(2, 3)) - } should be (true) - dsptools.Driver.execute( () => new SignedModule(FixedPoint(10.W, 4.BP)) ) { c => - new FixedPointFuncTester(c, Seq(2, -3), Seq(2, 3)) - } should be (true) - dsptools.Driver.execute( () => new SignedModule(DspReal()) ) { c => - new DspRealFuncTester(c, Seq(2, -3), Seq(2, 3)) - } should be (true) - } - "BinaryRepresentation[T].func() should work" in { - dsptools.Driver.execute( () => new BinaryRepresentationModule(SInt(10.W)) ) { c => - new SIntFuncTester(c, Seq(2, 3), Seq(8, 12)) - } should be (true) - dsptools.Driver.execute( () => new BinaryRepresentationModule(FixedPoint(10.W, 4.BP)) ) { c => - new FixedPointFuncTester(c, Seq(2, 3), Seq(8, 12)) - } should be (true) - dsptools.Driver.execute( () => new BinaryRepresentationModule(DspReal()) ) { c => - new DspRealFuncTester(c, Seq(2, 3), Seq(8, 12)) - } should be (true) - } -} diff --git a/src/test/scala/examples/CaseClassBundleSpec.scala b/src/test/scala/examples/CaseClassBundleSpec.scala deleted file mode 100644 index 9bfb47ba..00000000 --- a/src/test/scala/examples/CaseClassBundleSpec.scala +++ /dev/null @@ -1,50 +0,0 @@ -//// SPDX-License-Identifier: Apache-2.0 -// -package examples - -import chisel3._ -import chisel3.iotesters.PeekPokeTester - - - -//scalastyle:off magic.number - -//case class CaseClassBundle(a: SInt) extends Bundle -//case class CaseClassBundle(underlying: SInt) extends Bundle { - // val underlying = gen.cloneType - // override def cloneType: this.type = new CaseClassBundle(underlying.cloneType).asInstanceOf[this.type] -//} -class CaseClassBundle(gen: SInt) extends Bundle { - val underlying = gen -} - -class SimpleCaseClassModule(gen: SInt) extends Module { - val io = IO(new Bundle { - val in = Input(new CaseClassBundle(gen)) - val out = Output(new CaseClassBundle(gen)) - }) - - val register1 = Reg(io.out.cloneType) - - register1 := io.in - - io.out := register1 -} - -class SimpleCaseClassBundleTester(c: SimpleCaseClassModule) extends PeekPokeTester(c) { - - poke(c.io.in.underlying, 7) - step(1) - expect(c.io.out.underlying, 7) -} - -class SimpleCaseClassBundleSpec extends AnyFlatSpec with Matchers { - behavior of "SimpleCaseClassBundle" - - it should "push number through with one step delay" in { - chisel3.iotesters.Driver(() => new SimpleCaseClassModule(SInt(5.W))) { c => - new SimpleCaseClassBundleTester(c) - } should be(true) - - } -} diff --git a/src/test/scala/examples/ComplexMultiplierSpec.scala b/src/test/scala/examples/ComplexMultiplierSpec.scala deleted file mode 100644 index fcab1230..00000000 --- a/src/test/scala/examples/ComplexMultiplierSpec.scala +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -import chisel3._ -import chisel3.experimental.FixedPoint -import chisel3.iotesters.Backend -import chisel3.{Bundle, Module} -import dsptools.{DspContext, DspTester} -import dsptools.numbers._ - - -import spire.algebra.Ring - -//scalastyle:off magic.number -class SimpleComplexMultiplier extends Module { - val io = IO(new Bundle { - val a1 = Input(DspComplex(FixedPoint(6.W, 4.BP), FixedPoint(6.W, 4.BP))) - val a2 = Input(DspComplex(FixedPoint(8.W, 1.BP), FixedPoint(8.W, 1.BP))) - val c = Output(DspComplex(FixedPoint(14.W, 5.BP), FixedPoint(14.W, 5.BP))) - }) - // spatialAssert(Seq(io.a1), Seq(io.c), 5) - // spatialAssert(Seq(io.a2), Seq(io.c), "group1") - - val register1 = Reg(io.c.cloneType) - -// val registerReal = Reg(io.a1.real) -// val registerimag = Reg(io.a1.imag) - - register1 := io.a1 * io.a2 - - io.c := register1 -} -class SimpleComplexMultiplierTester(c: SimpleComplexMultiplier) extends DspTester(c) { - for { - i <- (BigDecimal(0.0) to 1.0 by 0.25).map(_.toDouble) - j <- (BigDecimal(0.0) to 4.0 by 0.5).map(_.toDouble) - } { - val expected = i * j - - poke(c.io.a1.real, i) - poke(c.io.a1.imag, 0.0) - poke(c.io.a2.real, j) - poke(c.io.a2.imag, 0.0) - step(1) - - expect(c.io.c.real, i * j) - - println(s"SimpleComplexMultiplier: $i * $j should make $expected got ${peek(c.io.c.real)}") - } -} -class SimpleComplexMultiplierSpec extends AnyFlatSpec with Matchers { - behavior of "SimpleComplexMultiplier" - - it should "multiply complex numbers excellently" in { - chisel3.iotesters.Driver(() => new SimpleComplexMultiplier) { c => - new SimpleComplexMultiplierTester(c) - } should be(true) - - } -} diff --git a/src/test/scala/examples/Demod.scala b/src/test/scala/examples/Demod.scala deleted file mode 100644 index dc7bd3f7..00000000 --- a/src/test/scala/examples/Demod.scala +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -import chisel3._ -import chisel3.util.log2Ceil -import dsptools.numbers._ - -//scalastyle:off magic.number - -case class DemodParams ( - QAMn: List[Int] = List(5), // List of supported n-QAM i.e. 4-QAM (QPSK), 16-QAM, 64-QAM, etc.2,4,16,64,256 - frameSizes: List[Int] = List(1024), // Supported frame sizes (see FFT sizes needed) - softDemod: Boolean = false, // If true, should do LLR calc, otherwise hard demod - - //Default graycode till 64QAM was taken from http://ecee.colorado.edu/~ecen4242/wlana/wireless802.11a.html. - graycode_bpsk: List[Int] = List(0,1), - graycode_qpsk : List[Int] = List(0,1), - graycode_16_QAM : List[Int] = List(0, 2, 3, 1), - graycode_64_QAM: List[Int] = List(0, 4, 6, 2, 3, 7, 5, 1), - //user-specified graycode for 256-QAM that can be modified. - graycode_256_QAM: List[Int] = List(0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8) -) - -class Demod[T <: Data:RealBits](gen: => T, p: DemodParams) extends Module { - class DemodIO(numberOfOutputs: Int) extends Bundle { - // Input either signed DSPFixed or DSPDbl, as set by gen - val symbolIn = Input(DspComplex(gen, gen)) - // # of "hard" bits required is set by the maximum n-QAM supported - // (toBitWidth converts from an integer to # of bits required to represent it) - // Note for 4-QAM, the UInt range is [0,3] - // For Fixed, output notation is Qn.m (width = n + m + 1 for sign bit) - // When performing hard decoding, n,m = 0, so each element of the vec should - // only be 1 bit wide (using the sign bit) - // When performing hard decoding, n = 0, m = ??? -- you should determine what ??? is (15 is a placeholder) - val m = if (p.softDemod) 15 else 0 - val demodOut = Output(Vec(numberOfOutputs, Bool())) -// val demodOut = Vec(UInt.toBitWidth(p.QAMn.max-1), Bool(OUTPUT)) - // If the bits of demodOut are interpreted as signed BigInt rather than fixed (i.e. renormalize wrt LSB), - // a large positive number is a very confident 0, and a small positive number is a less confident 0. - // Negative #'s are associated with confidence for being a 1. We chose the sign of the LLR as positive <-> 0 - // bit because then the 2's complement sign bit of the LLR is the same as the hard decoder decision. - // People aren't generally consistent about choosing positive LLRs to correspond to 0 or 1, so we choose - // one with a convenient interpretation in this context. - // Offset of the input sample relative to frame size (needs to support up to max frame size) - val offsetIn = Input(UInt(log2Ceil(p.frameSizes.max + 1).W)) - // If symbolIn --> corresponding demodOut takes n cycles, offsetOut should be offsetIn delayed n clocks - val offsetOut = Output(UInt(log2Ceil(p.frameSizes.max + 1).W)) - val reset = Input(Bool()) - //Constellation type to demodulate. (2,4,16,64,256) - val modulation_type = Input(UInt(log2Ceil(p.QAMn.max + 1).W)) - } - - val io = IO(new DemodIO(gen.getWidth)) - - implicit val parameters = p - - - - //check if the integer part of the inputs are odd - val real_odd = io.symbolIn.real.intPart.isOdd - val imag_odd = io.symbolIn.imag.intPart.isOdd - - //Set up the vector for each constellation. - val bpsk_out0 = Bool() - val qpsk_out = Vec(2, Bool()) - val QAM16_out = Vec(4, Bool()) - val QAM64_out = Vec(6, Bool()) - val QAM256_out = Vec(8, Bool()) - -// //Depending on the elements of QAMn, corresponding LUTs are initated and addresses are put in. -// //The output of the LUT is then stored in a vector. -// if (p.QAMn.indexOf(2) != -1) { //if support BPSK -// val LUT_bpsk= DSPModule(new IntLUT2Bools(p.graycode_bpsk,2)) -// LUT_bpsk.io.addr(0) := DSPUInt(((index_offset + real_input) >> 1), LUT_bpsk.io.addr(0).getRange.max) -// bpsk_out0 := (LUT_bpsk.io.dout(0))(0) ? (mod_type === DSPUInt(2)) -// } -// if (p.QAMn.indexOf(4) != -1) { //if support QPSK -// val LUT_qpsk= DSPModule(new IntLUT2Bools(p.graycode_qpsk,2)) -// LUT_qpsk.io.addr(0) := DSPUInt(((index_offset + real_input) >> 1), LUT_qpsk.io.addr(0).getRange.max) -// LUT_qpsk.io.addr(1) := DSPUInt(((index_offset + imag_input) >> 1), LUT_qpsk.io.addr(0).getRange.max) -// qpsk_out(0) := (LUT_qpsk.io.dout(0))(0) ? (mod_type === DSPUInt(4)) -// qpsk_out(1) := (LUT_qpsk.io.dout(1))(0) ? (mod_type === DSPUInt(4)) -// } -// if (p.QAMn.indexOf(16) != -1) { //if support 16_QAM -// val LUT_16_QAM= DSPModule(new IntLUT2Bools(p.graycode_16_QAM,2)) -// LUT_16_QAM.io.addr(0) := DSPUInt(((index_offset + real_input) >> 1), LUT_16_QAM.io.addr(0).getRange.max) -// LUT_16_QAM.io.addr(1) := DSPUInt(((index_offset + imag_input) >> 1), LUT_16_QAM.io.addr(0).getRange.max) -// QAM16_out(0) := (LUT_16_QAM.io.dout(0))(0) ? (mod_type === DSPUInt(16)) -// QAM16_out(1) := (LUT_16_QAM.io.dout(0))(1) ? (mod_type === DSPUInt(16)) -// QAM16_out(2) := (LUT_16_QAM.io.dout(1))(0) ? (mod_type === DSPUInt(16)) -// QAM16_out(3) := (LUT_16_QAM.io.dout(1))(1) ? (mod_type === DSPUInt(16)) -// } -// if (p.QAMn.indexOf(64) != -1) { //if support 64_QAM -// val LUT_64_QAM= DSPModule(new IntLUT2Bools(p.graycode_64_QAM,2)) -// LUT_64_QAM.io.addr(0) := DSPUInt(((index_offset + real_input) >> 1), LUT_64_QAM.io.addr(0).getRange.max) -// LUT_64_QAM.io.addr(1) := DSPUInt(((index_offset + imag_input) >> 1), LUT_64_QAM.io.addr(0).getRange.max) -// QAM64_out(0) := (LUT_64_QAM.io.dout(0))(0) ? (mod_type === DSPUInt(64)) -// QAM64_out(1) := (LUT_64_QAM.io.dout(0))(1) ? (mod_type === DSPUInt(64)) -// QAM64_out(2) := (LUT_64_QAM.io.dout(0))(2) ? (mod_type === DSPUInt(64)) -// QAM64_out(3) := (LUT_64_QAM.io.dout(1))(0) ? (mod_type === DSPUInt(64)) -// QAM64_out(4) := (LUT_64_QAM.io.dout(1))(1) ? (mod_type === DSPUInt(64)) -// QAM64_out(5) := (LUT_64_QAM.io.dout(1))(2) ? (mod_type === DSPUInt(64)) -// } -// if (p.QAMn.indexOf(256) != -1) { //if support 256_QAM -// val LUT_256_QAM= DSPModule(new IntLUT2Bools(p.graycode_256_QAM,2)) -// LUT_256_QAM.io.addr(0) := DSPUInt(((index_offset + real_input) >> 1), LUT_256_QAM.io.addr(0).getRange.max) -// LUT_256_QAM.io.addr(1) := DSPUInt(((index_offset + imag_input) >> 1), LUT_256_QAM.io.addr(0).getRange.max) -// QAM256_out(0) := (LUT_256_QAM.io.dout(0))(0) ? (mod_type === DSPUInt(256)) -// QAM256_out(1) := (LUT_256_QAM.io.dout(0))(1) ? (mod_type === DSPUInt(256)) -// QAM256_out(2) := (LUT_256_QAM.io.dout(0))(2) ? (mod_type === DSPUInt(256)) -// QAM256_out(3) := (LUT_256_QAM.io.dout(0))(3) ? (mod_type === DSPUInt(256)) -// QAM256_out(4) := (LUT_256_QAM.io.dout(1))(0) ? (mod_type === DSPUInt(256)) -// QAM256_out(5) := (LUT_256_QAM.io.dout(1))(1) ? (mod_type === DSPUInt(256)) -// QAM256_out(6) := (LUT_256_QAM.io.dout(1))(2) ? (mod_type === DSPUInt(256)) -// QAM256_out(7) := (LUT_256_QAM.io.dout(1))(3) ? (mod_type === DSPUInt(256)) -// } -// -// //Setting the appropriate output of the demodulator corresponding to the constellation type. -// io.demodOut(0) := bpsk_out0 ? (mod_type === DSPUInt(2)) | qpsk_out(0) ? (mod_type === DSPUInt(4)) | QAM16_out(0) ? (mod_type === DSPUInt(16)) | QAM64_out(0) ? (mod_type === DSPUInt(64)) | QAM256_out(0) ? (mod_type === DSPUInt(256)) -// if (p.QAMn.max >= 4) { -// io.demodOut(1) := qpsk_out(1) ? (mod_type === DSPUInt(4)) | QAM16_out(1)? (mod_type === DSPUInt(16)) | QAM64_out(1)? (mod_type === DSPUInt(64)) | QAM256_out(1) ? (mod_type === DSPUInt(256)) -// } -// if (p.QAMn.max >= 16) { -// io.demodOut(2) := QAM16_out(2)? (mod_type === DSPUInt(16)) | QAM64_out(2)? (mod_type === DSPUInt(64)) | QAM256_out(2) ? (mod_type === DSPUInt(256)) -// io.demodOut(3) := QAM16_out(3)? (mod_type === DSPUInt(16)) | QAM64_out(3)? (mod_type === DSPUInt(64)) | QAM256_out(3) ? (mod_type === DSPUInt(256)) -// } -// if (p.QAMn.max >= 64) { -// io.demodOut(4) := QAM64_out(4)? (mod_type === DSPUInt(64)) | QAM256_out(4) ? (mod_type === DSPUInt(256)) -// io.demodOut(5) := QAM64_out(5)? (mod_type === DSPUInt(64)) | QAM256_out(5) ? (mod_type === DSPUInt(256)) -// } -// if (p.QAMn.max >= 256) { -// io.demodOut(6) := QAM256_out(6)? (mod_type === DSPUInt(256)) -// io.demodOut(7) := QAM256_out(7)? (mod_type === DSPUInt(256)) -// } -// -// io.offsetOut := io.offsetIn -// debug(real_odd) -// debug(imag_odd) -// debug(real_input_unclamped) -// debug(imag_input_unclamped) -// debug(real_input) -// debug(imag_input) -// debug(index_real) -// debug(index_imag) -// debug(index_offset) -// debug(io.demodOut) -// debug(real_odd) -} diff --git a/src/test/scala/examples/ParameterizedAdderSpec.scala b/src/test/scala/examples/ParameterizedAdderSpec.scala deleted file mode 100644 index bb2e6cdf..00000000 --- a/src/test/scala/examples/ParameterizedAdderSpec.scala +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -import chisel3._ -import chisel3.experimental.FixedPoint -import dsptools.DspTester -import dsptools.numbers._ - - - -//scalastyle:off magic.number - -class ParameterizedAdder[T <: Data:Ring](gen:() => T) extends Module { - val io = IO(new Bundle { - val a1: T = Input(gen().cloneType) - val a2: T = Input(gen().cloneType) - val c = Output(gen().cloneType) - }) - - val register1 = Reg(gen().cloneType) - - register1 := io.a1 + io.a2 - - io.c := register1 -} - -class ParameterizedAdderTester[T<:Data:Ring](c: ParameterizedAdder[T]) extends DspTester(c) { - updatableDspVerbose.withValue(false) { - for { - i <- (BigDecimal(-2.0) to 1.0 by 0.25).map(_.toDouble) - j <- (BigDecimal(-2.0) to 4.0 by 0.5).map(_.toDouble) - } { - poke(c.io.a1, i) - poke(c.io.a2, j) - step(1) - - val result = peek(c.io.c) - - expect(c.io.c, i + j, s"parameterize adder tester $i + $j => $result should have been ${i + j}") - } - } -} - -class ParameterizedAdderSpec extends AnyFlatSpec with Matchers { - - behavior of "parameterized adder circuit on blackbox real" - - it should "allow registers to be declared that infer widths" in { - def getReal: DspReal = new DspReal - - dsptools.Driver.execute(() => new ParameterizedAdder(getReal _)) { c => - new ParameterizedAdderTester(c) - } should be (true) - } - - behavior of "parameterized adder circuit on fixed point" - - it should "allow registers to be declared that infer widths" in { - def getFixed: FixedPoint = FixedPoint(32.W, 16.BP) - - dsptools.Driver.execute(() => new ParameterizedAdder(getFixed _)) { c => - new ParameterizedAdderTester(c) - } should be (true) - - dsptools.Driver.execute(() => new ParameterizedAdder(getFixed _), Array("--backend-name", "verilator")) { c => - new ParameterizedAdderTester(c) - } should be (true) - } -} diff --git a/src/test/scala/examples/ParameterizedSaturatingAdder.scala b/src/test/scala/examples/ParameterizedSaturatingAdder.scala deleted file mode 100644 index 052a6a7f..00000000 --- a/src/test/scala/examples/ParameterizedSaturatingAdder.scala +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -import chisel3._ -import dsptools.{DspContext, DspTester, Saturate} -import dsptools.numbers._ - - - -class ParameterizedSaturatingAdder[T <: Data:Integer](gen:() => T) extends Module { - val io = IO(new Bundle { - val a1: T = Input(gen().cloneType) - val a2: T = Input(gen().cloneType) - val normalSum = Output(gen().cloneType) - val saturatedSum = Output(gen().cloneType) - }) - - val register1 = Reg(gen().cloneType) - val register2 = Reg(gen().cloneType) - - println(s"ParameterizedSaturatingAdder ${DspContext.current}") - register1 := io.a1 + io.a2 - - DspContext.withOverflowType(Saturate) { - register2 := io.a1 + io.a2 - } - io.normalSum := register1 - io.saturatedSum := register2 -} - -class ParameterizedSaturatingAdderTester[T<:Data:Integer](c: ParameterizedSaturatingAdder[T], width: Int) extends DspTester(c) { - val min = -(1 << (width - 1)) - val max = (1 << (width-1)) - 1 - println("Min = " + min.toString) - println("Max = " + max.toString) - def overflowint(x: Int): Int = { - if (x > max) overflowint(min + x - max - 1) - else if (x < min) overflowint(max + x - min + 1) - else x - } - def saturateint(x: Int): Int = { - if (x > max) max - else if (x < min) min - else x - } - for { - i <- min to max - j <- min to max - } { - println(s"I=$i and J=$j") - poke(c.io.a1, i) - poke(c.io.a2, j) - step(1) - - val resultNormal = peek(c.io.normalSum) - val resultSaturated = peek(c.io.saturatedSum) - - expect(c.io.normalSum, overflowint(i+j), s"parameterized normal adder $i + $j => $resultNormal should have been ${overflowint(i+j)}") - expect(c.io.saturatedSum, saturateint(i+j), s"parameterized saturating adder $i + $j => $resultSaturated should have been ${saturateint(i+j)}") - } -} - -class ParameterizedSaturatingAdderSpec extends AnyFlatSpec with Matchers { - behavior of "parameterized saturating adder circuit on SInt" - - ignore should "allow registers to be declared that infer widths" in { - - val width = 3 - def getSInt(): SInt = SInt(width.W) - - chisel3.iotesters.Driver(() => new ParameterizedSaturatingAdder(getSInt)) { c => - new ParameterizedSaturatingAdderTester(c, width) - } should be (true) - } - -} - diff --git a/src/test/scala/examples/RealAdderSpec.scala b/src/test/scala/examples/RealAdderSpec.scala deleted file mode 100644 index c6083067..00000000 --- a/src/test/scala/examples/RealAdderSpec.scala +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -import chisel3._ -import dsptools.{DspTester, ReplOptionsManager} -import dsptools.numbers.DspReal - - - -import scala.math.BigDecimal - -class RealAdder extends Module { - val io = IO(new Bundle { - val a1 = Input(new DspReal) - val a2 = Input(new DspReal) - val c = Output(new DspReal) - }) - - val register1 = Reg(new DspReal) - - register1 := io.a1 + io.a2 - - io.c := register1 -} - -object RealAdder { - def main(args: Array[String]) { - val optionsManager = new ReplOptionsManager - if(optionsManager.parse(args)) { - dsptools.Driver.executeFirrtlRepl(() => new RealAdder, optionsManager) - } - } -} - -class RealAdderTester(c: RealAdder) extends DspTester(c) { - for { - i <- (BigDecimal(0.0) to 1.0 by 0.25).map(_.toDouble) - j <- (BigDecimal(0.0) to 4.0 by 0.5).map(_.toDouble) - } { - poke(c.io.a1, i) - poke(c.io.a2, j) - step(1) - - expect(c.io.c, i + j) - } -} - - -class RealAdderSpec extends AnyFlatSpec with Matchers { - behavior of "adder circuit on blackbox real" - - it should "allow registers to be declared that infer widths" in { - dsptools.Driver.execute(() => new RealAdder, Array("--backend-name", "firrtl")) { c => - new RealAdderTester(c) - } should be (true) - } -} diff --git a/src/test/scala/examples/SimpleAdderSpec.scala b/src/test/scala/examples/SimpleAdderSpec.scala deleted file mode 100644 index b48b148c..00000000 --- a/src/test/scala/examples/SimpleAdderSpec.scala +++ /dev/null @@ -1,49 +0,0 @@ -//// SPDX-License-Identifier: Apache-2.0 -// -package examples - -import chisel3._ -import chisel3.experimental.FixedPoint -import dsptools.DspTester - - - -class SimpleAdder extends Module { - val io = IO(new Bundle { - val a1 = Input(FixedPoint(6.W, 4.BP)) - val a2 = Input(FixedPoint(8.W, 1.BP)) - val c = Output(FixedPoint(12.W, 5.BP)) - }) -// spatialAssert(Seq(io.a1), Seq(io.c), 5) -// spatialAssert(Seq(io.a2), Seq(io.c), "group1") - - val register1 = Reg(FixedPoint()) - - register1 := io.a1 + io.a2 - - io.c := register1 -} -class SimpleAdderTester(c: SimpleAdder) extends DspTester(c) { - for { - i <- BigDecimal(0.0) to 1.0 by 0.25 - j <- BigDecimal(0.0) to 4.0 by 0.5 - } { - val expected = i + j - - poke(c.io.a1, i) - poke(c.io.a2, j) - step(1) - - println(s"SimpleAdder: $i + $j should make $expected got ${peek(c.io.c)}") - } -} -class SimpleAdderSpec extends AnyFlatSpec with Matchers { - behavior of "SimpleAdder" - - it should "add to numbers excellently" in { - chisel3.iotesters.Driver(() => new SimpleAdder) { c => - new SimpleAdderTester(c) - } should be(true) - - } -} diff --git a/src/test/scala/examples/SimpleDspModuleSpec.scala b/src/test/scala/examples/SimpleDspModuleSpec.scala deleted file mode 100644 index 25fa16ed..00000000 --- a/src/test/scala/examples/SimpleDspModuleSpec.scala +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package SimpleDsp - -// Allows you to use Chisel Module, Bundle, etc. -import chisel3._ -// Allows you to use FixedPoint -import chisel3.experimental.FixedPoint -// If you want to take advantage of type classes >> Data:RealBits (i.e. pass in FixedPoint or DspReal) -import dsptools.numbers._ -// Enables you to set DspContext's for things like overflow behavior, rounding modes, etc. -import dsptools.DspContext -// Use DspTester, specify options for testing (i.e. expect tolerances on fixed point, etc.) -import dsptools.{DspTester, DspTesterOptionsManager, DspTesterOptions} -// Allows you to modify default Chisel tester behavior (note that DspTester is a special version of Chisel tester) -import iotesters.TesterOptions -// Scala unit testing style - - - -// IO Bundle. Note that when you parameterize the bundle, you MUST override cloneType. -// This also creates x, y, z inputs/outputs (direction must be specified at some IO hierarchy level) -// of the type you specify via gen (must be Data:RealBits = UInt, SInt, FixedPoint, DspReal) -class SimpleDspIo[T <: Data:RealBits](gen: T) extends Bundle { - val x = Input(gen.cloneType) - val y = Input(gen.cloneType) - val z = Output(gen.cloneType) -} - -// Parameterized Chisel Module; takes in type parameters as explained above -class SimpleDspModule[T <: Data:RealBits](gen: T, val addPipes: Int) extends Module { - // This is how you declare an IO with parameters - val io = IO(new SimpleDspIo(gen)) - // Output will be current x + y addPipes clk cycles later - // Note that this relies on the fact that type classes have a special + that - // add addPipes # of ShiftRegister after the sum. If you don't wrap the sum in - // DspContext.withNumAddPipes(addPipes), the default # of addPipes is used. - DspContext.withNumAddPipes(addPipes) { - io.z := io.x context_+ io.y - } -} - -// You create a tester that must extend DspTester to support Dsp type peeks/pokes (with doubles, complex, etc.) -class SimpleDspModuleTester[T <: Data:RealBits](c: SimpleDspModule[T]) extends DspTester(c) { - val x = Seq(-1.1, -0.4, 0.4, 1.1) - val z = x map (2 * _) - for (i <- 0 until (x.length + c.addPipes)) { - val in = x(i % x.length) - // Feed in to the x, y inputs - poke(c.io.x, in) - // Locally (just for the stuff in {}) change console print properties - // so that this second peek isn't displayed on the console - // (since the input value is the same as the first peek) - updatableDspVerbose.withValue(false) { - poke(c.io.y, in) - } - if (i >= c.addPipes) { - // Expect that the z output matches the expected value @ z(i - c.addPipes) to some tolerance - // as described below - expect(c.io.z, z(i - c.addPipes)) - } - // Step the clock by 1 period - step(1) - } -} - -// Scala style testing -class SimpleDspModuleSpec extends AnyFlatSpec with Matchers { - - // If you don't want to use default tester options, you need to create your own DspTesterOptionsManager - val testOptions = new DspTesterOptionsManager { - // Customizing Dsp-specific tester features (unspecified options remain @ default values) - dspTesterOptions = DspTesterOptions( - // # of bits of error tolerance allowed by expect (for FixedPoint, UInt, SInt type classes) - fixTolLSBs = 1, - // Generate a Verilog testbench to mimic peek/poke testing - genVerilogTb = true, - // Show all tester interactions with the module (not just failed expects) on the console - isVerbose = true) - // Customizing Chisel tester features - testerOptions = TesterOptions( - // If set to true, prints out all nested peeks/pokes (i.e. for FixedPoint or DspReal, would - // print out BigInt or base n versions of peeks/pokes -- rather than the proper decimal representation) - isVerbose = false, - // Default backend uses FirrtlInterpreter. If you want to simulate with the generated Verilog, - // you need to switch the backend to Verilator. Note that tests currently need to be dumped in - // different output directories with Verilator; otherwise you run into weird concurrency issues (bug!)... - backendName = "verilator") - // Override default output directory while maintaining other default settings - commonOptions = commonOptions.copy(targetDirName = "test_run_dir/simple_dsp_fix") - } - - behavior of "simple dsp module" - - it should "properly add fixed point types" in { - // Run the dsp tester by following this style: You need to pass in the module to test and your created DspTesterOptionsManager. - // Note that here, you're testing the module with inputs/outputs of FixedPoint type (Q15.12) and 3 registers (for retiming) at the output. - // You could alternatively use DspReal() - // Scala keeps track of which tests pass/fail. - // Supposedly, Chisel3 testing infrastructure might be overhauled to reduce the amount of boilerplate, but this is currently - // the endorsed way to do things. - dsptools.Driver.execute(() => new SimpleDspModule(FixedPoint(16.W, 12.BP), addPipes = 3), testOptions) { c => - new SimpleDspModuleTester(c) - } should be (true) - } - -} diff --git a/src/test/scala/examples/StreamingAutocorrelatorSpec.scala b/src/test/scala/examples/StreamingAutocorrelatorSpec.scala deleted file mode 100644 index df0001f3..00000000 --- a/src/test/scala/examples/StreamingAutocorrelatorSpec.scala +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -//scalastyle:off magic.number - -import chisel3._ -import chisel3.iotesters.PeekPokeTester -import dsptools.numbers.implicits._ - - - -import spire.algebra.{Ring, Field} - - -class StreamingAutocorrelatorTester(c: StreamingAutocorrelator[SInt]) - extends PeekPokeTester(c) { - - for(num <- -5 to 5) { - poke(c.io.input, BigInt(num)) - step(1) - println(peek(c.io.output).toString()) - } -} - -class StreamingAutocorrelatorSpec extends AnyFlatSpec with Matchers { - "StreamingAutocorrelatorFIR" should "compute a running average like thing" in { - val taps = Seq.tabulate(3) { x => x.S} - //implicit val DefaultDspContext = DspContext() - //implicit val evidence = (context :DspContext) => new SIntRing()(context) - - chisel3.iotesters.Driver(() => new StreamingAutocorrelator(SInt(10.W), SInt(20.W), 2, 3)) { c => - new StreamingAutocorrelatorTester(c) - } should be (true) - } -} diff --git a/src/test/scala/examples/TestVectors.scala b/src/test/scala/examples/TestVectors.scala deleted file mode 100644 index 047e2f57..00000000 --- a/src/test/scala/examples/TestVectors.scala +++ /dev/null @@ -1,162 +0,0 @@ -//// SPDX-License-Identifier: Apache-2.0 -// -//// TODO: IFFT -// -//package examples -// -//import dsptools.numbers.DspComplex -// -//import scala.math._ -//import scala.util.Random -//import dsptools._ -//import breeze.math.Complex -// -//object TestVectors{ -// -// // Config for random tests vs. mostly tones (only for non base radix FFTs) -// var randomTests = true -// -// // Minimum absolute value of expected outputs -// var outAbsMin: List[Double] = List() -// -// private var in:List[List[Complex]] = List(List()) -// private var out:List[List[Complex]] = List(List()) -// def getIn(idx: Int) = in(idx) -// def getOut(idx: Int) = out(idx) -// -// /** Fake twiddles for full butterfly test */ -// val twiddles = List( -// DspComplex(-0.25,-0.1), -// DspComplex(-0.025,0.04), -// DspComplex(-0.15,0.13), -// DspComplex(-0.05,-0.2), -// DspComplex(-0.005,-0.01), -// DspComplex(-0.125,0.1) -// ) -// -// /** Fake inputs for full butterfly test */ -// val inputs = Array( -// DspComplex(-0.0016156958292784854,-0.0038205920103660867), -// DspComplex(0.08396018021512272,-0.0013820177961438253), -// DspComplex(-0.013933768021206223,0.013053573473671093), -// DspComplex(-0.033684289651395055,0.028591395636659137), -// DspComplex(-0.015584356598410773,0.00337343167302713), -// DspComplex(0.015103657363909739,-0.012791286461996752), -// DspComplex(0.01926837435299409,-0.02547371574646024) -// ) -// -// /** Tones @ fraction of fs */ -// val realf = List(0.2,0.3,0.4,0.25) -// val reala = List(0.25,0.15,0.02,0.03) -// -// /** Init test vectors */ -// def apply(sizes: List[Int], frames: Int) : Tuple2[List[List[Complex]],List[List[Complex]]] = { -// val (i,o) = (for (e <- sizes) yield {apply(e,frames)}).unzip -// in = i -// out = o -// outAbsMin = o.map( -// _.map(x => math.abs(x.real).min(math.abs(x.imag))).min -// ) -// (i,o) -// } -// -// /** Create list of inputs */ -// def populateIn(FFTN: Int): List[Complex] = { -// var inProto = Array.empty[Complex] -// // Butterfly tests known set -// if (FFTN <= WFTA.getValidRad.max){ -// inputs.zipWithIndex.foreach { -// case (e, idx) => { -// if (idx < 2 | FFTN > idx) inProto = inProto :+ e -// } -// } -// } -// // Larger tonal FFT sizes -// else if (!randomTests){ -// for (i <- 0 until FFTN){ -// val r1 = (reala,realf).zipped.map( (a,f) => a*sin(2*Pi*f*i)) -// val r2 = r1.foldLeft(0.0001+i.toDouble/FFTN/100)(_ + _) -// inProto = inProto :+ DspComplex(r2 + 0.001*Random.nextGaussian,0.04*Random.nextGaussian) -// } -// } -// // Larger random tests -// else { -// // Assume FFT input has fewer significant bits than FFT output -// val outRange = DSPFixed.toRange(DSPFixed.paramsToWidth(DspComplex.getFixedParams)) -// val std = DSPFixed.toDouble((outRange._1.abs).max(outRange._2.abs),DspComplex.getFrac) -// inProto = Array.fill(FFTN)(DspComplex( -// clamp(std/FFTN*Random.nextGaussian,std/FFTN), -// clamp(std/FFTN*Random.nextGaussian,std/FFTN) -// )) -// } -// inProto.toList -// } -// -// /** Restrict range, min absolute value */ -// def clamp(in:Double, absMax:Double): Double = { -// val min = -1*absMax -// val temp = if (in > absMax) absMax else if (in < min) min else in -// // Restricts underflow (IMPORTANT! when comparing w/ double-precision calculated FFT -- -// // that input needs to be rounded) -// val sigFrac = 1 << (DspComplex.getFrac/1.5).toInt -// Math.round(temp * sigFrac).toDouble / sigFrac -// } -// -// /** Create list of outputs */ -// def populateOut(inProto: List[Complex], FFTN: Int) : List[DspComplex] = { -// -// import breeze.signal._ -// import breeze.linalg.DenseVector -// import breeze.math.Complex -// -// // Using Breeze FFT Cooley Tukey instead of slow DFT == WIN! -// -// val breezeIn = DenseVector(inProto.map(x => breeze.math.Complex(x.real,x.imag)).toArray) -// val breezeOut = fourierTr(breezeIn) -// breezeOut.map(x => DspComplex(x.real,x.imag)).toArray.toList -// -// /* -// var outProto = Array.fill(FFTN){DspComplex(0.0,0.0)} -// // Direct (inefficient) FFT calculation -// // exp(ix) = cos(x) + i*sin(x) -// // exp(-j*2*pi*n*k/FFTN) = cos(-2*pi*n*k/FFTN) + i*sin(-2*pi*n*k/FFTN) -// for (k <- 0 until FFTN; -// n <- 0 until FFTN){ -// val s = sin(-2*Pi*n*k/FFTN) -// val c = cos(-2*Pi*n*k/FFTN) -// val ir = inProto(n).real -// val ii = inProto(n).imag -// outProto(k).real = outProto(k).real + ir * c - ii * s -// outProto(k).imag = outProto(k).imag + ii * c + ir * s -// } -// outProto.toList -// */ -// -// } -// -// /** Create test vectors for particular FFTN */ -// def apply(FFTN : Int, frames: Int) : Tuple2[List[Complex],List[Complex]] = { -// // Each frame is different; consists of random symbols -// if (randomTests){ -// var inArray = Array.empty[List[Complex]] -// var outArray = Array.empty[List[Complex]] -// for (i <- 0 until frames){ -// val inProto = populateIn(FFTN) -// val outProto = populateOut(inProto, FFTN) -// inArray = inArray :+ inProto -// outArray = outArray :+ outProto -// } -// (inArray.toList.flatten,outArray.toList.flatten) -// } -// // Each frame is the same; consists of tones -// else { -// val inProto = populateIn(FFTN) -// val outProto = populateOut(inProto, FFTN) -// // Repeat for specified # of frames -// val inN = List.fill(frames)(inProto).flatten -// val outN = List.fill(frames)(outProto).flatten -// (inN, outN) -// } -// } -// -//} \ No newline at end of file diff --git a/src/test/scala/examples/TransposedStreamFIRSpec.scala b/src/test/scala/examples/TransposedStreamFIRSpec.scala deleted file mode 100644 index 290f3b53..00000000 --- a/src/test/scala/examples/TransposedStreamFIRSpec.scala +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package examples - -//scalastyle:off magic.number - -import chisel3._ -import chisel3.iotesters.{PeekPokeTester, TesterOptions} -import dsptools.numbers.implicits._ -import dsptools.{DspContext, Grow} - - -import dsptools.examples.{ConstantTapTransposedStreamingFIR, TransposedStreamingFIR} -import spire.algebra.{Field, Ring} - -class ConstantTapTransposedStreamingTester(c: ConstantTapTransposedStreamingFIR[SInt, Int]) - extends PeekPokeTester(c) { - val smallest = -5 - val biggest = 5 - println(s"Taps are ${c.taps.toString}") - - def checkAnswer(n: Int) : Int = { - // assumes inputs increase by 1 each time - c.taps.zipWithIndex.foldLeft(0) {case (s, (tap, idx)) => - s + tap * (if(n - idx >= smallest) n - idx else 0) - } - } - // initialize old state to 0 - poke(c.io.input.valid, 1) - poke(c.io.input.bits, BigInt(0)) - step(c.taps.length) - - for(num <- smallest to biggest) { - poke(c.io.input.bits, BigInt(-7)) - poke(c.io.input.valid, 0) - for (i<- 0 until 10) { - step(1) - expect(c.io.output.valid, 0, "Output should not be valid if input is invalid") - } - poke(c.io.input.valid, 1) - poke(c.io.input.bits, BigInt(num)) - step(1) - println(peek(c.io.output.bits).toString()) - println(s"Answer should be ${checkAnswer(num)}") - expect(c.io.output.bits, checkAnswer(num), "Output did should match expected data") - expect(c.io.output.valid, 1, "Output should be valid if input is valid") - } - -} - -class TransposedStreamingTester(c: TransposedStreamingFIR[SInt]) - extends PeekPokeTester(c) { - - for(num <- -5 to 5) { - poke(c.io.input, BigInt(num)) - step(1) - println(peek(c.io.output).toString()) - } -} - -class TransposedStreamFIRSpec extends AnyFlatSpec with Matchers { - "ConstantTapTransposedStreamingFIR" should "compute a running average like thing" in { - val taps = 0 until 3 - - chisel3.iotesters.Driver.execute(Array[String](), - () => new ConstantTapTransposedStreamingFIR(SInt(10.W), SInt(16.W), taps)) { - c => new ConstantTapTransposedStreamingTester(c) - } should be (true) - } -}