[Feature] Generics for code block

[taichi-ishitani]

SV's text macro is useful feature to reduce coding cost for repeated code blocks.
I need this kind of feature to import code below to Very.
https://github.com/rggen/rggen-sample/blob/b0439abf7d5fa6086c4d0aef0ffcdc6836506f06/uart_csr.sv#L1-L9

I think it can be achieved if the generics feature handle code blocks.

[dalance]

A syntax idea about generic block declaration.

block rggen_connect_bit_field_if::<RIF, FIF, LSB, WIDTH> {
    assign  FIF.valid                 = RIF.valid;
    assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH];
    assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH];
    assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH];
    assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data;
    assign  RIF.value[LSB+:WIDTH]     = FIF.value;
}

module ModuleA {
    inst u_block: rggen_connect_bit_field_if::<bit_field_if, bit_field_sub_if, 0, 8>;
}

[taichi-ishitani]

It looks good.
But why is instance name need? Is it to separate namespace?

[dalance]

It looks good. But why is instance name need? Is it to separate namespace?

Yes. And adding name-less instantiation increases syntax and name-resolver complexity.
The generated SV will become like below:

if (1) begin: u_block
    assign  FIF.valid                 = RIF.valid;
    assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH];
    assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH];
    assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH];
    assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data;
    assign  RIF.value[LSB+:WIDTH]     = FIF.value;
end