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Can't use for loop variable in expression in if_reset statement #964
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I think we do not have a mechanism to identify that the In the meantime, nananapo, you can use a generate loop which contains an |
I think always_ff{
if_reset {
for i : u32 in 0..32{
r[i] = i;
}
}
}
var N: u32;
always_ff{
if_reset {
for i : u32 in 0..N{
r[i] = i;
}
}
}
|
For SystemVerilog, following code causes elaboration error because operand of part selection must be constant. for (int i = 0;i < W;++i) begin
a[i:0] = i;
end Therefore, I think Veryl should treat a loop variable as a variable except when it is referred as a reset value. |
I think this rule is bit difficult, and may introduce ambiguous edge cases in the future. " |
Instead of this, how about removing reset value check? |
Even if the check is removed, |
I read before an article that reducing number of procedural blocks such as |
OK. I'll merge #974, but leave this issue. |
Regular variables also cause this error so we need to introduce an additional check. |
I think this check can be done by #788. |
I think #788 is not so easy.
|
There are 4 patterns of select operation. a = X[0]; // bit select
b = X[1:0]; // select by msb and lsb
c = X[1+:2]; // select by position and width
d = X[1 step 2]; // select by step For I think we have following choises.
|
I'm starting to feel that introducing I think inserting const check to |
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