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sharcfe.cpp
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sharcfe.cpp
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// license:BSD-3-Clause
// copyright-holders:Ville Linde
/******************************************************************************
Front-end for SHARC recompiler
******************************************************************************/
#include "emu.h"
#include "sharcfe.h"
#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
//#define ASTAT_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0)
//#define ASTAT_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0)
#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0)
#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0)
#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0)
#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0)
#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0)
#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0)
#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0)
#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0)
#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0)
#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0)
#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0)
#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0)
#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0)
#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0)
#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0)
#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0)
#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0)
#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0)
#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0)
#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0)
#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0)
#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0)
#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0)
#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0)
#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0)
#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0)
#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0)
#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0)
#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0)
#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0)
#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0)
#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0)
#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0)
#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0)
#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0)
#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0)
#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0)
#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0)
#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0)
#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0)
#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0)
#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0)
#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0)
#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0)
#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0)
#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0)
#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0)
#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0)
#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0)
sharc_frontend::sharc_frontend(adsp21062_device *sharc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
: drc_frontend(*sharc, window_start, window_end, max_sequence),
m_sharc(sharc)
{
m_loopmap = std::make_unique<LOOP_ENTRY[]>(0x20000);
}
void sharc_frontend::flush()
{
LOOP_ENTRY* map = m_loopmap.get();
memset(map, 0, sizeof(LOOP_ENTRY) * 0x20000);
}
void sharc_frontend::add_loop_entry(UINT32 pc, UINT8 type, UINT32 start_pc, UINT8 looptype, UINT8 condition)
{
UINT32 l2 = pc >> 17;
UINT32 l1 = pc & 0x1ffff;
if (l2 != 0x1)
fatalerror("sharc_frontend::add_loop_entry: PC = %08X", pc);
LOOP_ENTRY* map = m_loopmap.get();
UINT32 current_type = map[l1].entrytype;
if (current_type & type)
{
// check for mismatch if the entry is already used
if (map[l1].start_pc != start_pc ||
map[l1].looptype != looptype ||
map[l1].condition != condition)
{
fatalerror("sharc_frontend::add_loop_entry: existing entry does match: start_pc %08X/%08X, looptype %02X/%02X, cond %02X/%02X", start_pc, map[l1].start_pc, looptype, map[l1].looptype, condition, map[l1].condition);
}
}
current_type |= type;
map[l1].entrytype = current_type;
map[l1].looptype = looptype;
map[l1].condition = condition;
map[l1].start_pc = start_pc;
}
void sharc_frontend::insert_loop(const LOOP_DESCRIPTOR &loopdesc)
{
add_loop_entry(loopdesc.start_pc, LOOP_ENTRY_START, loopdesc.start_pc, loopdesc.type, loopdesc.condition);
add_loop_entry(loopdesc.end_pc, LOOP_ENTRY_EVALUATION, loopdesc.start_pc, loopdesc.type, loopdesc.condition);
if (loopdesc.astat_check_pc != 0xffffffff)
add_loop_entry(loopdesc.astat_check_pc, LOOP_ENTRY_ASTAT_CHECK, loopdesc.start_pc, loopdesc.type, loopdesc.condition);
}
bool sharc_frontend::is_loop_evaluation(UINT32 pc)
{
UINT32 l2 = pc >> 17;
UINT32 l1 = pc & 0x1ffff;
if (l2 != 0x1)
return false;
LOOP_ENTRY* map = m_loopmap.get();
if (map[l1].entrytype & LOOP_ENTRY_EVALUATION)
return true;
return false;
}
bool sharc_frontend::is_loop_start(UINT32 pc)
{
UINT32 l2 = pc >> 17;
UINT32 l1 = pc & 0x1ffff;
if (l2 != 0x1)
return false;
LOOP_ENTRY* map = m_loopmap.get();
if (map[l1].entrytype & LOOP_ENTRY_START)
return true;
return false;
}
bool sharc_frontend::is_astat_delay_check(UINT32 pc)
{
UINT32 l2 = pc >> 17;
UINT32 l1 = pc & 0x1ffff;
if (l2 != 0x1)
return false;
LOOP_ENTRY* map = m_loopmap.get();
if (map[l1].entrytype & LOOP_ENTRY_ASTAT_CHECK)
return true;
return false;
}
bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
{
//UINT64 opcode = desc.opptr.q[0] = m_sharc.m_direct->read_qword(desc.physpc, 0);
UINT64 opcode = desc.opptr.q[0] = m_sharc->pm_read48(desc.physpc);
desc.length = 1;
desc.cycles = 1;
// handle looping
/*
if (m_loop.size() > 0)
{
for (int i = 0; i < m_loop.size(); i++)
{
LOOP_DESCRIPTOR &loop = m_loop.at(i);
if (loop.start_pc == desc.pc)
{
desc.flags |= OPFLAG_IS_BRANCH_TARGET;
}
if (loop.astat_check_pc == desc.pc)
{
if (loop.type == LOOP_TYPE_CONDITIONAL)
{
UINT32 flags = m_sharc->do_condition_astat_bits(loop.condition);
if (flags & adsp21062_device::ASTAT_FLAGS::AZ) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AZ;
if (flags & adsp21062_device::ASTAT_FLAGS::AN) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AN;
if (flags & adsp21062_device::ASTAT_FLAGS::AV) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AV;
if (flags & adsp21062_device::ASTAT_FLAGS::AC) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AC;
if (flags & adsp21062_device::ASTAT_FLAGS::MN) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_MN;
if (flags & adsp21062_device::ASTAT_FLAGS::MV) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_MV;
if (flags & adsp21062_device::ASTAT_FLAGS::SV) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_SV;
if (flags & adsp21062_device::ASTAT_FLAGS::SZ) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_SZ;
if (flags & adsp21062_device::ASTAT_FLAGS::BTF) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_BTF;
}
}
if (loop.end_pc == desc.pc)
{
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = loop.start_pc;
if (loop.type == LOOP_TYPE_COUNTER)
{
desc.userflags |= OP_USERFLAG_COUNTER_LOOP;
}
else if (loop.type == LOOP_TYPE_CONDITIONAL)
{
desc.userflags |= OP_USERFLAG_COND_LOOP;
desc.userflags |= (loop.condition << 2) & OP_USERFLAG_COND_FIELD;
}
m_loop.erase(m_loop.begin()+i);
break;
}
}
}*/
if (is_astat_delay_check(desc.pc))
{
LOOP_ENTRY* map = m_loopmap.get();
int index = desc.pc & 0x1ffff;
if (map[index].looptype == LOOP_TYPE_CONDITIONAL)
{
UINT32 flags = m_sharc->do_condition_astat_bits(map[index].condition);
if (flags & adsp21062_device::ASTAT_FLAGS::AZ) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AZ;
if (flags & adsp21062_device::ASTAT_FLAGS::AN) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AN;
if (flags & adsp21062_device::ASTAT_FLAGS::AV) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AV;
if (flags & adsp21062_device::ASTAT_FLAGS::AC) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_AC;
if (flags & adsp21062_device::ASTAT_FLAGS::MN) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_MN;
if (flags & adsp21062_device::ASTAT_FLAGS::MV) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_MV;
if (flags & adsp21062_device::ASTAT_FLAGS::SV) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_SV;
if (flags & adsp21062_device::ASTAT_FLAGS::SZ) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_SZ;
if (flags & adsp21062_device::ASTAT_FLAGS::BTF) desc.userflags |= OP_USERFLAG_ASTAT_DELAY_COPY_BTF;
}
}
if (is_loop_start(desc.pc))
{
desc.flags |= OPFLAG_IS_BRANCH_TARGET;
}
if (is_loop_evaluation(desc.pc))
{
LOOP_ENTRY* map = m_loopmap.get();
int index = desc.pc & 0x1ffff;
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = map[index].start_pc;
if (map[index].looptype == LOOP_TYPE_COUNTER)
{
desc.userflags |= OP_USERFLAG_COUNTER_LOOP;
}
else if (map[index].looptype == LOOP_TYPE_CONDITIONAL)
{
desc.userflags |= OP_USERFLAG_COND_LOOP;
desc.userflags |= (map[index].condition << 2) & OP_USERFLAG_COND_FIELD;
}
}
switch ((opcode >> 45) & 7)
{
case 0: // subops
{
UINT32 subop = (opcode >> 40) & 0x1f;
switch (subop)
{
case 0x00: // NOP / idle |000|00000|
if (opcode & U64(0x008000000000))
{
// IDLE
desc.flags |= OPFLAG_END_SEQUENCE;
}
else
{
// NOP
}
break;
case 0x01: // compute |000|00001|
{
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
if (!describe_compute(desc, opcode))
return false;
break;
}
case 0x02: // immediate shift |000|00010|
{
int shiftop = (opcode >> 16) & 0x3f;
int rn = (opcode >> 4) & 0xf;
int rx = (opcode & 0xf);
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
if (!describe_shiftop_imm(desc, shiftop, rn, rx))
return false;
break;
}
case 0x04: // compute / modify |000|00100|
{
int g = (opcode >> 38) & 0x1;
int m = (opcode >> 27) & 0x7;
int i = (opcode >> 30) & 0x7;
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
if (!describe_compute(desc, opcode))
return false;
if (g)
{
// PM
PM_I_USED(desc, i);
PM_I_MODIFIED(desc, i);
PM_M_USED(desc, m);
}
else
{
// DM
DM_I_USED(desc, i);
DM_I_MODIFIED(desc, i);
DM_M_USED(desc, m);
}
break;
}
case 0x06: // direct jump|call |000|00110|
{
int j = (opcode >> 26) & 0x1;
int cond = (opcode >> 33) & 0x1f;
UINT32 address = opcode & 0xffffff;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
desc.targetpc = address;
desc.delayslots = (j) ? 2 : 0;
break;
}
case 0x07: // direct jump|call |000|00111|
{
int j = (opcode >> 26) & 0x1;
int cond = (opcode >> 33) & 0x1f;
UINT32 address = opcode & 0xffffff;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
desc.targetpc = desc.pc + SIGN_EXTEND24(address);
desc.delayslots = (j) ? 2 : 0;
break;
}
case 0x08: // indirect jump|call / compute |000|01000|
{
int j = (opcode >> 26) & 0x1;
int pmi = (opcode >> 30) & 0x7;
int pmm = (opcode >> 27) & 0x7;
int cond = (opcode >> 33) & 0x1f;
if (!describe_compute(desc, opcode))
return false;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
PM_I_USED(desc, pmi);
PM_M_USED(desc, pmm);
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = (j) ? 2 : 0;
break;
}
case 0x09: // indirect jump|call / compute |000|01001|
{
int j = (opcode >> 26) & 0x1;;
int cond = (opcode >> 33) & 0x1f;
if (!describe_compute(desc, opcode))
return false;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
desc.targetpc = desc.pc + SIGN_EXTEND6((opcode >> 27) & 0x3f);
desc.delayslots = (j) ? 2 : 0;
break;
}
case 0x0a: // return from subroutine / compute |000|01010|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
if (!describe_compute(desc, opcode))
return false;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = (j) ? 2 : 0;
break;
}
case 0x0b: // return from interrupt / compute |000|01011|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
if (!describe_compute(desc, opcode))
return false;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = (j) ? 2 : 0;
break;
}
case 0x0c: // do until counter expired |000|01100|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
LOOP_DESCRIPTOR loop;
loop.start_pc = desc.pc + 1;
loop.end_pc = desc.pc + offset;
loop.astat_check_pc = 0xffffffff;
loop.type = LOOP_TYPE_COUNTER;
loop.condition = 0;
insert_loop(loop);
break;
}
case 0x0d: // do until counter expired |000|01101|
{
int ureg = (opcode >> 32) & 0xff;
if (!describe_ureg_access(desc, ureg, UREG_READ))
return false;
int offset = SIGN_EXTEND24(opcode & 0xffffff);
LOOP_DESCRIPTOR loop;
loop.start_pc = desc.pc + 1;
loop.end_pc = desc.pc + offset;
loop.astat_check_pc = 0xffffffff;
loop.type = LOOP_TYPE_COUNTER;
loop.condition = 0;
insert_loop(loop);
break;
}
case 0x0e: // do until |000|01110|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
int cond = (opcode >> 33) & 0x1f;
LOOP_DESCRIPTOR loop;
loop.start_pc = desc.pc + 1;
loop.end_pc = desc.pc + offset;
loop.type = LOOP_TYPE_CONDITIONAL;
loop.condition = cond;
loop.astat_check_pc = loop.end_pc - 2;
if (loop.astat_check_pc < loop.start_pc)
fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc);
insert_loop(loop);
break;
}
case 0x0f: // immediate data -> ureg |000|01111|
{
int ureg = (opcode >> 32) & 0xff;
if (!describe_ureg_access(desc, ureg, UREG_WRITE))
return false;
break;
}
case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
case 0x11:
case 0x12:
case 0x13:
{
int ureg = (opcode >> 32) & 0xff;
int d = (opcode >> 40) & 1;
if (d)
{
if (!describe_ureg_access(desc, ureg, UREG_READ))
return false;
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
if (!describe_ureg_access(desc, ureg, UREG_WRITE))
return false;
desc.flags |= OPFLAG_READS_MEMORY;
}
break;
}
case 0x14: // system register bit manipulation |000|10100|
{
int bop = (opcode >> 37) & 0x7;
int sreg = (opcode >> 32) & 0xf;
UINT32 data = (UINT32)(opcode);
switch (bop)
{
case 0: // SET
case 1: // CLEAR
case 2: // TOGGLE
if (sreg == 0x7c) // ASTAT
{
if (data & adsp21062_device::AZ)
{
AZ_USED(desc); AZ_MODIFIED(desc);
}
if (data & adsp21062_device::AV)
{
AV_USED(desc); AV_MODIFIED(desc);
}
if (data & adsp21062_device::AN)
{
AN_USED(desc); AN_MODIFIED(desc);
}
if (data & adsp21062_device::AC)
{
AC_USED(desc); AC_MODIFIED(desc);
}
if (data & adsp21062_device::AS)
{
AS_USED(desc); AS_MODIFIED(desc);
}
if (data & adsp21062_device::AI)
{
AI_USED(desc); AI_MODIFIED(desc);
}
if (data & adsp21062_device::MN)
{
MN_USED(desc); MN_MODIFIED(desc);
}
if (data & adsp21062_device::MV)
{
MV_USED(desc); MV_MODIFIED(desc);
}
if (data & adsp21062_device::MU)
{
MU_USED(desc); MU_MODIFIED(desc);
}
if (data & adsp21062_device::MI)
{
MI_USED(desc); MI_MODIFIED(desc);
}
if (data & adsp21062_device::SV)
{
SV_USED(desc); SV_MODIFIED(desc);
}
if (data & adsp21062_device::SZ)
{
SZ_USED(desc); SZ_MODIFIED(desc);
}
if (data & adsp21062_device::SS)
{
SS_USED(desc); SS_MODIFIED(desc);
}
if (data & adsp21062_device::BTF)
{
BTF_USED(desc); BTF_MODIFIED(desc);
}
if (data & adsp21062_device::AF)
{
AF_USED(desc); AF_MODIFIED(desc);
}
}
break;
case 4: // TEST
case 5: // XOR
BTF_MODIFIED(desc);
break;
default:
fatalerror("sharc_frontend::describe: system reg bit manipulation %d", bop);
return false;
}
break;
}
case 0x16: // I register modify / bit-reverse |000|10110|
{
if (opcode & U64(0x008000000000)) // bit reverse
{
fatalerror("sharc_frontend::describe: bit reverse unimplemented");
}
else // modify
{
int g = (opcode >> 38) & 0x1;
int i = (opcode >> 32) & 0x7;
if (g)
PM_I_USED(desc, i);
else
DM_I_USED(desc, i);
}
break;
}
case 0x17: // push|pop stacks / flush cache |000|10111|
break;
case 0x18: // cjump |000|11000|
fatalerror("sharc_frontend::describe: cjump unimplemented");
break;
case 0x19: // rframe |000|11001|
fatalerror("sharc_frontend::describe: rframe unimplemented");
break;
default:
fatalerror("sharc_frontend::describe: unknown subop %02X in opcode %04X%08X", subop, (UINT16)(opcode >> 32), (UINT32)(opcode));
return false;
}
break;
}
case 1: // compute / dreg <-> DM / dreg <-> PM |001|
{
if (!describe_compute(desc, opcode))
return false;
int pm_dreg = (opcode >> 23) & 0xf;
int pmm = (opcode >> 27) & 0x7;
int pmi = (opcode >> 30) & 0x7;
int dm_dreg = (opcode >> 33) & 0xf;
int dmm = (opcode >> 38) & 0x7;
int dmi = (opcode >> 41) & 0x7;
int pmd = (opcode >> 37) & 0x1;
int dmd = (opcode >> 44) & 0x1;
PM_I_USED(desc, pmi);
PM_I_MODIFIED(desc, pmi);
PM_M_USED(desc, pmm);
if (pmd)
{
REG_USED(desc, pm_dreg);
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
REG_MODIFIED(desc, pm_dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
DM_I_USED(desc, dmi);
DM_I_MODIFIED(desc, dmi);
DM_M_USED(desc, dmm);
if (dmd)
{
REG_USED(desc, dm_dreg);
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
REG_MODIFIED(desc, dm_dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
break;
}
case 2: // compute / ureg <-> DM|PM, register modify |010|
{
if (!describe_compute(desc, opcode))
return false;
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
int cond = (opcode >> 33) & 0x1f;
int g = (opcode >> 32) & 0x1;
int d = (opcode >> 31) & 0x1;
int ureg = (opcode >> 23) & 0xff;
describe_if_condition(desc, cond);
if (d)
{
if (!describe_ureg_access(desc, ureg, UREG_READ))
return false;
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
if (!describe_ureg_access(desc, ureg, UREG_WRITE))
return false;
desc.flags |= OPFLAG_READS_MEMORY;
}
if (g)
{
// PM
PM_I_USED(desc, i);
PM_M_USED(desc, m);
}
else
{
// DM
DM_I_USED(desc, i);
DM_M_USED(desc, m);
}
break;
}
case 3:
{
if (!describe_compute(desc, opcode))
return false;
if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
{
int src_ureg = (opcode >> 36) & 0xff;
int dst_ureg = (opcode >> 23) & 0xff;
int cond = (opcode >> 31) & 0x1f;
describe_if_condition(desc, cond);
if (!describe_ureg_access(desc, src_ureg, UREG_READ))
return false;
if (!describe_ureg_access(desc, dst_ureg, UREG_WRITE))
return false;
}
else // compute / dreg <-> DM|PM, immediate modify |011|0|
{
int u = (opcode >> 38) & 0x1;
int d = (opcode >> 39) & 0x1;
int g = (opcode >> 40) & 0x1;
int dreg = (opcode >> 23) & 0xf;
int i = (opcode >> 41) & 0x7;
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
if (d)
{
REG_USED(desc, dreg);
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
REG_MODIFIED(desc, dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
if (g)
{
// PM
PM_I_USED(desc, i);
if (u) // post-modify with update
{
PM_I_MODIFIED(desc, i);
}
}
else
{
// DM
DM_I_USED(desc, i);
if (u) // post-modify with update
{
DM_I_MODIFIED(desc, i);
}
}
}
break;
}
case 4:
{
if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
int g = (opcode >> 37) & 0x1;
desc.flags |= OPFLAG_WRITES_MEMORY;
if (g)
{
// PM
PM_I_USED(desc, i);
PM_I_MODIFIED(desc, i);
PM_M_USED(desc, m);
}
else
{
// DM
DM_I_USED(desc, i);
DM_I_MODIFIED(desc, i);
DM_M_USED(desc, m);
}
}
else // immediate shift / dreg <-> DM|PM |100|0|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
int g = (opcode >> 32) & 0x1;
int d = (opcode >> 31) & 0x1;
int dreg = (opcode >> 23) & 0xf;
int shiftop = (opcode >> 16) & 0x3f;
int rn = (opcode >> 4) & 0xf;
int rx = (opcode & 0xf);
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
if (!describe_shiftop_imm(desc, shiftop, rn, rx))
return false;
if (d)
{
REG_USED(desc, dreg);
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
REG_MODIFIED(desc, dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
if (g)
{
// PM
PM_I_USED(desc, i);
PM_I_MODIFIED(desc, i);
PM_M_USED(desc, m);
}
else
{
// DM
DM_I_USED(desc, i);
DM_I_MODIFIED(desc, i);
DM_M_USED(desc, m);
}
}
break;
}
case 5: // ureg <-> DM|PM (indirect) |101|
{
int ureg = (opcode >> 32) & 0xff;
int d = (opcode >> 40) & 1;
int i = (opcode >> 41) & 0x7;
int g = (opcode >> 44) & 1;
if (d)
{
if (!describe_ureg_access(desc, ureg, UREG_READ))
return false;
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
if (!describe_ureg_access(desc, ureg, UREG_WRITE))
return false;
desc.flags |= OPFLAG_READS_MEMORY;
}
if (g)
PM_I_USED(desc, i);
else
DM_I_USED(desc, i);
break;
}
case 6: // indirect jump / compute / dreg <-> DM |110|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
int dmm = (opcode >> 38) & 0x7;
int pmi = (opcode >> 30) & 0x7;
int pmm = (opcode >> 27) & 0x7;
int cond = (opcode >> 33) & 0x1f;
int dreg = (opcode >> 23) & 0xf;
if (!describe_compute(desc, opcode))
return false;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
PM_I_USED(desc, pmi);
PM_M_USED(desc, pmm);
DM_I_USED(desc, dmi);
DM_I_MODIFIED(desc, dmi);
DM_M_USED(desc, dmm);
if (d)
{
REG_USED(desc, dreg);
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
REG_MODIFIED(desc, dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 0;
break;
}
case 7: // indirect jump / compute / dreg <-> DM |111|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
int dmm = (opcode >> 38) & 0x7;
int cond = (opcode >> 33) & 0x1f;
int dreg = (opcode >> 23) & 0xf;
if (!describe_compute(desc, opcode))
return false;
if (m_sharc->if_condition_always_true(cond))
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
else
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
describe_if_condition(desc, cond);
DM_I_USED(desc, dmi);
DM_I_MODIFIED(desc, dmi);
DM_M_USED(desc, dmm);
if (d)
{
REG_USED(desc, dreg);
desc.flags |= OPFLAG_WRITES_MEMORY;
}
else
{
REG_MODIFIED(desc, dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
desc.targetpc = desc.pc + SIGN_EXTEND6((opcode >> 27) & 0x3f);
desc.delayslots = 0;