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performance.s
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performance.s
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//
// performance.s
// CPU Dasher
//
// Created by zenny_chen on 12-9-12.
//
//
.text
.align 2
.globl _neonInt64x64, _neonInt128x128, _neonInt256x256, _neonInt512x512, _neonInt1024x1024
.globl _neonFloat64x64, _neonFloat128x128, _neonFloat256x256, _neonFloat512x512, _neonFloat1024x1024
.globl _duoInt64x64, _duoInt128x128, _duoInt256x256, _duoInt512x512, _duoInt1024x1024
.globl _duoFloat64x64, _duoFloat128x128, _duoFloat256x256, _duoFloat512x512, _duoFloat1024x1024
.globl _normalInt64x64, _normalInt128x128, _normalInt256x256, _normalInt512x512, _normalInt1024x1024
.globl _normalFloat64x64, _normalFloat128x128, _normalFloat256x256, _normalFloat512x512, _normalFloat1024x1024
_neonInt64x64:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(64 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonInt64x64_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
mov r6, r3
mov r7, #4 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonInt64x64_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonInt64x64_BUFFERING
// One col to all rows
mov r9, r0 // input 1
mov r6, #64 // row loop count
neonInt64x64_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #2 // mult loop count
veor q8, q8, q8 // for accumulation
neonInt64x64_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.s32 q0, q0, q4
vmul.s32 q1, q1, q5
vld1.64 {d18, d19, d20, d21}, [r4, :256]!
vmla.s32 q0, q2, q6
vmla.s32 q1, q3, q7
vld1.64 {d22, d23, d24, d25}, [r9, :256]!
vadd.s32 q8, q8, q0
vld1.64 {d8, d9, d10, d11}, [r4, :256]!
vmul.s32 q9, q9, q11
vmul.s32 q10, q10, q12
vadd.s32 q8, q8, q1
vld1.64 {d0, d1, d2, d3}, [r9, :256]!
vmla.s32 q9, q4, q0
vmla.s32 q10, q5, q1
vadd.s32 q8, q8, q9
subs r7, r7, #1
vadd.s32 q8, q8, q10
bne neonInt64x64_ONECOL_ONEROW
vpadd.i32 d0, d16, d17
subs r6, r6, #1
vmov.32 r8, d0[0]
vmov.32 r14, d0[1]
add r8, r8, r14
str r8, [r10], r5 // write to destination matrix
bne neonInt64x64_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #64
bne neonInt64x64_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonInt128x128:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(128 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonInt128x128_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
// preload
pld [r4]
mov r6, r3
mov r7, #8 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonInt128x128_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
// preload
pld [r4]
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonInt128x128_BUFFERING
// preload
pld [r0]
pld [r3]
// One col to all rows
mov r9, r0 // input 1
mov r6, #128 // row loop count
neonInt128x128_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #4 // mult loop count
veor q8, q8, q8 // for accumulation
neonInt128x128_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.s32 q0, q0, q4
vmul.s32 q1, q1, q5
vld1.64 {d18, d19, d20, d21}, [r4, :256]!
vmla.s32 q0, q2, q6
vmla.s32 q1, q3, q7
vld1.64 {d22, d23, d24, d25}, [r9, :256]!
vadd.s32 q8, q8, q0
vld1.64 {d8, d9, d10, d11}, [r4, :256]!
vmul.s32 q9, q9, q11
vmul.s32 q10, q10, q12
vadd.s32 q8, q8, q1
vld1.64 {d0, d1, d2, d3}, [r9, :256]!
vmla.s32 q9, q4, q0
vmla.s32 q10, q5, q1
vadd.s32 q8, q8, q9
subs r7, r7, #1
vadd.s32 q8, q8, q10
bne neonInt128x128_ONECOL_ONEROW
vpadd.i32 d0, d16, d17
subs r6, r6, #1
vmov.32 r8, d0[0]
vmov.32 r14, d0[1]
add r8, r8, r14
str r8, [r10], r5 // write to destination matrix
bne neonInt128x128_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #128
bne neonInt128x128_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonInt256x256:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(256 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonInt256x256_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
// preload
pld [r4]
mov r6, r3
mov r7, #16 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonInt256x256_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
// preload
pld [r4]
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonInt256x256_BUFFERING
// preload
pld [r0]
pld [r3]
// One col to all rows
mov r9, r0 // input 1
mov r6, #256 // row loop count
neonInt256x256_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #8 // mult loop count
veor q8, q8, q8 // for accumulation
neonInt256x256_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.s32 q0, q0, q4
vmul.s32 q1, q1, q5
vld1.64 {d18, d19, d20, d21}, [r4, :256]!
vmla.s32 q0, q2, q6
vmla.s32 q1, q3, q7
vld1.64 {d22, d23, d24, d25}, [r9, :256]!
vadd.s32 q8, q8, q0
vld1.64 {d8, d9, d10, d11}, [r4, :256]!
vmul.s32 q9, q9, q11
vmul.s32 q10, q10, q12
vadd.s32 q8, q8, q1
vld1.64 {d0, d1, d2, d3}, [r9, :256]!
vmla.s32 q9, q4, q0
vmla.s32 q10, q5, q1
vadd.s32 q8, q8, q9
subs r7, r7, #1
vadd.s32 q8, q8, q10
bne neonInt256x256_ONECOL_ONEROW
vpadd.i32 d0, d16, d17
subs r6, r6, #1
vmov.32 r8, d0[0]
vmov.32 r14, d0[1]
add r8, r8, r14
str r8, [r10], r5 // write to destination matrix
bne neonInt256x256_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #256
bne neonInt256x256_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonInt512x512:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(512 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonInt512x512_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
// preload
pld [r4]
mov r6, r3
mov r7, #32 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonInt512x512_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
// preload
pld [r4]
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonInt512x512_BUFFERING
// preload
pld [r0]
pld [r3]
// One col to all rows
mov r9, r0 // input 1
mov r6, #512 // row loop count
neonInt512x512_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #16 // mult loop count
veor q8, q8, q8 // for accumulation
neonInt512x512_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.s32 q0, q0, q4
vmul.s32 q1, q1, q5
vld1.64 {d18, d19, d20, d21}, [r4, :256]!
vmla.s32 q0, q2, q6
vmla.s32 q1, q3, q7
vld1.64 {d22, d23, d24, d25}, [r9, :256]!
vadd.s32 q8, q8, q0
vld1.64 {d8, d9, d10, d11}, [r4, :256]!
vmul.s32 q9, q9, q11
vmul.s32 q10, q10, q12
vadd.s32 q8, q8, q1
vld1.64 {d0, d1, d2, d3}, [r9, :256]!
vmla.s32 q9, q4, q0
vmla.s32 q10, q5, q1
vadd.s32 q8, q8, q9
subs r7, r7, #1
vadd.s32 q8, q8, q10
bne neonInt512x512_ONECOL_ONEROW
vpadd.i32 d0, d16, d17
subs r6, r6, #1
vmov.32 r8, d0[0]
vmov.32 r14, d0[1]
add r8, r8, r14
str r8, [r10], r5 // write to destination matrix
bne neonInt512x512_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #512
bne neonInt512x512_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonInt1024x1024:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(1024 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonInt1024x1024_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
mov r6, r3
mov r7, #64 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonInt1024x1024_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonInt1024x1024_BUFFERING
// One col to all rows
mov r9, r0 // input 1
mov r6, #1024 // row loop count
neonInt1024x1024_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #32 // mult loop count
veor q8, q8, q8 // for accumulation
neonInt1024x1024_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.s32 q0, q0, q4
vmul.s32 q1, q1, q5
vld1.64 {d18, d19, d20, d21}, [r4, :256]!
vmla.s32 q0, q2, q6
vmla.s32 q1, q3, q7
vld1.64 {d22, d23, d24, d25}, [r9, :256]!
vadd.s32 q8, q8, q0
vld1.64 {d8, d9, d10, d11}, [r4, :256]!
vmul.s32 q9, q9, q11
vmul.s32 q10, q10, q12
vadd.s32 q8, q8, q1
vld1.64 {d0, d1, d2, d3}, [r9, :256]!
vmla.s32 q9, q4, q0
vmla.s32 q10, q5, q1
vadd.s32 q8, q8, q9
subs r7, r7, #1
vadd.s32 q8, q8, q10
bne neonInt1024x1024_ONECOL_ONEROW
vpadd.i32 d0, d16, d17
subs r6, r6, #1
vmov.32 r8, d0[0]
vmov.32 r14, d0[1]
add r8, r8, r14
str r8, [r10], r5 // write to destination matrix
bne neonInt1024x1024_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #1024
bne neonInt1024x1024_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonFloat64x64:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(64 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonFloat64x64_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
mov r6, r3
mov r7, #4 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonFloat64x64_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonFloat64x64_BUFFERING
// One col to all rows
mov r9, r0 // input 1
mov r6, #64 // row loop count
neonFloat64x64_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #4 // mult loop count
veor q8, q8, q8 // for accumulation
neonFloat64x64_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.f32 q0, q0, q4
vmul.f32 q1, q1, q5
vmla.f32 q0, q2, q6
vmla.f32 q1, q3, q7
subs r7, r7, #1
vadd.f32 q0, q0, q1
vadd.f32 q8, q8, q0 // accumulate values
bne neonFloat64x64_ONECOL_ONEROW
vpadd.f32 d0, d16, d17
subs r6, r6, #1
vadd.f32 s0, s0, s1
vmov.32 r8, d0[0]
str r8, [r10], r5 // write to destination matrix
bne neonFloat64x64_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #64
bne neonFloat64x64_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonFloat128x128:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(128 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonFloat128x128_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
mov r6, r3
mov r7, #8 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonFloat128x128_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonFloat128x128_BUFFERING
// One col to all rows
mov r9, r0 // input 1
mov r6, #128 // row loop count
neonFloat128x128_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #8 // mult loop count
veor q8, q8, q8 // for accumulation
neonFloat128x128_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.f32 q0, q0, q4
vmul.f32 q1, q1, q5
vmla.f32 q0, q2, q6
vmla.f32 q1, q3, q7
subs r7, r7, #1
vadd.f32 q0, q0, q1
vadd.f32 q8, q8, q0 // accumulate values
bne neonFloat128x128_ONECOL_ONEROW
vpadd.f32 d0, d16, d17
subs r6, r6, #1
vadd.f32 s0, s0, s1
vmov.32 r8, d0[0]
str r8, [r10], r5 // write to destination matrix
bne neonFloat128x128_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #128
bne neonFloat128x128_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonFloat256x256:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(256 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonFloat256x256_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
mov r6, r3
mov r7, #16 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonFloat256x256_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5
subs r7, r7, #1
vst1.64 {d0, d1, d2, d3}, [r6, :256]!
vst1.64 {d4, d5, d6, d7}, [r6, :256]!
bne neonFloat256x256_BUFFERING
// One col to all rows
mov r9, r0 // input 1
mov r6, #256 // row loop count
neonFloat256x256_ONE_WHOLE_ROW:
mov r4, r3 // buffer
mov r7, #16 // mult loop count
veor q8, q8, q8 // for accumulation
neonFloat256x256_ONECOL_ONEROW:
vld1.64 {d0, d1, d2, d3}, [r4, :256]!
vld1.64 {d4, d5, d6, d7}, [r4, :256]!
vld1.64 {d8, d9, d10, d11}, [r9, :256]!
vld1.64 {d12, d13, d14, d15}, [r9, :256]!
vmul.f32 q0, q0, q4
vmul.f32 q1, q1, q5
vmla.f32 q0, q2, q6
vmla.f32 q1, q3, q7
subs r7, r7, #1
vadd.f32 q0, q0, q1
vadd.f32 q8, q8, q0 // accumulate values
bne neonFloat256x256_ONECOL_ONEROW
vpadd.f32 d0, d16, d17
subs r6, r6, #1
vadd.f32 s0, s0, s1
vmov.32 r8, d0[0]
str r8, [r10], r5 // write to destination matrix
bne neonFloat256x256_ONE_WHOLE_ROW
add r12, r12, #1
cmp r12, #256
bne neonFloat256x256_ALL_COL_LOOP
vpop.64 {d8-d15}
pop {r4-r10, pc}
_neonFloat512x512:
push {r4-r10, lr}
vpush.64 {d8-d15}
mov r5, #(512 * 4) // r5: the constant
mov r12, #0 // total column loop count
// All column loop
neonFloat512x512_ALL_COL_LOOP:
// Memory Access optimization
add r4, r1, r12, LSL #2
mov r6, r3
mov r7, #32 // loop count
add r10, r2, r12, LSL #2 // the current output buffer address
neonFloat512x512_BUFFERING:
vldr.32 s0, [r4]
add r4, r4, r5
vldr.32 s1, [r4]
add r4, r4, r5
vldr.32 s2, [r4]
add r4, r4, r5
vldr.32 s3, [r4]
add r4, r4, r5
vldr.32 s4, [r4]
add r4, r4, r5
vldr.32 s5, [r4]
add r4, r4, r5
vldr.32 s6, [r4]
add r4, r4, r5
vldr.32 s7, [r4]
add r4, r4, r5
vldr.32 s8, [r4]
add r4, r4, r5
vldr.32 s9, [r4]
add r4, r4, r5
vldr.32 s10, [r4]
add r4, r4, r5
vldr.32 s11, [r4]
add r4, r4, r5
vldr.32 s12, [r4]
add r4, r4, r5
vldr.32 s13, [r4]
add r4, r4, r5
vldr.32 s14, [r4]
add r4, r4, r5
vldr.32 s15, [r4]
add r4, r4, r5