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AArch64 special register designations Change range of o0 to [0, 3] #342

Merged
merged 2 commits into from
Oct 28, 2024
Merged

AArch64 special register designations Change range of o0 to [0, 3] #342

merged 2 commits into from
Oct 28, 2024

Commits on Sep 26, 2024

  1. AArch64 special register designations: Change range of o0 to [0, 3] 

    The documented syntax doesn't allow designation of all possible special registers (e.g. "ICC_CTLR_EL3" designated with "3:6:12:12:4").

clang supports the documented syntax but not gcc.

Both compilers support an alternative syntax with <o0> in [0, 3]: `s<o0>_<o1>_c<CRm>_c<CRn>_<o2>`.
    @v01dXYZ
    v01dXYZ authored and v01dxyz committed Sep 26, 2024
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Commits on Oct 28, 2024

  1. Merge branch 'main' into patch-1

    @vhscampos
    vhscampos authored Oct 28, 2024
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