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Updated drivers to SDK to 2.9.1
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@s-bruce13
s-bruce13 committed May 7, 2021
1 parent 376fda5 commit 0f4bc86
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Showing 33 changed files with 37,458 additions and 24,582 deletions.
1 change: 0 additions & 1 deletion targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ target_sources(mbed-mimxrt1170-evk
device/system_MIMXRT1176_cm7.c

drivers/fsl_anatop_ai.c
drivers/fsl_anatop.c
drivers/fsl_cache.c
drivers/fsl_clock.c
drivers/fsl_common.c
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800 changes: 728 additions & 72 deletions targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c
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216 changes: 145 additions & 71 deletions targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright 2018-2019 NXP
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
Expand All @@ -13,29 +13,11 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#if (defined(CPU_MIMXRT1171AVM8A) || \
defined(CPU_MIMXRT1172AVM8A) || \
defined(CPU_MIMXRT1175AVM8A_cm7) || defined(CPU_MIMXRT1175AVM8A_cm4) || \
defined(CPU_MIMXRT1176AVM8A_cm7) || defined(CPU_MIMXRT1176AVM8A_cm4))
#define AUTOMOTIVE_SERIES
#elif (defined(CPU_MIMXRT1171CVM8A) || \
defined(CPU_MIMXRT1172CVM8A) || \
defined(CPU_MIMXRT1173CVM8A_cm7) || defined(CPU_MIMXRT1173CVM8A_cm4) || \
defined(CPU_MIMXRT1175CVM8A_cm7) || defined(CPU_MIMXRT1175CVM8A_cm4) || \
defined(CPU_MIMXRT1176CVM8A_cm7) || defined(CPU_MIMXRT1176CVM8A_cm4))
#define INDUSTRIAL_SERIES
#elif (defined(CPU_MIMXRT1171DVMAA) || \
defined(CPU_MIMXRT1172DVMAA) || \
defined(CPU_MIMXRT1175DVMAA_cm7) || defined(CPU_MIMXRT1175DVMAA_cm4) || \
defined(CPU_MIMXRT1176DVMAA_cm7) || defined(CPU_MIMXRT1176DVMAA_cm4))
#define CONSUMER_SERIES
#else
#error "No valid CPU defined!"
#endif

#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */

#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */

/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
Expand All @@ -60,57 +42,148 @@ void BOARD_InitBootClocks(void);
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
#if __CORTEX_M == 7
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
#else
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
#endif

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL


/*******************************************************************************
* API for BOARD_BootClockRUN configuration
Expand All @@ -129,4 +202,5 @@ void BOARD_BootClockRUN(void);
}
#endif /* __cplusplus*/

#endif /* _FSL_CLOCK_CONFIG_H_ */
#endif /* _CLOCK_CONFIG_H_ */

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3 comments on commit 0f4bc86

@stongliang
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Hello,I am using the 1170 MIMXRT1170-EVK board. I can not find the Board by "select platform"->"add board".

@0xc0170
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Hello,I am using the 1170 MIMXRT1170-EVK board. I can not find the Board by "select platform"->"add board".

@s-bruce13 was this target already enabled for 6.11 ?

@s-bruce13
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@0xc0170 I believe when the pull request was merged it was 6.10.0.

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