Merge pull request #14724 from jeromecoutant/PR_G0PWR

STM32G0: correct voltage scaling control
ARMmbed · Jun 2, 2021 · d3ba2e1 · d3ba2e1
2 parents 0738aab + cadc328
commit d3ba2e1
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diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c
@@ -99,6 +99,7 @@ uint8_t SetSysClock_PLL_HSI(void)
 
     /** Configure the main internal regulator output voltage
     */
+    __HAL_RCC_PWR_CLK_ENABLE();
     HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
     /** Initializes the CPU, AHB and APB busses clocks
     */

diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c
@@ -97,6 +97,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 
     /** Configure the main internal regulator output voltage
     */
+    __HAL_RCC_PWR_CLK_ENABLE();
     HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
     /** Initializes the CPU, AHB and APB busses clocks
     */
@@ -139,6 +140,7 @@ uint8_t SetSysClock_PLL_HSI(void)
 
     /** Configure the main internal regulator output voltage
     */
+    __HAL_RCC_PWR_CLK_ENABLE();
     HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
     /** Initializes the CPU, AHB and APB busses clocks
     */