Mts 001 mtdot clk fix #15291
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Mts 001 mtdot clk fix #15291
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ciarmcom
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release-type: patch
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@reissjason, thank you for your changes. |
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| RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; | ||
| RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000; // VCO input clock = 2 MHz (8 MHz / 4) |
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Minor: comment is wrong
| RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) | ||
| #endif /* DEVICE_USBDEVICE */ | ||
| RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz or 96 MHz (depending on DEVICE_USBDEVICE) | ||
| RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (DEVICE_USBDEVICE=1) |
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Should be 4 to get 48MHz
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Is there a way to be able to update the PLLM, PLLQ and PLLP values of the original to accommodate the 26MHz external clock without affecting current other F411RE users?
@jeromecoutant Would you want me to submit a new PR with a change to the F411xE/system_clock.c to add the HSE_VALUE setting? And also include the comment change and PLLQ update to our system_clock.c
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Jun 8, 2022
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0xc0170
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Jun 10, 2022
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mbedmain
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release-version: 6.16.0
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Summary of changes
By default internal clock was being use and the external clock source could not be set to 26MHz using mbed_app.json.
The MTS_MDOT_F411RE will always have and external crystal available so it should be used as the default clock source.
Impact of changes
Migration actions required
Documentation
Pull request type
Test results
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