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Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board

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Created by: Angelo Jacobo
Date: October 28,2021

image

Materials:

OV7670_ULX3S

Two ways to run this design on your ULX3S FPGA Board:

  • Using Icestudio GUI
  • Using the FPGA Opensource Toolchain (Yosys+Nexpnr+Fujprog)

1. Using Icestudio GUI

  1. Install Icestudio
  2. Clone this repository on your desired directory:
    git clone https://github.com/AngeloJacobo/ULX3S_FPGA_Camera_Streaming.git
  3. Run OV7670_ULX3S.ice
  4. Click Tools>Build
  5. Click Tools>Upload
  6. Done!

2. Using the FPGA OpenSource Toolchain (Yosys+Nextpnr+Fujprog)

  1. Clone this repository on your desired directory:
    git clone https://github.com/AngeloJacobo/ULX3S_FPGA_Camera_Streaming.git
  2. Run make sram (or make flash if you want to download it directly to flash)
  3. Done!

If you do not yet have the FPGA opensource tools installed:

  1. Download the latest release of oss-cad-suite that matches your OS
  2. Follow the installation guide.
  3. Check if you can now call yosys , nextpnr-ecp5 , and fujprog on bash. If command not found, just add the directories of the oss-cad-suite/bin , oss-cad-suite/lib , and oss-cad-suite/py3bin to PATH.

About:

This project is ported from my previous design FPGA_OV7670_Camera_Interface that uses Spartan 6 FPGA Board. This design uses an HDMI interface instead of VGA. The OV7670 camera is a 0.3 Megapixel camera(640x480 @ 30fps). Data pixels are stored to SDRAM and retrieved by the HDMI which will then be displayed on the monitor.

  • btn3 - increase brightness
  • btn4 - decrease brightness
  • btn6 - increase contrast
  • btn5 - decrease contrast

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Connect with me at my linkedin: https://www.linkedin.com/in/angelo-jacobo/

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Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board

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