m1n1.hv: Improve context printout

Make the addresses virtual, add symbols

Signed-off-by: Hector Martin <[email protected]>

proxyclient/m1n1/asm.py

@@ -85,7 +85,10 @@ def disassemble(self):
         output = self._get(OBJDUMP, f"-zd {self.elffile}")
 
         for line in output.split("\n"):
-            if not line or line[0] != " ":
+            if not line or line.startswith("/"):
+                continue
+            sl = line.split()
+            if not sl or sl[0][-1] != ":":
                 continue
             yield line
 

proxyclient/m1n1/hv/__init__.py

@@ -615,6 +615,13 @@ def sym(self, addr):
 
         return self.symbols[idx]
 
+    def get_sym(self, addr):
+        a, name = self.sym(addr)
+        if addr == a:
+            return name
+        else:
+            return None
+
     def handle_msr(self, ctx, iss=None):
         if iss is None:
             iss = ctx.esr.ISS
@@ -734,7 +741,7 @@ def handle_hvc(self, ctx):
             if far is not None:
                 self.log(f"     FAR={self.addr(far)}")
             if elr_phys:
-                self.u.disassemble_at(elr_phys - 4 * 4, 9 * 4, elr_phys)
+                self.u.disassemble_at(elr_phys - 4 * 4, 9 * 4, elr - 4 * 4, elr, sym=self.get_sym)
             if self.sym(elr)[1] == "com.apple.kernel:_panic_trap_to_debugger":
                 self.log("Panic! Trying to decode panic...")
                 try:
@@ -905,7 +912,7 @@ def handle_exception(self, reason, code, info):
                     handled = self.handle_sync(ctx)
                 elif code == EXC.FIQ:
                     self.u.msr(CNTV_CTL_EL0, 0)
-                    self.u.print_context(ctx, False)
+                    self.u.print_context(ctx, False, sym=self.get_sym)
                     handled = True
             elif reason == START.HV:
                 code = HV_EVENT(code)
@@ -926,7 +933,7 @@ def handle_exception(self, reason, code, info):
         else:
             self.log(f"Guest exception: {reason.name}/{code.name}")
             self.update_pac_mask()
-            self.u.print_context(ctx, self.is_fault)
+            self.u.print_context(ctx, self.is_fault, sym=self.get_sym)
 
         if self._sigint_pending or not handled or user_interrupt:
             self._sigint_pending = False
@@ -1129,7 +1136,7 @@ def context(self):
         f = f" (orig: #{self.exc_orig_cpu})" if self.ctx.cpu_id != self.exc_orig_cpu else ""
         print(f"  == On CPU #{self.ctx.cpu_id}{f} ==")
         print(f"  Reason: {self.exc_reason.name}/{self.exc_code.name}")
-        self.u.print_context(self.ctx, self.is_fault)
+        self.u.print_context(self.ctx, self.is_fault, sym=self.get_sym)
 
     def bt(self, frame=None, lr=None):
         if frame is None:

proxyclient/m1n1/proxyutils.py

@@ -206,21 +206,30 @@ def push_adt(self):
         print(f"Pushing ADT ({adt_size} bytes)...")
         self.iface.writemem(adt_base, self.adt_data)
 
-    def disassemble_at(self, start, size, pc=None):
+    def disassemble_at(self, start, size, pc=None, vstart=None, sym=None):
         '''disassemble len bytes of memory from start
          optional pc address will mark that line with a '*' '''
         code = struct.unpack(f"<{size // 4}I", self.iface.readmem(start, size))
+        if vstart is None:
+            vstart = start
 
-        c = ARMAsm(".inst " + ",".join(str(i) for i in code), start)
-        lines = list(c.disassemble())
-        if pc is not None:
-            idx = (pc - start) // 4
+        c = ARMAsm(".inst " + ",".join(str(i) for i in code), vstart)
+        lines = list()
+        for line in c.disassemble():
+            sl = line.split()
             try:
-                lines[idx] = " *" + lines[idx][2:]
-            except IndexError:
-                pass
-        for i in lines:
-            print(" " + i)
+                addr = int(sl[0].rstrip(":"), 16)
+            except:
+                addr = None
+            if pc == addr:
+                line = " *" + line
+            else:
+                line = "  " + line
+            if sym:
+                if s := sym(addr):
+                    print()
+                    print(f"{' '*len(sl[0])}   {s}:")
+            print(line)
 
     def print_l2c_regs(self):
         print()
@@ -234,7 +243,7 @@ def print_l2c_regs(self):
         self.msr(L2C_ERR_STS_EL1, l2c_err_sts) # Clear the flag bits
         self.msr(DAIF, self.mrs(DAIF) | 0x100) # Re-enable SError exceptions
 
-    def print_context(self, ctx, is_fault=True, addr=lambda a: f"0x{a:x}"):
+    def print_context(self, ctx, is_fault=True, addr=lambda a: f"0x{a:x}", sym=None, num_ctx=9):
         print(f"  == Exception taken from {ctx.spsr.M.name} ==")
         el = ctx.spsr.M >> 2
         print(f"  SPSR   = {ctx.spsr}")
@@ -252,7 +261,9 @@ def print_context(self, ctx, is_fault=True, addr=lambda a: f"0x{a:x}"):
             print()
             print("  == Code context ==")
 
-            self.disassemble_at(ctx.elr_phys - 4 * 4, 9 * 4, ctx.elr_phys)
+            off = -(num_ctx // 2)
+
+            self.disassemble_at(ctx.elr_phys + 4 * off, num_ctx * 4, ctx.elr, ctx.elr + 4 * off, sym=sym)
 
         if is_fault:
             if ctx.esr.EC == ESR_EC.MSR or ctx.esr.EC == ESR_EC.IMPDEF and ctx.esr.ISS == 0x20: