Merge branch '53d010b72f072aa2ac4cfd9a9b239ac842e9d6c8' into aspeed-m…

…aster Signed-off-by: Jamin Lin <[email protected]> Change-Id: If025082191c764e69a54395a97e511555a91b192
AspeedTech-BMC · Oct 31, 2022 · a7f17f7 · a7f17f7
2 parents 7f91def + 53d010b
commit a7f17f7
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diff --git a/README.md b/README.md
@@ -29,3 +29,14 @@ west build -b ast1060_dcscm -p auto aspeed-zephyr-project/apps/aspeed-pfr
 west build -b ast1060_dual_flash -p auto aspeed-zephyr-project/apps/aspeed-pfr
 ```
 
+## AST2600 DCSCM board for AMD
+
+```
+west build -b ast1060_dcscm_amd -p auto aspeed-zephyr-project/apps/aspeed-pfr
+```
+
+## AST2600 Dual Flash for AMD
+
+```
+west build -b ast1060_dual_flash_amd -p auto aspeed-zephyr-project/apps/aspeed-pfr
+```
diff --git a/apps/aspeed-pfr/CMakeLists.txt b/apps/aspeed-pfr/CMakeLists.txt
@@ -4,8 +4,12 @@
 cmake_minimum_required(VERSION 3.13.1)
 
 find_package(Zephyr HINTS $ENV{ZEPHYR_BASE})
-project(aspeed-pfr)
+project(aspeed-pfr VERSION 01.03 LANGUAGES C)
 
+set(PROJECT_VERSION_MAJOR ${CMAKE_PROJECT_VERSION_MAJOR})
+set(PROJECT_VERSION_MINOR ${CMAKE_PROJECT_VERSION_MINOR})
+
+configure_file(build_config.h.in build_config.h)
 set(ASPEED_PFR_ROOT ${CMAKE_CURRENT_LIST_DIR})
 
 FILE(GLOB_RECURSE app_sources src/*.c)
@@ -20,6 +24,8 @@ zephyr_link_libraries(hrot_hal)
 zephyr_link_libraries(hrot_wrapper)
 zephyr_link_libraries(smf)
 zephyr_link_libraries(cerberus)
+zephyr_link_libraries(mbedTLS)
+zephyr_include_directories(mbedTLS)
 target_include_directories(
 	app
 	PRIVATE
@@ -29,5 +35,6 @@ target_include_directories(
 	${ASPEED_PFR_ROOT}/src/state_machine
 	${ZEPHYR_BASE}/include
 	${PROJECT_BINARY_DIR}/include/generated
+	${CMAKE_CURRENT_BINARY_DIR}
 )
 
diff --git a/apps/aspeed-pfr/Kconfig b/apps/aspeed-pfr/Kconfig
@@ -13,6 +13,19 @@ config BMC_DUAL_FLASH
 	help
 	  Enable if BMC has dual flash
 
+config INTEL_PFR
+	default y
+	bool "intel pfr solution"
+	help
+	  Intel PFR support
+
+config CERBERUS_PFR
+	depends on !INTEL_PFR
+	default n
+	bool "cerberus pfr solution"
+	help
+	  Cerberus PFR support
+
 config SPI_MUX_INVERSE
 	default n
 	bool "Invert SPI MUX"
@@ -31,12 +44,26 @@ config BMC_CHECKPOINT_RECOVERY
 	help
 	  Enable if BMC supports mailbox checkpoint
 
+config BMC_CHECKPOINT_EXPIRE_TIME
+	default 175000
+	int "Maximum timeout value for BMC checkpoint in mS"
+	help
+	  After system is provisioned, the watchdog will be armed during BMC
+	  booting. The expire time will be set to this number in milliseconds.
+
 config PCH_CHECKPOINT_RECOVERY
 	default n
 	bool "PCH Checkpoint timeout recovery function"
 	help
 	  Enable if PCH supports mailbox checkpoint
 
+config PCH_CHECKPOINT_EXPIRE_TIME
+	default 900000
+	int "Maximum timeout value for PCH checkpoint in mS"
+	help
+	  After system is provisioned, the watchdog will be armed during BIOS
+	  booting. The expire time will be set to this number in milliseconds.
+
 config PLATFORM_STATE_LED
 	default n
 	bool "Display platfrom state in 8 bits LED"
@@ -73,11 +100,41 @@ config PCH_STAGING_SIZE
 	help
 	  The max size of PCH staging area for putting signed PCH capsule.
 
+config BMC_PFR_STAGING_OFFSET
+	depends on CERBERUS_PFR
+	hex "PFR staging region offset in BMC flash"
+	help
+	  The starting offset of PFR staging region, and this is for Cerberus PFR provisioning.
+
 config INIT_POWER_SEQUENCE
 	default n
 	bool "Wait for CPLD power sequence to start PFR functionality"
 	help
 	  PFR state machine will stay in INIT state until CPLD power sequence releases
 	  RST_SRST_BMC_N and RST_RSMRST_N.
 
+config SEAMLESS_UPDATE
+	depends on INTEL_PFR
+	depends on !CERBERUS_PFR
+	default n
+	bool "Seamless update support"
+	help
+	  Support FVM verification and host firmware update by seamless capsule.
+	  PFR will update host firmware without going to t-1 state and rebooting host.
+
+config PIT_PROTECTION
+	depends on INTEL_PFR
+	depends on !CERBERUS_PFR
+	default n
+	bool "PIT protection support"
+	help
+	  Enable PIT protection functions and PIT mailbox commands.
+	  ROT will perform PIT check if PIT protection is enabled via mailbox command.
+
+config PFR_SW_MAILBOX
+	default n
+        bool "SW mailbox solution"
+        help
+          Enable SW mailbox support.
+
 source "Kconfig.zephyr"
diff --git a/apps/aspeed-pfr/boards/ast1060_dcscm.conf b/apps/aspeed-pfr/boards/ast1060_dcscm.conf
@@ -21,3 +21,6 @@ CONFIG_BMC_STAGING_SIZE=0x3de0000
 CONFIG_BMC_PCH_STAGING_SIZE=0x1000000
 CONFIG_BMC_PFR_STAGING_SIZE=0x500000
 CONFIG_PCH_STAGING_SIZE=0x1000000
+
+# Intel PFR 3.0
+CONFIG_SEAMLESS_UPDATE=y
diff --git a/apps/aspeed-pfr/boards/ast1060_dcscm.overlay b/apps/aspeed-pfr/boards/ast1060_dcscm.overlay
@@ -216,126 +216,12 @@
 	spi-max-buswidth = <4>;
 	spi-max-frequency = <50000000>;
 	status = "okay";
-
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* 896KB */
-		bmc_uboot_partition: partition@0 {
-			label = "bmc-uboot";
-			reg = <0x00000000 0x000e0000>;
-		};
-
-		/* 128KB */
-		bmc_pfm_partition: partition@e0000{
-			reg = <0x000e0000 0x00020000>;
-			label = "bmc-pfm";
-		};
-
-		/* 128KB */
-		bmc_ub_env_partition: partition@100000{
-			reg = <0x00100000 0x00020000>;
-			label = "bmc-ub-env";
-		};
-
-		/* 2048KB */
-		bmc_sofs_partition: partition@120000{
-			reg = <0x00120000 0x00200000>;
-			label = "bmc-sofs";
-		};
-
-		/* 18432KB */
-		bmc_rwfs_partition: partition@320000{
-			label = "bmc-rwfs";
-			reg = <0x00320000 0x01200000>;
-		};
-
-		/* 46080KB */
-		bmc_fitimg_partition: partition@1520000{
-			label = "bmc-fitimg";
-			reg = <0x01520000 0x02d00000>;
-		};
-
-		/* 63360KB */
-		bmc_rc_image_partition: partition@4220000{
-			label = "bmc-rc-image";
-			reg = <0x04220000 0x03de0000>;
-		};
-
-		/* 63360KB  */
-		bmc_stg_partition: partition@8000000{
-			label = "bmc-stg";
-			reg = <0x08000000 0x03de0000>;
-		};
-
-		/* 16384KB */
-		bmc_pch_stg_partition: partition@bde0000{
-			label = "bmc-pch-stg";
-			reg = <0x0bde0000 0x01000000>;
-		};
-
-		/* 5120KB */
-		bmc_pfr_stg_partition: partition@cde0000{
-			label = "bmc-pfr-stg";
-			reg = <0x0cde0000 0x00500000>;
-		};
-
-		/* 128KB */
-		afm_act_partition: partition@d2e0000 {
-			label = "afm-act";
-			reg = <0x0d2e0000 0x00020000>;
-		};
-
-		/* 128KB */
-		afm_rc_partition: partition@d300000 {
-			label = "afm-rc";
-			reg = <0x0d300000 0x00020000>;
-		};
-
-		/* 45952KB */
-		reserved_partition: partition@d320000 {
-			reg = <0x0d320000 0x02ce0000>;
-			label = "reserved";
-		};
-	};
 };
 
 &spi2_cs0 {
 	spi-max-buswidth = <4>;
 	spi-max-frequency = <50000000>;
 	status = "okay";
-
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* 8MB */
-		pch_active_partition: partition@0 {
-			label = "pch-act";
-			reg = <0x00000000 0x00800000>;
-		};
-
-		/* 8MB compressed pch recovery image */
-		pch_recovery_partition: partition@800000 {
-			label = "pch-rc";
-			reg = <0x00800000 0x00800000>;
-		};
-
-		/* 8MB compressed pch staging image */
-		pch_staging_partition: partition@1000000 {
-			label = "pch-stg";
-			reg = <0x01000000 0x00800000>;
-		};
-
-		/* 4MB */
-		pch_pfm_partition: partition@1800000 {
-			label = "pch-pfm";
-			reg = <0x01800000 0x00400000>;
-		};
-	};
 };
 
 &spi2_cs1 {

diff --git a/apps/aspeed-pfr/boards/ast1060_dcscm_amd.conf b/apps/aspeed-pfr/boards/ast1060_dcscm_amd.conf
@@ -0,0 +1,25 @@
+CONFIG_GPIO_ASPEED_SGPIOM=y
+CONFIG_GPIO_ASPEED=y
+CONFIG_SPI_ASPEED=y
+CONFIG_SPI_MONITOR_ASPEED=y
+CONFIG_SPI_MONITOR_SHELL_ASPEED=y
+CONFIG_SPI_NOR_ADDR_MODE_FALLBACK_DISABLED=y
+CONFIG_PFR_SHELL_ASPEED=y
+CONFIG_I2C_ASPEED=y
+CONFIG_I2C_PFR=y
+CONFIG_I2C_PFR_INIT_PRIORITY=60
+CONFIG_I2C_PFR_FILTER=y
+CONFIG_SHELL_ARGC_MAX=70
+CONFIG_WATCHDOG=y
+CONFIG_WDT_ASPEED=y
+CONFIG_UART_ASPEED=y
+CONFIG_ASPEED_DC_SCM=y
+CONFIG_PFR_SW_MAILBOX=y
+CONFIG_I2C_SWMBX_SLAVE=y
+CONFIG_PLATFORM_STATE_LED=y
+CONFIG_BMC_STAGING_SIZE=0x4000000
+CONFIG_BMC_PCH_STAGING_SIZE=0x2000000
+CONFIG_BMC_PFR_STAGING_SIZE=0x500000
+CONFIG_BMC_PFR_STAGING_OFFSET=0xe000000
+CONFIG_PCH_STAGING_SIZE=0xf10000
+