wip: clean up, athena is now a 64bits architecture

AthenaCPU · Dec 3, 2023 · d892c8f · d892c8f
1 parent fbc6b81
commit d892c8f
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Showing 37 changed files with 204 additions and 126 deletions.
diff --git a/base/basic.tex b/base/basic.tex
@@ -2,7 +2,7 @@ \chapter{Basic Architecture}
 
 \section{Addressing}
 
-The basic addressable unit is the 8-bit byte. 
+The basic addressable unit is the 8-bit byte. Virtual addresses are 64bits long.
 
 \section{Data Type}
 
@@ -29,6 +29,14 @@ \subsubsection{Word}
     \bitbox{32}{}
 \end{bytefield}
 
+\subsection{Quadword}
+
+\begin{bytefield}[%
+        bitformatting=\fakesfbits,
+        endianness=big]{16}
+    \bitheader{0-15} \\
+    \bitbox{16}{}
+\end{bytefield}
 
 \subsection{Signed Integer}
 
@@ -53,6 +61,17 @@ \subsubsection{Signed word}
     \bitbox{31}{}
 \end{bytefield}
 
+\subsubsection{Signed quadword}
+
+\begin{bytefield}[%
+    bitwidth=\widthof{\tiny ~Sign~},
+    bitformatting=\fakesfbits,
+    endianness=big]{16}
+\bitheader{0-15} \\
+ \bitbox{1}{Sign} & \bitbox{15}{}
+\end{bytefield}
+
+
 \section{CPU Registers}
 
 An Athena processor includes two types of registers: general purpose registers (GPR) and control/status registers (CRS). 
@@ -109,6 +128,13 @@ \subsection{Control and Status Registers}
     \hline
     N° & name & read & write & Description \\
     \hline
+    \multicolumn{5}{|c|}{Unprivileged Registers} \\
+    \hline
+    \multicolumn{5}{|c|}{Supervisor Registers} \\
+    \hline
+    \hline
+    \multicolumn{5}{|c|}{Machine Registers} \\
+    \hline
     0 & isa & \ok & \no & Machine ISA Register \\
     1 & status & \ok & \ok & Status Register \\
     2 & cause & \ok & \no & Cause Register \\
@@ -161,7 +187,6 @@ \subsubsection{Trap Vector Base Address Regiter}
 
 \subsection{Processor Id}
 
-
 \begin{bytefield}{32}
     \bitheader[endianness=big]{31,1,0} \\
     \bitbox{31}{base}

diff --git a/base/examples.tex b/base/examples.tex
@@ -0,0 +1,3 @@
+\chapter{Examples}
+
+\input{base/examples/basic}
diff --git a/base/examples/basic.tex b/base/examples/basic.tex
@@ -0,0 +1,5 @@
+\section{Basic operations}
+
+\subsection{Simple loop}
+
+\lstinputlisting[language={[Athena]Assembler}]{base/examples/loop.S}
diff --git a/base/examples/loop.S b/base/examples/loop.S
@@ -0,0 +1,4 @@
+	li r1, loop_count
+loop:
+	subi r1, r1, 1
+	bnez r1, loop
diff --git a/base/instr.tex b/base/instr.tex
@@ -2,6 +2,14 @@ \chapter{The Athena Instruction Set}
 
 \section{Instruction Format}
 
+There are 4 basic Athena instruction formats:
+\begin{itemize}
+    \item R-Format
+    \item I-Format
+    \item J-Format
+    \item LS-Format
+\end{itemize}
+
 \subsection{R-Format}
 
 \Rinstr{opcode}{ra}{rb}{rc}{shmat}{func}
@@ -23,20 +31,15 @@ \section{Alphabetical List of Instruction}
 \input{base/instructions/add}
 \input{base/instructions/addi}
 \input{base/instructions/addiu}
-\input{base/instructions/addu}
+\input{base/instructions/addw}
 \input{base/instructions/and}
 \input{base/instructions/andi}
-\input{base/instructions/b}
 \input{base/instructions/beq}
-\input{base/instructions/beqz}
 \input{base/instructions/bge}
 \input{base/instructions/bgeu}
-\input{base/instructions/bgez}
 \input{base/instructions/blt}
 \input{base/instructions/bltu}
-\input{base/instructions/bltz}
 \input{base/instructions/bne}
-\input{base/instructions/bnez}
 \input{base/instructions/call}
 \input{base/instructions/div}
 \input{base/instructions/divu}
@@ -46,14 +49,13 @@ \section{Alphabetical List of Instruction}
 \input{base/instructions/lh}
 \input{base/instructions/lhu}
 \input{base/instructions/lih}
+\input{base/instructions/lq}
 \input{base/instructions/lw}
-\input{base/instructions/mod}
-\input{base/instructions/modu}
+\input{base/instructions/lwu}
 \input{base/instructions/mult}
 \input{base/instructions/multu}
 \input{base/instructions/mvsrr}
 \input{base/instructions/mvsrw}
-\input{base/instructions/nop}
 \input{base/instructions/nor}
 \input{base/instructions/or}
 \input{base/instructions/ori}
@@ -68,8 +70,10 @@ \section{Alphabetical List of Instruction}
 \input{base/instructions/sub}
 \input{base/instructions/subi}
 \input{base/instructions/subiu}
-\input{base/instructions/subu}
+\input{base/instructions/subw}
+\input{base/instructions/sq}
 \input{base/instructions/sw}
+\input{base/instructions/swu}
 \input{base/instructions/trap}
 \input{base/instructions/xor}
 \input{base/instructions/xori}

diff --git a/base/instructions/add.tex b/base/instructions/add.tex
@@ -4,7 +4,7 @@ \subsection{ADD}
 
 \paragraph{Format} ADD ra, rb, rc
 
-\paragraph{Purpose} Add word, Trap on Overflow
+\paragraph{Purpose} Add quadword, Trap on Overflow
 
 \begin{lstlisting}[language=C]
     GPR[ra] = GPR[rb] + GPR[rc];

diff --git a/base/instructions/addi.tex b/base/instructions/addi.tex
@@ -4,10 +4,10 @@ \subsection{ADDI}
 
 \paragraph{Format} ADDI ra, rb, imm
 
-\paragraph{Purpose} Add immediate word, Trap on Overflow
+\paragraph{Purpose} Add immediate sign extended, Trap on Overflow
 
 \begin{lstlisting}[language=C]
-    GPR[ra] = GPR[rb] + (int32_t)(imm);
+    GPR[ra] = GPR[rb] + SEXT(imm);
 \end{lstlisting}
 
 \paragraph{Exceptions:} Integer Overflow
diff --git a/base/instructions/addiu.tex b/base/instructions/addiu.tex
@@ -4,8 +4,8 @@ \subsection{ADDIU}
 
 \paragraph{Format} ADDIU ra, rb, imm
 
-\paragraph{Purpose} Add immediate word
+\paragraph{Purpose} Add immediate zero extended
 
 \begin{lstlisting}[language=C]
-    GPR[ra] = GPR[rb] + (int32_t)(imm);
+    GPR[ra] = GPR[rb] + ZEXT(imm);
 \end{lstlisting}
diff --git a/base/instructions/addu.tex → base/instructions/addw.tex b/base/instructions/addu.tex → base/instructions/addw.tex
@@ -1,11 +1,11 @@
-\subsection{ADDU}
+\subsection{ADDW}
 
 \Rinstr{000000}{ra}{rb}{rc}{00000}{000010}
 
-\paragraph{Format} ADDU ra, rb, rc
+\paragraph{Format} ADDW ra, rb, rc
 
 \paragraph{Purpose} Add word
 
 \begin{lstlisting}[language=c]
-    GPR[ra] = GPR[rb] + GPR[rc];
+    GPR[ra] = SEXT((GPR[rb] + GPR[rc])<31:0>);
 \end{lstlisting}
diff --git a/base/instructions/and.tex b/base/instructions/and.tex
@@ -9,3 +9,5 @@ \subsection{AND}
 \begin{lstlisting}[language=c]
     GPR[ra] = GPR[rb] & GPR[rc];
 \end{lstlisting}
+
+\paragraph{Exceptions:} None
diff --git a/base/instructions/andi.tex b/base/instructions/andi.tex
@@ -6,5 +6,7 @@ \subsection{ANDI}
 
 \paragraph{Purpose} Logical and
 \begin{lstlisting}[language=c]
-    GPR[ra] = GPR[rb] & (uint32_t)(imm);
+    GPR[ra] = GPR[rb] & ZEXT(imm);
 \end{lstlisting}
+
+\paragraph{Exceptions:} None
diff --git a/base/instructions/b.tex b/base/instructions/b.tex
diff --git a/base/instructions/beq.tex b/base/instructions/beq.tex
@@ -9,6 +9,6 @@ \subsection{BEQ}
 \begin{lstlisting}[language=c]
     if (GPR[ra] == GPR[rb])
     {
-        PC += (int32_t)offset * 4;
+        PC += SEXT(offset) * 4;
     }
 \end{lstlisting}
diff --git a/base/instructions/beqz.tex b/base/instructions/beqz.tex
diff --git a/base/instructions/bgez.tex b/base/instructions/bgez.tex
diff --git a/base/instructions/bltz.tex b/base/instructions/bltz.tex
diff --git a/base/instructions/bnez.tex b/base/instructions/bnez.tex
diff --git a/base/instructions/lh.tex b/base/instructions/lh.tex
@@ -4,7 +4,7 @@ \subsection{LH}
 
 \paragraph{Format} LH ra, offset(rb)
 
-\paragraph{Purpose} Loads a 16bit value from memory then sign extended to 32bit before storing to `ra`
+\paragraph{Purpose} Loads a 16bit value from memory then sign extended to 64bit before storing to `ra`
 
 \begin{lstlisting}[language=C]
     GPR[ra] = *(int16_t)(GPR[rb] + offset);

diff --git a/base/instructions/lq.tex b/base/instructions/lq.tex
@@ -0,0 +1,11 @@
+\subsection{LQ}
+
+\LSinstr{001001}{ra}{rb}{11}{offset}
+
+\paragraph{Format} LQ ra, offset(rb)
+
+\paragraph{Purpose} Loads a 64bit value from memory then store to `ra`
+
+\begin{lstlisting}[language=C]
+    GPR[ra] = *(int32_t)(GPR[rb] + offset);
+\end{lstlisting}
diff --git a/base/instructions/lw.tex b/base/instructions/lw.tex
@@ -7,5 +7,6 @@ \subsection{LW}
 \paragraph{Purpose} Loads a 32bit value from memory then store to `ra`
 
 \begin{lstlisting}[language=C]
-    GPR[ra] = *(int32_t)(GPR[rb] + offset);
+    vaddr = GPR[rb] + SEXT(offset);
+    GPR[ra] = SEXT(*vaddr<31:0>);
 \end{lstlisting}
diff --git a/base/instructions/lwu.tex b/base/instructions/lwu.tex
@@ -0,0 +1,12 @@
+\subsection{LW}
+
+\LSinstr{001001}{ra}{rb}{10}{offset}
+
+\paragraph{Format} LW ra, offset(rb)
+
+\paragraph{Purpose} Loads a 32bit value from memory then store to `ra`
+
+\begin{lstlisting}[language=C]
+    vaddr = GPR[rb] + SEXT(offset);
+    GPR[ra] = ZEXT(*vaddr<31:0>);
+\end{lstlisting}
diff --git a/base/instructions/mod.tex b/base/instructions/mod.tex
diff --git a/base/instructions/modu.tex b/base/instructions/modu.tex
diff --git a/base/instructions/nop.tex b/base/instructions/nop.tex
diff --git a/base/instructions/ori.tex b/base/instructions/ori.tex
@@ -5,5 +5,5 @@ \subsection{ORI}
 \paragraph{Format} ORI ra, rb, imm
 
 \begin{lstlisting}[language=C]
-    GPR[ra] = GPR[rb] | imm;
+    GPR[ra] = GPR[rb] | ZEXT(imm);
 \end{lstlisting}
diff --git a/base/instructions/sq.tex b/base/instructions/sq.tex
@@ -0,0 +1,12 @@
+\subsection{SQ}
+
+\LSinstr{001000}{ra}{rb}{11}{offset}
+
+\paragraph{Format} SQ offset(ra), rb
+
+\paragraph{Purpose} Store the 64bit value from the low bits of register `rb` into memory
+
+\begin{lstlisting}[language=C]
+    vaddr = GPR[ra] + SEXT(offset);
+    *vaddr = rb;
+\end{lstlisting}
diff --git a/base/instructions/sub.tex b/base/instructions/sub.tex
@@ -5,3 +5,7 @@ \subsection{SUB}
 \paragraph{Purpose} SUB ra, rb, rc
 
 \paragraph{Exceptions:} Integer Overflow
+
+\begin{lstlisting}[language=C]
+    GPR[ra] = GPR[rb] - GPR[rc];
+\end{lstlisting}