feat!: Brillig with a stack and conditional inlining

avm-transpiler/src/bit_traits.rs

@@ -1,4 +1,4 @@
-use acvm::{AcirField, FieldElement};
+use acvm::{acir::brillig::MemoryAddress, AcirField, FieldElement};
 
 fn get_msb(n: u128) -> usize {
     let mut n = n;
@@ -56,6 +56,15 @@ impl BitsQueryable for usize {
     }
 }
 
+impl BitsQueryable for MemoryAddress {
+    fn num_bits(&self) -> usize {
+        match self {
+            MemoryAddress::Direct(address) => get_msb(*address as u128),
+            MemoryAddress::Relative(offset) => get_msb(*offset as u128),
+        }
+    }
+}
+
 pub fn bits_needed_for<T: BitsQueryable>(val: &T) -> usize {
     let num_bits = val.num_bits();
     if num_bits <= 8 {

avm-transpiler/src/instructions.rs

@@ -1,16 +1,11 @@
 use std::fmt::{self, Display};
 use std::fmt::{Debug, Formatter};
 
+use acvm::acir::brillig::MemoryAddress;
 use acvm::{AcirField, FieldElement};
 
 use crate::opcodes::AvmOpcode;
 
-/// Common values of the indirect instruction flag
-pub const ALL_DIRECT: u8 = 0b00000000;
-pub const ZEROTH_OPERAND_INDIRECT: u8 = 0b00000001;
-pub const FIRST_OPERAND_INDIRECT: u8 = 0b00000010;
-pub const SECOND_OPERAND_INDIRECT: u8 = 0b00000100;
-
 /// A simple representation of an AVM instruction for the purpose
 /// of generating an AVM bytecode from Brillig.
 /// Note: this does structure not impose rules like "ADD instruction must have 3 operands"
@@ -141,3 +136,55 @@ impl AvmOperand {
         }
     }
 }
+
+#[derive(Debug, Default)]
+pub(crate) struct AddressingModeBuilder {
+    indirect: Vec<bool>,
+    relative: Vec<bool>,
+}
+
+impl AddressingModeBuilder {
+    fn is_relative(&self, address: &MemoryAddress) -> bool {
+        match address {
+            MemoryAddress::Relative(_) => true,
+            MemoryAddress::Direct(_) => false,
+        }
+    }
+
+    pub(crate) fn direct_operand(mut self, address: &MemoryAddress) -> Self {
+        self.relative.push(self.is_relative(address));
+        self.indirect.push(false);
+
+        self
+    }
+
+    pub(crate) fn indirect_operand(mut self, address: &MemoryAddress) -> Self {
+        self.relative.push(self.is_relative(address));
+        self.indirect.push(true);
+
+        self
+    }
+
+    pub(crate) fn build(self) -> AvmOperand {
+        let num_operands = self.indirect.len();
+        assert!(num_operands <= 8, "Too many operands for building addressing mode bytes");
+
+        let mut result = 0;
+        for (i, (indirect, relative)) in
+            self.indirect.into_iter().zip(self.relative.into_iter()).enumerate()
+        {
+            if indirect {
+                result |= 1 << i;
+            }
+            if relative {
+                result |= 1 << (num_operands + i);
+            }
+        }
+
+        if num_operands <= 4 {
+            AvmOperand::U8 { value: result as u8 }
+        } else {
+            AvmOperand::U16 { value: result as u16 }
+        }
+    }
+}